SPLC063B1 80 Channel Segment LCD Driver Preliminary SEP. 19, 2007 Version 0.1 ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document. Contact ORISE Technology to obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent or other rights of third parties which may result from its use. In addition, ORISE Technology products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of ORISE Technology. Preliminary SPLC063B1 Table of Contents PAGE 1. GENERAL DESCRIPTION .......................................................................................................................................................................... 3 2. FEATURES.................................................................................................................................................................................................. 3 3. ORDERING INFORMATION........................................................................................................................................................................ 3 4. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5 6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6 6.1. DOT MATRIX LCD DRIVER WITH 80 CHANNEL OUTPUTS. ......................................................................................................................... 6 6.2. INPUT / OUTPUT SIGNAL ......................................................................................................................................................................... 6 6.3. LCD OUTPUT WAVEFORM ...................................................................................................................................................................... 6 7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 7 7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 7 7.2. DC CHARACTERISTICS ........................................................................................................................................................................... 7 7.3. AC CHARACTERISTICS ........................................................................................................................................................................... 7 7.4. TIMING CHARACTERISTIC ....................................................................................................................................................................... 8 8. APPLICATION CIRCUITS ........................................................................................................................................................................... 9 8.1. APPLICATION CIRCUIT FOR 1/16 DUTY, 1/5 BIAS ...................................................................................................................................... 9 8.2. APPLICATION CIRCUIT FOR 1/8 DUTY, 1/4 BIAS ........................................................................................................................................ 9 8.3. TIMING CHART OF INPUT AND OUTPUT DATA.......................................................................................................................................... 10 9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 11 9.1. PAD ASSIGNMENT ................................................................................................................................................................................11 9.2. PAD LOCATIONS .................................................................................................................................................................................. 12 9.3. PIN ASSIGNMENT ................................................................................................................................................................................ 13 9.4. PACKAGE INFORMATION ....................................................................................................................................................................... 14 10. LEAD FRAME PACKAGE PCB DESIGN AND MANUFACTURING GUIDELINES .................................................................................. 15 11. DISCLAIMER............................................................................................................................................................................................. 18 12. REVISION HISTORY ................................................................................................................................................................................. 19 © ORISE Technology Co., Ltd. Proprietary & Confidential 2 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 80 CHANNEL SEGMENT LCD DRIVER 1. GENERAL DESCRIPTION 2. FEATURES The SPLC063B1 is a LCD driver LSI which is fabricated by low Liquid crystal display driver with serial/parallel conversion power CMOS technology. Basically it consists of two set of 40-bit function. Interface compatible with the SPLC100; connectable with bi-directional shift registers, 40 data latch flip-flops and 40 liquid crystal display driver circuits. be applied as segment driver. It has 80-channel outputs and can SPLC780. Internal output circuits for LCD driver: 80 The SPLC063B1 receives serial display data from a display control LSI, converts it into parallel Internal serial/parallel conversion circuits: data and supplies liquid crystal display waveforms to the liquid — 40-bit bi-directional shift register X 2 crystal. — 40-bit latch X 2 Its interface is compatible with the SPLC100. It reduces Power supply: the number of LSI’s and lowers the cost of a LCD module. — Internal logic: 2.7V - 5.5V — Liquid crystal display driver circuit: 3.0V - 8V CMOS process. 3. ORDERING INFORMATION Product Number Package Type SPLC063B1-C Chip form SPLC063B1-HQ061 Green Package form - QFP 100L 4. BLOCK DIAGRAM Y1 Y2 Part1 V1 V2 LCD DRIVER V3 Y41 Y42 Y39 Y40 V4 V1 V2 V3 V4 Part2 Y79 Y80 LCD DRIVER Data Latch(40bit) Data Latch(40bit) VDD VSS VEE Bidirectional Shift Register(40bit) M CL1 CL2 Bidirectional Shift Register(40bit) SW CONTR LOGIC DL1 © ORISE Technology Co., Ltd. Proprietary & Confidential SHL1 DR1 3 DL2 SHL2 DR2 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 4.1. Block Functions 4.1.1. LCD driver Select one of four levels of voltage V1, V2, V3, and V4 for driving Y1 Y2 a LCD and transfer it to the output terminals according to the LCD driver outputs Y39 Y40 SHL1/SHL2=GND combination of M and the data in the latch circuit. CL1 1 2 Data Latch 39 40 1 2 Shift register 39 40 4.1.2. Data latch CL2 Latches the data input from the bi-directional shift register at the DL1/DL2 fall of CL1 and transfer its outputs to the LCD driver circuits. DR1/DR2 Y1 Y2 4.1.3. Bi-directional shift register Shifts the serial data at the fall of CL2 and transfuse the output of each bit of the register to the latch circuit. LCD driver outputs Y39 Y40 SHL1/SHL2=VDD CL1 1 2 Data Latch 39 40 1 2 Shift register 39 40 When SHL1/SHL2 = GND, the data input from DL1/DL2 shifts from bit 1 to bit 40 in CL2 order of entry. DR1/DR2 DL1/DL2 On the other hand, when SHL1/SHL2 = VDD, the data shifts from bit 40 to bit-1. Relation between SHL1/SHL2 and the Shift Direction The data of the last bit of the register is latched to be output from DR1/DR2 at the rise of CL2, when SHL1/SHL2 = GND. The data of the last bit of the register is latched to be output from DL1/DL2 at the rise of CL2 when SHL1/SHL2 = VDD. © ORISE Technology Co., Ltd. Proprietary & Confidential 4 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 5. SIGNAL DESCRIPTIONS Mnemonic (No.) Input VDD (59) VSS (GND) (55) Name Output Operating Voltage Power Negative Supply Voltage Interface For logical circuit (2.7V - 5.5V) Power Supply 0V (GND) For LCD driver circuit VEE (50) V1, V2 (51, 52) Input V3, V4 (53, 54) Input Y1 - Y40 Description LCD driver output voltage Bias voltage level for LCD driver (Select level) Bias voltage level for LCD driver level Power (Nonselect level) Output LCD driver LCD driver output LCD Selection of the shift direction of shift register SHL1 (57) DL1, DR1 (61, 62) Y41 - Y80 Input Part1 Data Interface Input SHL1 DL1 DR1 VDD OUT IN VSS IN OUT Data input/output of shift register (part1) Output Output LCD driver LCD driver output VDD or VSS Controller or SPLC063B1 LCD Selection of the shift direction of shift register SHL2 (58) DL2, DR2 (63, 64) Input Part2 Data Interface Input CL1, CL2 (56, 60) Input © ORISE Technology Co., Ltd. Proprietary & Confidential DL2 DR2 VDD OUT IN VSS IN OUT Data input/output of shift register (part 2) Input Output M (65) SHL2 Alternated signal for LCD The alternating signal to convert LCD driver driver output Data shift/latch clock waveform to AC CL1: Data latch clock CL2: Data shift clock 5 VDD or VSS Controller or SPLC063B1 Controller Controller SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 6. FUNCTIONAL DESCRIPTIONS 6.1. Dot Matrix LCD Driver with 80 Channel Outputs. 6.3. LCD Output Waveform 6.2. Input / Output Signal OUTPUT DATA — Output: 40 X 2 channel waveform for LCD driving — Input: M V2 V2 1). Serial display data and control pulse from the controller LSI. V4 OUTPUT (Y1 - Y80) 2). Bias voltage (V1 - V4). V4 V3 V1 V3 V1 V1, V2: selected level V3, V4: Non-selected level © ORISE Technology Co., Ltd. Proprietary & Confidential 6 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristic Symbol Value Unit Operation Voltage VDD -0.3 to +7.0 V LCD Driver Supply Voltage VEE VDD-10V to VDD+0.3V V TA -20 to +75 °C Storage Temperature TSTO -55 to +125 °C Input voltage (1) VIN1 -0.3 to VDD+0.3 V Input voltage (2) VIN2 VDD+0.3 to VEE-0.3 Operating Temperature V Note1: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. Note2: Input Voltage (2) applies to V1 - V4; Input Voltage (1) applies to other pins. 7.2. DC Characteristics (VDD = 2.7V - 5.5V, VDD - VEE = 3.0V - 8V, TA = +25℃) Characteristic Symbol Test Condition Min. Max. Unit Operating Current IDD fCL2 = 400KHz - 1.0 mA Supply Current IEE fCL1 = 1.0KHz - 10 µA Input High Voltage VIH 0.7VDD VDD Input Low Voltage VIL 0 0.3VDD Input Leakage Current ILKG -5.0 5.0 Output High Voltage VOH IOH = -0.4mA VDD-0.4 - Output Low Voltage VOL IOL = +0.4mA - 0.4 VD1 Voltage Descending VD2 Leakage Current VIN = 0 to VDD ION = 0.1mA ION = 0.05mA for each Y1 - Y80 VIN = VDD to VEE IV (Output Y1 - Y80; floating) VDD, VEE CL1, CL2, DL1, V DL2, DR1, DR2, µA SHL1, SHL2, M V DL1, DL2, DR1, DR2 V V(V1 - V4)-Y(Y1 - Y80) µA V1 - V4 1.1 - for one of Y1 - Y80 Applicable Pin - 1.5 -10 10 7.3. AC Characteristics (VDD = 2.7V - 5.5V, VDD - VEE = 3.0V - 8V, TA = +25℃) Characteristic Data shift frequency Symbol Application Pin Min. Max. Unit KHz fCL CL2 - 400 Clock High level Width tWCKH CL1, CL2 800 - Clock Low level Width tWCKL CL2 800 - Data set-up time tSU DL1, DL2, DR1, DR2 300 - Clock set-up time tSL 500 - Clock set-up time tLS CL1, CL2 500 - Clock rise/fall time tR/tF - 200 Date delay time tD DL1, DL2, DR1, DR2 - 500 Date hold time tDH DL1, DL2, DR1, DR2 300 - © ORISE Technology Co., Ltd. Proprietary & Confidential 7 ns Test Condition (CL2→CL1) (CL1→CL2) CL = 15pF SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 7.4. Timing Characteristic VIH VIH VIL tWCKL CL2 VIL tWCKH tF tR tDH tSU Data in (DL1,DL2) (DR1,DR2) VIH VIL tSL tD Data out (DL1,DL2) (DR1,DR2) VOH tLS VOL tLS VIH VIL tR CL1 tSU tWCKH tF VIH FLM VIL © ORISE Technology Co., Ltd. Proprietary & Confidential 8 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 8. APPLICATION CIRCUITS 40 D VDD R 80 Y1 - Y80 CL1 VDD Segment Signal 80 CL2 M SHL1 SHL2 SHL2 DL1 V1 V2 V3 V4 V5 DR1 DL2 R CL1 R DL1 DR2 DR1 DL2 CL1 CL2 CL2 M M VEE V1 V2 V3 V4 R Y1 - Y80 SHL1 SPLC063B1 SEG1 | SEG40 LCD 16 DR2 OPEN VEE V1 V2 V3 V4 COM1 | COM16 SPLC063B1 SPLC780E 8.1. Application Circuit for 1/16 Duty, 1/5 Bias R VR VDD GND or Other Voltage 40 D VDD R 80 Y1 - Y80 CL1 VDD Segment Signal 80 CL2 M SHL1 SHL2 SHL2 DL1 V1 V2 V3 V4 V5 DR1 DL2 R CL1 DR2 DL1 DR1 DL2 CL1 CL2 CL2 M M V EE V1 V2 V3 V4 R Y1 - Y80 SHL1 SPLC063B1 SEG1 | SEG40 LCD 8 DR2 OPEN V EE V1 V2 V3 V4 COM1 | COM8 SPLC063B1 SPLC780E 8.2. Application Circuit for 1/8 Duty, 1/4 Bias R VR VDD GND or Other Voltage © ORISE Technology Co., Ltd. Proprietary & Confidential 9 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 8.3. Timing Chart of Input and Output Data 1 2 78 3 CL 2 79 80 (Shift Clock) (Display Data) 1:on 0:off Input Data OUTPUT DATA CL 1 (Latch Clock) LCD Driver Output © ORISE Technology Co., Ltd. Proprietary & Confidential 10 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 9. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment SPLC063B1 Chip Size : 3296*2096µm Pad Size : 86*86 µm This IC’s substrate should be connected to VDD Note1: Chip size included scribe line. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. © ORISE Technology Co., Ltd. Proprietary & Confidential 11 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 9.2. PAD Locations PAD No. PAD Name X Y PAD No. PAD Name X Y 1 Y72 -1550 950 49 Y1 1550 -950 2 Y73 -1550 830 50 VEE 1550 -830 3 Y74 -1550 720 51 V1 1550 -720 4 Y75 -1550 610 52 V2 1550 -610 5 Y76 -1550 505 53 V3 1550 -505 6 Y77 -1550 400 54 V4 1550 -400 7 Y78 -1550 300 55 VSS 1550 -300 8 Y79 -1550 200 56 CL1 1550 -200 9 Y80 -1550 100 57 SHL1 1550 -100 10 Y40 -1550 0 58 SHL2 1550 0 11 Y39 -1550 -100 59 VDD 1550 100 12 Y38 -1550 -200 60 CL2 1550 200 13 Y37 -1550 -300 61 DL1 1550 300 14 Y36 -1550 -400 62 DR1 1550 400 15 Y35 -1550 -505 63 DL2 1550 505 16 Y34 -1550 -610 64 DR2 1550 610 17 Y33 -1550 -720 65 M 1550 720 18 Y32 -1550 -830 66 Y41 1550 830 19 Y31 -1550 -950 67 Y42 1550 950 20 Y30 -1435 -950 68 Y43 1435 950 21 Y29 -1325 -950 69 Y44 1325 950 22 Y28 -1215 -950 70 Y45 1215 950 23 Y27 -1110 -950 71 Y46 1110 950 24 Y26 -1005 -950 72 Y47 1005 950 25 Y25 -900 -950 73 Y48 900 950 26 Y24 -800 -950 74 Y49 800 950 27 Y23 -700 -950 75 Y50 700 950 28 Y22 -600 -950 76 Y51 600 950 29 Y21 -500 -950 77 Y52 500 950 30 Y20 -400 -950 78 Y53 400 950 31 Y19 -300 -950 79 Y54 300 950 32 Y18 -200 -950 80 Y55 200 950 33 Y17 -100 -950 81 Y56 100 950 34 Y16 0 -950 82 Y57 0 950 35 Y15 100 -950 83 Y58 -100 950 36 Y14 200 -950 84 Y59 -200 950 37 Y13 300 -950 85 Y60 -300 950 38 Y12 400 -950 86 Y61 -400 950 39 Y11 500 -950 87 Y62 -500 950 40 Y10 600 -950 88 Y63 -600 950 41 Y9 700 -950 89 Y64 -700 950 42 Y8 800 -950 90 Y65 -800 950 43 Y7 900 -950 91 Y66 -900 950 44 Y6 1005 -950 92 Y67 -1005 950 45 Y5 1110 -950 93 Y68 -1110 950 46 Y4 1215 -950 94 Y69 -1215 950 47 Y3 1325 -950 95 Y70 -1325 950 48 Y2 1435 -950 96 Y71 -1435 950 © ORISE Technology Co., Ltd. Proprietary & Confidential 12 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 9.3. PIN Assignment Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y80 Y79 Y78 Y77 Y76 Y75 Y74 Y73 Y72 Y71 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Y31 QFP 100L Top View Y30 1 80 Y70 Y29 2 79 Y69 Y28 3 78 Y68 Y27 4 77 Y67 Y26 5 76 Y66 Y25 6 75 Y65 Y24 7 74 Y64 Y23 8 73 Y63 Y22 9 72 Y62 Y21 10 71 Y61 Y20 11 70 Y60 Y19 12 69 Y59 Y18 13 68 Y58 Y17 14 Y16 15 67 Y57 SPLC063B1 Y15 16 Y14 17 66 Y56 65 Y55 64 Y54 30 51 Y41 © ORISE Technology Co., Ltd. Proprietary & Confidential 13 50 52 Y42 Y1 NC 29 48 49 53 Y43 Y2 M NC 28 DR2 47 54 Y44 Y3 DL2 46 55 Y45 27 DL1 44 DR1 45 26 Y4 VDD 42 CL2 43 Y5 41 56 Y46 NC 25 40 57 Y47 Y6 NC 58 Y48 24 SHL1 38 SHL2 39 23 Y7 VSS 36 CL1 37 59 Y49 Y8 35 22 V4 60 Y50 Y9 34 61 Y51 Y10 21 V3 62 Y52 Y11 20 33 Y12 19 V2 63 Y53 VEE 31 V1 32 Y13 18 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 9.4. Package Information QFP 100L Outline Dimensions Unit: Millimeter Dimension in mm Symbol Min. Nom. Max. A -- -- 3.40 A1 0.25 -- -- A2 2.73 2.85 2.97 b 0.25 0.30 0.38 c 0.13 0.15 0.23 D 23.00 23.20 23.40 D1 19.90 20.00 20.10 E 17.00 17.20 17.40 E1 13.90 14.00 14.10 e 0.65 BSC L1 1.60 REF © ORISE Technology Co., Ltd. Proprietary & Confidential 14 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 10. LEAD FRAME PACKAGE PCB DESIGN AND MANUFACTURING GUIDELINES 10.1. Purpose The purpose of this specification is to identify plastic surface mount devices (SMDs) those are sensitive to moisture-induced stress, so that they can be properly design PCB and assembly packaged, stored and handled to avoid subsequent mechanical damage during the assembly solder reflow attachment and /or repair operation. 10.2. Scope 10.2.1. PCB layout guideline 10.2.2. PCB process 10.2.3. Storage Condition and Period for Package 10.2.4. Recommended SMT Temperature Profile 10.3. Noun definition 10.3.1. NSMD: Non Solder Mask Defined 10.3.2. SMD: Solder Mask Defined 10.3.3. CSP: Chip scale Package 10.3.4. PCB :Printed Circuit Board 10.4. Responsibility unity: ORISE Quality Assurance unity 10.5. Contents 10.5.1. Applicable documents IPC-SM-782: Surface Mount Design & Land Pattern Standard IPC-7351Generic Requirements for Surface Mount Design and Land Pattern Standard. IPC-7525: Stencil Design Guidelines J-STD-020: IPC/JEDEC Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Device IPC JEDEC: J-STD-033A Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices IPC-HDBK-001: Handbook & Guide to the Requirements of Soldered Electronic Assemblies with Amendment 1 IPC -6016: Qualification & Performance Specification for High Density Interconnect (HDI) Layers or Boards IPC-STD-003: Solderability Tests for Printed Boards JESD22-B111: Board Level Drop Test of Components for Handheld Electronic Products JESD22-B110: Subassembly Mechanical Shock IPC-A-610: Acceptability of Electronic Assemblies 10.5.2. PCB layout guideline PCB designer comply with IPC-SM-782 and IPC-7095 requirements is recommended 10.5.3. PCB process 10.5.3.1. Board material The Glass transition temperature (Tg) of Board material greater than 170 degree C is recommended for Pb- free and Green package. 10.5.3.2. Surface Finishes In order to achieve high assembly yields, use of a surface finish that is planar And has good solderability performance is important. Below methods are all known to provide an acceptable land pad surface. *OSP (Organic Solderability Preservative) *Nihau (Electroplated nickel /gold) *Immersion Ag © ORISE Technology Co., Ltd. Proprietary & Confidential 15 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 *Immersion Sn 10.5.3.3. Solder Paste: No clean flux is recommended. 10.5.3.4. Stencil Design Guidelines: Refer to IPC-7525 Stencil Design Guidelines process 10.5.3.5. Reflow Oven: Forced convection reflow with nitrogen is recommended for Pb-free and Green package.. 10.5.3.6. Reflow profile: Using more than 8 zone oven is recommended for Pb-free and Green package. 10.5.3.7. To use IPC-A-610 is recommended for soldered electrical and electronic assemblies. 10.5.4. Storage condition and period for package Orise technology evaluates all plastic surface mount devices (SMDs) to ICP/JEDEC J-STD-020A, moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices, or refers to IPC JEDEC J-STD-033A Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices 10.5.4.1. The primary facts for the package storage include oxidation, static, and therefore, the following rules are recommended to be applied for the storage. 10.5.4.2. The storage temperature should be 25℃ ± 5℃, and the humidity should be in the range of 50% ± 10% R.H. after opening the dry pack. After the dry bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or equivalent processing. 10.5.4.3. Must be: a. Mounted within 168 hours(Level 3) and 72 hours(Level 4) at factory conditions of ≦ 30℃/ 60% R.H. or b. Stored at ≦ 20% R.H. 10.5.4.4. Devices require baking, before mounting, if: a. Humidity Indicator Card shown b. 10.5.4.3 warning message when read at 25℃±5℃, or is not met. 10.5.4.5. If baking is required. Devices may be baking for: a. 192 hour at 40℃+5℃/-0℃ and <5% R.H. for low temperature device containers, or b. 24 hours at 125±5℃ for high temperature device containers 10.5.4.6. The storage condition should be consistent with the operation condition to prevent dewing phenomena. 10.5.4.7. The storage location should be kept away from water and smoke; an isolated area with positive pressure control is preferred. 10.5.4.8. For a long-term storage, it is recommended to keep in a container with Nitrogen in it. 10.5.4.9. Avoid heavy objects stacked on the pack. 10.5.4.10. Avoid the static damage; use an anti-static bag for the package. 10.5.5. The classification of moisture sensitivity for Orise’s product packages are shown in the following For Lead Free / Green Packages Package Moisture sensitivity level Max. Reflow temperature Floor life storage condition Dry pack LEVEL 3 255 +5/-0℃ 168Hrs @ ≦ 30℃/ 60% R.H. Yes QFP 10.5.6. Recommended SMT Temperature Profile This “Recommended” temperature profile is a rough guideline for SMT process reference. Most of ORISE leadframe base product choice Matte Tin and Sn/Bi for plating recipe. For PPF (Pre-Plated Frame) product with 63/37 solder paste, we recommend 240℃~245℃ for peak temperature. © ORISE Technology Co., Ltd. Proprietary & Confidential 16 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 10.6. References IPC: http://www.ipc.org *NEMI (National Electronics Manufacturing Initiative) http://www.nemi.org *HDPUG (High Density Package Users Group) http://www.hdpug.org *JEDEC (Joint Electronic Device Engineering Council) http://www.jedec.org *JEITA (Japan Electronic Industry Association) http://www.jeita.org © ORISE Technology Co., Ltd. Proprietary & Confidential 17 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 11.DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by ORISE Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. ORISE Technology makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. applications. FURTHERMORE, ORISE Technology MAKES NO ORISE Technology reserves the right to halt production or Products described herein are intended for use in normal commercial Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by ORISE Technology for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © ORISE Technology Co., Ltd. Proprietary & Confidential 18 SEP. 19, 2007 Version: 0.1 Preliminary SPLC063B1 12. REVISION HISTORY Date Revision # SEP. 19, 2007 0.1 © ORISE Technology Co., Ltd. Proprietary & Confidential Description Original Page 19 19 SEP. 19, 2007 Version: 0.1