Driver IC (OTA5180A)

OTA5180A
1440x544 System-On-Chip Driver
for 480RGBx272 TFT LCD
Preliminary
APR. 01, 2008
Version 0.2
ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be
accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document.
Contact ORISE Technology to
obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, ORISE Technology products are not authorized for use as critical components in life
support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to
the user, without the express written approval of ORISE Technology.
Preliminary
OTA5180A
TABLE OF CONTENTS
PAGE
1.
GENERAL DESCRIPTION .............................................................................................................................................. 4
2.
FEATURES ...................................................................................................................................................................... 4
3.
ORDERING INFORMATION ............................................................................................................................................ 4
4.
BLOCK DIAGRAM .......................................................................................................................................................... 5
5.
SIGNAL DESCRIPTIONS ................................................................................................................................................ 6
6.
POWER APPLICATION CIRCUIT.................................................................................................................................... 9
7.
REGISTER BANK.......................................................................................................................................................... 10
7.1
THE EXECUTING TIME OF REGISTERS ............................................................................................................................................... 10
7.2
SERIAL CONTROL TIMING CHART ......................................................................................................................................................11
7.3
REGISTER SUMMARY ....................................................................................................................................................................... 12
7.4
REGISTER DESCRIPTION .................................................................................................................................................................. 13
7.4.1
R0: Direction setting........................................................................................................................................................ 13
7.4.2
R1: GRB、SHDB2、SHDB1、DISP .............................................................................................................................. 13
7.4.3
R2: CONSTRAST ........................................................................................................................................................... 14
7.4.4
R3: SUB-CONTRAST_R ................................................................................................................................................ 15
7.4.5
R4: SUB-CONTRAST_B................................................................................................................................................. 15
7.4.6
R5: BRIGHTNESS .......................................................................................................................................................... 15
7.4.7
R6: SUB- BRIGHTNESS _R........................................................................................................................................... 15
7.4.8
R7: SUB- BRIGHTNESS _B ........................................................................................................................................... 16
7.4.9
R8: HSYNC BLANKING.................................................................................................................................................. 16
7.4.10 R9: HSYNC BLANKING.................................................................................................................................................. 16
7.4.11
R10: SYNC、DCLKPOL、CP3_FREQ、CP2_FREQ、CP1_FREQ ............................................................................. 17
7.4.12 R11: LED_CURRENT、BL_DRV、DRV_FREQ、PFM_DUTY ..................................................................................... 19
7.4.13 R12: LED_ON_CYCLE、LED_ON_RATIO .................................................................................................................... 19
7.4.14 R13: OP .......................................................................................................................................................................... 21
7.4.15 R14: LC_TYPE ............................................................................................................................................................... 21
7.4.16 R15:VGH_SEL、VGL_SEL ............................................................................................................................................ 21
7.4.17 R16: INVERSION............................................................................................................................................................ 22
7.4.18 R17: VCOMH .................................................................................................................................................................. 22
7.4.19 R18: VCOML................................................................................................................................................................... 22
8.
ELECTRICAL SPECIFICATIONS .................................................................................................................................. 23
8.1
ABSOLUTE MAXIMUM RATINGS ......................................................................................................................................................... 23
8.2
DC CHARACTERISTICS (VDDIO=1.8V, VDD = 3.0V, AVDD = 5.5V, AGND = 0V, TA = -20℃ TO 80℃) .............................................. 23
8.3
8.2.1
For digital circuit.............................................................................................................................................................. 23
8.2.2
For analog circuit ............................................................................................................................................................ 23
OUTPUT SIGNAL CHARACTERISTICS ................................................................................................................................................. 24
8.3.1
8.4
8.5
Output Voltage ................................................................................................................................................................ 24
INPUT TIMING .............................................................................................................................................................................. 25
8.4.1
480XRGBX272 Vertical Timing....................................................................................................................................... 25
8.4.2
480XRGBX272 Horizontal Timing................................................................................................................................... 25
SYNC-DE MODE ............................................................................................................................................................................ 26
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Preliminary
OTA5180A
9.
OUTPUT TIMING ........................................................................................................................................................... 27
10. POWER ON/OFF SEQUENCE ...................................................................................................................................... 28
11. APPLICATION CIRCUIT FOR DC-DC CONVERTER .......................................................................................................... 29
12. CHIP INFORMATION..................................................................................................................................................... 30
12.1 PAD ASSIGNMENT ........................................................................................................................................................................... 30
12.2 PAD DIMENSION ............................................................................................................................................................................. 30
12.3 BUMP CHARACTERISTIC................................................................................................................................................................... 30
12.4 PAD LOCATIONS .............................................................................................................................................................................. 31
12.5 ALIGN KEY LOCATIONS .................................................................................................................................................................... 31
13. COG PRODUCTS MANUFACTURING GUIDELINES ................................................................................................... 32
14. DISCLAIMER................................................................................................................................................................. 33
15. REVISION HISTORY...................................................................................................................................................... 34
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Preliminary
OTA5180A
1440x544 TFT-LCD DRIVER AND CONTROLLER
1. GENERAL DESCRIPTION
OTA5180A is a single chip driver solution combining a source
„ Support both SYNC and SYNC-DE mode input timing
driver, a gate driver, a timing controller, a power supply circuit and
„ Support parallel RGB (24-bit) input interface and Serial RGB
a back-light control circuit, especially designed for color TFT LCDs.
(8-bit) input interface
„ Display control and configuration selected by 3-wire serial
The OTA5180A supports panel resolutions of 480xRGBx272. The
system can be configured through a R/W 3-wire serial interface.
communication control
„ Built-in DC-DC control circuit, charge pump circuit, VCOM
circuit with programmable adjustment
2. FEATURES
„ Built-in R-DAC gamma correction
„ LCD driver with timing controller
„ Output deviation: 20mV
„ Line/Frame Inversion
„ Power for LCD driving: 4.2V ~ 6V
„ 720 source output channels
„ Power for charge pump supply (VDD): 2.25V ~ 3.6V
„ 544 gate output channels
„ Power for digital interface: 1.8V ~ VDD
„ 8-bit resolution 256 gray scale with dithering (6 bits DAC +2 bit
„ COG package
„ Built-in power saving mode
dithering)
3. ORDERING INFORMATION
Product Number
Package Type
OTA5180A-C
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Chip form with Gold Bump
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Preliminary
OTA5180A
4. BLOCK DIAGRAM
CS
SDA
SCL
S1
SPI
Interface
S718 S719 S720
S2
Source Output Buffer
Digital to Analog Converter
DR[7:0]
DB[7:0]
GRST
STB
Vsync
Hsync
6
6
6
6
6
6
6
6
6
Level Shift
Level Shift CKT
DG[7:0]
6
Timing signal generator
Line Latch
6
Dithering
Shift Register
Shift Register(544)
DCLK
VDD
VDDIO
GND
AGND
Level Shift
Charge
Pump
VCOM
Driver
PFM
Control
Gate Output Buffer
G1
G3
G543 G544
FB
DRV
VCOMH
VCOML
VCOM
Proprietary & Confidential
VGH
VGL
DVDD
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Preliminary
OTA5180A
5. SIGNAL DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Serial Communication Interface / Timming Controller (Tcon) / Mode Selection
I
CS
Serial communication chip select
(VDDIO)
I/O
SDA
Serial communication data input and output
(VDDIO)
I
SCL
Serial communication clock input
(VDDIO)
Parallel 24-bit and Serial 8-bit data input selection.
PARA_SERI
DR0~DR7
DG0~DG7
DB0~DB7
DCLK
HSYNC
VSYNC
DE
SYNC
I
PARA_SERI=”H”, Parallel 24-bit RGB input through DR0~7, DB0~DB7,
(VDDIO) DG0~DG7 (Default)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
PARA_SERI=”L”, Serial 8-bit data input through DR0~DR7
When PARA_SERI=”H”, these will be treated as 8-bit digital Red data input
When PARA_SERI=”L”, these will be treated as serial 8-bit data input
8-bit digital Green data input, only valid when PARA_SERI=”H”
8-bit digital Blue data input, only valid when PARA_SERI=”H”
Clock signal; latching data at the falling edge
Horizontal sync signal; negative polarity
Vertical sync signal; negative polarity
Data input enable. Active High to enable the data input.
SYNC or SYNC-DE mode selection:
SYNC = “Low”: accepted SYNC-DE mode input timing (Default)
SYNC = “High”: accepted SYNC mode input timing
Horizontal scan direction control (Please refer to the register setting : HDIR)
HDIR
I
HDIR(pin) = “Low” : The definition of HDIR register setting is inversion from
original.
HDIR(register) = “0” : Shift from left to right;
HDIR(register) = “1” : Shift from right to left. (Default of the Register)
(VDDIO)
HDIR(pin) = “High”:The definition of HDIR register setting is invariant.
(Default)
HDIR(register) = “0” : Shift from right to left;
HDIR(register) = “1” : Shift from left to right. (Default of the Register)
Vertical scan direction control (Please refer to the register setting : VDIR)
VDIR
I
VDIR(pin) = “Low”: The definition of VDIR register setting is inversion from
original.
VDIR(register) = “0”: Shift from up to down;
VDIR(register) = “1”: Shift from down to up. (Default of the Register)
(VDDIO)
VDIR(pin) = “High”: The definition of VDIR register setting is invariant.
(Default)
VDIR(register) = “0”: Shift from down to up;
VDIR(register) = “1”: Shift from up to down. (Default of the Register)
Set the TN or MVA mode.
MVA_TN
I
MVA_TN=“Low＂: TN
(VDDIO) MVA_TN=“High＂: MVA mode. (Default)
TN_TYPE
TN_TYPE =“Low＂: The liquid crystal is TN mode1, with lower VCOM power applied.
I
(VDDIO) TN_TYPE =“High＂: The liquid crystal is TN mode2 or MVA, with higher VCOM power
To identify the liquid crystal is TN or not.
applied. (Default)
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OTA5180A
Charge pump power selection
PWR_SEL
I
When VDD=2.5V, PWR_SEL =“Low＂
(VDDIO) When VDD=3.3V, PWR_SEL =“High＂ (Default)
Source driver driving capability selection. OP0 and OP1 pins are internal
pulled to default setting.
OP0 - OP1
VDPOL
HDPOL
DCLKPOL
DATA_RB
GRB
LVR_EN
DISP
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
(VDDIO)
I
OP1
OP0
Driving capability
LOW
LOW
-25%
LOW (Default)
HIGH (Default)
Normal (Default)
HIGH
LOW
+25%
HIGH
HIGH
+50%
Vsync polarity control.
VDPOL=”1”, negative polarity (default)
VDPOL=0, positive polarity
Hsync polarity control.
HDPOL=”1”, negative polarity (default)
HDPOL=”0”, positive polarity
DCLK polarity control.
DCLKPOL=”1”, negative polarity (default)
DCLKPOL=”0”, positive polarity
Data R[7:0] & B[7:0] exchanged internally
DATA_RB=”1” R[7:0]→B[7:0](internally) B[7:0]→R[7:0](internally)
DATA_RB=”0” R[7:0]→R[7:0](internally)
B[7:0]→B[7:0](internally) (default)
Global reset. Active low, Internal pull high
Low voltage reset enable. Active high. Internal pull high.
Display control / standby mode selection.
DISP = “Low” : Standby; (Default)
(VDDIO) DISP = “High” : Normal display
Source / Gate Driver
S1~S720
O
G1~G544
O
Source driver output signals
Gate driver output signals
DC/DC Converter
DRV
O
FB
I
Power transistor gate signal for the boost converter
Main boost regulator feedback input. Connect feedback resistive divider to GND. FB
threshold can be selected by register setting, usually 0.6V (default).
VCOM Generator
VCOM
O
Frame polarity output for VCOM. Swing between VCOMH and VCOML.
VCOMH
C
Power supply for VCOM high level output.
VCOML
C
Power supply for VCOM low level output.
VDD
P
Power supply for digital circuit
GND
P
Ground pin for digital circuit
PVDD
P
Power supply for charge pump circuit
PGND
P
Ground pin for charge pump circuit
AGND
P
Ground for analog circuit
VDDIO
P
Power supply for digital interface I/O pins
V_OTP
P
Power input pin for customer OTP.
Power Supply
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OTA5180A
Capacitor connect pin for internal charge pump. Refer to the illustration of
V[1:10]
C
VDD_18
C
Power setting capacitor connect pin
VDD2
C
Power setting capacitor connect pins
VDDA
C
Power setting capacitor connect pins
VCL
C
Power setting capacitor connect pins
VGH
C
VGL
C
Others
TEST[0:34]
power application circuit.
Power setting capacitor connect pins. Positive power supply for gate driver
output.
Power setting capacitor connect pins. Negative power supply for gate driver
output.
T
Test pins for OriseTech internal testing only. User should leave it open.
Test pins for OriseTech internal testing only. Internal pull low. User should
TEST_S[0:2]
T
COMPASS_L[0:1]
S
Internal left pass line for COM signal between input and output pins
COMPASS_R[0:1]
S
Internal right pass line for COM signal between input and output pins
leave it open or connect it to “low”.
Classification of TYPE:
I: input, O: output, I/O: input/output, P: power input, PO: power out, D: dummy, S: short pin, T: test pin, M: mark, C: capacitor pin
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OTA5180A
6. POWER APPLICATION CIRCUIT
Reg.
PVDD
VDD_18V
PUMP1
V1
V2
V3
Reg.
V4
VDD2
VDDA
C5
C6
PUMP2
V9
PUMP3
V10 VCL
V7
V8
VGH
VCOM
V9
V10 VGL
VCOMH
VCOML
C13
C14
VDD
C1
C2
C3
C4
C7
C8
C9
C10
C11
C12
C2
Recommended
Value
1uF
C9,C11
1uF
>16V
C3,C4,C7
2.2uF
>6V
C10,C12
2.2uF
>16V
C5,C6,C8,C13,C14
4.7uF
>10V
Component
Voltage Proof
>10V
Remarks:
1. PVDD is connected to VDD externally
2. VDD2 is pumped from VDD by charge pump1:
When VDD=2.5V, PWR_SEL=L, VDD2=3x VDD
When VDD=3.3V, PWR_SEL=H, VDD2=2x VDD
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7. REGISTER BANK
7.1 The executing time of Registers
Registers are not executed immediately after accepting a command through serial interface.
It executes at the frame following that where command was set.
DOTCLK
HSYNC
Command input in above interval is executed at the next line
Command execution
Command execution
Serial Control Timing Chart
SCL
1
SDA
2
A6 A5
R /W
CS
3
4
5
6
A4 A3 A2
7
8
9
10
11
A1 A0 D7 D6 D5
Address/Command Byte
12
13
D4 D3
14
15
16
D2 D1 D0
I/O Data Byte
a. Each serial command consists of 16 bits of data which is loaded one bit a time at the rising edge of serial clock SCL.
b. Command loading operation starts from the falling edge of CS and is completed at the next rising edge of CS.
c. The serial control block is operational after power on reset, but commands are established by the VSYNC signal. If command is transferred
multiple times for the same register, the last command before the VSYNC signal is valid.
d. If less than 16 bits of SCL are input while CS is low, the transferred data is ignored.
e. If 16 bits or more of SCL are input while CS is low, the previous 16 bits of transferred data before the rising edge of CS pulse are valid data.
f. Serial block operates with the SCL clock
g. Serial data can be accepted in the power save mode.
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OTA5180A
R / W : Establishes the read mode when set to ‘1’, and the write mode when set to ‘0’.
Read M ode:
W riting to address register
& Setting of SDA pin in output m ode
Setting of SDA pin in input m ode
Setting of
Reset shift register and counter
Read Data
R / W bit
Close SDA pin
SCL
SD A
1
2
3
4
5
6
7
8
9
10
11
12
R /W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4 D3
13
14
15
16
1
2
D2
D1
D0
R /W
A6
3
A5 A4
CS
W rite M ode:
W riting to address register
Setting of SDA pin in input m ode
Setting of
Reset shift register and counter
W rite Data
R / W bit
SCL
1
R /W
SD A
2
3
A6
A5
4
5
6
7
A4
A3
A2
A1
8
A0
9
D7
10
11
D6
D5
12
13
D4 D3
14
15
16
1
2
3
D2
D1
D0
R /W
A6
A5
A4
CS
7.2 Serial Control Timing Chart
tWH1
50%
SCL
ts1
SDA
tWL1
50%
th1
S0
S1
S15
ts0
CS
th0
50%
50%
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OTA5180A
Symbol
Min.
CS input setup time
Item
ts0
50
Typ.
Max.
Unit
ns
Serial data input setup time
ts1
50
ns
CS input hold time
th0
50
ns
Serial data input hold time
th1
50
ns
SCL pulse high width
tWH1
50
ns
SCL pulse low width
tWL1
50
ns
CS pulse high width
tW2
400
ns
7.3 Register summary
Register Adress
Register
Register Data (Default)
R / W A6 A5 A4 A3 A2 A1 A0
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
0
X
VDIR(1) HDIR(1)
X
X
X
X
X
1
X
X
X
X
GRB(1)
SHDB2(1) SHDB1(0) DISP(0)
0
CONTRAST(40h)
1
X
SUB-CONTRAST_R(40h)
0
X
SUB-CONTRAST_B(40h)
1
BRIGHTNESS(40h)
0
X
SUB-BRIGHTNESS_R(40h)
1
X
SUB-BRIGHTNESS_B(40h)
0
HSYNC_BLANKING(2Bh)
1 VDPOL(1) HDPOL(1)
VSYNC BLANKING(0Ch)
0 SYNC(0) DCLKpol
CP3_FREQ(10)
CP2_FREQ(10)
CP1_FREQ(10)
1 LED_CURRENT(00)
BL_DRV(00)
DRV_FERQ(00)
PFM_DUTY(10)
0
LED_ON_CYCLE(0111)
LED_ON_RATIO(1111)
1
X
OP(1XX)
X
X
X
X
0
X
X
X
X
LC_TYPE(00)
X
X
1
X
X
VGH_SEL(1XX)
VGL_SEL(1XX)
0
X
X
X
INVERSION(1)
X
X
X
1
X
VCOMH(4Dh)
0
X
VCOML(1Bh)
X: reversed, please set to '0'
Note:
1. When GRB is low, all registers reset to default values
2. Serial commands are executed at next VSYNC signal
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7.4 Register description
7.4.1
R0: Direction setting
Address
Bit
00000000
[6:5]
Description
B6(VDIR)
Vertical shift direction setting
B5(HDIR)
Horizontal shift direction setting
B6
0
Default
0_1100110b
Function(VDIR)
Shift from down to up, Last line =
G1<G2<-…<G543<G544 = First line
U2D = 0, D2U = 1
1
Shift from up to down, First line =
G1->G2->…->G543->G544 = Last line (Default)
U2D = 1, D2U = 0
B5
0
Function(HDIR)
Shift from right to left, Last data =
S1<S2<-…<S719<S720 = First data
1
Shift from left to right, First data =
S1->S2->…->S719->S720 = Last data (Default)
7.4.2
R1: GRB、SHDB2、SHDB1、DISP
Address
Bit
00000001
[6:0]
Description
B3(GRB)
Register reset setting
B2(SHDB2)
Charge pump shutdown setting
B1(SHDB1)
DC-DC converter shutdown setting
B0(DISP)
Display control / standby mode setting
B3
0
1
Normal operation (Default)
B2
Function(SHDB2)
0
Charge pump is off
1
Charge pump is controlled by DISP and power on/off
sequence (Default)
B1
Function(SHDB1)
0
DC-DC converter is off (Default)
1
DC-DC converter is controlled by DISP and power
on/off sequence
0
0_1001100b
Function(GRB)
Reset all registers to default value
B0
Default
Function(DISP)
Standby mode (Display OFF). Timing control, driver,
and DC/DC converter are off and all output are
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High-Z.. (Default)
1
7.4.3
Normal operation (Display ON)
R2: CONSTRAST
Address
Bit
00000010
[7:0]
Description
RGB contrast level setting, the gain changes (1/64) / bit
B7-B0
Contrast Gain
00h
0
40h
1(default)
FFh
3.984
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Default
01000000b
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OTA5180A
7.4.4
R3: SUB-CONTRAST_R
Address
Bit
00000011
[6:0]
7.4.5
B6-B0
Sub-Contrast_R Gain
00h
0.75
40h
1(default)
7Fh
1.246
Bit
00000100
[6:0]
Description
B sub-contrast level setting, the gain changes (1/256) / bit
B6-B0
Sub-Contrast_B Gain
00h
0.75
40h
1(default)
7Fh
1.246
Default
0_1000000b
R5: BRIGHTNESS
Address
Bit
00000101
[7:0]
Description
RGB bright level setting, setting accuracy : 1 step / bit
B7-B0
7.4.7
Default
0_1000000b
R4: SUB-CONTRAST_B
Address
7.4.6
Description
R sub-contrast level setting, the gain changes (1/256) / bit
Default
01000000b
Brightness Setting
00h
Dark (-64)
40h
Center (0)(Default)
FFh
Bright (+191)
R6: SUB- BRIGHTNESS _R
Address
Bit
00000110
[6:0]
Description
R sub-brightness level setting, setting accuracy : 1 step / bit
B6-B0
Dark (-64)
40h
Center (0)(Default)
7Fh
Bright (+63)
Proprietary & Confidential
0_1000000b
Sub-Contrast_R Gain
00h
© Orise Technology Co., Ltd.
Default
15
APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
7.4.8
R7: SUB- BRIGHTNESS _B
Address
Bit
00000111
[6:0]
Description
B sub-brightness level setting, setting accuracy : 1 step / bit
B6-B0
Sub-Contrast_B Gain
00h
Dark (-64)
40h
Center (0)(Default)
7Fh
Bright (+63)
7.4.9
Default
0_1000000b
R8: HSYNC BLANKING
Address
Bit
00001000
[7:0]
Description
Horizontal blanking setting
B7-B0
HBLK(Unit: DCLK)
00h
0
2Bh
43(default)
FFh
255
Default
00101011b
1 H tH
HSYNC width thsw
HSYNC
H back porch thbp
DCLK
H blanking thb
H display thd
H front porch thfp
R [7:0]
G [7:0]
B [7:0]
7.4.10
R9: HSYNC BLANKING
Address
Bit
00001001
[7:0]
B7
Description
B7(VDPOL)
VSYNC polarity selection
B6(HDPOL)
HSYNC polarity selection
B5-B0(VYSNC_BLANKING)
Vertical blanking setting
Default
11001100b
Function(VDPOL)
0
Positive polarity
1
Negative polarity (Default)
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APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
B6
Function(HDPOL)
0
Positive polarity
1
Negative polarity (Default)
B5-B0
VSYNC BLANKING (Unit: H)
00h
0
0Ch
12(default)
3Fh
63
VSYNC
HSYNC
DATA
VSYNC width t vsw V back porch t vbp
V blanking t vb
Valid
ValidData
Data
V display
t vd
V front porch t vfp
1 frame
7.4.11
R10: SYNC、DCLKPOL、CP3_FREQ、CP2_FREQ、CP1_FREQ
Address
Bit
00001010
[7:0]
Description
B7(SYNC)
SYNC and SYNC-DE mode selection
B6(DCLKPOL)
DCLK polarity selection
B5-B4(PUMP3 Frequency)
Charge Pump3 Frequency Setting
B3-B2(PUMP2 Frequency)
Charge Pump2 Frequency Setting
B1-B0(PUMP1 Frequency)
Charge Pump1 Frequency Setting
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Default
01xx1010b
APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
B7
Function(SYNC)
0
SYNC-DE Mode(Default)
1
SYNC Mode
B6
Function(DCLKPOL)
0
Positive polarity
1
Negative polarity (Default)
Note: When the command is sent to ASIC, it will be executed immediately.
• HDPOL=1, VDPOL=1, CLKPOL=1
VSYNC
HSYNC
DCLK
DATA
D1 D2 D3 D4
• HDPOL=0, VDPOL=0, CLKPOL=0
VSYNC
HSYNC
DCLK
D1 D2 D3 D4
DATA
The Relationship of HDPOL/VDPOL/CLKPOL
CP1,2,3_FREQ
Function(Charge Pump Frequency)
0
0
1/2*HSYNC Freq.
0
1
1*HSYNC Freq.
1
0
2*HSYNC Freq.
1
1
4*HSYNC Freq.
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APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
7.4.12
R11: LED_CURRENT、BL_DRV、DRV_FREQ、PFM_DUTY
Address
Bit
00001011
[7:0]
Description
B7-B6(LED_CURRENT)
Adjust LED current
B5-B4(BL_DRV)
Backlight driving capability setting
B3-B2(DRV_FREQ)
DRV signal frequency setting
B1-B0(PFM_DUTY)
PFM duty cycle selection for back light power converter
Default
00000010b
DC2DC Feedback Voltage(V)
B7
B6
Function(LED_CURRENT)
0
0
0.6 V (default, 20mA)
0
1
0.75V (25mA)
1
0
0.45V (15mA)
1
1
0.3V (10mA)
B5
B4
Function(BL_DRV)
0
0
Normal capability (Default)
0
1
4 times the Normal capability
1
0
8 times the Normal capability
1
1
12 times the Normal capability
B3
B2
Function(DRV_FREQ)
0
0
DCLK / 32 (Default)
0
1
DCLK / 64
1
0
DCLK / 128
1
1
DCLK / 256
B3
B2
Function(PFM_DUTY)
NOTE
0
0
50 %
16/32
0
1
60 %
19/32
1
0
65 % (Default)
21/32
1
1
70 %
22/32
7.4.13
R12: LED_ON_CYCLE、LED_ON_RATIO
Address
Bit
00001001
[7:0]
Description
B7-B4 (LED_ON_CYCLE)
Default
Set the cycle of enable signal , and we can use it to adjust
01111111b
brightness of the LEDs.
B3-B0 (LED_ON_RATIO)
Set the active ratio of enable signal, and we can use it to adjust
brightness of the LEDs
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APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
B7
B6
B5
B4
Function (LED_ON_CYCLE)
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
6
1
0
1
0
1
1
0
7
0
1
1
1
8 (Default)
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
15
1
1
1
1
16
B3
B2
B1
B0
Function (LED_ON_RATIO)
0
0
0
0
1/16
0
0
0
1
2/16
0
0
1
0
3/16
0
0
1
1
4/16
0
1
0
0
5/16
0
1
0
1
6/16
0
1
1
0
7/16
0
1
1
1
8/16
1
0
0
0
9/16
1
0
0
1
10/16
1
0
1
0
11/16
1
0
1
1
12/16
1
1
0
0
13/16
1
1
0
1
14/16
1
1
1
0
15/16
1
1
1
16/16(Default)
1
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Preliminary Version: 0.2
Preliminary
OTA5180A
7.4.14
R13: OP
Address
Bit
00001011
[6:4]
Description
B6-B4(OP)
Source output driving capability selection
Default
0_1001100b
DAC output driving capacity
Function( OP )
B6
B5
B4
0
0
0
-25%
0
0
1
Normal (satisfy output settling time 2.6us)
0
1
0
+25% (satisfy output settling time 2.2us)
0
1
1
+50%
0
Controlled by input pin OP0, OP1 (Default)
1
0
7.4.15
R14: LC_TYPE
Address
Bit
00100000
[6:0]
Description
B3-B2(LC_TYPE)
LC type selection
10010000b
Function(LC_TYPE)
B3
B2
0
0
Setting by input pins TN_TYPE and MVA_TN (Default)
0
1
TN_Mode1 and Lower VCOM Power
1
0
MVA and Higher VCOM Power
1
1
TN_Mode2 and Higher VCOM Power
7.4.16
Default
R15:VGH_SEL、VGL_SEL
Address
Bit
00001111
[5:0]
Description
B5-B3(VGH_SEL)
VGH_SEL : VGH voltage Selection
B2-B0(VGL_SEL)
VGL voltage Selection
Default
011b
Unit: V
B5
B4
B3
Function( VGH_SEL )
0
0
0
|VGL|+2
0
0
1
|VGL|+3
0
1
0
|VGL|+4
0
1
1
|VGL|+5 (Default)
1
X
X
Auto Select by LC_TYPE
Unit: V
B2
B1
B0
Function( VGL_SEL )
0
0
0
-7
0
0
1
-8
0
1
0
-9
0
1
1
-10 (Default)
1
X
X
Auto Select by LC_TYPE
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Preliminary Version: 0.2
Preliminary
OTA5180A
7.4.17
R16: INVERSION
Address
Bit
01001111
[3]
Description
B3 (INVERSION)
B3
Line/Frame inversion control bit
Default
0_0000111b
Function (INVERSION)
0
Frame inversion
1
Line inversion (Default)
7.4.18
R17: VCOMH
Address
Bit
00010001
[6:0]
Description
B6-B0(VCOMH)
B6-B0
VCOMH level(Unit: V)
00h
2.46
1Bh
3
4Dh
4(default)
7Fh
5
7.4.19
VCOMH level adjustment
Default
1001101b
R18: VCOML
Address
Bit
00010010
[6:0]
Description
B6-B0(VCOML)
B6-B0
VCOML level(Unit: V)
00h
-0.46
1Bh
-1(default)
4Dh
-2
7Fh
-3
© Orise Technology Co., Ltd.
Proprietary & Confidential
VCOMH level adjustment
22
Default
0011011b
APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
8. ELECTRICAL SPECIFICATIONS
8.1 Absolute Maximum Ratings
Rating
Symbol
Digital supply voltage
Value
VDDIO
Unit
-0.3
to
+4.5
V
Power Supply for Pump
VDD
-0.3
to
+4.5
V
Analog supply voltage
VDD2
-0.3
to
+7.0
V
TSTG
-55
to
100
℃
TA
-30
to
85
Storage temperature
Operating temperature
℃
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
For normal operational
conditions see AC/DC Electrical Characteristics.
8.2 DC Characteristics (VDDIO=1.8V, VDD = 3.0V, AVDD = 5.5V, AGND = 0V, TA = -20℃ to 80℃)
8.2.1
For digital circuit
Item
Symbol
Min.
Typ.
Max.
Unit
VDDIO
1.65
1.8
VDD
V
VDD
3
3.3
3.6
V
PWR_SEL=H
PWR_SEL=L
Digital Supply Voltage
Power Supply for Pump
Conditions
VDD
2.25
2.5
3
V
Input Leakage Current
IL
-1.0
-
1.0
uA
Pull High/Low Resistor
RP
-
940K
-
ohm
Digital Stand-by current
IDST
-
5.0
20
uA
DCLK stopped, Output Hi-Z
Digital operation current
ICC
-
4
-
mA
DCLK = 9MHz
8.2.2
For analog circuit
Item
Symbol
Analog Supply Voltage
VDD2
VCOM Supply Voltage
FRP
Output Voltage Deviation
VOD
Min.
Typ.
Max.
6
-3
Unit
Conditions
V
-
5
V
mV
-
±20
±35
-
±15
±20
VO = 0.15V ~ 0.5V, 3.45V~3.8V
VO = 0.5V ~ 3.45V
0.2
-
3.8
MVA / TN4.5 Mode
Output Dynamic Range
VDR
Analog Operation Current
IDD
-
5.0
-
mA
Analog Standby Current
IAST
-
-
20
uA
Feed Back Voltage
VFB
0.57
0.6
0.63
V
Setting by Register (Default)
0.71
0.75
0.79
V
Setting by Register
0.43
0.45
0.47
V
Setting by Register
0.28
0.30
0.32
V
Setting by Register
0.15
3.15
TN3.2 Mode
Without panel loading
DRV Output Voltage
VDRV
0
-
VDD
V
DRV Drive Current
IDRV
-
-
20
mA
VDD = 3.0V, FB = 0.60V (Default)
-
-
25
mA
VDD = 3.0V, FB = 0.75V
© Orise Technology Co., Ltd.
Proprietary & Confidential
-
-
15
mA
VDD = 3.0V, FB = 0.45V
-
-
10
mA
VDD = 3.0V, FB = 0.30V
23
APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
8.3 Output Signal Characteristics
8.3.1
Output Voltage
Item
Symbol
Applicable pins
VGH
Output voltage 1
Conditions
Min.
Typ.
Max.
Unit
MVA
VGH
TN1
15
V
-10
V
TN2
MVA
Output voltage 2
VGL
VGL
TN1
TN2
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Preliminary Version: 0.2
Preliminary
OTA5180A
8.4 INPUT TIMING
8.4.1
480XRGBX272 Vertical Timing
Item
Min.
Typ.
V display tVD
272
V blanking tVB
12
V front porch tVFP
3
VSYNC width tVSW
10
1 frame
287
Max.
Unit
H
NOTE: tVB is programmable
VSYNC
HSYNC
DATA
V a lid D a ta
VSYNC width tvsw V back porch t
vbp
V front porch tvfp
V display tvd
V blanking tvb
1 frame
8.4.2
480XRGBX272 Horizontal Timing
640x240 mode
Min
Min
H display thd
480
1 H tH
576
H blanking thb (*)
88
H front porch thfp
8
HSYNC width thsw
41
Frequency
9.0
Max
UNIT
DCLK
MHz
NOTE: thb is programmable
1 H tH = 525 DCLK
HSYNC width thsw
HSYNC
H back porch thbp
DCLK
H blanking thb
(L1~L272)
H display thd = 480 DCLK
R [7:0]
R1
R2
R3
R4
R5
R476 R477 R478 R479 R480
G [7:0]
G1
G2
G3
G4
G5
G476 G477 G478 G479 G480
B [7:0]
B1
B2
B3
B4
B5
B476 B477 B478 B479 B480
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H front porch thfp
APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
8.5 SYNC-DE Mode
VSYNC
HSYNC
DE
INPUT
DATA
first
line
last
line
VSYNC
Blanking Time
Active Area
HSYNC
DE
DCLK
R[7:0]
G[7:0]
B[7:0]
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APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
9. OUTPUT TIMING
TBD
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APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
10. POWER ON/OFF SEQUENCE
The power sequence is shown in fig. power sequence.
1
1
1
2Frame
1
2 frame 2 frame
VDDIO,
VDD
VDDIO
VDD
VSYNC
VSYNC
DISP
(Pin/Register)
DISP
(Pin/Register)
VDD2
VDD2
VGH
VGH
VGL
VGL
VST,VCK
VST,VCK
VLED
VLED
DAC,FRP
Output=0V
White/
Black
Normal
Output=0V
DAC,FRP
Fig. Power Sequence
Note:
a. When MVA mode (Normally black LC) is applied, it needs to send black pattern to discharge the pixel.
b. When TN_MODE2 or TN_MODE1 mode (Normally white LC) is applied, it needs to send white pattern to discharge the
pixel.
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Preliminary Version: 0.2
Preliminary
OTA5180A
11. APPLICATION CIRCUIT for DC-DC Converter
The PWM controller provides high efficient boost power
the number of external components.
supply circuit control that generates the power of LED back
reference voltage with
A precision 0.6V
±0.01V Hysteresis is included.
light and Level Shift. The boost converter uses a Power
transistor to provide maximum efficiency and to minimize
VDD
OTA5180A
L100
C101
33uH
10uF
D100
SB07-03C
VLED
R101
DRV
4.7K
C103
Q100
FMMT618
LED1
10uF
PFM
Controller
FB
_
Pixel CLK
1nF
LED2
Vref
VDD
3.0V
C102
+
0.60V (Default)
(0.75V)
(0.45V)
(0.30V)
LED3
FB
LED1
LED2
LED3
R102
30
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APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
12. CHIP INFORMATION
12.1 PAD Assignment
Note: Dimension includes scribe line
12.2 PAD Dimension
Item
Size
PAD No.
Chip Size
-
Chip thickness
Pad pitch
Pad size
Unit
X
Y
20200
750
-
300 ± 25
Input Pads
59
-
Output Pads
15
-
Input Pads
35
100
Output Pads
15
100
µm
Note: Chip size includes scribe line.
12.3 Bump Characteristic
Item
Standard
Note
Bump Hardness
75HV
± 25HV
Bump Height
15µm
± 3µm
Co-planarity (in Chip)
R≦ 2µm
R : Max-Min
Roughness (in Bump)
R≦ 2µm
R : Max-Min
Bump Size
“X” ± 3µm x “Y” ± 3µm
X/Y: bump size
Shear Force
>4.5g/mil^2
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APR. 01, 2008
Preliminary Version: 0.2
Preliminary
OTA5180A
12.4 Pad Locations
TBD
12.5 Align Key Locations
--Alignment Mark coordinate
Left (-9963,-245)
Right (9963,-245)
--Alignment Mark size
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Preliminary Version: 0.2
Preliminary
OTA5180A
13. COG PRODUCTS MANUFACTURING GUIDELINES
13.1
Purpose:
The purpose of this specification is to identify ACF bonding process, so that customers can use properly ACF and Chip during the
assembly.
13.2
Scope:
ACF bonding
13.3
process
Noun definition
13.3.1 COG: Chip on Glass
13.3.2 ACF (Anisotropic Cunductive Film): .ACF is a functional adhesive tape which is able to connect
(conductivity, adhesion, insulation) multiterminals in one time.
13.3.3 CTE: Coefficient of thermal expansion
13.4
Responsibility unity:
ORISETECH Quality Assurance unity
13.5
Contents:
13.5.1 Applicable documents
IPC-SM-782: Surface Mount Design & Land Pattern Standard
IPC-7351Generic Requirements for Surface Mount Design and Land Pattern Standard.
IPC JEDEC: J-STD-033A Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices
JESD22-B111: Board Level Drop Test of Components for Handheld Electronic Products
IPC-A-610: Acceptability of Electronic Assemblies
13.5.2 ACF Characteristics:
Three factors to achieve the connection: Temperature, Pressure, Time.
13.5.3 ACF process :
To use Low Temperature and Low stress ACF is recommended for thin chip as 300 um.
Warp issues may happen if customers do not use Low Temperature and Low stress ACF for long chip .And
warp issues may induce chip broken after ACF bonding for the CTE mismatch of Glass and ACF and Chip.
To use 3um ACF is recommended for BUMP space is less than 13um.
To use Low temperature and long time bonding is recommended if delamination happens in edge of chip.
For fine pitch and thin chip (300 um) products, customer should review
ACF bonding condition with ACF maker.
13.6
References:
*IPC:
http://www.ipc.org
*HDPUG (High Density Package Users Group)
http://www.hdpug.org
*JEDEC (Joint Electronic Device Engineering Council)
http://www.jedec.org
*JEITA (Japan Electronic Industry Association)
http://www.jeita.org
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Preliminary
OTA5180A
14. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by ORISE Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only.
ORISE Technology makes no warranty, express, statutory implied or by description regarding the information in this publication
or regarding the freedom of the described chip(s) from patent infringement.
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
alter the specifications and prices at any time without notice.
Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders.
applications.
FURTHERMORE, ORISE Technology MAKES NO
ORISE Technology reserves the right to halt production or
Products described herein are intended for use in normal commercial
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by ORISE Technology for such applications.
Please note that
application circuits illustrated in this document are for reference purposes only.
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Preliminary Version: 0.2
Preliminary
OTA5180A
15. REVISION HISTORY
Date
Revision #
Description
1. Change default setting of SYNC pin and “SYNC” function register
APR. 01, 2008
MAR. 31, 2008
0.2
0.1
© Orise Technology Co., Ltd.
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Page
6, 12, 18
2. Update section 6
9
3. Update section 12.2 and 12.3.
30
4. Update section 12.5
31
5. Add COG PRODUCTS MANUFACTURING GUIDELINES.
32
Original
33
34
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