PBGA Plastic Ball Grid Array HIGHLIGHTS • Strip molded, cost effective, high I/O package solution • Wide range of tooled up body sizes for minimum cost of entry • Available in Pb-free and eutectic versions FEATURES • Full in-house package and substrate design capability • Full in-house electrical, thermal and mechanical simulation and measurement capability • Multiple metal layer options for signal, power and ground planes for improved electrical performance • Wide range of custom and open tool designs available • Flexible body sizes ranging from 15 x 15mm to 40 x 40mm • 0.65, 0.80, 1.00, 1.27 and 1.50mm ball pitch with greater than 1000 I/O available • Perimeter or full ball array • Pb-free and green material set options • Multiple chip design and optional passive/discrete components available (SiP) • JEDEC standard compliant APPLICATIONS • ASIC • DSPs and Memory • Gate Array • Microprocessors/Controllers/Graphics • PC Chipsets • Other advanced applications requiring enhanced thermal and electrical performance CROSS-SECTION www.statschippac.com DESCRIPTION BGA technology was first introduced as a solution for the increasingly high lead counts required for advanced semiconductors used in applications such as portable computers and wireless telecommunications. As the number of leads surrounding the ICs increased, high lead count packages experienced significant electrical shorting problems. BGA technology solves this problem by effectively creating leads on the bottom surface of the package in the form of small bumps or solder balls. BGA packages can be used for high performance applications with high I/O connections and high thermal and electrical requirements. The characteristics of BGA packages make them suitable for a wide variety of devices used in computing platforms, networking, hand-held consumer products, wireless communications devices, video cameras, home electronic devices and game consoles. STATS ChipPAC offers a range of BGA packages including the PBGA package family. The Plastic Ball Grid Array (PBGA) package is one of the most popular packages for high I/O devices in the industry today. PBGA utilizes laminate substrates, and is available over a variety of standard JEDEC body sizes and ball counts to meet a wide range of customer requirements. This package provides a cost-effective advanced packaging solution, offering higher density over traditional leadframe packages. STATS ChipPAC’s advanced design and simulation capabilities enable package optimizations needed for maximum electrical and thermal performance. STATS ChipPAC combines state of the art processing and equipment with proven material sets to achieve enhanced yield, reliability, and performance. Green and lead-free material sets are available for all PBGA package types. PBGA Plastic Ball Grid Array SPECIFICATIONS Die Thickness Gold Wire Pd/Cu Wire Bond Pad Pitch Mold Cap Thickness Marking Packing Options RELIABILITY Moisture Sensitivity Level Temperature Cycling High Temperature Storage Pressure Cooker Test Liquid Thermal Shock 150-381µm (6-15mils) 15-30µm (0.6/0.7/0.8/0.9/1.0/1.1/1.2mils) diameter 15-30µm (0.6/0.7/0.8/1.0mils) diameter 45µm inline or 25/50µm staggered capable 0.7~1.17mm Laser JEDEC tray/tape and reel JEDEC Level 3 -65°C/150°C, 1000 cycles (typical) 150°C, 1000 hrs (typical) 121°C, 100%RH, 2 atm, 168 hrs (Condition B) -55°C/125°C, 1000 cycles THERMAL PERFORMANCE, θja (°C/W) Thermal performance is highly dependent on package size, die size, substrate layers and thickness, and solder ball configuration. Simulation for specific applications should be performed to obtain maximum accuracy. Package 27 x 27 27 x 27 27 x 27 35 x 35 Body Size (mm) 2L 4L 4L 4L Ball Count 256 256 272 388 Die Size (mm) 7.8 x 7.8 7.8 x 7.8 7.8 x 7.8 10.2 x 10.2 Thermal Performance θja(ºC/W) 29.8 22.4 20.2 15.9 Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-9) under natural convection as defined in JESD51-2. ELECTRICAL PERFORMANCE Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire. onductor C Length Component (mm) Wire 2 Net (2L) 2 - 7 Total (2L) Wire 2 Net (4L) 2 - 7 Total (4L) Resistance (mOhms) 120 34 - 119 154 - 239 1201.65 34 - 119 154 - 239 Inductance (nH) 1.65 1.3 - 4.55 2.95 - 6.2 0.45 - 0.85 0.9 - 3.15 2.55 - 4.80 Inductance Mutual (nH) 0.45 - 0.85 0.26 - 2.28 0.71 - 3.13 0.1 0.18 - 1.58 0.63 - 2.43 Capacitance (pF) 0.1 0.25 - 0.95 0.35 - 1.05 0.01 - 0.02 0.35 - 1.1 0.45 - 1.2 Capacitance Mutual (pF) 0.01 - 0.02 0.06 - 0.42 0.07 - 0.44 0.06 - 0.42 0.07 - 0.44 Note: Net = Total Trace Length + Via + Solder Ball. PACKAGE CONFIGURATIONS Body Size (mm) Ball Count 15 x 15 17 x 17 17.2 x 17.2 19 x 19 21 x 21 23 x 23 27 x 27 31 x 31 35 x 35 37.5 x 37.5 40 x 40 Corporate Office Global Offices 160, 176, 196 192, 196, 208, 217, 252, 256 512 272, 289, 292, 296, 297, 300, 301, 305, 324, 376 400, 456, 484 169, 192, 208, 217, 233, 241, 288, 301, 304, 305, 318, 320, 324, 338, 340, 348, 352, 360, 376, 385, 388, 420, 456, 480, 484, 492 225, 256, 272, 277, 292, 300, 312, 316, 320, 324, 336, 352, 384, 388, 400, 416, 456, 472, 480, 484, 496, 508, 512, 544, 580, 585, 636, 650, 676 304, 320, 353, 385, 421, 433, 434, 448, 458, 460, 480, 540, 556, 560, 564, 604, 608, 609, 640, 644, 652, 676, 688, 692, 701, 721, 772, 896 304, 312, 313, 340, 352, 385, 388, 400, 420, 426, 432, 448, 452, 454, 456, 458, 474, 480, 484, 492, 496, 512, 516, 532, 542, 544, 548, 556, 564, 573, 580, 611, 624, 640, 648, 661, 665, 676, 680, 688, 700, 716, 729, 736, 740, 748, 756, 792, 816, 824, 840, 867, 868, 1012, 1156 435, 480, 552, 600, 601, 625, 627, 685, 701, 785, 788, 804, 840, 841 503, 557, 569, 596, 600, 745, 776, 928, 961, 1253 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-31-639-8915 TAIWAN 886-3-593-6565 SWITZERLAND 41-21-8047-200 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2014. STATS ChipPAC Ltd. All rights reserved. December 2014