Shrinking Silicon Feature Sizes Consequences for Reliability Hugh de Lacy - Technical Manager Alun Jones – Technical Director Micross Components Ltd., www.micross.com Given at CMSE, Portsmouth 2008 1 The Incredible Shrinking Die 2 Effects of Size Reduction • Increasing Parameter Variability • Wear-out Mechanisms – parameter degradation – catastrophic • Increased Susceptibility to Radiation – catastrophic – hard / recoverable – soft errors 3 Parameter Variability Static M ean Num ber of Dopant A to ms 10000 1000 100 10 1000 500 250 130 65 32 Technology Node (nm) Random Dopant Fluctuations Source: Intel 4 Parameter Variability Static 1 Lithography Wavelength 365nm 248nm micron 0.1 1000 Source: Mark Bohr, Intel 193nm nm 180nm 130nm 100 90nm Gap 65nm 45nm Generation 32nm 13nm EUV 0.01 1980 10 1990 2000 2010 2020 Sub-wavelength Lithography Source: Intel 5 Parameter Variability Dynamic 200 150 100 50 Heat Flux (W/cm2) 250 0 Heat Flux (W/cm2)—Vcc variation Source: Intel 6 Parameter Variability Mitigation • Maximise symmetry of layout – distribute power dissipating elements – include dummy features • Advanced lithography techniques – pattern compensation at design stage – alternating phase shift masks • Self compensating system design – feedback loops to optimise supply voltage, clock speed 7 Parameter Variability Layout Symmetry Source: Intel Dummy features reduce leakage Source: Chip Forensics 8 Parameter Variability Advanced Lithography Source: Intel Design Compensation Source: ASM Alternating Phase Shift Mask 9 Parameter Variability Self Compensation • Use of error correction techniques – established for memory components – now being adopted for logic devices • Some techniques apply feedback to adjust supply voltage and clock speed to minimise errors 10 Wear--Out Mechanisms Wear • Supply voltages progressively reduced but reduction doesn’t fully scale with dimensions • Electromigration of metals – Parameter degradation and catastrophic • Hot carrier effects – Parameter degradation • Time dependent dielectric breakdown – Catastrophic 11 Electromigration • Caused by transfer of electron momentum to metal lattice • Use of Cu has reduced electromigration by x10 but wire density greatly increased (5-7 layers common) • Avoidable with correct design rules Void caused by electromigration Source: JEDEC 12 Hot Carrier Effects • Carriers accelerated by high field in MOSFET drain region • Some carriers penetrate gate oxide and are trapped • Changes Vth and gm, increases gate leakage • Carriers that are not trapped contribute to gate leakage or substrate current • Worst at low temp (activation energy –0.1 to –0.2eV) 13 Time dependent dielectric breakdown (TDDB) • Breakdown of MOSFET gate insulation • Two different effects – Field-enhanced thermal bond breakage of SiO2/Si bonds, occurs at lower field strengths – Tunnelling current through dielectric causes impact ionisation damage, worse at higher fields • Recent adoption of high-k dielectrics has improved situation 14 TDDB Gate Oxide Thickness Trend (SiOn) Source: Intel 15 TDDB Intel High K Dielectric Source: Intel 16 Radiation Effects • Ionising radiation occurs from several natural sources • The most important for ground-based electronics are: – Cosmic rays, mainly neutrons – Alpha particles from packaging materials • Effects can be transient or catastrophic 17 Radiation Effects Terminology • SEE – single event effects – Transient effects caused by random individual particle interactions • SEU – single event upset – Transient which causes one-off effect that may corrupt data but does not halt operation of device or cause long term damage (soft error) • SEL – single event latch-up – Transient that causes latch-up that halts operation of device until power is removed. May cause destruction of device if excessive currents flow 18 Radiation Effects Cosmic Rays Characteristics of cosmic neutron flux Source: Cypress 19 Radiation Effects Cosmic Rays High energy neutron Elastic collision: no electrical effect Silicon nucleus recoil (~2µm) (~2 Source: TI 20 Radiation Effects Cosmic Rays Inelastic collision: charged particles created Source: TI 21 Radiation Effects Cosmic Rays Source: Actel 22 Radiation Effects Alpha Particles • Derive from trace radioactive elements in package materials – Sources include: Ceramic package materials, aluminum IC interconnect, and lead in solder bump material. – Ceramic package contamination due to uranium and thorium impurities in package material and lid attach glass. – Aluminium contamination due to uranium and thorium impurities in aluminium ore. – Lead contamination due to uranium and thorium impurities in lead ore including the radioactive lead decay products 210Pb and 212Pb 23 Radiation Effects Alpha Particles Typical Alpha Flux in IC Materials (α/cm2-hr) Processed wafers Copper interconnect metal Aluminum interconnect metal Mold compound Underfill Lead solder bumps Ceramic package 0.0009 0.0019 0.0014 0.024 - <0.002 0.002 - 0.0009 7.2 - <0.002 0.0011 24 Radiation Effects Device Sensitivity • Error rate = F x A x exp(-Qcrit/Qs) F: neutron flux, A: area, Qcrit: min charge to produce soft error, Qs: charge collection efficiency of device • Sensitivity tends to increase linearly with decreasing feature size • SRAM most sensitive (<5fC for 45nm 6 transistor SRAM cell with 1µm2 area) – Error correction used in µP cache memory • DRAM: depends on size of capacitor – 3D structures have increased capacitance • Random logic becoming more sensitive as geometries reduce and architectures change 25 Radiation Effects SRAM Sensitivity Trends Source: TI BPSG: borophosphosilicate glass 26 Radiation Effects DRAM Sensitivity Trends Source: TI 27 Radiation Effects Logic Sensitivity • Combinational logic: effects of masking – Logical masking occurs when a particle strikes a portion of the combinational logic that is blocked from affecting the output due to a subsequent gate whose result is completely determined by its other input values. – Electrical masking occurs when the pulse resulting from a particle strike is attenuated by subsequent logic gates due to the electrical properties of the gates to the point that it does not affect the result of the circuit. – Latching-window masking occurs when the pulse resulting from a particle strike reaches a latch, but outside the clock transition where the latch captures its input value 28 Radiation Effects Logic Sensitivity Source: Univ Texas / IBM Error rate = F x A x exp(-Qcrit/Qs) 29 Size Reduction Effects on Reliability • Other things being equal, reducing size tends to reduce reliability, but: – Authoritative data lacking, some data conflicting – Depends on design rules – Can be greatly influenced by system design – Newer process technologies mitigate worst effects 30 Reliability Published Data FIT Rates at 85° 85°C vs Feature Size 1000 100 FITs Actel Altera ADI Xilinx 10 1 0.5 0.35 0.22 0.18 0.15 0.13 0.09 0.065 Fe ature Size µm 31 Reliability Recommendations for Specifiers • Standard devices – Obtain reliability data from manufacturers (including typical failure modes) – Use older generation parts where practicable – Design tolerance and redundancy into system • Custom devices – – – – – Obtain reliability data Use conservative design rules Design in error correction if practicable Comprehensive testing Rigorous qualification procedures 32