Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CYBUS3384 Dual 5-Bit Bus Switch SCDS103 - May 1994 - Revised February 2000 1CYBUS3L384SCDS Features • • • • • • • • • • Functional Description Zero propagation delay 2Ω switches connect inputs to outputs Direct bus connection when switches are ON High (>500 Meg Ω) resistance when switch is OFF Performs bidirectional translator function between 3.3V and 5.0V power supplies CMOS for low power dissipation Edge-rate control circuitry for significantly improved noise characteristics Inputs and outputs interface with 5.0V CMOS, TTL, or 3.3V CMOS ESD > 2000V Power-off disable The CYBUS3384 is a ten-bit, two-port bidirectional bus switch that allows one bus to be connected directly to, or isolated from, another without introducing additional propagation delay or ground noise. The input and output voltage levels allow direct interface with TTL and CMOS devices. Two bus enable signals, BE1 and BE2, turn on the upper and lower five bits, respectively. Designed with a low resistance of 2Ω, the CYBUS3384 is ideal for use in VME or other high DC drive applications. The power-off disable feature enables modules and cards to be either inserted or withdrawn from operating equipment without shutting down power. Additionally, the CYBUS3384 facilitates bidirectional interfacing between 3.3V and 5V systems by placing a single diode in series with the 5V VCC line and a resistor from pin 24 to ground. The CYBUS3384 is also suitable for small signal analog applications where crosstalk and off isolation performance of –66 dB at 50 MHz are required. Logic Block Diagram Pin Configurations BE1 SOIC/QSOP Top View BE2 A0 B0 A1 B1 A2 B2 A3 B3 B4 A4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 1 24 VCC B0 2 23 B9 A0 3 22 A9 A1 B1 4 21 A8 5 20 B8 B2 6 19 B7 A2 7 18 A7 A3 8 17 A6 B3 9 16 B6 B4 10 15 B5 A4 11 14 GND 12 13 A5 BE2 BUS3384-2 BUS3384-1 Function Table[1] Pin Description Name BE1 Inputs Description A Bus A, Inputs or Outputs BE1 B Bus B, Inputs or Outputs H H High-Z High-Z Non-connect Bus Switch Enable L H A0–4 High-Z Connect H L High-Z A5–9 Connect L L A0–4 A5–9 Connect BE1, BE2 BE2 B0–4 B5–9 Function Note: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Copyright © 2000, Texas Instruments Incorporated CYBUS3384 Maximum Ratings[2, 3] (Above which the useful life may be impaired. For user guidelines, not tested.) Power Dissipation .......................................................... 0.5W Storage Temperature .................................–65°C to +165°C Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied .............................................–65°C to +135°C Operating Range Ambient Temperature VCC –40°C to +85°C 4.0V to 5.5V Supply Voltage to Ground Potential ............... –0.5V to +7.0V Range DC Input Voltage............................................ –0.5V to +7.0V Commercial DC Output Voltage ......................................... –0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin).......120 mA Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ.[4] Max. 2.0 Unit VIH Input HIGH Voltage Control Inputs Only VIL Input LOW Voltage Control Inputs Only VH Hysteresis[5] Control Inputs Only 0.2 VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V RON Switch On Resistance[6] VCC=4.75V, VIN=0.0V, ION=30 mA 2 4 W VCC=4.75V, VIN=2.4V, ION=15 mA 4 8 W ±1 µA ±1 µA ±1 µA 0.8 IIN Input Leakage Current VCC=Max., VIN=VCC IOZ Off State Current (High-Z) VCC=Max., VOUT=0.5V IOFF Power-Off Disable VCC=0V, VOUT=4.5V, VIN=VCC IOS Output Short Circuit Current[7] V 0.001 VCC=Max., VOUT=0.0V V V 100 mA On Resistance vs. VIN @ 4.75 VCC 14.00 12.00 10.00 8.00 RONΩ 6.00 4.00 2.00 0.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 VIN, Volts Notes: 2. Unless otherwise noted, these limits are over the operating free-air temperature range. 3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 4. Typical values are at VCC=5.0V, TA=+25˚C ambient. 5. This parameter is specified but not tested. 6. Measured by voltage drop between A and B pin at indicated current through the switch. On resistance is determined by the lower of the voltages on pin A or pin B. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 2 CYBUS3384 Capacitance[6] Parameter Description Typ.[4] Max. Unit CIN Input Capacitance 3 4 pF COUT Output Capacitance 7 8 pF Power Supply Characteristics Parameter ICC Test Conditions[8] Description Quiescent Power Supply Current VCC=Max., VIN≤GND or VCC, f=0 Typ.[4] Max. Unit 3384 0.2 3.0 µA 3L384 0.2 3.0 µA ∆ICC Quiescent Power Supply Current (Input HIGH)[9] VCC=Max., VIN=3.4V, f=0, Per Control Input 2.0 mA ICCD Dynamic Power Supply Current[10] VCC=Max., Control Input Toggling, @ 50% Duty Cycle, A & B Pins Open 0.12 mA/ MHz IC Total Power Supply Current[11, 12] VCC=Max., Two Control Inputs Toggling, @ 50% Duty Cycle, f1=10 MHz, VIN=3.4V 3384 4.4 mA 3L384 4.4 mA Switching Characteristics Over the Operating Range[13] Commercial Parameter Description tPLH tPHL Propagation Delay A to B[14, 15] tPZH tPZL Switch Turn On Delay, BE1, BE2 to A, B[13] tPHZ tPHZ Switch Turn Off Delay, BE1, BE2 to A, B[13, 14] |Qci| Charge Injection, Typical[16, 17] Min. Max. Unit .25 ns 1.5 6.5 ns 1.5 5.5 ns 1.5 pC Notes: 8. For conditions shown as MIN or MAX use the appropriate values specified under DC specifications. 9. Per TTL driven input (VIN=3.4V); A and B pins do not contribute to ICC. All other inputs at VCC or GND. 10. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A and B inputs generate no significant AC or DC currents as they transition. This parameter is not tested but is specified by design. = IQUIESCENT + IINPUTS + IDYNAMIC 11. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 12. Note that activity on A or B inputs do not contribute to IC. The switches merely connect and pass through activity on these pins. 13. See Test Circuit and Waveform. Minimum limits are specified but not tested. 14. This parameter is specified by design but not tested. 15. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant for the switch is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 16. Measured at switch turn off, A to C, load=50 pF in parallel with 10 meg scope probe, VIN at A=0.0V. 17. Tested initially and after any design change which may affect this parameter. 3 CYBUS3384 Ordering Information CYBUS3384 Speed (ns) 0.25 Package Name Ordering Code CYBUS3384QCT Q13 24-Lead (150-Mil) QSOP CYBUS3384SOCT S13 24-Lead (300-Mil) Molded SOIC A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 Operating Range Package Type Commercial 5.0 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 VOUT, Volts BE1 1K ohm 10K ohm 10 meg 4.0 3.0 2.0 1.0 0 0 0.5 1.0 1.5 2.0 2.5 Figure 1. CYBUS3384 The CYBUS3384 is organized into two groups of five N-Channel MOSFETs. Each group has an independent control input for output enable (see Figure 1). Because the N-channel MOSFET is physically symmetric, the device pin can act as an input or an output. The two enable input (BE1 and BE2) sense TTL level signals and drive the gates of the N-channel MOSFETs to VCC. With the gate at VCC, the output voltage will follow the input voltage up to VCC minus the threshold voltage. At this point the N-channel MOSFET begins to turn off, rapidly increasing the effective resistance (RON) such that further increases to input voltage no longer increase the output voltage (see Figure 2). When either the input or output of the CYBUS3384 is near zero volts and the gate is at VCC, the device is fully on, (low resistance) and available to pass large currents in either direction. In this condition, the CYBUS3384 inputs are directly connected to the outputs. The CYBUS3384 provides no signal drive itself. As a result the rise and fall times of the CYBUS3384 outputs are determined by the device driving the CYBUS3384 inputs rather than the CYBUS3384 itself. The propagation delay contributed by the CYBUS3384 is essentially zero when the N-channel gate is at VCC. 4.0 4.5 5.0 BUS3384-4 BUS3384-3 The CYBUS3384 is a ten-channel bidirectional solid state bus switch with a “near zero” propagation delay. 3.5 VIN, Volts BE2 Application Information 3.0 Figure 2. VOUT vs. Volts When the device is unpowered, the CYBUS3384 draws no current from the I/O or control inputs, and there is no current path from the I/O or control to the power pins. There are no back power or current drain problems when the device is unpowered. The CYBUS3384 provides an ideal interface between 5V and 3.3V components, since the CYBUS3384 provides no signal drive, the ICC demands are small, limited to AC switching of the N-channel gates, control circuitry, and a minute amount of I/O leakage. Due to the low current demands of the CYBUS3384, it is possible to lower the CYBUS3384 VCC from a standard 5.0V supply with a small, inexpensive diode and a resistor to provide a low-current full-bidirectional signal compatibility between 5V logic family signals and 3.3V logic family signals. By adding a small, inexpensive diode and a resistor, the CYBUS3384 VCC supply voltage can be shifted to 4.3V as shown in Figure 3. 5V signals will then be limited to 3.3V as they pass through the CYBUS3384. 3.3V signals will pass back through the CYBUS3384 unaltered and provide compatibility with 5V TTL input requirements. Note that the conversion is bidirectional and is limited to 3.3V independent of which side is driven to 5V. The CYBUS3384 could convert 5V signals for use on a 3.3V bus or convert a 5V bus to signals compatible with 3.3V components. 3.3V/5V Supply Operation In certain system applications, the CYBUS3384 must operate from either a 5V or 3.3V power supply, depending on the state 4 CYBUS3384 of the system. If this occurs, the circuit shown in Figure 4 can be added to step the 3.3V supply up to a nominal 5V level. The low-cost, high-efficiency Step Up regulator shown in the figure is available from Texas Instruments and other suppliers. The diode arrangement will automatically select the active supply. Standard silicon diodes can be used because the CYBUS3384 VCC is specified at 4.0V. in use. Usually the subsystem bus input ESD protection circuits consist of a pair of clamp diodes to limit input voltage excursions to a maximum of VCC+Vt and –Vt (see Figure 5). Removing power from these causes the VCC ESD clamp diode to connect the dead circuit inputs to GND, often significantly increasing bus loading and power dissipation (see Figure 6). The CYBUS3384 placed on the input of the load to be disconnected effectively prevents bus loading and its associated problems. +5V VCC 5.0V EPROM Vt 5.0V BUS CHIP SET Vt 3.3V LOGIC 4.3 VCC 3.3V CPU 5.0V I/O 3.3V DRAM CYBUS3384 3.3V < – > 5.0V CONVERTER BUS3384-7 5.0V I/O Figure 5. Gate Input (Power ON) BUS3384-5 VCC Figure 3. System with CYBUS3384 as 5V TTL to 3V Converter 5V 5V Vt STEP-UP REG. 3.3V VCC Vt CYBUS3384 BUS3384-6 Figure 4. 3.3V/5V Supply Switch BUS3384-8 Low Power Bus Isolation Figure 6. Gate Input (Power OFF) Modern battery-operated systems rely on internal power management schemes to disconnect power from subsystems not 5 CYBUS3384 BUS1 OWN BUSY Arbiter CYBUS3384 BE1/BE2 Static RAM DATA CYBUS3384 CYBUS3384 OWN BUSY Processor 1 ADDR/Enables Processor 2 BUS2 CYBUS3384 CYBUS3384 CYBUS3384 CYBUS3384 Enables 1 Address 1 Enables 2 Address 2 BUS3384-9 Figure 7. High Speed Dual Port RAM High Speed Dual Port RAM As shown in Figure 7, a high-speed, dual-port memory is implemented using a combination of commodity SRAM, a simple arbitration circuit, and the CYBUS3384. Processor 1 is the system host processor while Processor 2 is dedicated peripheral processor (such as a DSP for acquiring and manipulating data). Either processor can own the SRAM by first reading the BUSY bit to determine if the SRAM is available. If so, the requesting processor takes control by writing the OWN bit (which redirects the bus through the CYBUS3384s and sets the BUSY bit notifying the other bus the SRAM is not available). Processor 1 owns the bus and may now access the SRAM as needed. When finished, Processor 1 resets the OWN bit releasing the SRAM. The SRAM access sequence is identical for Processor 2. In this application, the CYBUS3384 saves 10 ns compared to using an F244 address buffer and an F245 data bus transceiver. This, in turn, allows the use of slower, less expensive SRAM, resulting in lower system cost and power savings. tance at room temperature and a 1 microampere input leakage current, a 1 volt “droop” from the initial voltage level would take 50 microseconds. Figure 9 shows the addition of a physical capacitor if there is insufficient stray capacitance. Figure 10 shows an active bus termination capable of sustaining the programmed logic for an indefinite period of time in the presence of VCC. RAM or Other Logic CYBUS3384 Stray Cap. (50pF) BUS3384-10 Figure 8. Latch Variation with Spray Capacitance RAM or Other Logic CYBUS3384 Selectable Termination Loads C1 In some applications, it is desirable to vary the characteristic termination impedance as the system configuration changes. This is a common problem in automatic test equipment applications. Because of their low ON resistance, miniature relays are often used to switch termination loads. A single CYBUS3384 can replace as many as 10 such relays resulting in faster switching operation, lower power, and significant cost savings. BUS3384-11 Figure 9. Latch Variation with Physical Capacitor RAM or Other Logic CYBUS3384 Fast Latch FCT244T Figures 8 and 9 show variations of a latch having a sub 1-ns propagational delay time using the CYBUS3384 in combination with other components. This circuit has the advantage of being four to ten times faster than an equivalent implementation using a 373 latch—and with no added noise. Figure 8 relies on the stray capacitance of the bus to maintain data when the CYBUS3384 opens. Assuming 50-pF stray capaci- BUS3384-12 1K Figure 10. Active Bus Termination 6 CYBUS3384 Document #: 38–00355 Package Diagrams 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) Molded SOIC S13 7 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CYBUS3384QC OBSOLETE SSOP/ QSOP DBQ 24 TBD Call TI Call TI CYBUS3384QCT OBSOLETE SSOP/ QSOP DBQ 24 TBD Call TI Call TI CYBUS3384SOC OBSOLETE SOIC DW 24 TBD Call TI Call TI CYBUS3384SOCT OBSOLETE SOIC DW 24 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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