CYPRESS CY28378OCT

CY28378
FTG for Pentium 4® and Intel® 845 Series Chipset
Features
• Compatible with Intel® CK-Titan and CK-408 Clock
Synthesizer/Driver specifications
• System frequency synthesizer for Intel Brookdale 845
and Brookdale – G Pentium 4® chipsets
• Programmable clock output frequency with less than
1-MHz increment
• Integrated fail-safe Watchdog timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when Watchdog timer
time-out
• Programmable 3V66 and PCI output frequency mode
XTAL
OSC
*FS0:4
VTT_PWRGD#
PCI
REF
48M
24_48M
x4
x 10
x2
x1
x1
VDD_CPU
*MULTSEL1/REF1
CPUT[0:1], CPUC[0:1],
VDD_REF
CPU_ITP, CPU_ITP#
VDD_PCI
PCI_F0:2
PCI0:6
VDD_48MHz
3V66_3/48MHz_1
VDD_48MHz
48MHz_0
PWRDWN#
24_48MHz
2
SMBus
Logic
X1
X2
GND_PCI
*FS2/PCI_F0
*FS3/PCI_F1
PCI_F2
VDD_PCI
*FS4/PCI0
PCI1
PCI2
GND_PCI
PCI3
PCI4
PCI5
PCI6
VDD_PCI
VTT_PWRGD#
RESET#
GND_48MHz
*FS0/48MHz_0
*FS1/24_48MHz
VDD_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CY28378
VDD_3V66
3V66_0:2
Fract.
Aligner
2
SDATA
SCLK
3V66
x3
PLL Ref Freq
Divider
Network
*MULTSEL0:1
PLL2
CPU
VDD_REF
REF0:1
~
PLL 1
Table 1. Frequency Table
Pin Configuration[1]
Block Diagram
X1
X2
• Capable of generating system RESET after a Watchdog
timer time-out or a change in output frequency via
SMBus interface occurs
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength support
• Programmable output skew support
• Power management control inputs
• Available in 48-pin SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/MULTSEL0**
GND_REF
VDD_CPU
CPU_ITP
CPU_ITP#
GND_CPU
PWRDWN#*
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
GNDC_CPU
IREF
VDD_CORE
GND_CORE
VDD_3V66
3V66_0
3V66_1
GND_3V66
3V66_2
3V66_3/48MHz_1
SCLK
SDATA
RESET#
SSOP-48
Note:
1. Signals marked with ‘*’ and ‘**’ have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation
Document #: 38-07519 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 28,2003
CY28378
Pin Description
Pin #
Name
Type
Description
3
X1
I
Crystal Connection or External Reference Frequency Input: This
pin has dual functions. It can be used as an external 14.318-MHz
crystal connection or as an external reference frequency input.
4
X2
O
Crystal Connection: Connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
48
REF0/MULTSEL0
I/O
Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz
clock output. This pin also serves as a power-on strap option to
determine the current multiplier for the CPU clock outputs. The
MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
150k internal pull down.
1
REF1/MULTSEL1
I/O
Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz
clock output. This pin also serves as a power-on strap option to
determine the current multiplier for the CPU clock outputs. The
MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
150k internal pull up.
41, 38, 40, 37
CPUT(0:1),
CPUC(0:1)
O
CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through
serial input interface.
44, 45
CPU_ITP,
CPU_ITP#
O
CPU Clock Output for ITP: Frequency is set by the FS0:4 inputs or
through serial input interface.
31, 30, 28
3V66_0:2
O
66MHz Clock Outputs: 3.3V fixed 66-MHz clock.
6
PCI_F0/FS2
I/O
Free-running PCI Output 0/Frequency Select 2: 3.3V free-running
PCI output. This pin also serves as a power-on strap option to
determine device operating frequency as described in the Frequency
Selection Table. 150k internal pull up.
7
PCI_F1/FS3
I/O
Free-running PCI Output 1/Frequency Select 3: 3.3V free-running
PCI output. This pin also serves as a power-on strap option to
determine device operating frequency as described in the Table 2.
150k internal pull up.
8
PCI_F2
O
Free-running PCI Output 2: 3.3V free-running PCI output.
10
PCI0/FS4
I/O
PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also
serves as a power-on strap option to determine device operating
frequency as described in Table 2. 150k internal pull up.
11, 12, 14, 15, 16,
17
PCI(1:6)
O
PCI Clock Output 1 to 6: 3.3V PCI clock outputs.
22
48MHz_0/FS0
I/O
48MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread
spectrum output. This pin also serves as a power-on strap option to
determine device operating frequency as described in Table 2.
This output will be used as the reference clock for USB host controller
in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms,
this output will be used as the VCH reference clock. 150k internal pull
up.
Document #: 38-07519 Rev. **
Page 2 of 22
CY28378
Pin Description
Type
Description
23
Pin #
24_48MHz/FS1
Name
I/O
24 or 48MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or
48-MHz non-spread spectrum output. This pin also serves as a
power-on strap option to determine device operating frequency as
described in Table 2. This output will be used as the reference clock
for SIO devices in Intel 845 (Brookdale) platforms. For Intel Brookdale
– G platforms, this output will be used as the reference clock for both
USB host controller and SIO devices. We recommend system designer
to configure this output as 48 MHz and “HIGH Drive” by setting Byte
[5], Bit [0] and Byte [9], Bit [7], respectively.150k internal pull up.
27
3V66_3/48MHz_1
O
48MHz or 66MHz Output: 3.3V output.
42
PWRDWN#
I
Power Down Control: 3.3V LVTTL compatible input that places the
device in power down mode when held low. 150k internal pull up.
26
SCLK
I
SMBus Clock Input: Clock pin for serial interface.
25
SDATA
20
RESET#
35
IREF
I
Current Reference for CPU Output: A precision resistor is attached
to this pin which is connected to the internal current reference.
19
VTT_PWRGD#
I
Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL
input. VTT_PWRGD# is a level sensitive strobe used to determine
when FS0:4 and MULTSEL0:1 inputs are valid and OK to be sampled
(Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this
input will be ignored.
2, 9, 18, 24, 32, 39, VDD_REF,
46
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
P
3.3V Power Connection: Power supply for CPU outputs buffers, 3V66
output buffers, PCI output buffers, reference output buffers and
48-MHz output buffers. Connect to 3.3V.
5, 13, 21, 29, 36,
43, 47
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_REF,
G
Ground Connection: Connect all ground pins to the common system
ground plane.
34
VDD_CORE
P
3.3V Analog Power Connection: Power supply for core logic, PLL
circuitry. Connect to 3.3V.
33
GND_CORE
G
Analog Ground Connection: Ground for core logic, PLL circuitry.
Document #: 38-07519 Rev. **
I/O
SMBus Data Input: Data pin for serial interface.
O (open-drain) System Reset Output: Open-drain system reset output.
Page 3 of 22
CY28378
Table 2. Frequency Selection Table
Input Conditions
Output Frequency
VCO
Freq.
PLL Gear
Constants
(G)
33.6
402.80
47.99750
67.3
33.6
403.60
47.99750
72.0
36.0
432.00
47.99750
101.2
67.5
33.7
404.80
47.99750
114.0
76.0
38.0
456.00
47.99750
1
117.0
78.0
39.0
468.00
47.99750
0
120.0
80.0
40.0
480.00
47.99750
1
1
123.0
82.0
41.0
492.00
47.99750
0
0
125.7
62.9
31.4
377.12
63.99667
0
0
1
130.3
65.1
32.6
390.80
63.99667
0
1
0
133.9
67.0
33.5
401.70
63.99667
1
0
1
1
134.2
67.1
33.6
402.60
63.99667
1
1
0
0
134.5
67.3
33.6
403.50
63.99667
0
1
1
0
1
148.0
74.0
37.0
444.00
63.99667
0
1
1
1
0
152.0
76.0
38.0
456.00
63.99667
0
1
1
1
1
156.0
78.0
39.0
468.00
63.99667
1
0
0
0
0
160.0
80.0
40.0
480.00
63.99667
1
0
0
0
1
164.0
82.0
41.0
492.00
63.99667
1
0
0
1
0
167.4
66.9
33.5
334.80
95.99500
1
0
0
1
1
170.0
68.0
34.0
340.00
95.99500
1
0
1
0
0
175.0
70.0
35.0
350.00
95.99500
1
0
1
0
1
180.0
72.0
36.0
360.00
95.99500
1
0
1
1
0
185.0
74.0
37.0
370.00
95.99500
1
0
1
1
1
190.0
76.0
38.0
380.00
95.99500
1
1
0
0
0
166.8
66.7
33.4
333.60
95.99500
1
1
0
0
1
100.2
66.8
33.4
400.80
47.99750
1
1
0
1
0
133.6
66.8
33.4
400.80
63.99667
1
1
0
1
1
200.4
66.8
33.4
400.80
95.99500
1
1
1
0
0
166.6
66.6
33.3
333.33
95.99500
1
1
1
0
1
100.0
66.6
33.3
400.00
47.99750
1
1
1
1
0
200.0
66.6
33.3
400.00
95.99500
1
1
1
1
1
133.3
66.6
33.3
400.00
63.99667
FS4
FS3
FS2
FS1
FS0
SEL4
SEL3
SEL2
SEL1
SEL0
CPU
3V66
PCI
0
0
0
0
0
100.7
67.1
0
0
0
0
1
100.9
0
0
0
1
0
108.0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
Swing Select Functions
MULTSEL0
Board Target
Trace/Term Z
Reference R, IREF =
MULTSEL1
0
0
50Ω
1
0
50Ω
Document #: 38-07519 Rev. **
Output
Current
VOH @ Z
Rr = 221 1%,
IREF = 5.00 mA
IOH = 4*Iref
1.0V @ 50
Rr = 475 1%,
IREF = 2.32 mA
IOH = 6*Iref
0.7V @ 50
VDD/(3*Rr)
Page 4 of 22
CY28378
Data Protocol
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface (SDI), various device functions such as
individual clock output buffers, etc. can be individually enabled
or disabled.
The register associated with the SDI initializes to it’s default
setting upon power-up, and therefore use of this interface is
optional. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power
management functions.
The clock driver serial protocol accepts byte write, byte read,
block write and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol.
The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit
Descriptions
0 = Block read or block write operation
1 = Byte read or byte write operation
7
Byte offset for byte read or byte write operation. For block read or block write operations, these
bits should be ‘0000000’.
6:0
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
Block Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
28
29:36
37
38:45
46
Command Code – 8 Bit
'00000000' stands for block operation
11:18
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
19
Acknowledge from slave
Byte Count – 8 bits
20
Repeat start
Acknowledge from slave
21:27
Slave address – 7 bits
Data byte 1 – 8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
30:37
38
Acknowledge
....
......................
....
Data Byte (N–1) –8 bits
47
....
Acknowledge from slave
48:55
....
Data Byte N –8 bits
....
Acknowledge from slave
....
Data bytes from slave/Acknowledge
....
Stop
....
Data byte N from slave – 8 bits
....
Not Acknowledge
....
Stop
Document #: 38-07519 Rev. **
39:46
Byte count from slave – 8 bits
56
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Page 5 of 22
CY28378
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
Byte Read Protocol
Description
Bit
Start
1
Slave address – 7 bits
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Data byte from master – 8 bits
28
Acknowledge from slave
29
Stop
11:18
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
19
Acknowledge from slave
20
Repeat start
21:27
Slave address – 7 bits
28
Read = 1
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Not Acknowledge
39
Stop
Byte Configuration Map
Byte 0
Bit
@Pup
Name
Bit 7
0
Spread Select2
Bit 6
0
Spread Select1
Bit 5
0
Spread Select0
Bit 4
0
SEL4
Bit 3
0
SEL3
Bit 2
0
SEL2
Bit 1
0
SEL1
Bit 0
Byte 1
0
SEL0
Bit
@Pup
Description
‘000’ = OFF
‘001’ = +0.12, – 0.62%
‘010’ = +0.25, – 0.75%
‘011’ = +0.50, – 1.00%
‘100’ = ± 0.25%
‘101’ = +0.00, – 0.50%
‘110’ = ±0.5%
‘111’ = ±0.38%
SW Frequency selection bits. See Table 2.
Name
Bit 7
1
CPUT1, CPUC1
Bit 6
1
CPUT0, CPUC0
Bit 5
1
48MHz
Description
(Active/Inactive)
(Active/Inactive)
Bit 4
1
24_48MHz
(Active/Inactive)
Bit 3
1
3V66_3
(Active/Inactive)
Bit 2
1
3V66_2
(Active/Inactive)
Bit 1
1
3V66_1
(Active/Inactive)
Bit 0
1
3V66_0
(Active/Inactive)
Document #: 38-07519 Rev. **
Page 6 of 22
CY28378
Byte 2
Bit
@pup
Name
Pin Description
Bit 7
0
Reserved
Reserved
Bit 6
1
PCI6
(Active/Inactive)
Bit 5
1
PCI5
(Active/Inactive)
Bit 4
1
PCI4
(Active/Inactive)
Bit 3
1
PCI3
(Active/Inactive)
Bit 2
1
PCI2
(Active/Inactive)
Bit 1
1
PCI1
(Active/Inactive)
Bit 0
Byte 3
1
PCI0
(Active/Inactive)
Bit
@Pup
Name
Pin Description
Bit 7
1
PCI_F2
(Active/Inactive)
Bit 6
1
PCI_F1
(Active/Inactive)
Bit 5
1
PCI_F0
(Active/Inactive)
Bit 4
0
Reserved
Reserved
Bit 3
1
CPU_ITP, CPU_ITP#
(Active/Inactive)
Bit 2
0
Reserved
Reserved
Bit 1
1
REF1
(Active/Inactive)
Bit 0
Byte 4
1
REF0
(Active/Inactive)
Bit
Bit 7
@Pup
0
Name
Pin Description
MULTSEL_Override
This bit control the selection of IREF multiple.
0 = HW control; IREF multiplier is determined by MULTSEL[0:1] input pins
1 = SW control; IREF multiplier is determined by Byte[4], Bit[5:6].
IREF multiplier
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
Bit 6
HW
SW_MULTSEL1
Bit 5
HW
SW_MULTSEL0
Bit 4
0
Reserved
Reserved
Bit 3
0
Reserved
Reserved
Bit 2
0
Reserved
Reserved
Bit 1
0
Reserved
Reserved
Bit 0
Byte 5
0
Reserved
Vendor Test Mode (always program to 0)
Bit
@Pup
Name
Bit 7
HW
Latched FS4 input
Bit 6
HW
Latched FS3 input
Bit 5
HW
Latched FS2 input
Bit 4
HW
Latched FS1 input
Bit 3
HW
Latched FS0 input
Bit 2
0
FS_Override
Pin Description
Latched FS[4:0] inputs. These bits are read only.
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
Bit 1
0
SEL 3V66
0 = 48-MHz output on pin 27, 1 = 66-MHz output on pin 27
Bit 0
1
SEL 48MHZ
0 = 24-MHz,1 = 48-MHz
Document #: 38-07519 Rev. **
Page 7 of 22
CY28378
Byte 6
Bit
@Pup
Name
Pin Description
Bit 7
0
Revision_ID3
Revision ID bit[3]
Bit 6
0
Revision_ID2
Revision ID bit[2]
Bit 5
0
Revision_ID1
Revision ID bit[1]
Bit 4
1
Revision_ID0
Revision ID bit[0]
Bit 3
1
Vendor_ID3
Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 2
0
Vendor_ID2
Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 1
0
Vendor _ID1
Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 0
Byte 7
0
Vendor _ID0
Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit
@Pup
Name
Pin Description
Bit 7
0
Reserved
Vendor Test Mode (always program to 0)
Bit 6
0
Reserved
Vendor Test Mode (always program to 0)
Bit 5
0
Reserved
Vendor Test Mode (always program to 0)
Bit 4
0
Reserved
Vendor Test Mode (always program to 0)
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
3V66 Fract_Align3 3V66 Frequency Fractional Aligner: These bits determine the 3V66 fixed frequency. This
3V66 Fract_Align2 option does not incorporate spread spectrum and is enabled through Byte10, bit 4
001067.533.7
3V66 Fract_Align1
001168.534.3
3V66 Fract_Align0
010069.534.8
010170.635.3
011071.635.8
011172.636.3
100073.636.8
100174.737.3
101075.737.8
101176.738.4
110077.738.9
110178.739.4
111079.839.9
111180.840.4
Byte 8
Bit
@Pup
Name
Pin Description
Bit 7
0
WD_Alarm
This bit is set to “1” when the Watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp
Bit 6
0
Frequency_Revert
This bit allows setting the Revert Frequency once the system is rebooted
0: Hardware
1: Last Programmed
Bit 5
0
Reserved
Reserved
Bit 4
0
WD_TIMER3
Watchdog timer time stamp selection:
Bit 3
0
WD_TIMER2
Bit 2
0
WD_TIMER1
Bit 1
0
WD_TIMER0
Bit 0
1
Reserved
Document #: 38-07519 Rev. **
0000: Off
0001: 1 second
0010: 2 seconds
.
.
.
1110: 14 seconds
1111: 15 seconds
Reserved
Page 8 of 22
CY28378
Byte 9
Bit
@Pup
Name
Pin Description
Bit 7
0
48MHz_DRV
48MHz and 24_48MHz clock output drive strength
0 = Normal
1 = High Drive
(Recommend to set to high drive if this output is being used to drive both
USB and SIO devices in Intel Brookdale – G platforms)
Bit 6
0
PCI_DRV
PCI clock output drive strength
0 = Normal
1 = High Drive
Bit 5
0
3V66_DRV
3V66 clock output drive strength
0 = Normal
1 = High Drive
Bit 4
0
Reserved
Reserved
Bit 3
0
Reserved
Reserved
Bit 2
0
Reserved
Reserved
Bit 1
0
Reserved
Reserved
Bit 0
Byte 10
0
Reserved
Reserved
Bit
@Pup
Name
Bit 7
0
CPU_Skew2
Bit 6
0
CPU_Skew1
Bit 5
0
CPU_Skew0
Bit 4
0
Fixed 3V66_SEL
Pin Description
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
3V66 and PCI output frequency select mode
0 = Set according to Frequency Selection Table
1 = Set according to Fractional Aligner settings
Bit 3
0
PCI_Skew1
Bit 2
0
PCI_Skew0
Bit 1
0
3V66_Skew1
Bit 0
0
3V66_Skew0
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
3V66 skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Byte 11
Bit
@Pup
Name
Pin Description
Bit 7
0
Reserved
Reserved
Bit 6
0
Reserved
Reserved
Bit 5
0
Reserved
Reserved
Bit 4
0
Reserved
Reserved
Bit 3
0
Reserved
Reserved
Bit 2
0
Reserved
Reserved
Bit 1
0
Reserved
Reserved
Bit 0
0
Reserved
Reserved
Document #: 38-07519 Rev. **
Page 9 of 22
CY28378
Byte 12
Bit
@Pup
Name
Pin Description
Bit 7
0
Reserved
Reserved
Bit 6
0
Reserved
Reserved
Bit 5
0
Reserved
Reserved
Bit 4
0
Reserved
Reserved
Bit 3
0
Reserved
Reserved
Bit 2
0
Reserved
Reserved
Bit 1
0
Reserved
Reserved
Bit 0
Byte 13
0
Reserved
Reserved
Bit
@Pup
Name
Bit 7
0
Reserved
Bit 6
0
CPU_FSEL_N6
Bit 5
0
CPU_FSEL_N5
Bit 4
0
CPU_FSEL_N4
Bit 3
0
CPU_FSEL_N3
Bit 2
0
CPU_FSEL_N2
Bit 1
0
CPU_FSEL_N1
Bit 0
Byte 14
0
CPU_FSEL_N0
Bit
@Pup
Pin Description
If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[6:0] and
CPU_FSEL_M[5:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[4:0] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
Name
Pin Description
Bit 7
0
Pro_Freq_EN
Programmable output frequencies enabled
0 = disabled
1 = enabled
Bit 6
0
Reserved
Reserved
Bit 5
0
CPU_FSEL_M5
Bit 4
0
CPU_FSEL_M4
Bit 3
0
CPU_FSEL_M3
Bit 2
0
CPU_FSEL_M2
Bit 1
0
CPU_FSEL_M1
If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[6:0] and
CPU_FSEL_M[5:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[4:0] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
Bit 0
0
CPU_FSEL_M0
Watchdog Self Recovery Sequence
This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang up due to the
frequency change.
When the system sends an SMBus command requesting a
frequency change through the Dial-a-Frequency Control
Registers, it must have previously sent a command to the
Watchdog Timer to select which time out stamp the Watchdog
must perform, otherwise the System Self Recovery feature will
not be applicable. Consequently, this device will change
frequency and then the Watchdog timer starts timing.
Document #: 38-07519 Rev. **
Meanwhile, the system BIOS is running its operation with the
new frequency. If this device receives a new SMBus command
to clear the bits originally programmed in the Watchdog Timer
bits (reprogram to 0000) before the Watchdog times out, then
this device will keep operating in its normal condition with the
new selected frequency.
The Watchdog timer will also be triggered if you program the
software frequency select bits (FSEL) to a new frequency
selection. If the Watchdog times out before the new SMBus
reprograms the Watchdog Timer bits to (0000), then this
device will send a low system reset pulse, on SRESET# and
changes WD Time-out bit to “1.”
Page 10 of 22
CY28378
RESET W ATCHDOG TIMER
Set WD(0:3) Bits = 0
INITIALIZE W ATCHDOG TIMER
Set Frequency Revert Bit
Set WD(0:3) = (# of Sec ) x 2
SET SOFTW ARE FSEL
Set SW Freq_Sel = 1
Set FS(0:4)
SET DIAL-A-FREQUENCY
Load M and N Registers
Set Pro_Freq_EN = 1
Wait for 6msec For
Clock Output to Ramp to
Target Frequency
N
Hang?
CLEAR W D
Set WD(0:3) Bits = 0
Exit
Y
W ATCHDOG TIMEOUT
Frequency Revert Bit =
0
Set Frequency to
FS_HW_Latched
Frequency Revert Bit =
1
Set Frequency to FS_SW
Set SRESET# = 0 for 6 msec
Reset
Figure 1. Watchdog Flowchart
Program the CPU output frequency
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation:
Fcpu = G * N/M.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 2.
The ratio of N and M need to be greater than “1” [N/M> 1].
The following table lists set of N and M values for different
frequency output ranges. This example use a fixed value for
the M-Value Register and select the CPU output frequency by
changing the value of the N-Value Register.
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
Table 6. Examples of N and M Value for Different CPU Frequency Range
Fixed Value for M-Value Register
Range of N-Value Register for Different
CPU Frequency
47.99750
48
66 – 127
63.99667
40
80 – 127
Frequency Ranges
Gear Constants
66 – 127
128 – 203
Document #: 38-07519 Rev. **
Page 11 of 22
CY28378
Table 7. Maximum Lumped Capacitive Output Loads
Clock
PCI, PCI_F
Max Load
Units
20
pF
3V66
30
pF
48M_24MHz, 48MHz
20
pF
30
pF
See Figure 4
pF
REF
CPUT/C
CPU_ITP
Table 8. Group Timing Relationship and Tolerances
3V66 to PCI
Offset
Tolerance
(or Range)
Conditions
Notes
Typical 2.5 ns
1.5 – 3.5 ns
3V66 leads
See Note 2
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low “stopped” state.
PD# – Assertion
PWRDWN#
CPUT, 133MHz
CPUC, 133MHz
AGP, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.131818
Figure 2. Power-down Assertion Timing Waveforms
Document #: 38-07519 Rev. **
Page 12 of 22
CY28378
PD# – Deassertion
Tstable
<1.8ms
PWRDWN#
CPUT, 133MHz
CPUC, 133MHz
AGP, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.131818
Tdrive_PWRDN#
<300µs, >200mV
Figure 3. Power-down Deassertion Timing Waveforms
After the clock chip internal PLL is powered up and locked, all
outputs will be enabled within a few clock cycles of each other,
with the first to last active clock taking no more than two full
PCI clock cycles.
Table 9. PWRDWN# Functionality
PWRDWN#
CPUT
CPUC
3V66
PCI_F/PCI
48MHz
1
Normal
Normal
66MHz
3V66/2
48M
0
Iref x2
Float
Low
Low
Low
Document #: 38-07519 Rev. **
Page 13 of 22
CY28378
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDDA
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to V SS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
0
70
°C
TJ
Temperature, Junction
Functional
–
150
°C
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
UL–94
Flammability Rating
At 1/8 in.
MSL
Moisture Sensitivity Level
2000
–
V
15
°C/W
45
°C/W
V–0
1
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
3.135
3.465
V
VDD_REF,
VDD_PCI,
VDD_CORE,
VDD_3V66,
VDD_48 MHz,
VDD_CPU,
3.3V Supply Voltages
Cin
Input Pin Capacitance
5
pF
CXTAL
XTAL Pin Capacitance
22.5
pF
CL
Max. Capacitive Load on 48MHz, REF
PCICLK, 3V66
2030
pF
f(REF)
Reference Frequency
Oscillator Nominal Value
VIH
High-level Input Voltage
Except Crystal Pads. Threshold voltage for
crystal pads = VDD/2
14.318 14.318
2.0
VIL
Low-level Input Voltage
Except Crystal Pads
VOH
High-level Output Voltage
48MHz, REF, 3V66
IOH = –1 mA
2.4
PCI
IOH = –1 mA
2.4
VOL
Low-level Output Voltage
48MHz, REF, 3V66
IOL = 1 mA
PCI
IOL = 1 mA
IIH
Input High Current
IIL
Input Low Current
0 < VIN < VDD
IOH
High-level Output Current
CPU
For IOH =6*IRef
Configuration
Type X1, VOH = 0.74V
REF, 48 MHz
Type 3, VOH = 1.00V
Type X1, VOH = 0.65V
Type 5, VOH = 1.00V
Low-level Output Current
REF, 48MHz
Type 3, VOL = 1.95V
Type 5, VOL =1.95 V
Type 5, VOL = 0.4V
IOZ
Output Leakage Current
Document #: 38-07519 Rev. **
Three-state
V
0.55
V
5
mA
–5
5
12.9
mA
mA
14.9
–29
–23
–33
–33
29
Type 3, VOL = 0.4V
3V66, PCI,
V
–5
Type 5, VOH = 3.135V
IOL
V
V
0.4
Type 3, VOH = 3.135V
3V66, PCI
V
0.8
0 < VIN < VDD
MHz
mA
27
30
38
10
mA
Page 14 of 22
CY28378
DC Electrical Specifications (continued)
Max.
Unit
IDD3
Parameter
3.3V Power Supply Current
Description
VDD_CORE/VDD33 = 3.465V, FCPU = 133 MHz
Condition
Min.
250
mA
IDDPD3
3.3V Shutdown Current
VDD_CORE/VDDQ3 = 3.465V
25
mA
AC Electrical Specifications[2]
Parameter
Output
Description
Cycle[3]
Test Conditions
Min.
Max.
Unit
t1A/(t1B)
45
55
%
t1
All
Output Duty
t2
CPUT/C
Rise Time
Measured at 20% to 80% of Voh
175
800
ps
t2
48MHz, REF
Rising Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t2
PCI, 3V66,
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t3
CPUT/C
Fall Time
Measured at 80% to 20% of Voh
175
800
ps
t3
48MHz, REF
Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
V/ns
t3
PCI, 3V66
Falling Edge Rate
Between 2.4V and 0.4V
0.7
4.0
V/ns
t4
CPUT/C
CPU-CPU Skew
Measured at Crossover
150
ps
t5
3V66 [0:1]
3V66-3V66 Skew
Measured at 1.5V
500
ps
t6
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
t7
3V66,PCI
3V66-PCI Clock Skew
3V66 leads. Measured at 1.5V
4.5
ns
t8
CPUT/C
Cycle-Cycle Clock Jitter
Measured at Crossover t8 = t8A – t8B
with all outputs running
600
ps
t9
3V66
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
600
ps
t9
48MHz
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
600
ps
t9
PCI
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
600
ps
t9
REF
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
1000
ps
CPUT/C, PCI
Settle Time
CPU and PCI clock stabilization from
power-up
3
ms
CPUT/C
Rise/Fall Matching
Measured with test loads[4, 5]
30
tRFM
1.0
loads[5]
VOVS
CPUT/C
Overshoot
Measured with test
VUDS
CPUT/C
Undershoot
Measured with test loads[5]
–0.2
loads[5]
VOH
VOL
VOX
CPUT/C
CPUT/C
CPUT/C
High-level Output Voltage Measured with test
Low-level Output Voltage
Crossover Voltage
V
V
0.65
0.74
V
[5]
0.0
0.05
V
loads[5]
250
550
mv
Measured with test loads
Measured with test
Voh + 0.2
Notes:
2. All parameters specified with loaded outputs.
3. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
4. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge.
5. The test load is Rs = 33.2W, Rp = 49.9W in test circuit.
Document #: 38-07519 Rev. **
Page 15 of 22
CY28378
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
T PCB
33Ω
Measurem ent Point
CPUT
49.9Ω
2pF
MULTSEL
33Ω
T PCB
Measurem ent Point
CPUC
49.9Ω
2pF
IREF
475Ω
Figure 4. 0.7V Configuration
O u tp u t u n d e r T e s t
P ro b e
Load Cap
3 .3 V s ig n a l s
tD C
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0V
Tr
Tf
Figure 5. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement)
Document #: 38-07519 Rev. **
Page 16 of 22
CY28378
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
State 0
Wait for
VTT_PWRGD#
State 1
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
Off
State 3
On
On
Off
Figure 6. VTT_PWRGD# Timing Diagram[6]
S2
S1
Delay
>0.25mS
VTT_PWRGD# = Low
Sample
Inputs straps
VDDA = 2.0V
Wait for 1.146ms
S0
S3
VDDA = off
Power Off
Normal
Operation
Enable Outputs
VTT_PWRGD# = toggle
Figure 7. Clock Generator Power-up/Run State Diagram
Switching Waveforms
Duty Cycle Timing
(Single-ended Output)
t1B
t1A
Note:
6. Device is not affected, VTT_PWRGD# is ignored.
Document #: 38-07519 Rev. **
Page 17 of 22
CY28378
Switching Waveforms (continued)
Duty Cycle Timing (CPU Differential Output)
t1B
t1A
All Outputs Rise/Fall Time
VDD
OUTPUT
0V
t3
t2
CPU-CPU Clock Skew
Host_b
Host
Host_b
Host
t4
3V66-3V66 Clock Skew
3V66
3V66
t5
PCI-PCI Clock Skew
PCI
PCI
t6
3V66-PCI Clock Skew
3V66
PCI
t7
Document #: 38-07519 Rev. **
Page 18 of 22
CY28378
Switching Waveforms (continued)
CPU Clock Cycle-Cycle Jitter
t8A
t8B
Host_b
Host
Cycle-Cycle Clock Jitter
t9A
t9B
CLK
Ordering Information
Ordering Code
Package Type
Operating Range
CY28378OC
48-pin Small Shrunk Outline Package (SSOP)
Commercial, 0°C to 70°C
CY28378OCT
48-pin Small Shrunk Outline Package (SSOP) –Tape and Reel
Commercial, 0°C to 70°C
Document #: 38-07519 Rev. **
Page 19 of 22
CY28378
Layout Example
FB
VDDQ3
.005µF
G
G
G
G
VDDQ3
5Ω
48
47
V
46
G
45
44
G 43
42
41
G 40
V 39
G
38
37
G
36
G 35
V 34
G
3
V
32
G
31
30
G 29
28
27
26
G 25
G
CY28378
1
2 VG
3
4
5 G
6
7
8 G
9 V
G
10
11
12
13 G
14
15
16
17 G
18 V
19 G
20
21 G
22
23
24 *
G
C5 G
C3
G
G
G
G
G
G
G C6
FB = Dale ILB1206 - 300 (300 Ω @ 100 MHz)
Cermaic Caps C3 = 10 - 22 µF
G = VIA to GND plane layer
C4 = .005 µF
C5 = 10µF
C6 = .1µF
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = .1µf ceramic
* For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3
Document #: 38-07519 Rev. **
Page 20 of 22
CY28378
Package Diagram
48-Lead Shrunk Small Outline Package O48
51-85061-C
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07519 Rev. **
Page 21 of 22
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY28378
Document History Page
Document Title: CY28378 FTG for Pentium 4® and Intel® 845 Series Chipset
Document Number: 38-07519
REV.
**
ECN NO. Issue Date
123742
03/06/03
Document #: 38-07519 Rev. **
Orig. of
Change
RGL
Description of Change
New Data Sheet
Page 22 of 22