CY28344 FTG for Intel Pentium 4 CPU and Chipsets Features • Compatible to Intel® CK-Titan and CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel Brookdale (845) and Brookdale G Pentium® 4 Chipsets • Programmable clock output frequency with less than 1MHz increment • Integrated fail-safe Watchdog timer for system recovery • Automatically switch to HW-selected or SW-programmed clock frequency when Watchdog timer time-out • Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus byte Read/Write and block Read/Write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength support • Programmable output skew support • Power management control inputs • Available in 48-pin SSOP CPU 3V66 PCI REF 48M ×3 ×4 ×9 ×1 ×2 Pin Configuration[1] Block Diagram X1 X2 PLL Ref Freq Divider Network VDD_CPU CPU0:2, CPU0:2#, ~ PLL 1 FS0:4 VDD_REF REF_2X XTAL OSC MULTSEL0 VDD_3V66 3V66_0/VCH_CLK VTTPWRGD/PD# VDD_PCI PCI_F0:1 PCI0:6 VDD_48MHz 48MHz PLL2 SMBus Logic RST# REF_2X/FS2^ CPU0 CPU0# VDD_CPU CPU1 CPU1# GND_CPU VDD_CPU CPU2 CPU2# MULTSEL0 IREF GND_CPU 48MHz/FS3^ 24_48MHz VDD_48MHz GND_48MHz 3V66_0/VCH_CLK/FS4^ VDD_3V66 GND_3V66 SCLK SDATA VTTPWRGD/PD#* GND_CORE Note: 1. Signals marked with “*” and “^,” respectively, have internal pull-up and pull-down resistors. Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SSOP-48 24_48MHz 2 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY28344 VDD_3V66 3V66_1:3 VDD_REF X1 X2 GND_REF ^FS0/PCI_F0 ^FS1/PCI_F1 VDD_PCI GND_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI GND_PCI PCI4 PCI5 PCI6 VDD_3V66 GND_3V66 3V66_1 3V66_2 3V66_3 RST# VDD_CORE Page 1 of 21 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com CY28344 Pin Definitions X1 Pin No. 2 Pin Type I X2 3 O REF_2X/FS2 48 I/O MULTSEL0 38 I Pin Name CPU0:2, CPU0:2# 47, 44, 40, 46, 43,39 3V66_1:3 20, 21, 22 3V66_0/VCH_CLK/F 31 S4 O O I/O PCI_F0/FS0 5 I/O PCI_F1/FS1 6 I/O O 48MHz/FS3 9, 10, 11, 12, 15, 16, 17 35 24_48MHz SCLK SDATA RST# 34 28 27 23 IREF 37 VTT_PWRGD/PD# 26 PCI0:6 VDD_REF, VDD _PCI, VDD_48MHz, VDD_3V66, VDD_CPU VDD_48MHz GND_PCI, GND_48MHz, GND_3V66, GND_CPU, GND_REF, 1, 7, 13, 18, 30, 33, 41, 45 33 4, 8, 14, 19, 29, 32, 36, 42 Rev 1.0, November 21, 2006 I/O Pin Description Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Reference Clock/Frequency Select 2: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Current Multiplier Selection 0: 3.3V input to select the current multiplier for CPU clock outputs. The MULTSEL0 is as follows: MULTSEL0 0 = Ioh is 4 × IREF 1 = Ioh is 6 × IREF CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input interface. 66MHz Clock Outputs: 3.3V 66-MHz clock. 66MHz Clock Output/Frequency Select 4: 3.3V 66-MHz or 48-MHz clock output. The selection is determined by the control byte register. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Free-running PCI Output 0/Frequency Select 0: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Free-running PCI Output 1/Frequency Select 1: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. PCI Clock Output 0 to 6: 3.3V PCI clock outputs. 48MHz Output/Frequency Select 3: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. 24 or 48MHz Output: 3.3V fixed 24-MHz or 48-MHz non-spread spectrum output. SMBus Clock Input: Clock pin for serial interface. SMBus Data Input: Data pin for serial interface. System Reset Output: Open-drain system reset output. I/O I I/O O (opendrain) I Current Reference for CPU output: A precision resistor is attached to this pin, which is connected to the internal current reference. I Powergood from Voltage Regulator Module (VRM)/PD#: 3.3V LVTTL input. VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4 and MULTSEL0 inputs are valid and OK to be sampled (Active HIGH). P 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. P G 3.3V Power Connection: 48MHz output buffers. Connect to 3.3V. Ground Connection: Connect all ground pins to the common system ground plane. Page 2 of 21 CY28344 Pin Definitions (continued) Pin Name VDD_CORE GND_CORE Pin No. 24 Pin Type P 25 G Pin Description 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. Analog Ground Connection: Ground for core logic, PLL circuitry. Swing Select Functions (SW control) SW_MULTSEL1 0 SW_MULTSEL0 0 Board Target Trace/Term Z 50 Ohm 0 0 60 Ohm 0 1 50 Ohm 0 1 60 Ohm 1 0 50 Ohm 1 0 60 Ohm 1 1 50 Ohm 1 1 60 Ohm 0 0 50 Ohm 0 0 60 Ohm 0 1 50 Ohm 0 1 60 Ohm 1 0 50 Ohm 1 0 60 Ohm 1 1 50 Ohm 1 1 60 Ohm Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Rr = 475 1%, IREF = 2.32 mA Output Current IOH = 4*Iref VOH @ Z 1.0V @ 50 IOH = 4*Iref 1.2V @ 60 IOH = 5*Iref 1.25V @ 50 IOH = 5*Iref 1.5V @ 60 IOH = 6*Iref 1.5V @ 50 IOH = 6*Iref 1.8V @ 60 IOH = 7*Iref 1.75V @ 50 IOH = 7*Iref 2.1V @ 60 IOH = 4*Iref 0.47V @ 50 IOH = 4*Iref 0.56V @ 60 IOH = 5*Iref 0.58V @ 50 IOH = 5*Iref 0.7V @ 60 IOH = 6*Iref 0.7V @ 50 IOH = 6*Iref 0.84V @ 60 IOH = 7*Iref 0.81V @ 50 IOH = 7*Iref 0.97V @ 60 Swing Select Functions (HW control) MULTSEL0 0 Board Target Trace/Term Z 50 Ohm 0 60 Ohm 1 50 Ohm 1 60 Ohm Rev 1.0, November 21, 2006 Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Rr = 221 1%, IREF = 5.00 mA Output Current IOH = 4*Iref VOH @ Z 1.0V @ 50 IOH = 4*Iref 1.2V @ 60 IOH = 6*Iref 1.5V @ 50 IOH = 6*Iref 1.8V @ 60 Page 3 of 21 CY28344 Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to it’s default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The clock driver serial protocol accepts byte Write, byte Read, block Write and block Read operation from the controller. For block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte Write and byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block Write and block Read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte Write and byte Read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit Descriptions 0 = Block Read or block Write operation 1 = Byte Read or byte Write operation 7 Byte offset for byte Read or byte Write operation. For block Read or block Write operations, these bits should be “0000000” 6:0 Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bit Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bit 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 Command Code – 8 bit “00000000” stands for block operation 11:18 Command Code – 8 bit “00000000” stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave 21:27 Slave address – 7 bits Data byte 0 – 8 bits 28 Read Acknowledge from slave 29 Acknowledge from slave Data byte 1 – 8 bits 46 Acknowledge from slave ... Data Byte N/Slave Acknowledge... ... Data Byte N – 8 bits ... Acknowledge from slave ... Stop Rev 1.0, November 21, 2006 30:37 38 39:46 47 48:55 Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits 56 Acknowledge ... Data bytes from slave/acknowledge ... Data byte N from slave – 8 bits ... Not acknowledge ... Stop Page 4 of 21 CY28344 Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 Byte Read Protocol Description Bit Start 1 Slave address – 7 bit 2:8 Description Start Slave address – 7 bit 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 Command Code – 8 bit “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave 11:18 19 Data byte – 8 bits 20 28 Acknowledge from slave 29 Stop 21:27 Command Code – 8 bit “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits 28 Read 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not acknowledge 39 Stop Data Byte Configuration Map Data Byte 0 Bit Pin# Name Description SW Frequency selection bits. See Table 4. Power On Default Bit 7 -- SEL3 Bit 6 -- SEL2 0 0 Bit 5 -- SEL1 0 Bit 4 -- SEL0 0 Bit 3 -- FS_Override 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings 0 Bit 2 -- SEL4 SW Frequency selection bits. See Table 4. 0 Bit 1 -- Spread Spectrum Enable 0 = OFF; 1 = Enabled 0 Bit 0 -- Reserved Reserved 0 Data Byte 1 Bit Pin# Name Description Power On Default Bit 7 40, 39 CPU2, CPU2# (Active/Inactive) 1 Bit 6 44, 43 CPU1, CPU1# (Active/Inactive) 1 Bit 5 47, 46 CPU0, CPU0# (Active/Inactive) 1 Latched FS[4:0] inputs. These bits are Read-only. X Bit 4 -- Latched FS4 input Bit 3 -- Latched FS3 input X Bit 2 -- Latched FS2 input X Bit 1 -- Latched FS1 input X Bit 0 -- Latched FS0 input X Rev 1.0, November 21, 2006 Page 5 of 21 CY28344 Data Byte 2 Bit Pin# Name Power On Default Pin Description Bit 7 -- Reserved Reserved 0 Bit 6 17 PCI6 (Active/Inactive) 1 Bit 5 16 PCI5 (Active/Inactive) 1 Bit 4 15 PCI4 (Active/Inactive) 1 Bit 3 12 PCI3 (Active/Inactive) 1 Bit 2 11 PCI2 (Active/Inactive) 1 Bit 1 10 PCI1 (Active/Inactive) 1 Bit 0 9 PCI0 (Active/Inactive) 1 Data Byte 3 Bit Pin# Name Power On Default Pin Description Bit 7 34 24_48MHz (Active/Inactive) 1 Bit 6 35 48MHz (Active/Inactive) 1 Bit 5 -- Reserved Reserved 0 Bit 4 -- Reserved Reserved 0 Bit 3 31 3V66_0/VCH_CLK 0 = 66 MHz; 1 = 48 MHz 0 Bit 2 31 3V66_0/VCH_CLK (Active/Inactive) 1 Bit 1 6 PCI_F1 (Active/Inactive) 1 Bit 0 5 PCI_F0 (Active/Inactive) 1 Data Byte 4 Bit Pin# Name Power On Default Pin Description Bit 7 -- MULTSEL_Override This bit control the selection of IREF multiple. 0 = HW control; IREF multiplier is determined by MULTSEL[0:1] input pins 1 = SW control; IREF multiplier is determined by Byte[4], Bit[5:6]. 0 Bit 6 -- SW_MULTSEL1 0 Bit 5 -- SW_MULTSEL0 IREF multiplier 00 = Ioh is 4 × IREF 01 = Ioh is 5 × IREF 10 = Ioh is 6 × IREF 11 = Ioh is 7 × IREF Bit 4 48 REF_2X (Active/Inactive) Drive 1 Bit 3 -- REF_DRV 0 = Normal, 1 = HIGH 0 Bit 2 22 3V66_3 (Active/Inactive) 1 Bit 1 21 3V66_2 (Active/Inactive) 1 Bit 0 20 3V66_1 (Active/Inactive) 1 Rev 1.0, November 21, 2006 0 Page 6 of 21 CY28344 Data Byte 5 Bit Pin# Name Pin Description Power On Default Bit 7 -- Spread Option 1 “00” = ± 0.25% 0 Bit 6 -- Spread Option 0 “01” = – 0.5% 0 “10” = ±0.5% “11” = ±0.38% Bit 5 -- Reserved Reserved 0 Bit 4 -- Reserved Reserved 0 Bit 3 -- Reserved Reserved 0 Bit 2 -- Reserved Reserved 0 Bit 1 -- Reserved Reserved 0 Bit 0 34 24_ 48MHZ 0 = 24 MHz 1 = 48 MHz 1 Data Byte 6 Bit Pin# Name Pin Description Power On Default Bit 7 Revision_ID3 Revision ID bit[3] 0 Bit 6 Revision_ID2 Revision ID bit[2] 0 Bit 5 Revision_ID1 Revision ID bit[1] 0 Bit 4 Revision_ID0 Revision ID bit[0] 0 Bit 3 Vendor_ID3 Bit[3] of Cypress Vendor ID. This bit is Read-only. 1 Bit 2 Vendor_ID2 Bit[2] of Cypress Vendor ID. This bit is Read-only. 0 Bit 1 Vendor _ID1 Bit[1] of Cypress Vendor ID. This bit is Read-only. 0 Bit 0 Vendor _ID0 Bit[0] of Cypress Vendor ID. This bit is Read-only. 0 Data Byte 7 Bit Pin# Name Pin Description Power On Default Bit 7 -- Reserved Reserved 0 Bit 6 -- Reserved Reserved 0 Bit 5 -- Reserved Reserved 0 Bit 4 -- Reserved Reserved 0 Bit 3 -- Reserved Reserved 0 Bit 2 -- Reserved Reserved 0 Bit 1 -- Reserved Reserved 0 Bit 0 -- Reserved Reserved 0 Data Byte 8 Bit Pin# Name Pin Description Power On Default Bit 7 -- Reserved Reserved 0 Bit 6 -- Reserved Reserved 0 Rev 1.0, November 21, 2006 Page 7 of 21 CY28344 Data Byte 8 (continued) Bit Pin# Name Bit 5 -- WD_TIMER4 Bit 4 -- WD_TIMER3 Bit 3 -- WD_TIMER2 Bit 2 -- WD_TIMER1 Bit 1 -- WD_TIMER0 Bit 0 -- WD_PRE_SCALER Power On Default Pin Description These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the pre-scaler. The timer can support values from 150 ms – 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 – 80 seconds. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. 1 0 = 150 ms 1 = 2.5 sec 0 1 1 1 1 Data Byte 9 Bit Pin# Name Power On Default Pin Description Bit 7 -- 48MHz_DRV 48MHz and 24_48MHz clock output drive strength 0 = Normal 1 = High Drive 0 Bit 6 -- PCI_DRV PCI clock output drive strength 0 = Normal 1 = High Drive 0 Bit 5 -- 3V66_DRV 3V66 clock output drive strength 0 = Normal 1 = High Drive 0 Bit 4 -- RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled 0 Bit 3 -- RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled 0 Bit 2 -- WD_TO_STATUS Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) 0 Bit 1 -- WD_EN 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note: CY28344 will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, CY28344 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28344 from its recovery frequency mode by clearing the WD_EN bit. 0 Bit 0 -- Reserved Reserved 0 Rev 1.0, November 21, 2006 Page 8 of 21 CY28344 Data Byte 10 Bit Pin# Name Power On Default Pin Description CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 Reserved Reserved 0 PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps 0 3V66 skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps 0 Bit 7 -- CPU_Skew2 Bit 6 -- CPU_Skew1 Bit 5 -- CPU_Skew0 Bit 4 -- Bit 3 -- PCI_Skew1 Bit 2 -- PCI_Skew0 Bit 1 -- 3V66_Skew1 Bit 0 -- 3V66_Skew0 0 0 0 0 Data Byte 11 Bit Pin# Name Bit 7 -- ROCV_FREQ_N7 Bit 6 -- ROCV_FREQ_N6 Bit 5 -- ROCV_FREQ_N5 Bit 4 -- ROCV_FREQ_N4 Bit 3 -- ROCV_FREQ_N3 Bit 2 -- ROCV_FREQ_N2 Bit 1 -- ROCV_FREQ_N1 Bit 0 -- ROCV_FREQ_N0 Power On Default Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 0 0 0 0 0 0 0 Data Byte 12 Bit Bit 7 Pin# -- Name ROCV_FREQ_SEL Rev 1.0, November 21, 2006 Power On Default Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] 0 Page 9 of 21 CY28344 Data Byte 12 (continued) Bit Pin# Name Bit 6 -- ROCV_FREQ_M6 Bit 5 -- ROCV_FREQ_M5 Bit 4 -- ROCV_FREQ_M4 Bit 3 -- ROCV_FREQ_M3 Bit 2 -- ROCV_FREQ_M2 Bit 1 -- ROCV_FREQ_M1 Bit 0 -- ROCV_FREQ_M0 Power On Default Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs. The setting of FS_Override bit determine the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 0 0 0 0 0 0 Data Byte 13 Bit Pin# Name Bit 7 -- CPU_FSEL_N7 Bit 6 -- CPU_FSEL_N6 Bit 5 -- CPU_FSEL_N5 Bit 4 -- CPU_FSEL_N4 Bit 3 -- CPU_FSEL_N3 Bit 2 -- CPU_FSEL_N2 Bit 1 -- CPU_FSEL_N1 Bit 0 -- CPU_FSEL_N0 Power On Default Pin Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 0 0 0 0 0 0 0 Data Byte 14 Bit Pin# Name Power On Default Pin Description Bit 7 -- Pro_Freq_EN Programmable output frequencies enabled 0 = disabled 1 = enabled 0 Bit 6 -- CPU_FSEL_M6 0 Bit 5 -- CPU_FSEL_M5 Bit 4 -- CPU_FSEL_M4 Bit 3 -- CPU_FSEL_M3 Bit 2 -- CPU_FSEL_M2 Bit 1 -- CPU_FSEL_M1 Bit 0 -- CPU_FSEL_M0 If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 0 0 0 0 0 Data Byte 15 Bit Pin# Name Pin Description Power On Default Bit 7 -- Reserved Reserved 0 Bit 6 -- Reserved Reserved 0 Bit 5 -- Reserved Reserved 0 Bit 4 -- Reserved Reserved 0 Bit 3 -- Reserved Reserved 0 Bit 2 -- Reserved Reserved 0 Bit 1 -- Vendor Test Mode Reserved. Write with “1” 1 Bit 0 -- Vendor Test Mode Reserved. Write with “1” 1 Rev 1.0, November 21, 2006 Page 10 of 21 CY28344 Data Byte 16 Bit Pin# Name Pin Description Power On Default Bit 7 -- Reserved Reserved 0 Bit 6 -- Reserved Reserved 0 Bit 5 -- Reserved Reserved 0 Bit 4 -- Reserved Reserved 0 Bit 3 -- Reserved Reserved 0 Bit 2 -- Reserved Reserved 0 Bit 1 -- Reserved Reserved 0 Bit 0 -- Reserved Reserved 0 Data Byte 17 Bit Pin# Name Pin Description Power On Default Bit 7 -- Reserved Reserved 0 Bit 6 -- Reserved Reserved 0 Bit 5 -- Reserved Reserved 0 Bit 4 -- Reserved Reserved 0 Bit 3 -- Reserved Reserved 0 Bit 2 -- Reserved Reserved 0 Bit 1 -- Reserved Reserved 0 Bit 0 -- Reserved Reserved 0 Rev 1.0, November 21, 2006 Page 11 of 21 CY28344 Table 4. Frequency Selection Table Input Conditions Output Frequency FS4 FS3 FS2 FS1 FS0 SEL4 Bit[2] SEL3 Bit[7] SEL2 Bit[6] SEL1 Bit[5] SEL0 Bit[4] CPU 3V66 PCI PLL Gear Constants (G) 0 0 0 0 0 100.90 67.27 33.63 48.00741 0 0 0 0 1 100.00 66.67 33.33 48.00741 0 0 0 1 0 103.00 68.67 34.33 48.00741 0 0 0 1 1 105.00 70.00 35.00 48.00741 0 0 1 0 0 107.00 71.33 35.67 48.00741 0 0 1 0 1 109.00 72.67 36.33 48.00741 0 0 1 1 0 111.00 74.00 37.00 48.00741 0 0 1 1 1 114.00 76.00 38.00 48.00741 0 1 0 0 0 117.00 78.00 39.00 48.00741 0 1 0 0 1 120.00 80.00 40.00 48.00741 0 1 0 1 0 127.00 84.67 42.33 48.00741 0 1 0 1 1 130.00 86.67 43.33 48.00741 0 1 1 0 0 133.33 88.89 44.44 48.00741 0 1 1 0 1 170.00 56.67 28.33 48.00741 0 1 1 1 0 180.00 60.00 30.00 48.00741 0 1 1 1 1 190.00 63.33 31.67 48.00741 1 0 0 0 0 133.90 66.95 33.48 48.00741 1 0 0 0 1 133.33 66.67 33.33 48.00741 1 0 0 1 0 120.00 60.00 30.00 48.00741 1 0 0 1 1 125.00 62.50 31.25 48.00741 1 0 1 0 0 134.90 67.45 33.73 48.00741 1 0 1 0 1 137.00 68.50 34.25 48.00741 1 0 1 1 0 139.00 69.50 34.75 48.00741 1 0 1 1 1 141.00 70.50 35.25 48.00741 1 1 0 0 0 143.00 71.50 35.75 48.00741 1 1 0 0 1 145.00 72.50 36.25 48.00741 1 1 0 1 0 150.00 75.00 37.50 48.00741 1 1 0 1 1 155.00 77.50 38.75 48.00741 1 1 1 0 0 160.00 80.00 40.00 48.00741 1 1 1 0 1 170.00 85.00 42.50 48.00741 1 1 1 1 0 66.67 66.67 33.34 48.00741 1 1 1 1 1 200.00 66.67 33.33 48.00741 Rev 1.0, November 21, 2006 Page 12 of 21 CY28344 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 – 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. Table 5. Register Summary Name Description Pro_Freq_EN Programmable output frequencies enabled 0 = disabled (default) 1 = enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs. FS_Override When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes CPU_FSEL_N, CPU_FSEL_M When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. WD_EN 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. WD_TO_STATUS Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) Rev 1.0, November 21, 2006 Page 13 of 21 CY28344 Table 5. Register Summary (continued) Name Description WD_TIMER[4:0] These bits store the time-out value of the Watchdog timer. The scale of the timer is determined by the prescaler. The timer can support a value of 150 ms – 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec – 80 sec. When the Watchdog timer reaches “0,” it will set the WD_TO_STATUS bit. WD_PRE_SCALER 0 = 150 ms 1 = 2.5 sec RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Program the CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3). “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 4. The ratio of (N+3) and (M+3) needs to be greater than “1” [(N+3)/(M+3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example uses a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Table 6. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges Gear Constants Fixed Value for M-Value Register Range of N-Value Register for Different CPU Frequency 50 MHz – 129 MHz 48.00741 93 97 – 255 130 MHz – 248 MHz 48.00741 45 127 – 245 Rev 1.0, November 21, 2006 Page 14 of 21 CY28344 Maximum Ratings[2] Storage Temperature (Non-Condensing) ....–65qC to +150qC (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ....................... +260qC Supply Voltage..................................................–0.5 to +7.0V Package Power Dissipation............................................... 1: Input Voltage.............................................. –0.5V to VDD+0.5 Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................ > 2000V Junction Temperature................................................ +150qC Operating Conditions Over which Electrical Parameters are Guaranteed Parameter Description Min. Max. Unit V VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_48 MHz, VDD_CPU, 3.3V Supply Voltages 3.135 3.465 VDD_48 MHz 48 MHz Supply Voltage 2.85 3.465 V TA Operating Temperature, Ambient 0 70 qC Cin Input Pin Capacitance 5 pF CXTAL XTAL Pin Capacitance 22.5 pF CL Max. Capacitive Load on 48 MHz, REF PCICLK, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage VIL Low-level Input Voltage Except Crystal Pads VOH High-level Output Voltage 48 MHz, REF, 3V66 IOH = –1 mA 2.4 V PCI IOH = –1 mA 2.4 V 48 MHz, REF, 3V66 IOL = 1 mA 0.4 V PCI IOL = 1 mA 0.55 V VOL Low-level Output Voltage Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 2.0 V 0.8 V IIH Input High Current 0 < VIN < VDD –5 5 mA IIL Input Low Current 0 < VIN < VDD –5 5 mA IOH High-level Output Current CPU For IOH = 6*IRef Configuration Type X1, VOH = 0.74V REF, 48 MHz Type 3, VOH = 1.00V Type X1, VOH = 0.65V 12.9 14.9 –29 Type 3, VOH = 3.135V 3V66, PCI Type 5, VOH = 1.00V –23 –33 Type 5, VOH = 3.135V IOL Low-level Output Current REF, 48 MHz Type 3, VOL = 1.95V –33 29 Type 3, VOL = 0.4V 3V66, PCI, Type 5, VOL =1.95 V Type 5, VOL = 0.4V IOZ Output Leakage Current IDD3 IDDPD3 Three-state mA mA 27 30 38 10 mA 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 250 mA 3.3V Shutdown Current 20 mA VDD_CORE/VDD3.3 = 3.465V Note: 2. The voltage on any input or any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Rev 1.0, November 21, 2006 Page 15 of 21 CY28344 - Switching Characteristics[3] Over the Operating Range, PCI,3V66 Clock Outputs.(Lump CapacitanceTest Load = 20 pF) Parameter Output Description Test Conditions Min. Max. Unit t1 All Output Duty Cycle[4] Measured at 1.5V 45 55 % t3 USB, REF, DOT Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 ps t3 PCI,3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t5 3V66[0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps t5 66BUFF[0:2] 66BUFF-66BUFF Skew Measured at 1.5V 175 ps t6 PCI PCI-PCI Skew Measured at 1.5V 500 ps t7 3V66,PCI 3V66-PCI Clock Jitter 3V66 leads. Measured at 1.5V 3.5 ns t9 3V66 Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps t9 USB, DOT Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps 1.5 CPU 1.0V Switching Characteristics t2 CPU RiseTime Measured differential waveform from –0.35V to +0.35V 175 467 ps t3 CPU Fall Time Measured differential waveform from –0.35V to +0.35V 175 467 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B 150 ps 325 mV CPU Rise/Fall Matching Measured with test loads[5] loads[5] 0.92 1.45 V Voh CPU High-level Output Voltage including overshoot Measured with test Vol CPU Low-level Output Voltage including undershoot Measured with test loads[5] -0.2 0.35 V Vcrossover CPU Crossover Voltage Measured with test loads[5] 0.51 0.76 V CPU 0.7V Switching Characteristics t2 CPU RiseTime Measured single ended waveform from 0.175V to 0.525V 175 700 ps t3 CPU Fall Time Measured single ended waveform from 0.175V to 0.525V 175 700 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B With all outputs running 150 ps CPU Rise/Fall Matching Measured with test loads[3,4] 20 % 0.85 V loads[4] Voh CPU High-level Output Voltage including overshoot Measured with test Vol CPU Low-level Output Voltage including undershoot Measured with test loads[4] -0.15 Vcrossover CPU Crossover Voltage Measured with test loads[4] 0.28 V 0.43 V Notes: 3. All parameters specified with loaded outputs. 4. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 5. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge. 6. The 0.7V test load is Rs = 33.2 ohm, Rp = 49.9 ohm in test circuit. 7. The 1.0V test load is shown on test circuit page. Rev 1.0, November 21, 2006 Page 16 of 21 CY28344 Switching Waveforms Duty Cycle Timing (Single-Ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD OUTPUT 0V t3 t2 CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 Rev 1.0, November 21, 2006 Page 17 of 21 CY28344 Switching Waveforms (continued) PCI-PCI Clock Skew PCI PCI t6 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A t8B Host_b Host Cycle-Cycle Clock Jitter t9A t9B CLK Rev 1.0, November 21, 2006 Page 18 of 21 CY28344 Layout Example +3.3V Supply FB VDDQ3 0.005PF 10 PF C2 G C1 G G V G G G V G 10 G G G 11 12 13 14 15 16 17 18 19 20 21 22 23 24 V G V G Core V G 48 47 G 46 V 45 44 G 43 42 V 41 G 40 39 38 37 G 36 35 G 34 *Option A 33 G G 32 31 V 30 29 G 28 27 26 G 25 G G G CY28344 1 2 3 4 5 6 7 8 9 G VDDQ3 : C5 G *Option B G C6 G FB = Dale ILB1206 – 300 or 2TDKACB2012L – 120 or 2 Murata BLM21B601S Ceramic Caps C1 = 10 – 22 PF C2 = 0.005 PF C5 = 0.1 PF C6 = 10 PF G = VIA to GND plane layer V = VIA to respective supply plane layer Note. Each supply plane or strip should have a ferrite bead and capacitors. * If on-board video uses 48 MHz or Dot clock uses Option B All bypass caps on VDD pin = 0.1 uF Low ESR Rev 1.0, November 21, 2006 Page 19 of 21 CY28344 Test Circuit VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU 0.7V Test Load 4, 8, 14, 19, 25, 29, 32, 36, 42 Rp 7, 13, 18, 24, 30, 33, 41, 45 Ref,USB Outputs Test Node Rs Test Nodes OUTPUTS 20 pF PCI,3V66 Outputs Test Node 2pF CPU 2pF Rs Rp 30 pF Note: Each supply pin must have an individual decoupling capacitor. Note: All capacitors must be placed as close to the pins as is physically possible. 0.7V amplitude: RS = 33 ohm, RP = 50 ohm VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU 4, 8, 14, 19, 25, 29, 32, 36, 42 1.0V Test Load 33 7, 13, 18, 24, 30, 33, 41, 45 2pF Ref,USB Outputs Test Node 475 CPU 33 OUTPUTS 20 pF Test Nodes 2pF PCI,3V66 Outputs Test Node 30 pF Rev 1.0, November 21, 2006 63.4 63.4 1.0V Amplitude Page 20 of 21 CY28344 Ordering Information Ordering Code CY28344PVC Package Type 48-pin Small Shrunk Outline Package (SSOP) Operating Range Commercial Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 51-85061-B While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 Page 21 of 21