CY28408 Clock Synthesizer with Differential CPU Outputs Features • Six copies of 3V66 clocks • Compatible to Intel® CK 408 Mobile Clock Synthesizer • Support Intel P4 and Brookdale CPU • Specifications • SMBus support with read back capabilities • Spread Spectrum electromagnetic interference (EMI) reduction • Dial-A-Frequency® features • 3.3V power supply • Dial-A-dB features • Three differential CPU clocks • 56-pin TSSOP package • Ten copies of PCI clocks Table 1. Frequency Table[1] S2 S1 S0 CPU(0:2) 3V66 PCI_PCIF REF USB/DOT 1 0 0 100 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 133 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 1 0 1 1 1 0 Reserved 1 1 1 166 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 0 0 0 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 100 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 0 0 1 0 1 0 Reserved 0 1 1 133 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz M 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z M 0 1 TCLK/2 TCLK/4 TCLK/8 TCLK TCLK/2 Pin Configuration Block Diagram XIN XOUT CPUT(0:2) CPUC(0:2) PLL1 CPU_STP# IREF VSSIREF 3V66_0 S(0:2) 3V66_1/VCH MULT0 VTT_PWRGD# /2 PCI_STP# PCI(0:6) PCI_F(0:2) PLL2 48M_USB 48M_DOT PD# WD Logic SDATA SCLK I2C Logic VDDA Power Up Logic 3V66[2:5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CY28408 VDD XIN XOUT VSS PCIF0 PCIF1 PCIF2 VDD VSS PCI0 EPCI1/PCI1 PCI2 EPCI3/PCI3 VDD VSS PCI4 PCI5 PCI6 VDD VSS 3V66_2 3V66_3 3V66_4 3V66_5 PD# VDDA VSSA VTT_PWRGD# REF 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF S1 S0 CPU_STP# CPUT0 CPUC0 VDD CPUT1 CPUC1 VSS VDD CPUT2 CPUC2 MULT0 IREF VSSIREF S2 48M_USB 48M_DOT VDD VSS 3V66_1/VCH PCI_STP# 3V66_0 VDD VSS SCLK SDATA Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, an 0 state will be latched into the device’s internal state register. Cypress Semiconductor Corporation Document #: 38-07617 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 17, 2003 CY28408 Pin Description Pin 2 3 Name XIN XOUT 52, 51, 49, 48, CPUT(0:2), 45, 44 CPUC(0:2) 10, 12, 16, 17, 18 PCI(0,2)/(3:5) 11,13 EPCI/PCI(1,3) PWR VDD VDD I/O I O VDD O VDDP VDD Description Oscillator buffer input. Connect to a crystal or to an external clock. Oscillator buffer output. Connect to a crystal. Do not connect when an external clock is applied at XIN. Differential host output clock pairs. See Table 1 for frequencies and functionality. PCI clock outputs. Synchronous to the 3V66 clock. See Table 1. Early or normal PCI clock outputs. There is an internal 250kΩ pull-down resistor. See Table 8. 33-MHz PCI clocks, which are ÷2 copies of 3V66 clocks, may be free running (not stopped when PCI_STP# is asserted LOW) or may be stoppable depending on the programming of SMBus register Byte3, Bits (3:5). Buffered output copy of the device’s XIN clock. Current reference programming input for CPU buffers. A resistor is connected between this pin and VSSIREF. Qualifying input that latches S(0:2) and MULT0. When this input is at a logic low, the S(0:2) and MULT0 are latched Fixed 48-MHz USB clock outputs. Fixed 48-MHZ DOT clock outputs. 3.3V 66-MHz fixed frequency clock. 3.3V clock selectable with SMBus byte0, Bit5, when Byte5, Bit5. When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When byte0, Bit5 is a logic 0, then this is a 66-MHz output clock (default). 3.3V 66-MHz fixed frequency clock. This pin is a power-down mode pin. A logic LOW level causes the device to enter a power-down state. All internal logic is turned off except for the SMBus logic. All output buffers are stopped. Programming input selection for CPU clock current multiplier. 0 = 4 * IREF, 1 = 6 * =IREF Frequency select inputs. See Table 1 Serial data input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. Serial clock input. Conforms to the SMBus specification. 5, 6, 7 PCIF (0:2) VDD O I/O PD O 56 42 REF IREF VDD VDD O I 28 VTT_PWRGD# VDD I 39 38 33 35 48M_USB 48M_DOT 3V66_0 3V66_1/VCH VDD48 VDD48 VDD VDD O O O O 21, 22, 23, 24 25 3V66(2:5) PD# VDD VDD O I PU 43 MULT0 VDD 55, 54 29 S(0,1) SDATA VDD VDD I PU I I/O PU 30 SCLK VDD 40 S2 VDD 34 PCI_STP# VDD 53 CPU_STP# VDD 1, 8, 14, 19, 32, 37, 46, 50 4, 9, 15, 20, 27, 31, 36, 47 41 VDD – Frequency select input. See Table 1. This is a tri-level input that is driven HIGH, LOW, or driven to a intermediate level. PCI clock disable input. When asserted LOW, PCI (0:6) clocks are synchronously disabled in a LOW state. This pin does not effect PCIF (0:2) clock outputs if they are programmed to be PCIF clocks via the device’s SMBus interface. I CPU clock disable input. When asserted LOW, CPUT (0:2) clocks are PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchronously disabled in a LOW state. PWR 3.3V power supply. VSS – PWR Common ground. VSSIREF – 26 VDDA – PWR Current reference programming input for CPU buffers. A resistor is connected between this pin and IREF. This pin should also be returned to device VSS. PWR Analog power input. Used for PLL and internal analog circuits. It is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate. Document #: 38-07617 Rev. ** I PU I T I PU Page 2 of 19 CY28408 Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The clock driver serial protocol accepts block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Write 10 18:11 19 27:20 28 36:29 37 45:38 Bit 1 Slave address – 7 bits 9 Block Read Protocol 8:2 Description Start Slave address – 7 bits 9 Write Acknowledge from slave 10 Acknowledge from slave Command Code – 8 Bits 18:11 Command Code – 8 Bits Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start Acknowledge from slave 27:21 Slave address – 7 bits Data byte 1 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N –8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Bte N from slave – 8 bits .... NOT Acknowledge ... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 Description Start Slave address – 7 bits Write Byte Read Protocol Bit 1 8:2 9 Description Start Slave address – 7 bits Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits Document #: 38-07617 Rev. ** Page 3 of 19 CY28408 Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 19 27:20 Byte Read Protocol Description Bit Acknowledge from slave 19 Data byte – 8 bits 20 28 Acknowledge from slave 29 Stop 27:21 Description Acknowledge from slave Repeated start Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Byte 0: CPU Clock Register[2] Bit @Pup Name Description 0 Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On This is a Read and Write control bit. 6 0 CPU clock Power-down Mode Select. 0 = Drive CPUT to 4 or 6 IREF and drive CPUC to low when PD# is asserted LOW. 1 = Three-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to CPU_STP#. 5 0 3V66_1/VCH 4 Pin 53 CPU_STP# Reflects the current value of the external CPU_STP#. This bit is Read-only. 3 Pin 34 PCI_STP# Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin. This is a Read and Write control bit. 2 Pin 40 SEL2 Frequency Select Bit 2. Reflects the value of SEL2. This bit is Read-only. 1 Pin 55 SEL1 Frequency Select Bit 1. Reflects the value of SEL1. This bit is Read-only. 0 Pin 54 SEL0 Frequency Select Bit 0. Reflects the value of SEL0. This bit is Read-only. 7 3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected This is a Read and Write control bit. Byte 1: CPU Clock Register Bit @Pup 7 Pin 43 Name Description MULT0 Value. This bit is Read-only. 6 0 Controls functionality of CPUT/C outputs when CPU_STP# is asserted. 0 = Drive CPUT to 4 or 6 IREF and drive CPUC to low when CPU_STP# is asserted LOW. 1 = Tri-state all CPU outputs when CPU_STP# is asserted.This bit will override Byte0, Bit6 such that even if it is a 0, when PD# goes low the CPU outputs will be tri-stated. 5 0 Controls CPU2 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 4 0 Controls CPU1 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 3 0 Controls CPUT0 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. 2 1 CPUT/C2 CPUT/C2 Output Control 1 = enabled, 0 = three-state CPUT/C2 This is a Read and Write control bit. Note: 2. PU = Internal Pull-up. PD = Internal Pull-down. T = Tri-level logic input. Document #: 38-07617 Rev. ** Page 4 of 19 CY28408 Byte 1: CPU Clock Register (continued) Bit @Pup Name Description 1 1 CPUT/C1 CPUT/C1 Output Control 1 = enabled, 0 = three-state CPUT/C1 This is a Read and Write control bit. 0 1 CPUT/C0 CPUT/C0 Output Control 1 = enabled, 0 = three-state CPUT/C0 This is a Read and Write control bit. Byte 2: PCI Clock Control Register (all bits are read- and write-functional) Bit @Pup Name Description 7 0 REF REF Output Control. 0 = high strength, 1 = low strength 6 1 PCI6 PCI6 Output Control 1 = enabled, 0 = forced LOW 5 1 PCI5 PCI5 Output Control 1 = enabled, 0 = forced LOW 4 1 PCI4 PCI4 Output Control 1 = enabled, 0 = forced LOW 3 1 PCI3 PCI3 Output Control 1 = enabled, 0 = forced LOW 2 1 PCI2 PCI2 Output Control 1 = enabled, 0 = forced LOW 1 1 PCI1 PCI1 Output Control 1 = enabled, 0 = forced LOW 0 1 PCI0 PCI0 Output Control 1 = enabled, 0 = forced LOW Byte 3: PCI_F Clock and 48M Control Register (all bits are read- and write-functional) Bit @Pup Name 7 1 48M_DOT 48M_DOT Output Control 1 = enabled, 0 = forced LOW 6 1 48M_USB 48M_USB Output Control 1 = enabled, 0 = forced LOW 5 0 PCI_STP#, control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 4 0 PCI_STP#, control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 3 0 PCI_STP#, control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW 2 1 PCI_F2 PCI_F2 Output Control 1 = running, 0 = forced LOW 1 1 PCI_F1 PCI_F1 Output Control 1 = running, 0 = forced LOW 0 1 PCI_F0 PCI_F0 Output Control 1 = running, 0 = forced LOW Document #: 38-07617 Rev. ** Description Page 5 of 19 CY28408 Byte 4: 3V66 Control Register (all bits are read- and write-functional) Bit @Pup Name Description 7 0 SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread) 6 0 Reserved 5 1 3V66_0 4 1 3V66_1/VCH 3 1 3V66_5 3V66_5 Output Enable 1 = enabled, 0 = disabled 2 1 3V66_4 3V66_4 Output Enabled 1 = enabled, 0 = disabled 1 1 3V66_3 3V66_3 Output Enabled 1 = enabled, 0 = disabled 0 1 3V66_2 3V66_2 Output Enabled 1 = enabled, 0 = disabled 3V66_0 Output Enabled, 1 = enabled, 0 = disabled 3V66_1/VCH Output Enable 1 = enabled, 0 = disabled Byte 5: Spread Spectrum Control Register (all bits are read and write functional) Bit @Pup Name Description 7 0 SS1 Spread Spectrum control bit 6 1 SS0 Spread Spectrum control bit 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 0 48M_DOT edge rate control. When set to 1, the edge is slowed by 40%. 1 0 Reserved 0 0 USB edge rate control. When set to 1, the edge is slowed by 40%. Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI reduction generated by repetitive digital signals. A clock presents the generated EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. Table 5 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Table 5. Spread Spectrum SS2 SS1 SS0 Spread Mode Spread% 0 0 0 Down +0.00, –0.25 0 0 1 Down +0.00, –0.50 0 1 0 Down +0.00, –0.75 0 1 1 Down +0.00, –1.00 1 0 0 Center +0.13, –0.13 1 0 1 Center +0.25, –0.25 1 1 0 Center +0.37, –0.37 1 1 1 Center +0.50, –1.50 Byte 6: Silicon Signature Register (all bits are read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Document #: 38-07617 Rev. ** Description Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Page 6 of 19 CY28408 Byte 7: Reserved Bit @Pup Name Description 7 0 Reserved 6 0 Reserved 5 0 Reserved 4 0 Reserved 3 1 Reserved 2 1 Reserved 1 1 Reserved 0 0 N8, MSB Byte 8: Dial-a-Frequency Control Register N (all bits are read and write functional) Bit @Pup Name Description 7 0 N7 6 0 N6 5 0 N5 4 0 N4 3 0 N3 2 0 N2 1 0 N3 0 0 N0, LSB Byte 9: Dial-a-Frequency™ Control Register R (all bits are read and write functional) Bit @Pup 7 0 Name R6 MSB Description 6 0 R5 5 0 R4 4 0 R3 3 0 R2 2 0 R1 1 0 R0, LSB 0 0 R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from DAF (SMBus) registers. Dial-a-Frequency Feature USB and DOT 48M Phase Relationship SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. See our App Note AN-0025 for details on our Dial-a-Frequency feature. The 48M_USB and 48M_DOT clocks are normally in phase. It is understood that the difference in edge rate will introduce some inherent offset. When 3V66_1/VCH clock is configured for VCH (48-MHz) operation it is also in phase with the USB and DOT outputs. See Figure 1. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 6. Table 6. P Value S(1:0) P 00 32005333 01 48008000 10 96016000 11 64010667 Document #: 38-07617 Rev. ** Page 7 of 19 CY28408 48MUSB 48MDOT Figure 1. 48M_USB and 48M_DOT Phase Relationship Table 7. Group Timing Relationship and Tolerances Description 3V66 to PCI 48M_USB to 48M_DOT Skew 3V66 Offset Tolerance 2.5 ns ±1.0 ns 0 or 10.4 ns ±1.0 ns Conditions 3V66 Leads PCI Tpci PCI PCI_F Figure 2. 3V66 to PCI and PCI_F Phase Relationship 3V66_1/VCH Clock Output Table 8. Early PCI Select Functions[3] EPCI3 EPCI1 EPCI(3,1) 0 0 0.0 ns 1 0 0.8 ns 1 1 1.6 ns Special Functions PCI_F and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. ANY two of the PCI_F clock outputs can be used as IOAPIC 33-MHz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event these clocks are not required, then these clocks can be used as general PCI clocks or disabled via the assertion of the PCI_STP# pin. The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. If Byte0, Bit 5 = ‘1’, then the output is configured as a 48-MHz non-spread spectrum output. This output is phase aligned with the other 48M outputs (USB and DOT), to within 1 ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power on. When the SMBus Bit 5 of Byte 0 is programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH output may glitch while transitioning to 48M output mode. CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# – Assertion When CPU_STP# pin is asserted, all CPUT/C outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two falling CPUT/C clock edges. The final state of the stopped CPU signals is CPUT = HIGH and CPU0C = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal will not be driven. Due to external pull-down circuitry CPUC will be LOW during this stopped state. Note: 3. 0 = 10K Pull-down resistor, 1 = 10k Pull-up resistor. Document #: 38-07617 Rev. ** Page 8 of 19 CY28408 CPU_STP# CPUT CPUC CPUT CPUC Figure 3. CPU_STP# Assertion Waveform CPU_STP# CPUT CPUC CPUT CPUC Figure 4. CPU_STP# Deassertion Waveform Three-state Control of CPU Clocks Clarification CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces when the clock resumes. The maximum latency from the deassertion to active outputs is no more than 2 CPUC clock cycles. During CPU_STP# and PD# modes, CPU clock outputs may be set to driven or undriven (three-state) by setting the corresponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1. Table 9. Cypress Clock Power Management Truth Table B0b6 B1b6 PD# 0 0 1 CPU_STP# Stoppable CPUT 1 Stoppable CPUC Non-Stop CPUT Non-Stop CPUC Running Running Running Running 0 0 1 0 Iref x6 Iref x6 Running Running 0 0 0 1 Iref x2 Low Iref x2 Low 0 0 0 0 Iref x2 Low Iref x2 Low 0 1 1 1 Running Running Running Running 0 1 1 0 Hi Z Hi Z Running Running 0 1 0 1 Hi Z Hi Z Hi Z Hi Z 0 1 0 0 Hi Z Hi Z Hi Z Hi Z 1 0 1 1 Running Running Running Running 1 0 1 0 Iref x6 Iref x6 Running Running 1 0 0 1 Hi Z Hi Z Hi Z Hi Z 1 0 0 0 Hi Z Hi Z Hi Z Hi Z Document #: 38-07617 Rev. ** Page 9 of 19 CY28408 Table 9. Cypress Clock Power Management Truth Table (continued) B0b6 B1b6 PD# CPU_STP# Stoppable CPUT Stoppable CPUC Non-Stop CPUT Non-Stop CPUC 1 1 1 1 Running Running Running Running 1 1 1 0 Hi Z Hi Z Running Running 1 1 0 1 Hi Z Hi Z Hi Z Hi Z 1 1 0 0 Hi Z Hi Z Hi Z Hi Z PCI_STP# Assertion PD# (Power-down) Clarification The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see Figure 7). The PCI_F clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running. The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. PCI_STP# – Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCI_F clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. Note that the PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs to the function are logically ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the devices stoppable PCI clocks are not running. PD# – Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 x Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. t setup PCI_STP# PCI_F PCI Figure 5. PCI_STP# Assertion Waveform t setup PCI_STP# PCI_F PCI Figure 6. PCI_STP# Deassertion Waveform Document #: 38-07617 Rev. ** Page 10 of 19 CY28408 PD# CPUT CPUC PCI 3V66 48M_USB REF Figure 7. Power-down Assertion Timing Waveforms PD# – Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 1.8 ms. Tstable <1.8ms PD# CPUT CPUC PCI 3V66 48M_USB REF Tdrive_PWRDN# <300µs, >200mV Figure 8. Power-down Assertion Timing Waveforms Table 10.PD# Functionality PD# 3V66 PCI_F PCI USB/DOT 1 66 MHz 33 MHz 33 MHz 48 MHz 0 Low Low Low Low Document #: 38-07617 Rev. ** Page 11 of 19 CY28408 S0,S1 VTT_PWRGD# PWRGD 0.2-0.3mS Delay VDD Clock Gen Clock State Clock Outputs Clock VCO State 0 Device is not affected, VTT_PWRGD# is ignored. Wait for Sample Sels VTT_PWRGD# State 1 State 2 Off State 3 On On Off Figure 9. VTT_PWRGD# Timing Diagram S2 S1 Delay >0.25mS VTT_PWRGD# = Low Sample Inputs straps VDDA = 2.0V Wait for <1.8ms S0 Power Off S3 VDDA = off Normal Operation Enable Outputs VTT_PWRGD# = toggle Figure 10. Clock Generator Power-up/Run State Diagram Document #: 38-07617 Rev. ** Page 12 of 19 CY28408 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDD_A Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to V SS –0.5 VDD+0.5 VDC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 20.62 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 62.26 °C/W UL–94 Flammability Rating @1/8 in. MSL Moisture Sensitivity Level 2000 – V V–0 1 DC Electrical Specifications Parameter Description Conditions VDD, VDDA 3.3 Operating Voltage 3.3V ± 5% VILI2C Input Low Voltage SDATA, SCLK VIHI2C Input High Voltage SDATA, SCLK VIL Input Low Voltage VIH Input High Voltage VILS2 S2 Input Low Voltage VDD = 3.3V Min. Max. Unit 3.135 3.465 V – – 1.0 2.2 – – VSS – 0.5 0.8 V 2.0 VDD + 0.5 V VSS – 0.5 0.7 V VIMS2 S2 Input Mid Voltage VDD = 3.3V 1.2 1.6 V VIHS2 S2 Input High Voltage VDD = 3.3V 2.0 VDD + 0.5 V IIL Input Leakage Current except Pull-ups or Pull downs 0 < VIN < VDD –5 5 µA VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA – 0.4 V 2.4 – V –10 10 µA 2 5 pF IOZ High-Impedance Output Current CIN Input Pin Capacitance COUT Output Pin Capacitance 3 6 pF LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7VDD VDD V VXIL Xin Low Voltage 0 0.3VDD V IDD Dynamic Supply Current At 166 MHz and all outputs loaded per Table 11 and Figures 11 and 12 – 280 mA IPD Power-down Supply Current PD# Asserted, Byte0 bit 6=”1” – 2.0 mA Min. Max. Unit AC Electrical Specifications Parameter Description Condition Crystal TDC XIN Duty Cycle When driven from external source TPERIOD XIN period Measured at VDD/2 TR / TF XIN Rise and Fall Times TCCJ XIN Cycle to Cycle Jitter Document #: 38-07617 Rev. ** 47.5 52.5 % 69.841 71.0 ns Measured between 0.3VDD and 0.7VDD – 10.0 ns When driven from external source – 500 ps Page 13 of 19 CY28408 AC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit 45 55 % CPU at 0.7V TDC CPUT and CPUC Duty Cycle Measured at VOX TPERIOD 100MHz CPUT and CPUC Period Measured at VOX 5.9 6.1 ns TPERIOD 133 MHz CPUT and CPUC Period Measured at VOX 9.85 10.2 ns TPERIOD 166 MHz CPUT and CPUC Period Measured at VOX 7.35 7.65 ns TSKEW Any CPUT/C to CPUT/C Clock Skew See Figure 12 – 100 ps TCCJ CPUT/C Cycle to Cycle Jitter See Figure 12 TR / TF CPUT and CPUC Rise and Fall Times Measured from 0.175 to 0.525 TRFM Rise/Fall Matching Fraction of 2x(TR–TF)/(TR+TF) – 20 % ∆TR Rise Time Variation Measured from 0.175 to 0.525 – 150 ps ∆TF Fall Time Variation Measured from 0.525 to 0.175 VOX Crossing Point Voltage at 0.7V Swing See Figure 12 – 255 ps 175 1000 ps – 150 ps 280 430 mv CPU at 1.0V TDC CPUT and CPUC Duty Cycle Measured at VOX 45 55 % TPERIOD 100MHz CPUT and CPUC Period Measured at VOX 5.9 6.1 ns TPERIOD 133 MHz CPUT and CPUC Period Measured at VOX 9.85 10.2 ns TPERIOD 166 MHz CPUT and CPUC Period Measured at VOX 7.35 7.65 ns TSKEW Any CPUT/C to CPUT/C Clock Skew See Figure 11 – 100 ps TCCJ CPUT/C Cycle to Cycle Jitter See Figure 11 – 255 ps TR / TF CPUT and CPUC Rise and Fall Times Measured differentially from –0.35 to 0.35 175 1000 ps VOX Crossing Point Voltage at 0.7V Swing See Figure 11 510 760 mv ∆ Slew Absolute Single Ended Rise/Fall Waveform Symmetry Measured from 0.41 to 0.36 – 325 ps 3V66 Duty Cycle Measured at 1.5V 45 55 % TPERIOD 3V66 Period Measured at 1.5V 15.0 15.3 ns THIGH 3V66 High Time Measured at 2.4V 4.95 – ns TLOW 3V66 Low Time Measured at 0.4V 4.55 – ns TR / TF 3V66 Rise and Fall Times Measured from 0.4V to 2.4V 0.5 2.3 ns TSKEW Any 3V66 to Any 3V66 Clock Skew Measured at 1.5V – 500 ps TCCJ 3V66 Cycle to Cycle Jitter Measured at 1.5V. See Table 11 – 400 ps PCI /PCI_F Duty Cycle Measure at 1.5V 45 55 % TPERIOD PCIF/PCI Period Measured at 1.5V 30 ns THIGH PCIF and PCI high time Measured at 1.5V 12.0 – ns TLOW PCIF and PCI low time Measured at 0.4V 12.0 – ns TR / TF PCIF and PCI rise and fall times Measured at 0.4V to 2.4V 0.5 2.3 ns TSKEW Any PCI clock to Any PCI clock Skew Measured at 1.5V – 500 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measured at 1.5V. See Table 11 – 325 ps 48M_DOT TDC Duty Cycle Measured at 1.5V 45 55 TPERIOD Period Measured at 1.5V 20.837 TR / TF Rise and Fall Times Measured at 0.4 to 2.4V TCCJ REF Cycle to Cycle Jitter Measured at 1.5V. See Table 11 3V66 TDC PCI/PCIF TDC Document #: 38-07617 Rev. ** % ns 0.5 1.0 ns – 350 ps Page 14 of 19 CY28408 AC Electrical Specifications (continued) Parameter Description Min. Max. Unit Measured at 1.5V 45 55 % Period Measured at 1.5V 20.8299 20.8333 ns Rise and Fall Times Measured at 0.4 to 2.4V 1.0 2.0 ns TCCJ Cycle to Cycle Jitter Measured at 1.5V. See Table 11 – 350 ps REF TDC REF Duty Cycle Measured at 1.5V 45 55 % TPERIOD REF Period Measured at 1.5V 69.84 71.0 ns TR / TF REF Rise and Fall Times Measured at 0.4 to 2.4V 0.5 2.0 V/ns TCCJ REF Cycle to Cycle Jitter Measured at 1.5V. See Table 11 48M_USB TDC Duty Cycle TPERIOD TR / TF Condition – 1000 ps ENABLE/DISABLE and SETUP TPZL/TPZH Output Enable Delay (all outputs) 1.0 10.0 ns TPLZ/TPHZ Output Disable Delay (all outputs) 1.0 10.0 ns TSTABLE Clock Stabilization from Power-up – 3.0 ms TSS Stopclock Setup Time 10.0 – ns TSH Stopclock Hold Time 0 – ns Table 11.Maximum Lumped Capacitive Output Loads Clock PCI Clocks Max Load Unit 30 pF 3V66 30 pF 48M_USB Clock 20 pF 48M_DOT 10 pF REF Clock 50 pF Document #: 38-07617 Rev. ** Page 15 of 19 CY28408 Test and Measurement Set-up For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs. T PCB CPUT 33.2Ω M eas ure m en t P o int 2p F 475 Ω M U LT S E L 33.2Ω T PCB CPUC 63.4Ω M easurem ent P oin t 2pF 6 3.4Ω 2 21Ω Figure 11. 1.0V Test Load Termination TPCB 33Ω VDD Measurement Point CPUT 49.9Ω 2pF MULTSEL TPCB 33Ω CPUC 49.9Ω Measurement Point 2pF 475Ω Figure 12. 0.7V Test Load Termination Document #: 38-07617 Rev. ** Page 16 of 19 CY28408 For Single-Ended Output Signals Output under Test Probe Load Cap 3.3V signals tDC - - 3.3V 2.4V 1.5V 0.4V 0V Tr Tf Figure 13. Buffer Characteristics Current Mode CPU Clock Buffer Characteristics The current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. The following parameters are used to specify output buffer characteristics: 1. Output impedance of the current mode buffer circuit – Ro (see Figure 14). 2. Minimum and maximum required voltage operation range of the circuit – Vop (see Figure 14). 3. Series resistance in the buffer circuit – Ros (see Figure 14). 4. Current accuracy at given configuration into nominal test load for given configuration. VDD3 (3.3V +/- 5%) Slope ~ 1/R0 Ro Iout Ros 0V 1.2V Iout Vout = 1.2V max Vout Figure 14. Document #: 38-07617 Rev. ** Page 17 of 19 CY28408 Table 12.Host Clock (HCSL) Buffer Characteristics Characteristic Minimum Maximum Ro 3000 Ohms (recommended) N/A N/A 1.2V Ros Vout Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage at the pin of the device. The various output current configurations are shown in the host swing select functions table. For all configurations, the deviation from the expected output current is ±7% as shown in the current accuracy table. Table 13.CPU Clock Current Select Function Mult0 Board Target Trace/Term Z Reference R, Iref – Vdd (3*Rr) Output Current Voh @ Z 0 50 Ohms Rr = 221 1%, Iref = 5.00mA Ioh = 4*Iref 1.0V @ 50 1 50 Ohms Rr = 475 1%, Iref = 2.32mA Ioh = 6*Iref 0.7V @ 50 Ordering Information Part Number Package Type Product Flow CY28408ZC 56-Pin TSSOP Commercial, 0° to 70°C CY28408ZCT 56-Pin TSSOP - Tape and Reel Commercial, 0° to 70°C Package Drawings and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56 0.249[0.009] 28 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 7.950[0.313] 8.255[0.325] PACKAGE WEIGHT 0.42gms 5.994[0.236] 6.198[0.244] PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 29 56 13.894[0.547] 14.097[0.555] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0°-8° SEATING PLANE 0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008] 51-85060-*C Intel is a registered trademark of Intel Corporation. Dial-A-Frequency is a registered trademark, and Dial-a-dB is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07617 Rev. ** Page 18 of 19 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28408 Document History Page Document Title: CY28408 Clock Synthesizer with Differential CPU Outputs Document Number: 38-07617 REV. ECN NO. Issue Date Orig. of Change ** 131468 12/22/03 RGL Document #: 38-07617 Rev. ** Description of Change New Data Sheet Page 19 of 19