CY7C192 64K x 4 Static RAM with Separate I/O Features Functional Description • High speed The CY7C192 is a high-performance CMOS static RAM organized as 65,536 x 4 bits with separate I/O. Easy memory expansion is provided by active LOW Chip Enable (CE) and tri-state drivers. It has an automatic power-down feature, reducing the power consumption by 75% when deselected. — 12 ns • CMOS for optimum speed/power • Low active power Writing to the device is accomplished when the Chip Enable (CE) and write enable (WE) inputs are both LOW. — 860 mW • Low standby power Data on the four input pins (I0 through I3) is written into the memory location specified on the address pins (A0 through A15). — 55 mW • TTL-compatible inputs and outputs • Automatic power-down when deselected Reading the device is accomplished by taking the Chip Enable (CE) LOW while the Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data output pins. • Available in non Pb-free 28-Lead Molded SOJ package. The output pins stay in high-impedance state when Write Enable (WE) is LOW, or Chip Enable (CE) is HIGH. A die coat is used to insure alpha immunity. Logic Block Diagram Pin Configurations I0 SOJ Top View I1 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 I0 I1 CE GND I2 I3 INPUT BUFFER 64K x 4 ARRAY SENSE AMPS O0 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 O1 O2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A5 A4 A3 A2 A1 A0 I3 I2 O3 O2 O1 O0 WE O3 POWER DOWN CE A10 A11 A12 A13 A14 A15 COLUMN DECODER WE Selection Guide -12 12 155 10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Cypress Semiconductor Corporation Document #: 38-05047 Rev. *C • 198 Champion Court -15 15 145 10 • Unit ns mA mA San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] Feedback CY7C192 DC Input Voltage[1].................................... −0.5V to VCC + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied.................................................. −55°C to +125°C Supply Voltage to Ground Potential .................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ........................................ −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................. >900V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range -12 Parameter Description Test Conditions Min. -15 Max. Min. VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.3V VIL Input LOW Voltage[1] −0.5 0.8 IIX Input Leakage Current GND < VI < VCC −5 +5 IOZ Output Leakage Current GND < VO < VCC, Output Disabled −5 +5 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 ISB2 2.4 Max. Unit 2.4 V 0.4 0.4 V 2.2 VCC + 0.3V V −0.5 0.8 V −5 +5 µA −5 +5 µA 155 145 mA Automatic CE Power-Down Max. VCC, CE > VIH, VIN > VIH or Current—TTL Inputs VIN < VIL, f = fMAX 30 30 mA Automatic CE Power-Down Max. VCC, CE > VCC − 0.3V, Current—CMOS Inputs VIN > VCC − 0.3V or VIN < 0.3V, f = 0 10 10 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 8 pF 10 pF AC Test Loads and Waveforms[4] R1 481Ω 5V OUTPUT R1 481Ω 5V ALL INPUT PULSES OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE (a) 3.0V R2 255Ω 5 pF INCLUDING JIG AND SCOPE (b) GND 10% 90% < tr 90% 10% < tr Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Notes: 1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. 4. tr = < 3 ns for the -12 and -15 speeds. tr = < 5 ns for the -20 and slower speeds. Document #: 38-05047 Rev. *C Page 2 of 8 [+] Feedback CY7C192 Switching Characteristics Over the Operating Range[5] -12 Parameter Description Min. -15 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 12 tAA Address to Data Valid tOHA Output Hold from Address Change tACE CE LOW to Data Valid [6] tLZCE CE LOW to Low Z CE HIGH to High Z tPU CE LOW to Power-Up tPD Write 12 3 3 15 15 5 ns ns 7 0 12 ns ns 3 0 CE HIGH to Power-Down ns 3 12 [6,7] tHZCE 15 ns ns 15 ns Cycle[8] tWC Write Cycle Time 12 15 ns tSCE CE LOW to Write End 9 10 ns tAW Address Set-Up to Write End 9 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 8 9 ns tSD Data Set-Up to Write End 8 9 ns tHD Data Hold from Write End 0 0 ns Z[6] tLZWE WE HIGH to Low tHZWE WE LOW to High Z[6,7] 3 3 7 ns 7 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZW\E is less than tLZWE for any given device. These parameters are guaranteed by design and not 100% tested. 7. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05047 Rev. *C Page 3 of 8 [+] Feedback CY7C192 Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2[9, 11] tRC CE tACE DATA OUT tHZCE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (WE Controlled)[8] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED Notes: 9. WE is HIGH for read cycle. 10. Device is continuously selected, CE = VIL. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05047 Rev. *C Page 4 of 8 [+] Feedback CY7C192 Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[8, 12] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tHD tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE Note: 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05047 Rev. *C Page 5 of 8 [+] Feedback CY7C192 Typical DC and AC Characteristics SB 1.4 1.2 ICC 0.8 VIN =5.0V TA =25°C 0.4 0.2 1.0 0.8 0.6 VCC =5.0V VIN =5.0V 0.4 0.2 ISB 0.0 4.0 1.2 4.5 5.0 5.5 ISB 0.0 –55 6.0 1.6 1.3 1.4 NORMALIZED tAA NORMALIZED tAA 1.4 1.2 1.1 TA =25°C 1.0 1.2 1.0 VCC =5.0V 0.8 0.9 4.5 5.0 5.5 6.0 0.6 -55 80 VCC =5.0V TA =25°C 60 40 20 0 0.0 1.0 25 TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 2.5 25.0 DELTA t AA (ns) 30.0 2.0 1.5 1.0 3.0 4.0 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 VCC =5.0V TA =25°C 40 20 0 0.0 125 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 3.0 2.0 OUTPUT VOLTAGE (V) AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) NORMALIZED I CC vs. CYCLE TIME 1.25 20.0 15.0 VCC =4.5V TA =25°C 10.0 1.00 VCC =5.0V TA =25°C VIN =0.5V 0.75 5.0 0.5 0.0 0.0 100 125 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 0.8 4.0 120 AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE (V) NORMALIZED IPO 25 OUTPUT SINK CURRENT (mA) 0.6 ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE NORMALIZED ICC 1.0 NORMALIZED ICC NORMALIZED ICC SB 1.4 OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) Document #: 38-05047 Rev. *C 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Page 6 of 8 [+] Feedback CY7C192 Ordering Information Speed (ns) Ordering Code 12 CY7C192-12VC 15 CY7C192-15VC Package Diagram 51-85031 Package Type Operating Range 28-Lead Molded SOJ Commercial Package Diagram 28-Lead (300-Mil) Molded SOJ (51-85031) NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE MIN. MAX. 3. DIMENSIONS IN INCHES DETAIL A EXTERNAL LEAD DESIGN PIN 1 ID 14 1 0.291 0.300 15 0.330 0.350 28 OPTION 1 0.697 0.713 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 0.050 TYP. 0.026 0.032 0.013 0.019 A 0.007 0.013 0.004 0.025 MIN. 0.262 0.272 51-85031-*C All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05047 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C192 Document History Page Document Title: CY7C192 64K x 4 Static RAM with Separate I/O Document Number: 38-05047 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107149 09/10/01 SZV Change Spec number from: 38-00076 to 38-05047 *A 359716 See ECN AJU Changed Static Discharge Voltage limit in the Maximum Ratings section (page 2) from 2001V to 900V Removed references to CY7C191 *B 419549 See ECN AJU Added Pb-free parts to the Ordering Information table and replaced the Package Name column with Package Diagram *C 492500 See ECN NXR Removed 20 ns and 25 ns speed bins Changed the Low active power from 220 mW to 55 mW Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Removed 28-Lead (300-Mil) PDIP package from product offering Updated Ordering Information table Document #: 38-05047 Rev. *C Page 8 of 8 [+] Feedback