EMC EM65101

EM65101
128COM/160SEG
16 Gray Scale Level
LCD Driver
Product
Specification
DOC. VERSION 0.4
ELAN MICROELECTRONICS CORP.
August 2005
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes
no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN
Microelectronics makes no commitment to update, or to keep current the information and material contained in
this specification. Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Hsinchu, Taiwan 30077
Tel: +886 3 563-9977
Fax: +886 3 563-9966
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information Technology
Group
Rm. 1005B, 10/F Empire
Centre
68 Mody Road, Tsimshatsui
Kowloon , HONG KONG
Tel: +852 2723-3376
Fax: +852 2723-7780
[email protected]
1821 Saratoga Ave., Suite 250
Saratoga, CA 95070
USA
Tel: +1 408 366-8223
Fax: +1 408 366-8220
Europe:
Shenzhen:
Shanghai:
Elan Microelectronics Corp.
(Europe)
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai Corporation, Ltd.
Siewerdtstrasse 105
8050 Zurich, SWITZERLAND
Tel: +41 43 299-4060
Fax: +41 43 299-4079
http://www.elan-europe.com
SSMEC Bldg., 3F, Gaoxin S.
Ave.
Shenzhen Hi-Tech Industrial Park
Shenzhen, Guandong,
CHINA
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
23/Bldg. #115 Lane 572, Bibo Road
Zhangjiang Hi-Tech Park
Shanghai, CHINA
Tel: +86 021 5080-3866
Fax: +86 021 5080-4600
Contents
Contents
1
General Description ...................................................................................... 1
2
Feature ........................................................................................................... 1
3
Applications ................................................................................................... 2
4
Pin Configurations ........................................................................................ 2
4.1
Alignment Key .................................................................................................... 2
4.2
Pin Dimensions .................................................................................................. 3
4.3
Recommended COG ITO Traces Resistor ......................................................... 3
4.3
PAD Coordinates Table ...................................................................................... 4
5
Functional Block Diagram ............................................................................ 9
6
Pin Description ............................................................................................ 10
7
6.1
Power Supply Pins ........................................................................................... 10
6.2
LCD Power Supply Circuit Pins........................................................................ 10
6.3
System Bus Pins .............................................................................................. 11
6.4
LCD Driver Circuit Signals................................................................................ 12
6.5
Oscillating Circuit Pins...................................................................................... 12
6.6
EEPROM Power Pins....................................................................................... 12
Functional Description................................................................................ 13
7.1
MPU Interface .................................................................................................. 13
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
Writing Data to Display RAM and Control Register .......................................... 15
7.2.1
7.2.2
7.3
Writing Data Operation......................................................................................15
Writing Data to Display RAM Data ....................................................................16
Y and X Address Circuits.................................................................................. 16
7.3.1
7.3.2
7.3.3
7.4
Reset Pin Description (RESB) ..........................................................................13
Selection of Interface Type................................................................................13
Parallel Input .....................................................................................................13
Read/Write Functions of the Register and Display RAM ..................................13
Serial Interface ..................................................................................................14
7.1.5.1 4-Wire Serial Interface........................................................................14
7.1.5.2 3-Wire Serial Interface........................................................................14
Y Address Circuit...............................................................................................16
X Address Circuit...............................................................................................16
EM65101 Display RAM Mapping ......................................................................18
Internal Register Read ..................................................................................... 19
7.4.1
7.4.2
Read Display RAM Operation ...........................................................................19
Register Read Operation ..................................................................................19
7.4
Display RAM Access Using Window Function ................................................. 20
7.5
Display RAM Data and LCD ............................................................................. 20
Product Specification (V0.4) 08.15.2005
• iii
Contents
7.6
Display Timing Circuit....................................................................................... 21
7.6.1
7.6.2
7.6.3
7.7
Signal Generation for the Display Line Counter and
the Display Data Latching Circuit ......................................................................21
Generation of the Alternate Signal M (Internal) and
the Synchronous Signal FLM (Internal).............................................................21
Display Data Latching Circuit ............................................................................21
LCD Driver Output Timing ................................................................................ 22
7.7.1
7.7.2
LCD Drive Circuit...............................................................................................22
Oscillator Circuit ................................................................................................22
7.8
Power Supply Circuit ........................................................................................ 23
7.9
Booster Circuit.................................................................................................. 23
7.10 Electronic Volume............................................................................................. 24
7.11 Voltage Regulator............................................................................................. 25
7.12 Voltage Generation Circuit ............................................................................... 25
7.13 EEPROM Function ........................................................................................... 27
7.13.1 EEPROM Program, Read, and Erase Flow Charts ..........................................28
7.13.2 Vop Calibration Offset Examples ......................................................................30
7.14 Partial Display Function.................................................................................... 33
7.15 Discharge Circuit .............................................................................................. 34
7.16 Scroll Function.................................................................................................. 34
7.17 Initial Values ..................................................................................................... 37
7.18 Safety Measures when Switching Power ON and OFF.................................... 37
7.18.1 When Using the External Power Supply ............................................................37
7.18.2 When Using the Built-in Power Supply ..............................................................38
7.18.3 Power Supply Rising Time .................................................................................38
7.19 Register Setting Examples ............................................................................... 39
7.19.1 Initialization ........................................................................................................39
7.19.2 Display Data .......................................................................................................40
7.19.3 Power OFF.........................................................................................................40
8
Control Register .......................................................................................... 41
8.1
Control Registers.............................................................................................. 41
8.1.1
8.1.2
8.1.3
8.2
Functions of the Control Registers ................................................................... 44
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
iv •
Control Register (Bank 0)..................................................................................41
Control Register (Bank 1)..................................................................................42
Control Register (Bank 2)..................................................................................43
X Address Register (AX) ...................................................................................44
Y Address Register (AY)....................................................................................44
n Line Alternated Register (N)...........................................................................45
Display Control Display (1) Register .................................................................46
Display Control (2) Register ..............................................................................46
Increment Control Register Set.........................................................................47
Power Control Register .....................................................................................50
LCD Duty (DS) ..................................................................................................51
Booster Setup (VU) ...........................................................................................52
Product Specification (V0.4) 08.15.2005
Contents
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.2.16
8.2.17
8.2.18
8.2.19
8.2.20
8.2.21
8.2.22
8.2.23
8.2.24
8.2.25
8.2.26
8.2.27
8.2.28
8.2.29
8.2.30
9
Bias Setting Register (B)...................................................................................52
Display Start Common.......................................................................................53
Temperature Compensation Set .......................................................................53
Electronic Volume Register ...............................................................................54
Internal Register Read Address ........................................................................55
Resistance Ratio of the CR Oscillator...............................................................55
Extended Power Control ...................................................................................56
Regulator Multiple Ratio Control .......................................................................56
Line Reverse Start Address...............................................................................57
Line Reverse End Address................................................................................58
Line Reverse Control.........................................................................................58
Window End X Address.....................................................................................59
Window End Y Address.....................................................................................59
EEPROM Mode Select Register .......................................................................60
Vop Calibration Offset Register.........................................................................60
EEPROM Address Select Register ...................................................................61
Scroll Top Address.............................................................................................61
Scroll Bottom Address .......................................................................................62
Scroll Specified Address....................................................................................62
Scroll Start Address ...........................................................................................63
Scroll Mode Select ............................................................................................63
Absolute Maximum Ratings........................................................................ 63
9.1
Recommended Operating Conditions .............................................................. 64
10 DC Characteristics ...................................................................................... 64
11 AC Characteristic ........................................................................................ 67
11.1 80-Family MCU Write Timing........................................................................... 67
11.2 80-Family MCU Read Timing .......................................................................... 68
11.3 68-Family MCU Write Timing........................................................................... 69
11.4 68-Family MCU Read Timing .......................................................................... 71
11.5 Serial Interface Timing Diagram ...................................................................... 72
11.6 Clock Input Timing........................................................................................... 73
11.7 Reset Timing ................................................................................................... 74
12 Application Circuit....................................................................................... 75
13 Tray Information .......................................................................................... 76
Product Specification (V0.4) 08.15.2005
•v
Contents
Specification Revision History
Doc. Version
0.1
Revision Description
Date
Initial version
January 10, 2005
1. Add pin related information
2. Modify reset time
0.2
3. Modify write timing
February 22, 2005
4. Add V0 specification
5. Modify application circuit on CK and VBA pins
6. Remove Nline reverse figure
0.3
1. Modify Extending command
March 08, 2005
2. Modify read EEPROM sequence
1. Modify Nline settingvalue
2. Modify the EEPROM programming voltage
3. Modify AXI, AIM function description
4. Remove the CF and VTC description
5. Modify the write timing on 68-family and SPI mode
6. The V4 voltage limit when setting bias=1/4 and 1/5
0.4
August 15, 2005
7. Modify the read address on RF register
8. Modify the DC spec with dynamic current and Fosc
9. Modify the contrast value setting
10. Modify the SC description
11. Add tray information
12. Modify application circuit and description on VREF
and VBA pins
vi •
Product Specification (V0.4) 08.15.2005
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
1
General Description
The EM65101 is an LCD controller for 16-level gray scale graphic dot-matrix liquid
crystal display system. It is a (160 x 128) for segment and common driver circuit. It has
a built-in display RAM, a power supply circuit for LCD driver. It also supports EEPROM
function for programming information to tune the VLCD offset voltage to get the best
contrast which helps in compacting system design. Its “partial display”1 function
realizes results in low power consumption.
2
Feature
16-level gray scale display with the PWM method
LCD output circuit:
160 segment / 128 common outputs
Display RAM capacity: 128 x 160 x 4 = 81920 bits
Built-in display RAM and power supply circuit:
Booster: 2 to 6 times
On-chip electronic contrast function (65 steps)
Voltage follower (LCD bias: 1/4 to 1/13)
Partial display function
Microprocessor interface:
8-bit parallel bi-direction interface with the 6800-series or 8080-series
4-line Serial Peripheral Interface (4-line SPI)
3-line Serial Peripheral Interface (3-line SPI)
Operating voltage range:
Logical power supply voltage: 2.2 to 3.3 V
Analog power supply voltage: 2.4 to 3.3 V
Screen scrolling function
EEPROM function to change the tuning LCD operating voltage Vop
Write cycle time: 200 ns
Package:
Part Number
Package
EM65101AH*
Bare chip (aluminum pad without bump, see Figure 4-1 below)
EM65101AGH*
Gold bumped chip
EM65101AF*
COF chip
EM65101AT*
TAB (TCP) chip
* EM65101=ELAN base P/N; A=package type version; H/GH/F/T=packaging category
1
A function that utilizes only part of the screen, thus reducing power consumption.
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
•1
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
3
Applications
Mobile phone
Small PDA
4
Pin Configurations
417
170
418
169
147
440
1
146
Figure 4-1 EM65101AH Pin Configuration (Sample)
NOTE
The ELAN logo is at the left side end and Pin1 is at the bottom-left corner.
4.1 Alignment Key
Mark
Coordinates (X,Y)
Mark
Coordinates (X,Y)
U-Left
-5019.95, 273.5
U-Right
5020.75, 273.5
D-Left
-5019.95, –321.65
D-Right
5020.75, –321.65
D-Left and D-Right:
U-Left and U-Right:
40
100um
20
100um
40
100um
40 20 40
100um
Figure 4-2 Pin Alignment Key
2•
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
4.2 Pin Dimensions
Item
Pad No.
Pad Pitch
X
Y
-
10850
1380
1 ~ 3 ; 144 ~ 146
4 ~ 51 ; 99 ~ 143
52 ~ 98
147 ~ 169 ; 418 ~ 440
88
35
50
96
38
78
61
28
170 ~ 417
1 ~ 3 ; 144 ~ 146
4 ~ 51 ; 99 ~ 143
52 ~ 98
147 ~ 169 ; 418 ~ 440
170 ~ 417
Min pitch
28
Chip size
Bump Size
Bump Size
Unit
96
103
50
65
43
43
43
Die thickness
(excluding bumps)
20 ± 1 mil (500 ± 25 um)
Bump Height
17 ± 3 um
Minimum Bump Gap
15 um
Coordinate Origin
Chip center
µm
4.3 Recommended COG ITO Traces Resistor
Interface
ITO Traces Resistances
V0~V4
CAP1+, CAP1-, CAP2+, CAP2-,CAP3+,CAP3CAP4+, CAP5+, VOUT, V2X
VDD, VEE, VSS
Max=50Ω
WRB,RDB,CSB,…, D0~D7
RESB
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Max=3KΩ
Max=5~10KΩ
•3
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
4.3 PAD Coordinates Table
4•
Pin No.
Pad Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DUMMY
DUMMY
DUMMY
DUMMY
VSS
TEST
P/S
VDD
M86
VSS
CSB
CSB
RESB
RS
RS
CK
CK
WRB
WRB
RDB
RDB
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
VSS
CKS
VDD
VDD
VDD
VDD
VBA
VREF
VPP
VPP
VPP
VSS
VSS
Coordinate
(X,Y)
-5305.0, -595.0
-5202.0, -595.0
-5099.0, -595.0
-5004.6, -579.0
-4954.6, -579.0
-4904.6, -579.0
-4854.6, -579.0
-4804.6, -579.0
-4754.6, -579.0
-4704.6, -579.0
-4654.6, -579.0
-4604.6, -579.0
-4554.6, -579.0
-4504.6, -579.0
-4454.6, -579.0
-4404.6, -579.0
-4354.6, -579.0
-4304.6, -579.0
-4254.6, -579.0
-4204.6, -579.0
-4154.6, -579.0
-4104.6, -579.0
-4054.6, -579.0
-4004.6, -579.0
-3954.6, -579.0
-3904.6, -579.0
-3854.6, -579.0
-3804.6, -579.0
-3754.6, -579.0
-3704.6, -579.0
-3654.6, -579.0
-3604.6, -579.0
-3554.6, -579.0
-3504.6, -579.0
-3454.6, -579.0
-3404.6, -579.0
-3354.6, -579.0
-3304.6, -579.0
-3254.6, -579.0
-3204.6, -579.0
-3154.6, -579.0
-3104.6, -579.0
-3054.6, -579.0
-3004.6, -579.0
-2954.6, -579.0
-2848.2, -579.0
-2798.2, -579.0
-2748.2, -579.0
-2698.2, -579.0
-2648.2, -579.0
Pin No.
Pad Name
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VSS
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
CAP5+
CAP5+
CAP3+
CAP3+
CAP3CAP3CAP3CAP3CAP2CAP2CAP2CAP2CAP2CAP2+
CAP2+
CAP2+
CAP2+
CAP2+
CAP2+
CAP4+
CAP4+
CAP4+
CAP4+
CAP4+
CAP4+
VEE
VEE
VEE
CAP1CAP1CAP1CAP1+
CAP1+
CAP1+
CAP1+
V2X
V2X
V2X
VSS
VSS
VSS
VSS
VSS
Coordinate
(X,Y)
-2598.2, -579.0
-2515.6, -587.5
-2450.6, -587.5
-2385.6, -587.5
-2320.6, -587.5
-2255.6, -587.5
-2190.6, -587.5
-2125.6, -587.5
-1780.1, -587.5
-1715.1, -587.5
-1369.3, -587.5
-1304.3, -587.5
-1239.3, -587.5
-932.3, -587.5
-867.3, -587.5
-802.3, -587.5
-737.3, -587.5
-672.3, -587.5
-430.3, -587.5
-365.3, -587.5
-300.3, -587.5
-235.3, -587.5
-170.3, -587.5
-105.3, -587.5
-40.3, -587.5
24.7, -587.5
89.7, -587.5
154.7, -587.5
219.7, -587.5
284.7, -587.5
349.7, -587.5
414.7, -587.5
479.7, -587.5
951.7, -587.5
1016.7, -587.5
1081.7, -587.5
1146.7, -587.5
1518.7, -587.5
1583.7, -587.5
1648.7, -587.5
1948.7, -587.5
2013.7, -587.5
2078.7, -587.5
2143.7, -587.5
2515.7, -587.5
2580.7, -587.5
2645.7, -587.5
2710.7, -587.5
2804.6, -579.0
2854.6, -579.0
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Pin No.
Pad Name
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VSS
VSS
VSS
VSS
V4
V4
V4
V4
V4
V4
V4
V3
V3
V3
V3
V3
V3
V3
V2
V2
V2
V2
V2
V2
V2
V1
V1
V1
V1
V1
V1
V1
V1
V0
V0
V0
V0
V0
V0
V0
V0
V0
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM63
COM62
COM61
Coordinate
(X,Y)
2904.6, -579.0
2954.6, -579.0
3004.6, -579.0
3054.6, -579.0
3104.6, -579.0
3154.6, -579.0
3204.6, -579.0
3254.6, -579.0
3304.6, -579.0
3354.6, -579.0
3404.6, -579.0
3454.6, -579.0
3504.6, -579.0
3554.6, -579.0
3604.6, -579.0
3654.6, -579.0
3704.6, -579.0
3754.6, -579.0
3804.6, -579.0
3854.6, -579.0
3904.6, -579.0
3954.6, -579.0
4004.6, -579.0
4054.6, -579.0
4104.6, -579.0
4154.6, -579.0
4204.6, -579.0
4254.6, -579.0
4304.6, -579.0
4354.6, -579.0
4404.6, -579.0
4454.6, -579.0
4504.6, -579.0
4554.6, -579.0
4604.6, -579.0
4654.6, -579.0
4704.6, -579.0
4754.6, -579.0
4804.6, -579.0
4854.6, -579.0
4904.6, -579.0
4954.6, -579.0
5004.6, -579.0
5099.0, -595.0
5202.0, -595.0
5305.0, -595.0
5305.0, -500.0
5305.0, -457.0
5305.0, -414.0
5305.0, -371.0
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Pin No.
Pad Name
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
DUMMY
DUMMY
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
Coordinate
(X,Y)
5305.0, -328.0
5305.0, -285.0
5305.0, -242.0
5305.0, -199.0
5305.0, -156.0
5305.0, -113.0
5305.0, -70.0
5305.0, -27.0
5305.0, 16.0
5305.0, 59.0
5305.0, 102.0
5305.0, 145.0
5305.0, 188.0
5305.0, 231.0
5305.0, 274.0
5305.0, 317.0
5305.0, 360.0
5305.0, 403.0
5305.0, 446.0
5310.5, 570.0
5267.5, 570.0
5224.5, 570.0
5181.5, 570.0
5138.5, 570.0
5095.5, 570.0
5052.5, 570.0
5009.5, 570.0
4966.5, 570.0
4923.5, 570.0
4880.5, 570.0
4837.5, 570.0
4794.5, 570.0
4751.5, 570.0
4708.5, 570.0
4665.5, 570.0
4622.5, 570.0
4579.5, 570.0
4536.5, 570.0
4493.5, 570.0
4450.5, 570.0
4407.5, 570.0
4364.5, 570.0
4321.5, 570.0
4278.5, 570.0
4235.5, 570.0
4192.5, 570.0
4149.5, 570.0
4106.5, 570.0
4063.5, 570.0
4020.5, 570.0
•5
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
6•
Pin No.
Pad Name
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
Coordinate
(X,Y)
3977.5, 570.0
3934.5, 570.0
3891.5, 570.0
3848.5, 570.0
3805.5, 570.0
3762.5, 570.0
3719.5, 570.0
3676.5, 570.0
3633.5, 570.0
3590.5, 570.0
3547.5, 570.0
3504.5, 570.0
3461.5, 570.0
3418.5, 570.0
3375.5, 570.0
3332.5, 570.0
3289.5, 570.0
3246.5, 570.0
3203.5, 570.0
3160.5, 570.0
3117.5, 570.0
3074.5, 570.0
3031.5, 570.0
2988.5, 570.0
2945.5, 570.0
2902.5, 570.0
2859.5, 570.0
2816.5, 570.0
2773.5, 570.0
2730.5, 570.0
2687.5, 570.0
2644.5, 570.0
2601.5, 570.0
2558.5, 570.0
2515.5, 570.0
2472.5, 570.0
2429.5, 570.0
2386.5, 570.0
2343.5, 570.0
2300.5, 570.0
2257.5, 570.0
2214.5, 570.0
2171.5, 570.0
2128.5, 570.0
2085.5, 570.0
2042.5, 570.0
1999.5, 570.0
1956.5, 570.0
1913.5, 570.0
1870.5, 570.0
Pin No.
Pad Name
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
Coordinate
(X,Y)
1827.5, 570.0
1784.5, 570.0
1741.5, 570.0
1698.5, 570.0
1655.5, 570.0
1612.5, 570.0
1569.5, 570.0
1526.5, 570.0
1483.5, 570.0
1440.5, 570.0
1397.5, 570.0
1354.5, 570.0
1311.5, 570.0
1268.5, 570.0
1225.5, 570.0
1182.5, 570.0
1139.5, 570.0
1096.5, 570.0
1053.5, 570.0
1010.5, 570.0
967.5, 570.0
924.5, 570.0
881.5, 570.0
838.5, 570.0
795.5, 570.0
752.5, 570.0
709.5, 570.0
666.5, 570.0
623.5, 570.0
580.5, 570.0
537.5, 570.0
494.5, 570.0
451.5, 570.0
408.5, 570.0
365.5, 570.0
322.5, 570.0
279.5, 570.0
236.5, 570.0
193.5, 570.0
150.5, 570.0
107.5, 570.0
64.5, 570.0
21.5, 570.0
-21.5, 570.0
-64.5, 570.0
-107.5, 570.0
-150.5, 570.0
-193.5, 570.0
-236.5, 570.0
-279.5, 570.0
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Pin No.
Pad Name
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
SEG133
SEG134
SEG135
SEG136
Coordinate
(X,Y)
-322.5, 570.0
-365.5, 570.0
-408.5, 570.0
-451.5, 570.0
-494.5, 570.0
-537.5, 570.0
-580.5, 570.0
-623.5, 570.0
-666.5, 570.0
-709.5, 570.0
-752.5, 570.0
-795.5, 570.0
-838.5, 570.0
-881.5, 570.0
-924.5, 570.0
-967.5, 570.0
-1010.5, 570.0
-1053.5, 570.0
-1096.5, 570.0
-1139.5, 570.0
-1182.5, 570.0
-1225.5, 570.0
-1268.5, 570.0
-1311.5, 570.0
-1354.5, 570.0
-1397.5, 570.0
-1440.5, 570.0
-1483.5, 570.0
-1526.5, 570.0
-1569.5, 570.0
-1612.5, 570.0
-1655.5, 570.0
-1698.5, 570.0
-1741.5, 570.0
-1784.5, 570.0
-1827.5, 570.0
-1870.5, 570.0
-1913.5, 570.0
-1956.5, 570.0
-1999.5, 570.0
-2042.5, 570.0
-2085.5, 570.0
-2128.5, 570.0
-2171.5, 570.0
-2214.5, 570.0
-2257.5, 570.0
-2300.5, 570.0
-2343.5, 570.0
-2386.5, 570.0
-2429.5, 570.0
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Pin No.
Pad Name
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
SEG137
SEG138
SEG139
SEG140
SEG141
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
SEG152
SEG153
SEG154
SEG155
SEG156
SEG157
SEG158
SEG159
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
Coordinate
(X,Y)
-2472.5, 570.0
-2515.5, 570.0
-2558.5, 570.0
-2601.5, 570.0
-2644.5, 570.0
-2687.5, 570.0
-2730.5, 570.0
-2773.5, 570.0
-2816.5, 570.0
-2859.5, 570.0
-2902.5, 570.0
-2945.5, 570.0
-2988.5, 570.0
-3031.5, 570.0
-3074.5, 570.0
-3117.5, 570.0
-3160.5, 570.0
-3203.5, 570.0
-3246.5, 570.0
-3289.5, 570.0
-3332.5, 570.0
-3375.5, 570.0
-3418.5, 570.0
-3461.5, 570.0
-3504.5, 570.0
-3547.5, 570.0
-3590.5, 570.0
-3633.5, 570.0
-3676.5, 570.0
-3719.5, 570.0
-3762.5, 570.0
-3805.5, 570.0
-3848.5, 570.0
-3891.5, 570.0
-3934.5, 570.0
-3977.5, 570.0
-4020.5, 570.0
-4063.5, 570.0
-4106.5, 570.0
-4149.5, 570.0
-4192.5, 570.0
-4235.5, 570.0
-4278.5, 570.0
-4321.5, 570.0
-4364.5, 570.0
-4407.5, 570.0
-4450.5, 570.0
-4493.5, 570.0
-4536.5, 570.0
-4579.5, 570.0
•7
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8•
Pin No.
Pad Name
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
COM100
COM101
COM102
COM103
COM104
COM105
COM106
DUMMY
DUMMY
COM107
COM108
COM109
COM110
COM111
COM112
COM113
COM114
COM115
COM116
COM117
COM118
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
DUMMY
Coordinate
(X,Y)
-4622.5, 570.0
-4665.5, 570.0
-4708.5, 570.0
-4751.5, 570.0
-4794.5, 570.0
-4837.5, 570.0
-4880.5, 570.0
-4923.5, 570.0
-4966.5, 570.0
-5009.5, 570.0
-5052.5, 570.0
-5095.5, 570.0
-5138.5, 570.0
-5181.5, 570.0
-5224.5, 570.0
-5267.5, 570.0
-5310.5, 570.0
-5305.0, 446.0
-5305.0, 403.0
-5305.0, 360.0
-5305.0, 317.0
-5305.0, 274.0
-5305.0, 231.0
-5305.0, 188.0
-5305.0, 145.0
-5305.0, 102.0
-5305.0, 59.0
-5305.0, 16.0
-5305.0, -27.0
-5305.0, -70.0
-5305.0, -113.0
-5305.0, -156.0
-5305.0, -199.0
-5305.0, -242.0
-5305.0, -285.0
-5305.0, -328.0
-5305.0, -371.0
-5305.0, -414.0
-5305.0, -457.0
-5305.0, -500.0
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
5
Functional Block Diagram
COM0
VDD
V0
V1
V2
V3
V4
VSS
----
COM127 SEG0
------------------------------
SEGC159
Segment Driver
Common Driver
Gradation Selection Circuit
Shift Register
Data Latch
PWM Function Circuit
Display Line Register
Display RAM
(DDRAM)
160 X 128 X 4 bits
Display Line Counter
Line Address Decoder
Y Address Decoder
Y Address Counter
Y Address Register
Voltage Converter
Booster Circuit
CAP1CAP1+
CAP2CAP2+
CAP3CAP3+
CAP4+
CAP5+
V2X
VOUT
VEE
VREF
VBA
X Address Decoder
RAM Interface
X Address Counter
Input/Output Buffer
D7
D6
D5
D4/SPOL
D3/SMODE
D2
D1/SDA
D0/SCL
X Address Register
Alternation Circuit
Bus Holder
MPU Interface
CSB RS RDB WRB P/S M86 RESB TEST
(E) (R/WB)
Instruction Decoder
OSC
Register Read
Display Timing Gen.
CK CKS
Figure 5-1 System Block Diagram
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
•9
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
6
Pin Description
6.1 Power Supply Pins
Symbol
VDD
VSS
V0
V1
V2
V3
V4
I/O
Power
Supply
Power
Supply
Power
Supply
Description
Power supply pin for logic circuit to +2.2 to 3.3V
Ground pin, connect to 0V
Bias power supply pin for LCD drive voltage
When using an external power supply, convert the impedance by using the
resistance-division of the LCD drive power supply or operation amplifier before
adding the voltage to the pins. These voltages should have the following
relationship: VSS<V4<V3<V2<V1<V0
When the internal power supply circuit is active, these voltages are generated by
the built-in booster and voltage converter. Then, you must connect each
capacitor to VSS.
6.2 LCD Power Supply Circuit Pins
10 •
Symbol
I/O
Description
CAP1+
O
CAP1-
O
CAP2+
O
CAP2-
O
CAP3+
O
CAP3-
O
CAP4+
O
CAP5+
O
VEE
Power
Supply
VOUT
O
V2X
O
VBA
O
Output pin for the regulator voltage of VBA AMP.
VREF
O
Output pin for temperature compensation output voltage
The capacitor must be connected between this pin and VSS.
Connecting pin for the built-in booster’s capacitor + side.
The capacitor is connected between CAP1- and CAP1+.
Connecting pin for the built-in booster’s capacitor – side.
The capacitor is connected between CAP1- and CAP1+.
Connecting pin for the built-in booster’s capacitor + side.
The capacitor is connected between CAP2- and CAP2+.
Connecting pin for the built-in booster’s capacitor – side.
The capacitor is connected between CAP2- and CAP2+.
Connecting pin for the built-in booster’s capacitor + side.
The capacitor is connected between CAP3- and CAP3+.
Connecting pin for the built-in booster’s capacitor – side.
The capacitor is connected between CAP3- and CAP3+.
Connecting pin for the built-in booster’s capacitor + side.
The capacitor is connected between CAP2- and CAP4+.
Connecting pin for the built-in booster’s capacitor + side.
The capacitor is connected between CAP3- and CAP5+.
Voltage supply pin for the booster circuit. Usually this has the same voltage
level as VDD.
Output pin of the boosted voltage in the built-in booster.
The capacitor must be connected between this pin and VSS.
Output pin which is equal to 2 x VEE.
The capacitor must be connected between this pin and VSS.
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
6.3 System Bus Pins
Symbol
RESB
D0/SCL
D1/SDA
D2
D3/SMODE
D4.SPOL
D5-D7
I/O
I
I/O
CSB
I
RS
I
RDB
(E)
I
WRB
(R/WB)
I
M86
I
TEST
I
Description
Reset input pin.
When RESB is “L,” initialization is executed.
Data bus/ Signal interface related pins.
When the parallel interface is selected (P/S = “H”), the D7-D0 are 8-bit
bi-directional data bus connecting to the MPU data bus.
When the serial interface is selected (P/S = “L”), D0 and D1 (SCL, SDA) are used
as serial interface pins.
SCL: Input pin for data transfer clock
SDA: Serial data input pin
SMODE: Serial transfer mode select pin
SPOL: RS pole select pin when the 3-wire serial interface is selected.
SDA data is latched at the rising edge of SCL.
Internal serial/parallel conversion into 8-bit data occurs at the rising edge of the 8th
clock of SCL. After data transfer is complete or when making no access, you must
set SCL to “L.”
Chip select input pin
CSB = “L”: accepts access from MPU
CSB = “H”: denies access from MPU
RAM/Register select input pin
RS = “0”: D7-D0 to display RAM data
RS = “1”: D7-D0 to control register data
Read/Write control pin
Select 80-family MPU type (M86 = “L”)
The RDB is a data read signal. When RDB is “L”, D7-D0 are in an output status.
Select 68-family MPU type (M86 = “H”)
R/WB = “H”: When E is “H,” D7-D0 are in an output status.
R/WB = “L”: Data on D7-D0 are latched at the falling edge for the E signal.
Read/Write control pin
Select 80-family MPU type (M86 = “L”)
The WRB is a data write signal. Data on D7-D0 are latched at the rising edge of the
WRB signal.
Select 68-family MPU type (M86 = “H”)
Read/Write control input pin.
R/W = “H”: Read
R/W = “L”: Write
MPU interface type select input pin.
M86 = “H”: 68-family interface
M86 = “L”: 80-family interface
Fixed at either “H” or “L”
For testing. Fix to “L.”
Parallel/Serial interface select pin
P/S
I
P/S Chip Select Data Identification
H
CSB
RS
L
CSB
RS
Data Read/Write Serial Clock
D0-D7 RDB, WRB
SDA
Write only
SCL
P/S = “H”: For parallel interface
P/S = “L”: For serial interface. Fixed D15-D5 pins are Hi-Z, RDB and WRB pins to
either “H” or “L.”
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 11
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
6.4 LCD Driver Circuit Signals
Symbol
I/O
Description
Segment output pins for LCD drives.
According to the Display RAM data, not lighted at “0”, lighted at “1” (Normal
Mode). Not lighted at “1”, lighted at “0” (Reverse Mode) and, by a combination of
the M signal and display data, one signal level among V0,V2,V3 and VSS signal
levels are selected.
SEG0
to
SEG159
M Signal
(internal)
Display RAM
Data
O
Normal Mode
V2
V0
V3
VSS
Reverse Mode
V0
V2
VSS
V3
Common output pins for the LCD drivers. By combining the scanned data and M
signal, one signal level among V0, V1, V4 and VSS signal level is selected.
COM0
to
COM127
O
Data
H
L
H
L
M
H
H
L
L
Output Level
VSS
V1
V0
V4
6.5 Oscillating Circuit Pins
Symbol
I/O
CKS
I
CK
I/O
Description
Display timing clock source select input pin.
CKS = “H”: Use external clock from CK pin.
CKS = “L”: Use internal oscillated clock.
In the case of TCP, draw it as a separate terminal.
External clock input pin for displaying the timing (CKS=1) or internal clock output
pin for displaying the timing (CKS=0).
When using the internal oscillated clock, CK must be floating.
6.6 EEPROM Power Pins
12 •
Symbol
I/O
VPP
I
Description
External power-forcing pin for programming or erasing EEPROM, 17~18V.
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7
Functional Description
7.1 MPU Interface
7.1.1 Reset Pin Description (RESB)
Hold the RESB at low for at least 40us after which the EM65101 accepts this reset
command.
RESB
T > 40uS
Figure 7-1 RESB Timing
7.1.2 Selection of Interface Type
The EM65101 transfers data through the 8-bit parallel I/O (D7-D0) or serial data input
(SDA, SCL). You can use the P/S pin to select the parallel or serial interface. When the
serial interface is selected, you are allowed to write data but data reading is not
allowed.
P/S
I/F Type
CSB
RS
RDB
WRB
M86
SDA
SCL
Data
H
L
Parallel
Serial
CSB
CSB
RS
RS
RDB
-
WRB
-
M86
-
SDA
SCL
D7~D0
-
7.1.3 Parallel Input
When the parallel interface is selected with the P/S pin, the EM65101 allows data to be
transferred in parallel to an 8-bit MPU through the data bus. For the 8-bit MPU, you can
use the M86 pin to select either the 80-family or the 68-family MPU interface.
M86
MPU Type
CSB
RS
RDB
WRB
Data
H
68-family MPU
CSB
RS
E
R/WB
D7~D0
L
80-family MPU
CSB
RS
RDB
WRB
D7~D0
7.1.4 Read/Write Functions of the Register and Display RAM
The EM65101 have four read/write functions in parallel interface mode. Each
read/write function is selected by combinations of RS, RDB, and WRB signals.
80-family
RS
68-family
R/WB
RDB
WRB
1
1
0
1
Read internal Register
1
0
0
0
1
0
1
0
1
0
1
0
Write internal Register
Read display data
Write display data
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Function
• 13
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.1.5 Serial Interface
The EM65101 has two types of serial interfaces, i.e., 3-wire or 4-wire serial interface.
Use the SMODE pin to select the serial interface type.
SMODE = “L”: 4-wire serial interface
SMODE = “H”: 3-wire serial interface
7.1.5.1 4-Wire Serial Interface
When chip select is active (CSB = “L”), 4-wires type serial interface works through the
SDA and SCL input pins. When chip select is inactive (CSB = “H”), the internal shift
register and counter are reset to the initial condition. Serial data SDA are input
sequentially in the order of D7 to D0 at the rising edge of the serial clock (SCL). The RS
pin determines whether serial data input (SDA) is used as display RAM data or as
control register data.
RS = “L”: display RAM data
RS = “H”: register control data
After completing the 8-bit data transfer, or when making no access, be sure to set the
serial clock input (SCL) to “L.” Care should be taken during PCB layout to avoid
external noise from contaminating the SDA and SCL signals. To prevent any transfer
error due to external noise, release chip select (CSB = “H”) after every complete 8-bit
data transfer.
CSB
RS
SDA
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
SCL
Figure 7-2 4-Wire Serial Interface
7.1.5.2 3-Wire Serial Interface
When chip select is active (CSB = “L”), 3-wire serial interface works through the SDA
and SCL input pins. When chip select is inactive (CSB = “H”), the internal shift register
and counter are reset to the initial condition. Serial data SDA are input sequentially in
the order of RS, D7 to D0 at the rising edge of the serial clock (SCL). The first serial
input data (RS) and the SPOL pin determine whether serial data input (SDA) is used as
display RAM data or as control register data.
14 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
SPOL = “0”
RS
SPOL = “1”
Display RAM/Register
RS
Display RAM/Register
0
Display RAM Data
0
Control Register Data
1
Control Register Data
1
Display RAM Data
After completing the 9-bit data transfer, or when making no access, be sure to set the
serial clock input (SCL) to “L.” Care should be taken during PCB layout to avoid
external noise from contaminating the SDA and SCL signals. To prevent any transfer
error due to external noise, release chip select (CSB = “H”) after every complete 9-bit
data transfer.
CSB
SDA
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
SCL
Figure 7-3 3-Wire Serial Interface
7.2 Writing Data to Display RAM and Control Register
The procedure to write data to the display RAM and Control Register is similar except
for the RS selection to select the accessed object.
RS = “L”: Display RAM data
RS = “H”: Control register data
In the case of the 80-family MPU, data is written at the rising edge of WRB. In the case
of the 68-family MPU, data is written at the falling edge of signal E.
7.2.1 Writing Data Operation
D7~D0
Data0
Data1
Data2
Data3
Data4
Data5
WRB
RS
Write to control register
Write to display RAM
Figure 7-4 Writing Data Operation
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 15
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.2.2 Writing Data to Display RAM Data
The EM65101 is a 128-row by 160-column addressable array. Each pixel can be
accessed when the X and Y addresses are specified. The 128 rows are divided into 16
Y addresses of 8 lines. Data is read from or written to the 8 lines of X address directly
through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor
correspond to the LCD common lines. The microcomputer can read from and write to
RAM through the I/O buffer. Since the LCD controller operates independently, data
can be written into RAM and displayed at the same time without causing any LCD
flicker.
7.3 Y and X Address Circuits
7.3.1 Y Address Circuit
This circuit incorporates 4-bit Y address register which can only be changed by the “Y
address” instruction. The Y address is set from 0 to 15.
7.3.2 X Address Circuit
This circuit assigns display RAM a line address corresponding to the first line (COM0)
of the display. Therefore, by setting the X address repeatedly, it is possible to scroll the
screen and switch the Y address without changing the contents of the on-chip RAM. It
incorporates the 7-bit Y address register which can only be changed by the initial
display line instruction and the 7-bit counter circuit. At the beginning of each LCD
frame, the contents of the register are copied to the X address counter which is
incremented by the FLM signal. Thus generating the X address for transferring the
128-bit RAM data to the display latch circuit.
The REF select instruction makes it possible to invert the relationship between the X
address and the segment outputs. It is necessary to rewrite the display data on the
built-in RAM after issuing a REF select instruction. See and refer the following Figures
7-5 and 7-6.
16 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
1
1
1
1
0
0
0
0
:
1
1
0
0
1
1
0
0
:
1
0
1
0
1
0
1
0
:
0
0
0
0
0
0
0
0
:
1
1
1
1
0
0
0
0
:
1
1
0
0
1
1
0
0
:
1
0
1
0
1
0
1
0
:
......
1
1
1
1
0
0
0
0
:
1
1
0
0
1
1
0
0
:
1
0
1
0
1
0
1
0
:
0
0
0
0
0
0
0
0
:
1
1
1
1
0
0
0
0
:
1
1
0
0
1
1
0
0
:
1
0
1
0
1
0
1
0
:
280 byte
27F byte
27E byte
27D byte
27C byte
27B byte
27A byte
279 byte
8th byte
7th byte
6th byte
5th byte
4th byte
3rd byte
2nd byte
1st byte
MCU
REF=0
:
27F
1
1
1
1
1
1
1
1
:
27E
278
LSB...........MSB
1
1
1
1
1
1
1
1
:
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
:
27D
......
Internal
column
address
27C
9FH
27B
9EH
279
......
27A
01H
07
00H
06
X address
05
SEG159
04
SEG158
03
......
02
SEG1
01
SEG0
00
Segment
Output
Segment
Output
SEG0
SEG1
......
SEG158
SEG159
X address
00H
01H
......
9EH
9FH
1
0
1
0
1
0
1
0
:
1
1
1
1
1
1
1
1
:
1
1
1
1
0
0
0
0
:
1
1
0
0
1
1
0
0
:
1
0
1
0
1
0
1
0
:
0
0
0
0
0
0
0
0
:
1
1
1
1
0
0
0
0
:
1
1
0
0
1
1
0
0
:
1
0
1
0
1
0
1
0
:
:
......
280 byte
27F byte
27E byte
27D byte
27C byte
27B byte
27A byte
279 byte
8th byte
7th byte
6th byte
5th byte
4th byte
3rd byte
2nd byte
1st byte
MCU
REF=1
27F
07
1
1
0
0
1
1
0
0
:
27E
06
1
1
1
1
0
0
0
0
:
27D
05
0
0
0
0
0
0
0
0
:
27C
04
1
0
1
0
1
0
1
0
:
27B
03
1
1
0
0
1
1
0
0
:
27A
02
1
1
1
1
0
0
0
0
:
279
01
1
1
1
1
1
1
1
1
:
278
00
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
:
......
LSB...........MSB
Internal
column
address
Figure 7-5 REF Control of the Relationship between the X Address and the Segment Outputs
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 17
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.3.3 EM65101 Display RAM Mapping
0
0
0
0
1
1
1
1
0
1
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
REF=0
00
01
02
03
9C
9D
9E
9F
REF=1
9F
9E
9D
9C
03
02
01
00
Y address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
COM112
COM113
COM114
COM115
COM116
COM117
COM118
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
SEG159
SEG158
SEG157
SEG156
SEG3
SEG2
SEG1
SEG0
D3 D2 D1 D0
.
.
.
.
.
.
.
.
.
.
0
MSB
0
LSB
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
X address
SEG
Figure 7-6 Display RAM Mapping Diagram
18 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.4 Internal Register Read
When reading data from the display RAM, a dummy read is initially required. The
designated address data is not output to the read operation immediately after the
address is set to the AX or AY register. It is output when the second data is read.
Dummy read is always initially required after address is set and the write cycle is
started.
7.4.1 Read Display RAM Operation
WRB
D7~D0
RDB
n
***
n
n+1
n+2
Address set (AX,AY)
Address = n
Dummy
Read
Data Read
Address=n
Data Read
Address=n+1
Data Read
Address=n+2
RS
Figure 7-7 Read Display RAM Operation
The EM65101 can read the control registers. When issuing a control register read
operation, the upper data bus nibble (D7-D4) is used for the register address (0 to FH).
Up to 16 registers can be accessed directly. However, more than 16 registers are
provided. To solve this over supply problem, the EM65101 uses the register bank
control to access the RE register with a bank number. You can access the RE register
through any bank. The following lists the steps to be taken when accessing the specific
register using the bank access control.
1. Write 01H to the RE register for accessing the RA register.
2. Write the specific register address to the RA register.
3. Write the specific register bank to the RE register.
4. Read the specific register contents.
7.4.2 Register Read Operation
WRB
D0~D7
RDB
01H
addr
bank
data
Bank number write
to RE for RA
Address write
to RA
Bank number
write to RE
read specific
register
RS
Figure 7-8 Register Read Operation
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 19
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.4 Display RAM Access Using Window Function
The EM65101 has a window area setting command for accessing a specified display
RAM area. To use the window function, you need to set up the X & Y address
positions. In addition, you also need to enable the auto-increment mode (AXI=”1”,
AYI=”1”). These two positions represent the window start position and window end
position. Set the X address (AX) and Y address (AY) registers to specify the window
start position of X and Y respectively. Set the Window X End address (EX) and
Window Y End address (AY) to specify the window end positions of X and Y
respectively. When accessing the window function, you can set AIM to “1” to modify
write access. You should set the following registers before accessing RAM when you
use the window function. Note that the Window Y End address setting can be set only
as COM8, COM16…, COM127.
WIN = “1,” AXI=”1,” AYI=”1”
X address, Y address, Window X End address, Window Y End address
Moreover, these addresses should be kept in the following conditions:
Window End X address(EX) ≧ Window Start X address (AX)
Window End Y address(EY) ≧ Window Start Y address (AY)
X Direction
Y D ir ec ti on
The Window
accessed area
X,Y Start Address
The entire RAM
display area
(shaded + Window
accessed areas)
X,Y End Address
Figure 7-9 Window XY Address Location Within RAM Display
7.5 Display RAM Data and LCD
One bit of display RAM data corresponds to one dot of LCD. Normal display and
reverse display by the REV register are set up as follows:
Normal display (REV=0): RAM data = “0,” not lit
RAM data = “1,” lit
Reverse display (REV=1): RAM data = “0,” lit
RAM data = “1” not lit
20 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.6 Display Timing Circuit
The display timing circuit generates internal signals and timing pulses (internal LP,
FLM, and M) by the clock.
Symbol
Description
LP (internal)
The LP is a latch clock signal.
At the raising edge, count the display line counter. At the falling edge,
output the LCD drive signal.
FLM (internal)
The signal for the LCD display synchronous signals.
When FLM is set to “H,” the display start-line address is present.
M (internal)
The signal for alternate signals of LCD drive output
7.6.1 Signal Generation for the Display Line Counter and the
Display Data Latching Circuit
Clock frequencies are generated to the line counter and the display data latching circuit
from the display clock (internal LP). Synchronized with the display clock (internal LP),
the line addresses of Display RAM are generated and the 160-segement bits display
data are latched to display data latching circuit to output to the LCD drive circuit
(Segment outputs). Display data read out of to the LCD drive circuit is completely
independent of MPU. Thus, MPU has no relationship to the read-out operation which
accesses the display data.
7.6.2 Generation of the Alternate Signal M (Internal) and the
Synchronous Signal FLM (Internal)
LCD alternate signal M (internal) and synchronous signal FLM (internal) are generated
by the display clock LP (internal). FLM generates alternated drive waveform to the
LCD drive circuit. Normally, FLM generates alternate drive waveform every frame
(M-signal level is reversed every single frame). However, by setting up data in an n-line
reverse register and n-line alternate control bit (NLIN), an n-line reverse waveform is
generated at “1.” These control bits are NLIN and EOR.
When NLIN = “H” :
EOR=0
M always reverses on the nth raster row regardless of whether the end of a
frame is reached.
EOR=1
M reverses at the nth raster row and restarts the raster row count at the start
of every frame.
7.6.3 Display Data Latching Circuit
Display data latching Circuit temporally latches display data that outputs display data to
the LCD driver circuit from display RAM every one common period. Normal
display/reverse display, display ON/OFF, and display all on functions are operated by
controlling data in the display data latch. Therefore, no data within display RAM
changes.
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 21
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.7 LCD Driver Output Timing
Display timing at Normal (not reverse mode), 1/128 Duty.
127
128
1
2
3
128
1
2
3
128
1
LP
FLM
M
V0
V1
COM0
V4
V4
VSS
VSS
V0
V1
V1
V1
COM1
V4
V4
VSS
V0
V0
V2
SEG0
V3
V3
VSS
V0
V2
SEG1
V2
V3
V2
V3
V3
VSS
Figure 7-10 Normal Mode Display Timing Diagram
7.7.1 LCD Drive Circuit
This drive circuit generates four levels of LCD drive voltages. The circuit has
160-segment outputs and 128-common outputs and the outputs combine the display
data and internal signal M. The common drive circuit that contains a shift register
sequentially outputs common scan signals.
7.7.2 Oscillator Circuit
The EM65101 provides a CR oscillator. The output from this oscillator is used as the
timing source for display signal and clock source for the clock booster.
When the external clock is used, the clock source is fed to the CK pin.
The duty cycle of the external clock must be 50%.
22 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
The ratio of the resistance at the CR oscillator is programmable. When you change this
ratio, the frame frequency display is also changed.
7.8 Power Supply Circuit
This power circuit supplies the voltages necessary to drive an LCD. The circuit
consists of a booster and a voltage converter.
Boosted voltage from the booster is fed to the voltage converter that converts this input
voltage into V0, V1, V2, V3, and V4 that are used to drive the LCD. This internal power
supply should not be used to drive a large LCD panel containing many pixels.
Otherwise, the display quality will be degraded considerably. Instead, use an external
power supply. When using external power supply, turn off the internal power supply
(AMPON, DCON=”00”), disconnect pins CAP1-, CAP1+, CAP2+, CAP2-, CAP3+,
CAP3-, CAP4+, CAP5+,V2X, VOUT, and VEE. Then, feed the external LCD drive
voltages to Pins V0, V1, V2, V3, and V4. The power circuit can be controlled by power
circuit related registers.
DCON
AMPON
Booster Circuit
Voltage Conversion Circuit
0
0
Disable
Disable1
0
1
Disable
Enable2
1
1
Enable
Enable
1
Because the booster and the voltage converter are not operating, disconnect Pins
CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP3-, CAP4+, CAP5+,V2X, VOUT and
VEE.
Apply external LCD drive voltages to the corresponding pins.
2
Because the booster is not operating, disconnect Pins CAP1+, CAP1-, CAP2+,
CPA2-, CAP3+, CAP3-, CAP4+, CAP5+, and VEE.
Derive the voltage source to be supplied to the voltage converter from VOUT and the
V2X pins.
7.9 Booster Circuit
Placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across
CAP3+ and CAP3-, across CAP4+ and CAP2-, across CAP5+ and CAP3-, and across
VOUT/V2X and VSS, will boost the voltage coming from VEE and VSS n-times and
output the boost up voltage to the VOUT pin. Voltages that are boost-up twice, three
times, four times, and five times are output to the VOUT pin by the boost step register
set. You can set the boost step registers.
(1) In cases where the twice boost-up voltage is used, place C1 across CAP1+ and
CAP1- , across V2X and VSS; and open CAP2+, CAP2-, CAP3+, CAP3-, CAP4+,
CAP2-, CAP5+, and CAP3-.
(2) In cases where the voltage that is boosted three times is used, place C1 only
across CAP1+ and CAP1-, across CAP2+ and CAP2- , across V2X and VSS; and
open CAP3+, CAP3-, CAP4+, CAP2-, CAP5+, and CAP3-
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 23
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
(3) In cases where the four times boosted voltage is used, place C1 only across
CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3- , across
V2X and VSS; and open CAP4+, CAP2-, CAP5+, and CAP3(4) In cases where the voltage that is boosted five times is used, place C1 only across
CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3- across
CAP4+ and CAP2- , across V2X and VSS; and open CAP5+ and CAP3(5) In cases where the voltage that is boosted six times is used, place C1 only across
CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3-, across
CAP4+ and CAP2-, across CAP5+ and CAP3-, and across V2X and VSS
When you use the built-in booster circuit, make sure the output voltage (VOUT) is less
than the recommended operating voltage (18.0 Volt). If the output voltage (VOUT) is
more than the recommended operating voltage, correct chip operation can NOT be
guaranteed.
VOUT=18V
VOUT=9V
VEE=3V
VEE=3V
VSS=0V
VSS=0V
Boosted 3 times
Boosted 6 times
Figure 7-11 Correlation Between VEE and VOUT Boost-up Voltages
NOTE
The maximum voltage VOUT of 18V is automatically limited by hardware to avoid
damage to the IC.
7.10 Electronic Volume
The voltage conversion circuit has a built-in electronic volume control, which allows
VBA to be controlled by DV register settings. The DV registers are 7 bits providing 65
voltage values for the VBA. The relationship between VBA and DV is summarized in
the following equation:
VBA= (1+( M + offset) / 381)* VREF
V0 = VBA * N
Where:
M = DV register setting (offsets CV5 ~ CV0 setting on EEPROM)
N = RM register setting
VREF = Internal temperature compensation output voltage
24 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.11 Voltage Regulator
The EM65101 has a built-in reference voltage regulator, which regulates the amplified
voltage from the internal temperature compensation output (VREF pin) to generate the
LCD drive voltage (V0). Even if the boost-up voltage level fluctuates, V0 remains
stable as long as VOUT is higher than V0. Stable power supply can be obtained by
using this constant voltage, even if the load fluctuates. The EM65101 uses the
generated LCD drive voltage (V0) level as the reference level for the electronic volume.
7.12 Voltage Generation Circuit
The voltage converter contains the voltage generation circuit. The LCD drive voltages
other than V0, that is; V1, V2, V3, and V4 are obtained by dividing V0 through a resistor
network. The LCD drive voltage from EM65101 is biased at 1/4, 1/5, 1/6, 1/7, 1/8, 1/9,
1/10, 1/11, 1/12, & 1/13. When using the internal power supply, connect a stabilizing
capacitor to each of Pins V0 to V4. The capacitor should be determined while selecting
the LCD panel to be used. When using the external power supply, apply external LCD
drive voltages to V0, V1, V2, V3, & V4. Disconnect Pins CAP1+, CAP1-, CAP2+,
CAP2-, CAP3+, CAP3-, CAP4+, CAP5+,V2X, VOUT, & VEE. When using only the
voltage conversion circuit, turn off the internal booster circuit, disconnect Pins CAP1+,
CAP1-, CAP2+, CAP2-, CAP3+, CAP3-, CAP4+, CAP5+ and VEE. Get the voltage
source to be supplied to the voltage converter from VOUT and V2X pins.
The following figure shows an application circuit on capacitor connections when using
the internal power circuit (with the voltage boosted several times as shown).
Boosted 6 times
VDD
Boosted 5 times
VDD
VDD
VEE
VBA
VREF
CVREF
CVREF
VDD
VEE
VBA
VREF
CVREF
CAP5+
CAP3+
CAP3CAP2C1
CAP2+
C1
CAP4+
CAP3CAP2C1
CAP2+
C1
CAP4+
CAP5+
CAP3+
CAP3CAP2C1
CAP2+
CAP4+
CAP1+
C1
CAP1C1
V2X
CAP1+
C1
CAP1C1
V2X
CAP1+
C1
CAP1C1
V2X
C1
C1
C1
C1
C1
C1
C1
C1
vss
VDD
VDD
VEE
VBA
VREF
C1
vss
Boosted 4 times
CAP5+
CAP3+
C1
C1
C1
VOUT
V0
V1
V2
V3
V4
vss
C1
C1
C1
C1
C1
vss
VOUT
V0
V1
V2
V3
V4
vss
C1
C1
C1
C1
C1
vss
VOUT
V0
V1
V2
V3
V4
Figure 7-12a Internal Power Capacitor Connections Application Circuits
(Voltage Boosted 6, 5 and 4 Times)
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 25
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Boosted 3 times
VDD
Boosted 2 times
VDD
VDD
VEE
VEE
VBA
VREF
CVREF
VREF
CAP5+
CAP3+
CAP5+
CAP3+
CAP3-
CAP3-
CAP2C1
CAP2+
CAP2-
CAP4+
CAP4+
CAP1+
C1
CAP1C1
V2X
CAP1+
C1
CAP1C1
V2X
C1
C1
C1
C1
C1
vss
VBA
CVREF
CAP2+
C1
vss
VDD
C1
VOUT
V0
vss
C1
C1
C1
V1
V2
V3
V4
C1
C1
vss
VOUT
V0
V1
V2
V3
V4
Figure 7-12b Internal Power Capacitor Connections Application Circuits
(Voltage Boosted 3 and 2 Times)
NOTE
1. Recommended values for C1 is 1uF, and for CVREF is 0.1uF.
2. To attain a stable voltage, it is recommended that you use VREF to connect a
capacitor across CVREF and VSS.
4. Use of capacitor type X5R is recommended for C1 and CVREF.
26 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.13 EEPROM Function
The EM65101 supports EEPROM function that allows you to change the LCD
operating voltage Vop. It can also select EEPROM operating mode and set to use
internal or external power supply for EEPROM. In the EEPROM select register (Bank2
[0H]), then use (M1, M0) to select the operating mode for EEPROM:
(M1, M0)
EEPROM Operating Mode
Delay Time
00
Read
> 10 uS
01
Program
> 4 mS
10
Erase
> 4 mS
11
Reserve
-
NOTE
When using the EEPROM function, VDD must be larger than 2.8V (VDD≧2.8V)
You can get the Vop calibration offset voltage by setting the Vop calibration offset
register (Bank 2[1H & 2H]).
CV5~CV0
Calibration Offset
011111
+31
011110
+30
…
…
000001
+1
000000
0
100000
-32
100001
-31
…
…
111111
-1
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 27
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.13.1 EEPROM Program, Read, and Erase Flow Charts
The following are the EEPROM Program, Read and Erase flow charts for achieving
correct Vop offset voltage.
set
C V 5~C V 4
(u p n ib b le
reg ister)
set
C V 3~C V 0
(lo w n ib b le
reg ister)
selec t E E P R O M
a d d ress to p ro g ra m
(N IB 1 ,N IB 0 ) set 0 1
W R sta rt :
(M 1 ,M 0 ) set 0 1
selec t E E P R O M
a d d ress to rea d
(N IB 1 ,N IB 0 ) set 0 0
d ela y > 4 m s
R D sta rt :
(M 1 ,M 0 ) set 0 0
W R en d :
(M 1 ,M 0 ) set 1 1
d ela y > 1 0 u s
R eset
R D en d :
(M 1 ,M 0 ) set 1 1
W R sta rt :
(M 1 ,M 0 ) set 0 1
selec t E E P R O M
a d d ress to rea d
(N IB 1 ,N IB 0 ) set 0 1
G et c o rrec t
V o p o ffset
v o lta g e
d ela y > 4 m s
R D sta rt :
(M 1 ,M 0 ) set 0 0
W R en d :
(M 1 ,M 0 ) set 1 1
d ela y > 1 0 u s
selec t E E P R O M
a d d ress to p ro g ra m
(N IB 1 ,N IB 0 ) set 0 0
R D en d :
(M 1 ,M 0 ) set 1 1
Figure 7-13 Program Flow Chart
28 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
s e le c t E E P R O M
a d d r e s s to r e a d
(N IB 1 ,N IB 0 ) s e t 1 1
select EEPROM
address to erase
(NIB1,NIB0) set 01
delay > 4 ms
RD end:
(M1,M0) set 11
Erase end:
(M1,M0) set 11
select EEPROM
address to read
(NIB1,NIB0) set 00
R D s ta r t :
(M 1 ,M 0 ) s e t 0 0
Erase start :
(M1,M0) set 10
d e la y > 1 0 u s
delay > 4 ms
R D end:
(M 1 ,M 0 ) s e t 1 1
Erase end:
(M1,M0) set 11
D E C (N IB 1 ,N IB 0 )
Reset
select EEPROM
address to read
(NIB1,NIB0) set 01
RD start :
(M1,M0) set 00
delay > 10 us
y
N IB 1 ,N IB 0 < 1 1
n
select EEPROM
address to erase
(NIB1,NIB0) set 00
RD start :
(M1,M0) set 00
Erase start :
(M1,M0) set 10
delay > 10 us
RD end:
(M1,M0) set 11
R e a d P ro c e ss e n d
Figure 7-14 Read Flow Chart
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Figure 7-15 Erase Flow Chart
• 29
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.13.2 Vop Calibration Offset Examples
1) Program
Vop calibration offset is +30, CV5~CV0 is set to 011110
WRITE
#F2H
// set RE FLAG 010
INSTRUCTION Bank 2
WRITE
#11H
// set CV5~CV4=01
WRITE
#2EH
// set CV3~CV0=1110
WRITE
#51H
// set NIB1~NIB0=01
WRITE
#02H
// set EEPROM operating mode
programming; EEPROM power is from internal V0
program CV5~CV4
DELAY > 4 MS
// wait > 4 ms to finish programming
WRITE
#06H
// set EEPROM mode
WRITE
#50H
// set NIB1~NIB0=00
WRITE
#02H
// set EEPROM operating mode
programming; EEPROM power is from internal V0
reserve (finish programming)
program CV3~CV0
DELAY > 4 MS
// wait > 4 ms to finish programming
WRITE
#06H
// set EEPROM mode
WRITE
#F0H
// set RE FLAG 000
WRITE
#81H
// EM65101 reset
WRITE
#F2H
// set RE FLAG 010
WRITE
#51H
// set NIB1~NIB0=01
WRITE
#00H
// set EEPROM operating mode
reading;
read data from EEPROM to the CV5~CV4 registers
DELAY
>10 uS
// wait >10 uS to finish reading
WRITE
#06H
// set EEPROM mode
reserve (finish reading data
from EEPROM to the CV5~CV4 registers)
WRITE
#50H
// set NIB1~NIB0=00
WRITE
#00H
// set EEPROM operating mode
reading; read data
from EEPROM to the CV3~CV0 registers
DELAY
>10 uS
// wait >10 uS to finish reading
WRITE
#06H
// set EEPROM mode
reserve (finish reading data
from EEPROM to the CV3~CV0 registers)
reserve (finish programming)
INSTRUCTION Bank 0
INSTRUCTION Bank 2
read CV5~CV4
read CV3~CV0
NOTE
When setting CV5~CV0, you must set CV5~CV4 (upper nibble registers) first,
then set CV3~CV0 (lower nibble registers), and then start to program.
The programming sequence of CV5~CV4 and CV3~CV0 is not restricted.
30 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
2) Read
WRITE
#F2H
// set RE FLAG 010
INSTRUCTION Bank 2
WRITE
#53H
// set NIB1~NIB0=11
WRITE
#00H
// set EEPROM operating mode
read data from EEPROM
DELAY
>10 uS
// wait >10 uS to finish reading
WRITE
#06H
// set EEPROM mode
from EEPROM
WRITE
#52H
// set NIB1~NIB0=10
WRITE
#00H
// set EEPROM operating mode
read data from EEPROM
DELAY
>10 uS
// wait >10 uS to finish reading
WRITE
#06H
// set EEPROM mode
from EEPROM
WRITE
#51H
//set NIB1~NIB0=01
WRITE
#00H
// set EEPROM operating mode
reading;
read data from EEPROM to the CV5~CV4 registers
DELAY
>10 uS
// wait >10 uS to finish reading
WRITE
#06H
// set EEPROM mode
reserve (finish reading data
from EEPROM to the CV5~CV4 registers)
WRITE
#50H
//set NIB1~NIB0=00
WRITE
#00H
// set EEPROM operating mode
reading; read data
from EEPROM to the CV3~CV0 registers
DELAY
>10 uS
// wait >10 uS to finish reading
WRITE
#06H
// set EEPROM mode
reserve (finish reading data
from EEPROM to the CV3~CV0 registers)
read Extension Command
reading;
reserve (finish reading data
read Extension Command
reading;
reserve (finish reading data
read CV5~CV4
read CV3~CV0
NOTE
When reading from CV5~CV0, you must read the EEPROM data to CV5~CV4 (upper
nibble register) first, then read the EEPROM data to CV3~CV0 (lower nibble
registers).
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 31
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
3) Erase
WRITE
#F2H
// set RE FLAG 010
INSTRUCTION Bank 2
WRITE
#51H
// set NIB1~NIB0=01
WRITE
#04H
// set EEPROM operating mode
erasing;
EEPROM power is from internal V0
erase CV5~CV4
DELAY > 4 MS
// wait > 4 ms to finish erasing
WRITE
#06H
// set EEPROM mode
WRITE
#50H
// set NIB1~NIB0=00
WRITE
#04H
// set EEPROM operating mode
erasing;
EEPROM power is from internal V0
reserve (finish erasing)
erase CV3~CV0
DELAY > 4 MS
// wait > 4 ms to finish erasing
WRITE
#06H
// set EEPROM mode
reserve (finish erasing)
WRITE
#F0H
// set RE FLAG 000
INSTRUCTION Bank 0
WRITE
#81H
// EM65101 reset
WRITE
#F2H
// set RE FLAG 010
WRITE
#51H
// set NIB1~NIB0=01
WRITE
#00H
// set EEPROM operating mode
reading;
read data from EEPROM to the CV5~CV4 registers
DELAY
>10 uS
// wait >10 uS to finish reading
WRITE
#06H
// set EEPROM mode
reserve (finish reading data
from EEPROM to CV5~CV4 register)
WRITE
#50H
// set NIB1~NIB0=00
WRITE
#00H
// set EEPROM operating mode
reading; read data
from EEPROM to the CV3~CV0 registers
DELAY
>10 uS
// wait >10 uS to finish reading
WRITE
#06H
// set EEPROM mode
reserve (finish reading data
from EEPROM to CV3~CV0 register)
INSTRUCTION Bank 2
read CV5~CV4
read CV3~CV0
NOTE
CV5~CV0 should be equal to 1111 after erasing
32 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.14 Partial Display Function
The EM65101 has a partial display function, which can display a part of graphic display
area. This function is used to set lower bias ratio, lower boost step, and lower LCD
drive voltage. When setting the partial display function, the EM65101 consumes less
power. The Partial display function is suitable for clock indication or calendar indication
when portable equipment is on stand-by.
ELAN
LCD DRIVER
Low Power and
Low Voltage
LCD DRIVER
Normal Display
Partial Display
Figure 7-16 Partial Display Block Diagram
When using the partial display function, it is necessary to follow the sequence shown
below.
Any display condition
Display off (ON/OFF= "0")
Power circuit off (DCON= "0", AMPON= "0")
WAIT
Setting Power Function
* Boost step set
* Electronic volume set
* Bias Ratio set
Power circuit on (DCON= "1", AMPON= "1")
WAIT
Setting Display Function
* Duty Ratio set * Display start common
Display on (ON/OFF= "1")
Partial Display
Figure 7-17 Partial Display Function Sequential Flow
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 33
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Select a display duty ratio for the partial display from 1/8 to 1/128 using the DS (LCD
duty ratio) register.
Set the most suitable values for LCD drive bias ratio, LCD drive voltage, electronic
volume, the number of boosting steps, and others according to the actual LCD panel
and selected duty ratio in use.
7.15 Discharge Circuit
The EM65101 has a built-in the discharge circuit, which discharges electricity from the
capacitors to provide stable power sources (V0~V4). The discharge circuit is valid
when the DIS register is set to “1.” When the built-in power supply is used, be sure to
set DIS=”1” after the power source is turned off (DCON, AMPON)=(0, 0).
CAUTION!!!
Do NOT turn on both the built-in power source and the external power source (V0~V4,
VOUT) while DIS =”1.”
7.16 Scroll Function
This function specifies a portion of screen for scrolling. It sets the scroll top address,
scroll bottom address, scroll specified address, scroll mode of the scrolling area, and
scroll start address. Note that the scroll top address should be smaller than the scroll
bottom address, i.e.,
0 <= scroll top address, scroll bottom address, scroll specified address <= 127;
scroll top address <= scroll start address <= scroll bottom address.
34 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
160 X 128 Line Panel
160 X 128 Line display RAM
Scroll address
RAM address
Top fixed area 2004/11/18
AM 8:00
2
Scroll start
address=2
Scroll area
125
Bottom fixed area Menu
Phone book
Scroll specified address=125
Scroll start
address=3
Scroll start
address=4
Scroll start
address=63
Scroll start
address=124
0
1 2004/11/18
2
3
.
.
.
124
125
126 Menu
127
0
1 2004/11/18
2
3
.
.
.
124
125
126
127 Menu
0
1 2004/11/18
2
3
.
.
.
124
125
126 Menu
127
0
1 2004/11/18
2
3
.
.
.
124
125
126
127 Menu
0
1 2004/11/18
2
3
.
.
.
124
125
126
127 Menu
AM 8:00
COM 0
COM 1
COM 126
Phone book COM 127
AM 8:00
COM 0
COM 1
COM 126
Phone book COM 127
AM 8:00
COM 0
COM 1
COM 126
Phone book COM 127
AM 8:00
COM 0
COM 1
COM 126
Phone book COM 127
AM 8:00
COM 0
COM 1
COM 126
Phone book COM 127
Figure 7-18 Example on Scroll Function Display vs. Address Values
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 35
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Set the scroll top address and scroll bottom address to define the area of scrolling data
in RAM
Example:
160 X 128 Line display RAM
RAM address
Scroll top address
2
2004/11/18
AM 8:00
Top fixed area
Scroll data area
Scroll bottom address
125
Menu
Phone book
Bottom fixed area
Figure 7-19 Setting the Scrolling Data Area in RAM
Set the scroll specified address according to the panel size and duty selection to
specify the address to which to jump relative to the scroll bottom address. Then display
the fixed bottom data area. Note that scroll specified address = scroll top address +
panel scroll area – 1
Example: (160 x 128 Line panel; 1/32 duty, partial display)
160 X 128 Line display RAM
1/32 duty partial display
RAM address
COM 0
Scroll top address
Scroll specified
address
2
COM 2
29
Scroll bottom address
COM 29
jump to bottom
address
125
COM 31
(setting specified address=29)
COM 0
2
COM 2
COM 29
Scroll specified
address
31
COM 31
jump to bottom
address
125
(setting specified address=31)
Figure 7-20 Setting the Scroll Bottom Address of a Scrolling Area
36 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
NOTE
You must set the scroll top address, the scroll bottom address, the scroll specified
address, and the scroll start address carefully when using the scroll function. If there
is any error, the scrolling result will be inaccurate. Follow the rules shown below:
※ Scroll top address <= Scroll bottom address
※ Scroll specified address = Scroll top address + panel scroll area – 1
※ Scroll top address <= Scroll start address <= Scroll bottom address
7.17 Initial Values
ITEM
Display RAM
Initial Value
Not fixed
X Address
00H set
Y Address
00H set
Display starting common
Set at the first common(0H)
Display ON/OFF
Display OFF
Display Normal/Reverse
Normal
Display duty
1/128
n-line alternated
Every frame unit
(BF1,BF0)
(0,0)
Common shift direction
COM0 → COM127
Increment mode
Increment OFF
Register in electronic volume
(0,0,0,0,0,0,0)
Power Supply
OFF
Bias ratio
1/12 bias
Booster
6 times
Discharge Register
Disabled
RM value
8.9 times
Windows function
Disabled
Scrolling function
Disabled
7.18 Safety Measures when Switching Power ON and OFF
The high current that may occur when a voltage is supplied to the LCD driver power
supply while the system power supply is floating, could permanently damage the LSI.
Hence, the precautionary actions as detailed below should be taken into
considerations seriously when switching power on and off.
7.18.1 When Using the External Power Supply
Power ON Proper Sequence:
1) Logic system (VDD) power ON, perform a reset operation
2) Supply the external LCD drive voltage to the corresponding pins (V0, V1, V2, V3
and V4)
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 37
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Power OFF Proper Sequence:
1) Set the HALT register to “1” or perform a reset operation
2) Cut off external LCD drive voltage
3) Logic system (VDD) power OFF
NOTE
Connect the serial resistor (50 to 100Ω) or fuse to the LCD drive power V0 or VOUT
(when using the internal voltage conversion circuit) of the system as a current limiter.
In addition, set a suitable resister value of the resistor depending on the quality of the
LCD display.
7.18.2 When Using the Built-in Power Supply
Power ON Proper Sequence:
1) Logic system (VDD) power ON
2) Booster circuit system (VEE) power ON
3) Perform a reset operation and enable the booster and voltage conversion circuit.
NOTE
If the VDD and VEE voltages do NOT have the same potential, the logic system
(VDD) is automatically powered on first.
Power OFF Proper Sequence:
1) Set the HALT register to “1” or perform a reset operation
2) Booster circuit system (VEE) power OFF
3) Logic system (VDD) power OFF
If VDD and VEE do NOT have the same potential, cut off VEE first. After the VEE,
VOUT, V0, V1, V2, V3, and V4 voltages are below the LCD ON voltage (threshold
voltage when the Liquid Crystal is turned on), power off the logic system (VDD).
7.18.3 Power Supply Rising Time
Although there is no constraint on the rising time of the power supply, the Tr (rising
time) as illustrated below is recommended for practical applications.
90%
VDD,VEE
10%
Tr
Item
Recommended
Rising Time (Tr)
Applicable Power
Tr
30µS ~ 10ms*
VDD, VEE
* The rising time is the time between 10% adnd 90% of VDD, VEE
Figure 7-21 Recommended Rising Time (Tr) for Practical Application
38 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.19 Register Setting Examples
7.19.1 Initialization
Power ON (VDD,VEE-VSS)
Power will stable
RESET
W AIT
Setting Operational Functions
* Electrical volume set
* Bias Ratio set
Setting Operational Functions
* Setting power control
(DCON= "1", AMPON= "1")
End of initialization
Figure 7-22 Initialization Register Setting Sequential Flow
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 39
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.19.2 Display Data
End of initialization
Setting Operational Functions
* Setting display start common
* Setting address increment control
* Setting X address
* Setting Y address
Setting Operational Functions
* Write display data
Setting Operational Functions
* Setting display on/off control
(ON/OFF= "1")
End of display data setting
Figure 7-23 Display Data Register Setting Sequential Flow
7.19.3 Power OFF
Any condition
Setting Operational Functions
* Setting HALT=1 or make reset operation
(LCD driver output VSS level)
* Setting DIS= "1"
(Discharge V0-V4 capacitor)
WAIT
Power OFF ( VEE,VDD)
Figure 7-24 Power Off Register Setting Sequential Flow
40 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8
Control Register
8.1 Control Registers
8.1.1 Control Register (Bank 0)
Pins (for 80-Family) & Bank
Control Register
Address & Code
CSB RS WRB RDB RE2 RE1 RE0 D7
D6
D5
D4
D3
D2
Function
D1
D0
X Address
(Lower nibble)
[0H]
0
1
0
1
0
0
0
0
0
0
0
AX3 AX2 AX1 AX0
Set of X direction Address
in display RAM
X Address
(Upper nibble)
[1H]
0
1
0
1
0
0
0
0
0
0
1
AX7 AX6 AX5 AX4
Set of X direction Address
in display RAM
Y Address
[2H]
0
1
0
1
0
0
0
0
0
1
0
AY3 AY2 AY1 AY0
Set of Y direction Address
in display RAM
n-line altemation
(Lower nibble)
[3H]
0
1
0
1
0
0
0
0
0
1
1
N3
N2
N1
N0
Set the number of alternate
reverse line
n-line alternation
(Upper nibble)
[4H]
0
1
0
1
0
0
0
0
1
0
0
*
N6
N5
N4
Set the number of alternate
reverse line
SHIFT:
Select common
shift direction
ALL ON/
SHI
ALLON All display ON
*
ON OFF ON/OFF: Display ON/OFF
FT
control
REV: Display
normal/reverse
NLIN: n line reverse control
REV NLIN EOR REF EOR: Exclusive OR-ing the
AC waveform
REF: segment
normal/reverse
WIN: Select window.
AIM: Select increment
mode
WIN AIM AYI AXI
AYI: Y increment, AXI: X
increment
AMPON: Internal AMP. ON
HALT: Power saving
AMP HA DC
ACL
DCON: Boosting circuit ON
ON LT ON
ACL: Resetting
Display control (1)
[5H]
0
1
0
1
0
0
0
0
1
0
1
Display control (2)
[6H]
0
1
0
1
0
0
0
0
1
1
0
Increment control
[7H]
0
1
0
1
0
0
0
0
1
1
1
Power control
[8H]
0
1
0
1
0
0
0
1
0
0
0
[9H]
0
1
0
1
0
0
0
1
0
0
1
DS3 DS2 DS1 DS0
Set LCD drive duty ratio
[AH]
0
1
0
1
0
0
0
1
0
1
0
DS3 DS2 DS1 DS0
Set LCD drive duty ratio
Booster
[BH]
0
1
0
1
0
0
0
1
0
1
1
*
Bias ratio control
[CH]
0
1
0
1
0
0
0
1
1
0
0
B3
[EH]
0
1
0
1
0
0
0
1
1
1
0
SC3 SC2 SC1 SC0
[FH]
0
1
0
1
0/1
0/1
0/1
1
1
1
1
RE2 RE1 RE0
LCD Duty ratio
(Lower nibble)
LCD Duty ratio
(Upper nibble)
Register access
control
Display start
common
VU2 VU1 VU0
B2
B1
B0
Set number of boosting step
for booster circuit
Set bias ratio
for LCD driving voltage
Set common driver start line
RE: set register bank
number
NOTE: Address for the control register are enclosed in brackets [ ].
* = Don’t Care
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 41
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.1.2 Control Register (Bank 1)
Pins (for 80-Family) & Bank
Address & Code
Control Register
Function
CSB
Temperature
compensation
RS WRB RDB RE2 RE1 RE0
D7
D6
D5
D4
D3
D2
*
*
D1
D0
[0H]
0
1
0
1
0
0
1
0
0
0
0
[1H]
0
1
0
1
0
0
1
0
0
0
1
[2H]
0
1
0
1
0
0
1
0
0
1
0
Register read control
[3H]
0
1
0
1
0
0
1
0
0
1
1
RA3 RA2 RA1 RA0
Set RF
[4H]
0
1
0
1
0
0
1
0
1
0
0
RF3 RF2 RF1 RF0
Extend Power Control
[5H]
0
1
0
1
0
0
1
0
1
0
1
BF1 BF0
Regulator multiple ratio
Control
[6H]
0
1
0
1
0
0
1
0
1
1
0
Start address for line
reverse (Low nibble)
[7H]
0
1
0
1
0
0
1
0
1
1
1
Start address for line
reverse (Upper nibble)
[8H]
0
1
0
1
0
0
1
1
0
0
0
End address for line
reverse (Low nibble)
[9H]
0
1
0
1
0
0
1
1
0
0
1
End address for line
reverse (Upper nibble)
[AH]
0
1
0
1
0
0
1
1
0
1
0
Electronic Volume
(Low nibble)
Electronic Volume
(Upper nibble)
Line reverse
[BH]
0
1
0
1
0
0
1
1
0
1
1
Window X end address
(Low nibble)
[CH]
0
1
0
1
0
0
1
1
1
0
0
Window X end address
(Upper nibble)
[DH]
0
1
0
1
0
0
1
1
1
0
1
Window Y end Address
[EH]
0
1
0
1
0
0
1
1
1
1
0
Register Access Control
[FH]
0
1
0
1
0/1
0/1
0/1
1
1
1
1
TCS1 TCS0
DV3 DV2 DV1 DV0
*
*
DV6 DV5 DV4
*
Temperature
compensation set
Set electronic
volume register
Set register
address for read
Select RF ratio of
OSC circuit
Set booster
frequency
DIS
Discharge V0~V4
capacitors
RM2 RM1 RM0
Set regulator
multiple ratio
LS3 LS2 LS1 LS0
*
Set start line for
line reverse
LS6 LS5 LS4 display
LE3 LE2 LE1 LE0
*
*
LE6 LE5 LE4
*
Set end line for
line reverse
display
BT Reverse type
select
BT LREV
LREV: Line
reverse control
EX3 EX2 EX1 EX0 Set X end
address for
window function
EX7 EX6 EX5 EX4 access
Set Y end
EY3 EY2 EY1 EY0 address for
window function
RE: Set register
RE2
RE1
RE0
*
bank number
NOTE: Address for the control register are enclosed in brackets [ ].
* = Don’t Care
42 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.1.3 Control Register (Bank 2)
Pins (for 80-Family) & Bank
Address & Code
Control Register
Function
CSB
RS WRB RDB RE2 RE1 RE0
D7
D6
D5
D4
D3
D2
D1
*
M1
M0
D0
VPP_ EEPROM mode
EXT select
EEPROM mode select
[0H]
0
1
0
1
0
1
0
0
0
0
0
Vop calibration offset
select (Low nibble)
[1H]
0
1
0
1
0
1
0
0
0
0
1
Vop calibration offset
select (Upper nibble)
[2H]
0
1
0
1
0
1
0
0
0
1
0
*
*
CV5 CV4
EEPROM address select [5H]
0
1
0
1
0
1
0
0
1
0
1
*
*
NIB1 NIB0
Scroll top address
(Low nibble)
[6H]
0
1
0
1
0
1
0
0
1
1
0
Scroll top address
(Upper nibble)
[7H]
0
1
0
1
0
1
0
0
1
1
1
Scroll bottom address
(Low nibble)
[8H]
0
1
0
1
0
1
0
1
0
0
0
Scroll bottom address
(Upper nibble)
[9H]
0
1
0
1
0
1
0
1
0
0
1
Scroll specified address
(Low nibble)
[AH]
0
1
0
1
0
1
0
1
0
1
0
Scroll specified address
(Upper nibble)
[BH]
0
1
0
1
0
1
0
1
0
1
1
Scroll start address
(Low nibble)
[CH]
0
1
0
1
0
1
0
1
1
0
0
Scroll start address
(Upper nibble)
[DH]
0
1
0
1
0
1
0
1
1
0
1
*
Scroll mode select
[EH]
0
1
0
1
0
1
0
1
1
1
0
*
[FH]
0
1
0
1
0/1
0/1
0/1
1
1
1
1
*
Register Access Control
CV3 CV2 CV1 CV0
STA3 STA2 STA1 STA0
*
STA6 STA5 STA4
SBA3 SBA2 SBA1 SBA0
*
SBA6 SBA5 SBA4
SSA3 SSA2 SSA1 SSA0
*
SSA6 SSA5 SSA4
SAY3 SAY2 SAY1 SAY0
SAY6 SAY5 SAY4
*
SM1 SM0
RE2 RE1 RE0
Vop calibration
offset select
Select
EEPROM
address
Set scroll top
address
Set scroll
bottom address
Set scroll
specified
address
Set scroll start
address
Scroll mode
select
RE: set register
bank number
NOTE: Address for the control register are enclosed in brackets [ ].
*= Don’t Care
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 43
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2 Functions of the Control Registers
The EM65101 has many control registers. When accessing the control registers, the
upper nibble of the data bus (D7~D4) represent the register address while the lower
nibble of the data bus (D3~D0) represent data. The following figure shows an access
example. The Pins CSB, RS, RDB, & WRB) settings are for the 80-family MPU
interface. Only the setting of the terminals RDB & WRB are different when it is
accessed by the 68-family MPU.
(Example) X Address:
D7
0
D6
0
D5
0
D4
0
D3
AX3
Register address
D2
AX2
D1
AX1
D0
AX0
CSB
0
Data
RS
1
RDB
1
WRB
0
Pins setting
RE2
0
RE1
0
RE0
0
Register Bank
When writing to the control register, it is used directly by addressing D7~D4 of the data
bus. When reading, you must first set the RA register for the specific register address
before you can read specific register. Therefore, a 2-step procedure is required to
perform a read register operation. After reading, the specific register will output to
D3~D0 of the data bus. All nibbles, except D3~D0, of the data bus are all “H.” Access
to undefined register address area is prohibited. When RS is “L,” all read/write
operations are accessed to display RAM. Then the data bus does not include the
register address. When writing, D3~D0 data is written to the register designated at
D7~D4 on the rising edge of the WRB signal. When reading, the register can output to
data bus during RDB active period. The control register and display RAM have equal
access sequence
8.2.1 X Address Register (AX)
D7
D6
D5
D4
0
0
0
0
D3
D2
D1
D0
AY3 AX2 AY1 AY0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
0
(At the time of reset: {AX3, AX2, AX1, AX0} = 0H, read address: 0H)
D7
D6
D5
D4
0
0
0
1
D3
D2
D1
D0
AX7 AX6 AX5 AX4
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
0
(At the time of reset: {AX7, AX6, AX5, AX4} = 0H, read address: 1H)
The AX register is set to X-direction address of display RAM. In data setting, command
is divided into lower and upper sections at 4-bit of data each in order to accommodate
the required 8-bit of total data.
8.2.2 Y Address Register (AY)
D7
D6
D5
D4
0
0
1
0
D3
D2
D1
D0
AY3 AX2 AY1 AY0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
0
(At the time of reset: {AY3, AY2, AY1, AY0} =0H, read address: 2H)
The AY register is set to Y-direction address of display RAM. 00H to 0FH are
applicable to the values for AY3 to AY0.
44 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.3 n Line Alternated Register (N)
D7
D6
D5
D4
D3
D2
D1
D0
CSB
0
0
1
1
N3
N2
N1
N0
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
0
(At the time of reset: {N3, N2, N1, N0}=3H, read address: 3H)
D7
D6
D5
D4
D3
D2
D1
D0
CSB
0
1
0
0
*
N6
N5
N4
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
0
(At the time of reset: {N7, N6, N5, N4}=0H, read address: 4H)
The EM65101 supports not only the LCD reversed AC drive in one-frame unit, but also
the n-line reversed AC drive which alternates in an n-line unit from 2 to 128 lines. The
reversed AC drive is controlled by the “NLIN” and “EOR” control bits. The values set up
by the alternating register become enabled when the NLIN control bit is “1.” When the
NLIN control bit is “0,” the alternate drive waveform is generated reserving each frame.
When a problem affecting display quality occurs, the n-line reversed AC drive can
improve the quality. Determine the number of the n-line reverse for alternating after
confirming the display quality with the actual LCD panel.
However, if the number of AC reversed lines are reduced, the LCD alternating
frequency becomes high. As a result, the charge or discharge current is increased in
the LCD cells.
N6
N5
N4
N3
N2
N1
N0
EOR=0
N Line Number
EOR=1
N Line Number
0
0
0
0
0
0
0
No operation
No operation
0
0
0
0
0
0
1
2
2
0
0
0
0
0
1
0
3
3
0
0
0
0
0
1
1
4
4
0
0
0
0
1
0
0
5
5
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
64
64
:
:
:
:
:
:
:
:
1
1
0
0
0
1
1
100
1
1
0
0
1
0
0
101
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
128
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Prohibited Code
• 45
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.4 Display Control Display (1) Register
D7
0
D6
1
D5
0
D4
1
D3
D2
D1
D0
CSB
*
ALL
ON
ON/
OFF
0
SHIFT
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
0
(At the time of reset: {SHIFT, ALLON, ON/OFF}=0H, read address: 5H)
ON/OFF: Control display ON/OFF
ON/OFF = “0”: Display OFF
ON/OFF = “1”: Display ON
ALLON: Regardless of the data for display, all is ON.
This control has priority over display normal/reverse commands.
ALLON = “0”: Normal display
ALLON = “1”: All display lighted
SHIFT
The shift direction of display scanning data in the common driver output is selected.
SHIFT = “0”: COM0 COM127 shift-scan
SHIFT = “1”: COM127 COM0 shift-scan
8.2.5 Display Control (2) Register
D7
D6
D5
D4
0
1
1
0
D3
D2
D1
D0
REV NLIN EOR REF
CSB
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
0
(At the time of reset: {REV, NLIN, EOR, REF} = 0H, read address: 6H)
REV: To the corresponding display RAM data, the lighting or non-lighting control of the
display is set.
REV =”0”: When RAM data is “H,” and LCD at ON voltage (normal)
REV =”1”: When RAM data is “L,” and LCD at ON voltage (reverse)
NLIN: The n-line alternate drive NLIN control.
NLIN = “0”: n-line alternate drive is OFF. In each frame, the alternate signals (M) are
reversed.
NLIN =”1”: n-line alternated drive is ON. Depending on data set up in the n-line
alternated register, alternation is made.
EOR: The n-line alternate drive EOR control.
46 •
EOR=0:
M always reverses at the nth raster row regardless of whether the end of a
frame is reached.
EOR=1:
M reverses at the nth raster row and restarts the raster row count at the start
of every frame.
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
REF: When MPU accesses display RAM, address X and data are switched. The
following figure shows the action of the REF.
SEG0
SEG1
SEG2
00H
SEG3
SEG156
01H
SEG157
SEG158 SEG159
4EH
4FH
1 1 0 0 0 1 0 1 1 0 1 0 0 0 0 1
1 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1
1 1 1 1
0
0 1
0 1 1 0
1 0
1 0 1 1 1
0 0 1 1
1 0 0
0
1 1
0 1
0 0 1
0 0
1 0
1 1 0 1
0 1
0 1 0 0
1
Figure 8-1 REF Register Function
8.2.6 Increment Control Register Set
D7
D6
D5
D4
0
1
1
1
D3
D2
D1
D0
CSB
WIN AIM AYI
AXI
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
0
(At the tine of reset: {WIN, AIM, AYI, AXI} = 0H, read address: 7H)
This register controls the increment mode and the window function when accessing
display RAM. The increment operation of the AXI and AYI registers are controlled by
the settings at the AIM, AYI, and AXI registers, and every write or read access to
display RAM. The AYI register directly connects to display RAM as Y address. The
AXI register connects to the address converter, and then outputs to display RAM as X
address in auto increment mode. The AXI and AYI registers are incremented, but do
not directly increment the X and Y addresses.
When setting this control register, the address increment operation can be made
without setting successive addresses for writing or reading data to display RAM from
MPU.
The WIN register is used for window function control.
WIN=”0”: Normal RAM access
WIN=”1”: Window function access
When using the window function to access RAM, be sure to set the following register
first.
WIN=”1,” AXI=”1,” AYI=”1”
X Address, Y Address, Window X End Address, Window Y End Address
In addition, the following condition must be met.
Window end X address ≧ Window start X address
Window end Y address ≧ Window start Y address
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 47
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
The increment control of X and Y addresses by AIM, AYI, and AXI registers are listed
as follows.
AIM
0
1
Address Increment Timing
When writing to Display RAM or reading from Display RAM
This is effective when accessing successive address area
Only when writing to Display RAM
This is effective in the case of “Read Modify Write”
Sequence for Read Modify Write
Set
AXI=1,AYI=1
AIM=1
Set Modify read
Dummy read
X address
autoincrement 1
Read 1 byte RAM
data
Repeat 4
times
Write 1 byte
RAM data
Yes
Write
Continuous?
No
End
Figure 8-2 Read Modify Write Flow Chart
48 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
AYI
AXI
0
0
1
1
0
1
0
1
Select Address Increment Operation
Remark
Address is not incremented
X-Address is incremented
Y-Address is incremented
X and Y both are incremented
*1
*2
*3
*4
*1 Regardless of AIM, no increment for the AX and AY registers.
*2 Depending on the setting of AIM, address X automatically changes.
Transition of AX Register
00H
01H
.......
maxH*
*maxH: The maximum internal X-address value in each access mode
*3 Depending on the setting of AIM, address Y automatically changes.
Transition of AY Register
00H
01H
.......
Transition of Y Address
0FH
Same as AY register
*4 Depending on the setting of AIM, addresses X and Y also change. When the X
address exceeds maxH, Y address is incremented.
Transition of AX and AY Register
Transition of X and Y Address
AX:
AY:
00H
00H
maxH*
Same as AX and AY register
When each AX exceed maxH*, increment AY
00H
00H
9FH
*maxH: The maximum internal X-address value in each access mode
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 49
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
The following shows how address is incremented when using the window function.
Transition of AX and AY Register
Transition of X and Y Address
AX:
START
Address
START
Address+1
END
Address
AY:
When each AX exceed AE, increment AY
START
Address
START
Address+1
Same as AX and AY register
END
Address
In each operation mode, the following increment operation is performed:
When gradation display mode and 8-bit access are selected
Address is incremented as described above.
8.2.7 Power Control Register
D7
D6
D5
D4
1
0
0
0
D3
D2
D1
D0
CSB RS RDB WRB RE2 RE1 RE0
AMPON HALT DCON ACL
0
1
1
0
0
0
0
(At the tine of reset: {AMPON, HALT, DCON, ACL} = 0H, read address: 8H)
AMPON: This command sets the internal OP-AMP circuit block (voltage regulator,
electronic volume, and voltage conversion circuit) ON or OFF.
AMPON = “0”: The internal OP-AMP circuit is OFF
AMPON = ”1”: The internal OP-AMP circuit is ON
HALT:
This command sets power saving ON or OFF.
HALT = “0”: Normal operation
HALT=”1”: Power-saving operation
When power-saving is ON, the consumed current can be reduced to a value near to the
standby current.
The internal condition at power saving are as follows.
(1) The oscillating circuit and the power supply circuit are OFF.
(2) The LCD drive is OFF, and the output of the segment driver and common driver is
at the VSS level.
(3) The clock input from the CK pin is prohibited.
(4) The contents of Display RAM data are stored.
(5) The operational mode stores the state of command executed before the power
saving command is performed.
50 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
DCON: This command sets the internal booster circuit ON or OFF.
DCON = “0”: Booster circuit OFF
DCON=”1”: Booster circuit ON
ACL: This command initializes the internal circuit.
ACL = “0”: Normal operation
ACL = “1”: Initialization ON
When the reset operation begins internally after the ACL register is set to “1,” the ACL
register is automatically cleared to “0.” The internal reset signal is generated with a
clock (built-in oscillation circuit or CK input) for display. Therefore, set the WAIT period
to at least two display clock cycles. After the WAIT period, the subsequent operation is
then executed.
8.2.8 LCD Duty (DS)
D7
D6
D5
D4
1
0
0
1
D3
D2
D1
D0
DS3 DS2 DS1 DS0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
0
(At the time of reset: {DS3, DS2, DS1, DS0} = 0H, read address: 9H)
D7
D6
D5
D4
1
0
1
0
D3
D2
D1
D0
DS7 DS6 DS5 DS4
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
0
(At the time of reset: {DS7, DS6, DS5, DS4} = 8H, read address: AH)
The DS register set to LCD display duty.
Selectable
Duty ratio
DS7
DS6
DS5
DS4
DS3
DS2
DS1
DS0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1/8
0
0
0
0
1
0
0
1
1/9
:
:
:
:
:
:
:
:
:
0
1
1
0
0
1
0
0
1/100
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1
1/127
1/128
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
No operation
No operation
Partial display can be made possible by setting an arbitrary duty ratio.
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 51
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.9 Booster Setup (VU)
D7
D6
D5
D4
1
0
1
1
D3
D2
D1
D0
CSB
VU2 VU1 VU0
*
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
0
(At the time of reset: {VU2, VU1, VU0} = 5H, read address: BH)
The booster steps are set to the VU register
VU2
VU1
VU0
Booster Operation
0
0
0
Booster disable (No operation)
0
0
1
2 times voltage output
0
1
0
3 times voltage output
0
1
1
4 times voltage output
1
0
0
5 times voltage output
1
0
1
6 times voltage output
1
1
0
1
1
1
Prohibited code
8.2.10 Bias Setting Register (B)
D7
D6
D5
D4
D3
D2
D1
D0
CSB
1
1
0
0
B3
B2
B1
B0
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
0
(At the time of reset: {B3, B2, B1, B0} = 8H, read address: CH)
This register is used to set a bias ratio. A bias ratio can be selected from 1/4 to 1/13
through B3, B2, B1, and B0 set up.
B3
0
0
0
0
0
0
0
0
1
1
1
:
1
B2
0
0
0
0
1
1
1
1
0
0
0
:
1
B1
0
0
1
1
0
0
1
1
0
0
1
:
1
B0
0
1
0
1
0
1
0
1
0
1
0
:
1
Bias
1/4 Bias
1/5 Bias
1/6 Bias
1/7 Bias
1/8 Bias
1/9 Bias
1/10 Bias
1/11 Bias
1/12 Bias
1/13 Bias
Prohibited code
NOTE
When setting bias=1/4 and 1/5, V4 must be less than the VDD voltage
52 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.11 Display Start Common
D7
D6
D5
D4
1
1
1
0
D3
D2
D1
D0
CSB
RS
0
1
SC3 SC2 SC1 SC0
RDB WRB RE2 RE1 RE0
1
0
0
0
0
(At the time of reset: {SC3, SC2, SC1, SC0} = 0H, read address: EH)
The SC register sets the scanning start output of the common driver.
SC3
SC2
SC1
Display Starting Common
SC0
When SHIFT=0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
When SHIFT=1
COM0
COM8
COM16
COM24
COM32
COM40
COM48
COM56
COM64
COM72
COM80
COM88
COM96
COM104
COM112
COM120
COM127
COM119
COM111
COM103
COM95
COM87
COM79
COM71
COM63
COM55
COM47
COM39
COM31
COM23
COM15
COM7
8.2.12 Temperature Compensation Set
D7
D6
D5
D4
D3
D2
0
0
0
0
*
*
D1
D0
TCS1 TCS0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
1
* = Don’t Care
(At the time of reset: { TCS1, TCS0 } = 0H, read address: 0H)
TCS1
TCS0
0
0
1
1
0
1
0
1
Temperature Compensation Slope
-0.05% per °C
-0.1% per °C
-0.15% per °C
-0.2% per °C
VREF (T) (Temperature compensation output voltage) is controlled by TCS1, TCS0 and
the previous environment temperature T.
V REF (T ) = VREF 0 [(1 + TCS (T − 25 0 C )]
TCS is selected by TCS1 and TCS0
VREF0 = 1.5V at 25°C
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 53
EM65101
LCD driving voltage
128COM/160SEG 16 Gray Scale Level LCD Driver
TCS: 00 -0.05% / °C
TCS: 01 -0.1% / °C
TCS: 10 -0.15% / °C
TCS: 11 -0.2% / °C
Temperature
Figure 8-3 Temperature Compensation Slope
8.2.13 Electronic Volume Register
D7
D6
D5
D4
0
0
0
1
D3
D2
D1
D0
CSB
RS
0
1
DV3 DV2 DV1 DV0
RDB WRB RE2 RE1 RE0
1
0
0
0
1
(At the time of reset:{ DV3~DV0 } = 0H, read address: 1H)
D7
D6
D5
D4
D3
0
0
1
0
*
D2
D1
D0
CSB
DV6 DV5 DV4
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
1
* = Don’t Care
(At the time of reset:{ DV6~DV4 } = 0H, read address: 2H)
The DV register controls the VBA voltage. This 7-bit register provides up to 65 levels of
voltage selections.
DV6
0
0
:
0
0
:
1
1
:
1
DV5
0
0
:
0
1
:
1
1
:
1
DV4
0
0
:
1
0
:
0
0
:
1
DV3
0
0
:
1
0
:
0
0
:
1
DV2
0
0
:
1
0
:
0
0
:
1
DV1
0
0
:
1
0
:
0
0
:
1
DV0
0
1
:
1
0
:
0
1
:
1
Output Voltage
Prohibit code
32
:
96
Prohibited code
VBA= (1+( M + offset) / 381)* VREF
V0 = VBA * N
M : DV register setting ; offset : CV0~CV5 set on EEPROM function
N : RM register setting
VREF : internal temperature compensation output voltage
54 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
In order to prevent the transient voltage from generating when an electronic volume
code is set, the circuit design is such that the set value is not reflected as a level
immediately. The value is reflected after the upper bits(DV6-DV4) of the electronic
code have been set. The set value becomes valid when the lower bits (DV3-DV0) of
the electronic control volume code have also been set.
NOTE
When writing code to set the electronic volume register, you must set DV6~DV4 first
before setting DV3~DV0.
8.2.14 Internal Register Read Address
D7
D6
D5
D4
0
0
1
1
D3
D2
D1
D0
RA3 RA2 RA1 RA0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
1
(At the time of reset: {RA3, RA2, RA1, RA0} = 7H, read address: 3H)
The RA register specifies the address for register read operation. The EM65101 has
many registers and one register bank. Therefore, the following 4-step procedure is
required to read the specific register.
(1) Write 01H to the RE register for accessing the RA register
(2) Writes the specific register address to the RA register
(3) Write the specific register bank to the RE register
(4) Read specific contents
8.2.15 Resistance Ratio of the CR Oscillator
D7
D6
D5
D4
0
1
0
1
D3
D2
D1
D0
RF3 RF2 RF1 RF0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
1
(At the time of reset: {RF3, RF2, RF1, RF0} = 0H, read address: 8H)
The RF registers can control the resistance ratio of the CR oscillator. Therefore the
frame frequency can change the settings at the RF registers.
When changing the RF registers, make sure to check the LCD display quality.
RF3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RF2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RF1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RF0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Operation
Initial Resistance Ratio
0.52 times of initial Resistance Ratio
0.60 times of initial Resistance Ratio
0.68 times of initial Resistance Ratio
0.74 times of initial Resistance Ratio
0.80 times of initial Resistance Ratio
0.88 times of initial Resistance Ratio
0.94 times of initial Resistance Ratio
1.06 times of initial Resistance Ratio
1.12 times of initial Resistance Ratio
1.20 times of initial Resistance Ratio
1.28 times of initial Resistance Ratio
1.36 times of initial Resistance Ratio
1.44 times of initial Resistance Ratio
1.52 times of initial Resistance Ratio
1.60 times of initial Resistance Ratio
• 55
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.16 Extended Power Control
D7
D6
D5
D4
0
1
0
1
D3
D2
D1
D0
CSB
*
DIS
0
BF1 BF0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
1
* = Don’t Care
(At the time of reset: {BF1, BF0, DIS} = 0H; read address: 5H)
DIS: is the register that controls the capacitors (connected between the power supply
V0-V4 for the LCD drive voltage and VSS) voltage discharged to VSS.
DIS = “0”: Disable
DIS = “1”: Enable
BF1~BF0: The operating frequency in the booster is selected. When the boosting
frequency is high, the driving ability of the booster become high, but the current
consumption is increased. You must take the external capacitors and the current
consumption into consideration when adjusting the boosting frequency.
BF1
BF0
0
0
1
1
0
1
0
1
Operating Clock Frequency in the Booster
3K Hz * 8
3K Hz * 4
3K Hz * 2
3 K Hz
8.2.17 Regulator Multiple Ratio Control
D7
D6
D5
D4
D3
0
1
1
0
*
D2
D1
D0
RM2 RM1 RM0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
1
* = Don’t Care
(At the time of reset: {RM2, RM1, RM0} = 6H, read address: 6H)
The V0 modified range setting for RM register
56 •
RM2
RM1
RM0
Regulator Multiple Ratio Control
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.0 times voltage output
4.0 times voltage output
5.0 times voltage output
6.5 times voltage output
8.0 times voltage output
8.5 times voltage output
8.9 times voltage output
Prohibited code
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Vref=1.5V, V0 modified range is shown in the following figure:
The relationship between DV and V0
19
16
V0
RM=3
13
RM=4
10
RM=5
RM=6.5
7
RM=8
4
RM=8.5
0
30
60
90
120
RM=8.9
DV value
Figure 8-4 V0 Modified Range
8.2.18 Line Reverse Start Address
D7
D6
D5
D4
0
1
1
1
D3
D2
D1
D0
CSB
LS3 LS2 LS1 LS0
RS RDB WRB RE2 RE1 RE0
0
1
1
0
0
0
1
(At the time of reset: {LS3, LS2, LS1, LS0} = 0H, read address: 7H)
D7
D6
D5
D4
D3
1
0
0
0
*
D2
D1
D0
LS6 LS5 LS4
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
1
* = Don’t Care
(At the time of reset: { LS6, LS5, LS4} = 0H, read address: 8H)
When setting the line reverse range, the panel on the defined range will be reversed.
NOTE
The RAM data is not changed.
LS6
0
0
:
1
1
LS5
0
0
:
1
1
LS4
0
0
:
1
1
LS3
0
0
:
1
1
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
LS2
0
0
:
1
1
LS1
0
0
:
1
1
LS0
0
1
:
0
1
Start Common Number
COM0
COM1
:
COM126
COM127
• 57
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.19 Line Reverse End Address
D7
D6
D5
D4
1
0
0
1
D3
D2
D1
D0
CSB
RS
0
1
LE3 LE2 LE1 LE0
RDB WRB RE2 RE1 RE0
1
0
0
0
1
(At the time of reset: {LE3, LE2, LE1, LE0} = 0H, read address: 9H)
D7
D6
D5
D4
D3
1
0
1
0
*
D2
D1
D0
CSB
RS
0
1
LE6 LE5 LE4
RDB WRB RE2 RE1 RE0
1
0
0
0
1
* = Don’t Care
(At the time of reset: { LE6, LE5, LE4} = 0H, read address: AH)
The LE registers sets the line reverse end address.
LE6
0
0
:
1
1
LE5
0
0
:
1
1
LE4
0
0
:
1
1
LE3
0
0
:
1
1
LE2
0
0
:
1
1
LE1
0
0
:
1
1
LE0
0
1
:
0
1
End Common Number
COM0
COM1
:
COM126
COM127
8.2.20 Line Reverse Control
D7
D6
D5
D4
D3
D2
D1
D0
CSB
1
0
1
1
*
*
BT
LREV
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
0
1
* = Don’t Care
(At the time of reset: {BT, LREV} = 0H, read address: BH)
LREV: is the register that sets the line reverse display function.
LREV = “0”: Normal display (Not reverse).
LREV = “1”: Line reverse display enable.
The area specified by the Line Reverse Start/End register reverses the display.
BT: is the register that selects the reverse type.
When using the Line Reverse Display function, the LS and LE registers must meet the
following condition.
LS ≦ LE
The BT register control line reverse type is an option of the line reverse display
function. This BTs setting is only available when LREV=”1”
BT = “0”: Reverse display
BT = “1”: Reverse display at each 32 frame.
Display change
each 32 frame
Figure 8-5 Blink Example (LREV=”1,” BT=”1”)
58 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.21 Window End X Address
D7
D6
D5
D4
1
1
0
0
D3
D2
D1
D0
EX3 EX2 EX1 EX0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
1
(At the time of reset: {EX3, EX2, EX1, EX0} = 1H, read address: CH)
D7
D6
D5
D4
1
1
0
1
D3
D2
D1
D0
EX7 EX6 EX5 EX4
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
1
(At the time of reset: {EX7, EX6, EX5, EX4} = 0H, read address: DH)
The EX registers set the X direction end address of the window function.
EX7
EX6
EX5
EX4
EX3
EX2
EX1
EX0
0
0
:
0
0
:
1
1
0
0
:
1
1
:
0
0
0
0
:
1
1
:
0
0
0
0
:
1
1
:
1
1
0
0
:
1
1
:
1
1
0
0
:
1
1
:
1
1
0
0
:
1
1
:
1
1
0
1
:
0
1
:
0
1
Window Column
Address
Prohibited Code
1
:
126
127
:
158
159
8.2.22 Window End Y Address
D7
D6
D5
D4
1
1
1
0
D3
D2
D1
D0
EY3 EY2 EY1 EY0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
0
1
(At the time of reset: {EY3, EY2, EY1, EY0} = 0H, read address: EH)
The EY registers set the Y direction end address of the window function.
EY3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
EY2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
EY1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EY0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Window Y Address
COM7
COM15
COM23
COM31
COM39
COM47
COM55
COM63
COM71
COM79
COM87
COM95
COM103
COM111
COM119
COM127
• 59
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.23 EEPROM Mode Select Register
D7
0
D6
D5
0
D4
0
0
D3
*
D2
M1
D1
D0
CSB
RS
M0
VPP_
EXT
0
1
RDB WRB RE2 RE1 RE0
1
0
0
1
0
* = Don’t Care
(At the time of reset: {M1, M0, VPP_EXT } = 6H, read address: 0H)
The (M1,M0) register controls the EEPROM mode
(M1,M0)
00
01
10
11
EEPROM Operating Mode
Read
Program
Erase
Reserve
Delay Time
> 10 uS
> 4 mS
> 4 mS
-
The VPP_EXT register controls the EEPROM power selection.
VPP_EXT=0
Program or Erase EEPROM voltage from internal power.
VPP_EXT=1
Program or Erase EEPROM voltage from external power. Forces
17~18V from the VPP pin externally.
8.2.24 Vop Calibration Offset Register
D7
D6
D5
D4
0
0
0
1
D3
D2
D1
D0
CV3 CV2 CV1 CV0
CSB
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
1
0
(At the time of reset: {CV3, CV2, CV1, CV0} = 0H, read address: 1H)
D7
D6
D5
D4
D3
D2
0
0
1
0
*
*
D1
D0
CV5 CV4
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
1
0
* = Don’t Care
(At the time of reset: {CV5, CV4} = 0H, read address: 2H)
The CV5~CV0 registers control the Vop calibration offset voltage selection
VBA= (1+ (M + offset) / 381)* VREF
M : DV register setting ; offset : CV5~CV0 setting
CV5~CV0
011111
011110
…
000001
000000
100000
100001
…
111111
60 •
Calibration Offset
+31
+30
…
+1
0
-32
-31
…
-1
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.25 EEPROM Address Select Register
D7
D6
D5
D4
D3
D2
0
1
0
1
*
*
D1
D0
NIB1 NIB0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
1
0
* = Don’t Care
(At the time of reset: {NIB1, NIB0} = 0H, read address: 5H)
The NIB register selects whether to access the low nibble or high nibble data of
EEPROM.
NIB1
0
0
NIB0
0
1
EEPROM Address
Bank 2[1H] (CV3~CV0)
Bank 2[2H] (CV5~CV4)
NOTE
When settings CV5~CV0, you must set CV5~CV4 (upper nibble registers) first,
then set CV3~CV0 (lower nibble registers), and then start program execution.
The programming sequence of CV5~CV4 and CV3~CV0 has no restriction.
When reading from CV5~CV0, you must read EEPROM data to CV5~CV4
(upper nibble registers) first, then read EEPROM data to CV3~CV 0(lower
nibble registers).
8.2.26 Scroll Top Address
D7
D6
D5
D4
0
1
1
0
D3
D2
D1
D0
STA3 STA2 STA1 STA0
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
1
0
(At the time of reset: {STA3, STA2, STA1, STA0} = 0H, read address: 6H)
D7
D6
D5
D4
D3
0
1
1
1
*
D2
D1
D0
STA6 STA5 STA4
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
1
0
* = Don’t Care
(At the time of reset: {STA6, STA5, STA4} = 0H, read address: 7H)
Set the top address of scroll data area in RAM. 0 <= Scroll top address <= 127; Scroll
top address must be less than the Scroll bottom address
STA6
0
0
:
1
:
1
STA5
0
0
:
1
:
1
STA4
0
0
:
0
:
1
STA3
0
0
:
0
:
1
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
STA2
0
0
:
0
:
1
STA1
0
0
:
1
:
1
STA0
0
1
:
1
:
1
Top Common Line
COM0
COM1
:
COM99
:
COM127
• 61
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.27 Scroll Bottom Address
D7
D6
D5
D4
1
0
0
0
D3
D2
D1
D0
CSB
RS
0
1
SBA3 SBA2 SBA1 SBA0
RDB WRB RE2 RE1 RE0
1
0
0
1
0
(At the time of reset: {SBA3, SBA2, SBA1, SBA0} = FH, read address: 8H)
D7
D6
D5
D4
D3
1
0
0
1
*
D2
D1
D0
CSB
RS
0
1
SBA6 SBA5 SBA4
RDB WRB RE2 RE1 RE0
1
0
0
1
0
* = Don’t Care
(At the time of reset: {SBA6, SBA5, SBA4} = 7H, read address: 9H)
Set the bottom address of scroll data area in RAM. 0 <= Scroll bottom address <= 127 ;
The Scroll top address must be less than the scroll bottom address
SBA6
SBA5
SBA4
SBA3
SBA2
SBA1
SBA0
0
0
:
1
:
1
0
0
:
1
:
1
0
0
:
0
:
1
0
0
:
0
:
1
0
0
:
0
:
1
0
0
:
1
:
1
0
1
:
1
:
1
bottom common line
Mode0
COM0
COM1
:
COM99
:
COM127
8.2.28 Scroll Specified Address
D7
D6
D5
D4
1
0
1
0
D3
D2
D1
D0
CSB
RS
0
1
SSA3 SSA2 SSA1 SSA0
RDB WRB RE2 RE1 RE0
1
0
0
1
0
(At the time of reset: {SSA3, SSA2, SSA1, SSA0} = 0H, read address: AH)
D7
D6
D5
D4
D3
1
0
1
1
*
D2
D1
D0
SSA6 SSA5 SSA4
CSB
RS
0
1
RDB WRB RE2 RE1 RE0
1
0
0
1
0
* = Don’t Care
(At the time of reset: {SSA6, SSA5, SSA4} = 0H, read address: BH)
Depending on the display panel size or the duty ratio selection, set the specified
address in RAM to jump to the scroll bottom address and display the fixed data area.
Scroll specified address = scroll top address + panel scroll area – 1
62 •
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
0
0
:
1
:
1
0
0
:
1
:
1
0
0
:
0
:
1
0
0
:
0
:
1
0
0
:
1
:
1
0
0
:
0
:
1
0
1
:
0
:
1
Specified Common Line
Mode0
COM0
COM1
:
COM99
:
COM127
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
8.2.29 Scroll Start Address
D7
D6
D5
D4
1
1
0
0
D3
D2
D1
D0
CSB
0
SAY3 SAY2 SAY1 SAY0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
1
0
(At the time of reset: {SAY3, SAY2, SAY1, SAY0} = 0H, read address: CH)
D7
D6
D5
D4
1
1
0
1
D3
*
D2
D1
D0
CSB
RS
0
1
SAY6 SAY5 SAY4
RDB WRB RE2 RE1 RE0
1
0
0
1
0
* = Don’t Care
(At the time of reset: { SAY6, SAY5, SAY4} = 0H, read address: DH
Set the starting address of the area scrolling and then execute the area scrolling
operation. The scroll start address must be in the scrolling area.
Scroll top address <= Scroll start address <= Scroll bottom address
NOTE
You must set the scroll start address registers in the sequence: SAY[6:4] (Bank
2[DH]) first, then SAY[3:0] (Bank 2[CH]), to avoid any error.
8.2.30 Scroll Mode Select
D7
D6
D5
D4
D3
D2
1
1
1
0
*
*
D1
D0
CSB
SM1 SM0
0
RS RDB WRB RE2 RE1 RE0
1
1
0
0
1
0
* = Don’t Care
(At the time of reset: {SM1, SM0} = 0H, read address: EH)
SM1
0
0
1
1
9
SM0
0
1
0
1
Type of Area Scroll
Center screen scroll
Top screen scroll
Bottom screen scroll
Whole screen scroll
Absolute Maximum Ratings
Absolute maximum ratings
Item
Symbol
Condition
Pin Used
Rating
Unit
Supply voltage (1)
VDD
VDD
-0.3 ~ + 4.0
V
Supply voltage (2)
VEE
VEE
-0.3 ~ + 4.0
V
Supply voltage (3)
VOUT
VOUT
--0.3 ~ + 19
V
Supply voltage (4)
V0
V0
-0.3 ~ + 18.5
V
Supply voltage (5)
V1,V2,V3,V4
V1,V2,V3,V4
-0.3 ~ V0+ 0.3
V
Input voltage
VI
*1
-0.3 ~ VDD+ 0.3
V
Storage
temperature
Tstg
-45 ~ +125
℃
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Ta=25℃
• 63
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
9.1 Recommended Operating Conditions
Item
Supply voltage
Operating voltage
Symbol
Pin
Min.
VDD1
VDD
VDD2
Max.
Unit
Remarks
2.2
3.3
V
VDD
2.4
3.3
V
VEE
VEE
2.4
3.3
V
V0
V0
4.5
18.5
V
*1
*2
*3
*4
VOUT
VOUT
19
V
VREF
VREF
Operating
temperature
Typ.
1.5
Topr
V
-30
85
*5
℃
* 1 Power supply for the logic circuit.
* 2 Power supply for the analog circuit.
* 3 Power supply for the internal boosting circuit. If applied the same voltage as VDD,
connect to VDD.
* 4 Voltage V0>V1>V2>V3>V4>VSS must always be satisfied.
* 5 Voltage VOUT > V0 must always be satisfied.
10 DC Characteristics
VSS=0V , VDD = 2.2 ~3.3V , Ta = -30 ~85 ℃
Item
Symbol
Condition
Min.
Typ.
Max.
Unit Pin Used
High level input
voltage
VIH
0.8VDD
0.9VDD
VDD
V
*1
Low level input
voltage
VIL
0
0.1VDD
0.2VDD
V
*1
High level output
current
IOH1
VOH = VDD-0.4V
-2.7
-3.2
-3.5
mA
*2
Low level output
current
IOL1
VOL= 0.4V
2.7
3.2
3.5
mA
*2
High level output
current
IOH2
VOH = VDD-0.4V
-0.8
-1.0
-1.2
mA
*3
Low level output
current
IOL2
VOL= 0.4V
0.8
1.0
1.2
mA
*3
Input leakage
current
ILI1
VI = VSS or VDD
-2
0
2
µA
*4
Output leakage
current
ILO
VI = VSS or VDD
-2
0
2
µA
*5
V0=10V
1.0
1.3
1.6
V0=6V
1.2
1.7
2.2
KΩ
*6
5
15
µA
*7
340
350
KHz
*8
LCD driver output
resistance
RON
∆ |Von| =
0.5V
Standby current
through VDD pin
ISTB
CK=0, CSB=VDD, Ta=25℃,
VDD=3V
Oscillator frequency
(16 gradation mode)
Fosc
64 •
VDD=3V, Ta=25 ℃,
Rf setting = (Rf2,Rf1,Rf0)=(000)
330
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Item
Booster output
voltage on VOUT
pin
Unit
Pin
Used
6*VEE *0.95 6*VEE *0.98 6*VEE *0.99
V
*9
VOUT2
Five times boosting
5*VEE *0.95 5*VEE *0.98 5*VEE *0.99
RL = 500KΩ (VOUT-VSS)
V
*10
VOUT3
Four times boosting
4*VEE *0.95 4*VEE *0.98 4*VEE *0.99
RL = 500KΩ (VOUT-VSS)
V
*11
VOUT4
Three times boosting
3*VEE *0.95 3*VEE *0.98 3*VEE *0.99
RL = 500KΩ (VOUT-VSS)
V
*12
VOUT5
Two times boosting
RL = 500KΩ(VOUT-VSS)
2*VEE *0.95 2*VEE *0.98 2*VEE *0.99
V
*13
IDD1
VDD = 3V, 6 times booster
All ON pattern
270
µA
*14
IDD2
VDD = 3V, 6 times booster
Checker pattern
380
µA
*15
VBA
VDD =2.4V~3.3V
V
*16
VREF
VDD = 2.4 ~ 3.3V
V
*17
V0
VDD = 2.4 ~ 3.3V
V
-
Symbol
Condition
VOUT1
Six times boosting
RL = 500KΩ (VOUT-VSS)
Current
consumption
VBA output voltage
VREF output
voltage
V0 output voltage
*1
*2
*3
*4
*5
*6
Min.
Typ.
1.5
Max.
2.0
1.5
0.99*V0
V0
1.01*V0
D0-D7, CSB, RS, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins
D0~D7 pins
CLK pins
CSB, RS, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins
Applied when D0~D7 are in high impedance state
SEG0~SEGA159, COM0~COM127 pins Resistance when applied 0.5V between each output pin and each power
supply (V0, V1, V2, V3, V4) and when applied 1/12 bias
*7
*8
*9
VDD pin, VDD pin current without loading when the internal oscillating clock stops and CSB=VDD
Oscillating frequency when the built-in oscillating circuit (16 gray scale level display mode) is used
VOUT pin. When the built-in oscillating circuit, the built-in power supply, and the voltage (boosted 6 times) are
used, this pin is applied. When VEE = 2.4 ~ 3.3V, the electronic control is set to code (“1 1 1 1 1 1 1”).
Measuring conditions: bias=1/4~1/13, 1/128 duty, without loading. RL=500 KΩ (between VOUT and VSS),
C1=C2=1.0µF, C3=0.1µF, DCON=AMPON=”1,” BF=”11”
*10
VOUT pin. When the built-in oscillating circuit, the built-in power supply, and the voltage (boosted 5 times) are
used, this pin is applied. When VEE = 2.4 ~ 3.3V, the electronic control is set to code (“1 1 1 1 1 1 1”).
Measuring conditions: bias=1/4~1/13, 1/128 duty, without loading. RL=500 KΩ (between VOUT and VSS),
C1=C2=1.0µF, C3=0.1µF, DCON=AMPON=”1,” BF=”11”
*11
VOUT pin. When the built-in oscillating circuit, the built-in power supply, and the voltage (boosted 4 times) are
used, this pin is applied. When VEE = 2.4 ~ 3.3V, the electronic control is set to code (“1 1 1 1 1 1 1”).
Measuring conditions: bias=1/4~1/13, 1/128 duty, without loading. RL=500 KΩ (between VOUT and VSS),
C1=C2=1.0µF, C3=0.1µF, DCON=AMPON=”1,” BF=”11”
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 65
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
*12
VOUT pin. When the built-in oscillating circuit, the built-in power supply, and the voltage (boosted 3 times) are
used, this pin is applied. When VEE = 2.4 ~ 3.3V, the electronic control is set to code (“1 1 1 1 1 1 1”).
Measuring conditions: bias=1/4~1/13, 1/128 duty, without loading. RL=500 KΩ (between VOUT and VSS),
C1=C2=1.0µF, C3=0.1µF, DCON=AMPON=”1,” BF=”11”
*13
VOUT pin. When the built-in oscillating circuit, the built-in power supply, and the voltage (boosted 2 times) are
used, this pin is applied. When VEE = 2.4 ~ 3.3V, the electronic control is set to code (“1 1 1 1 1 1 1”).
Measuring conditions: bias=1/4~1/13, 1/128 duty, without loading. RL=500 KΩ (between VOUT and VSS),
C1=C2=1.0µF, C3=0.1µF, DCON=AMPON=”1,” BF=”11”
*14
VDD, VEE pin. When the built-in oscillating circuit and the built-in power supply are used and there is no access
from MPU, this pin is applied. Display ALL ON pattern {Rf3, Rf2, Rf1, Rf0 = (“0 0 0 0 ”)} and the LCD driver pin has
no loading. Measuring conditions: VDD=VEE=3V, V0=15V, C1=C2=1.0µF, C3=0.1µF, DCON=AMPON=”1,”
NLIN=”0,” 1/128 duty, 1/12 bias
*15
VDD, VEE pin. When the built-in oscillating circuit and the built-in power supply are used and there is no access
from MPU, this pin is applied. Voltage which is boosted 6 times is used and the electronic control is set to code.
Display a checkered pattern, {Rf3, Rf2, Rf1, Rf0 = (“0 0 0 0 ”)} and the LCD driver pin has no loading. Measuring
conditions: VDD=VEE=3V, V0=15V, C1=C2=1.0µF, C3=0.1µF, DCON=AMPON=”1” , NLIN=”0,” 1/128 duty, 1/12
bias
*16
VBA pin. Measuring conditions: N times boosting (N=2~6), electronic control = “1 1 1 1 1 1 1,” display a checkered
pattern, DCON=AMPON=”1,” NLIN=”0,” 1/128 duty, VDD=VEE, C1=C2=1.0µF, C3=0.1µF, no loading
*17
VREF pin. Measuring conditions: VDD = 3 volt, N times boosting (N=2 ~ 6), electronic control = “1 1 1 1 1 1 1,”
DCON=AMPON=”1,” NLIN=”0,” 1/128 duty.
The relationship of oscillating frequency (fosc) and external clock frequency (fCK) with
LCD frame frequency (fFLM) in each display mode is shown below:
Original
Display Mode
Oscillating
Clock
When using
Simple 16 gray
the built-in
scale levels
oscillating
circuit (fosc)
When using
the external
Simple 16 gray
scale levels
clock from CK
pin (fCK)
66 •
Ratio of Display Duty Cycle (1/D)
1/128 to 1/89
1/88 to 1/44
1/43 to 1/22
1/21 to 1/11
1/10~1/8
fosc/(2*16*D)
fosc/(4*16*D)
fosc/(8*16*D) fosc/(16*16*D) fosc/(32*16*D)
fCK/(2*16*D)
fCK/(4*16*D)
fCK/(8*16*D)
fCK/(16*16*D) fCK/(32*16*D)
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
11 AC Characteristic
NOTE
All the timings must be specified relative to 20% and 80% of the VDD voltage.
11.1 80-Family MCU Write Timing
tAH8
tAS8
CSB
RS
tWRLW8
WRB
tWRHW8
tDH8
tDS8
D0-D7
tCYCWR8
Figure 11-1 80-Family MCU Write Timing Diagram
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85℃
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Address hold time
tAH8
0
ns
Address setup time
tAS8
0
ns
System cycle time in
tCYCWR8
write
200
ns
Write pulse “L” width tWRLW8
30
ns
Write pulse “H” width tWRHW8
135
ns
Data setup time
tDS8
60
ns
Data hold time
tDH8
5
ns
Pin
Used
CSB
RS
WRB
(R/WB)
D0~D7
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85℃
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Address hold time
tAH8
0
ns
Address setup time
tAS8
0
ns
System cycle time in
tCYCWR8
write
250
ns
Write pulse “L” width
tWRLW8
50
ns
Write pulse “H” width tWRHW8
160
ns
Data setup time
tDS8
80
ns
Data hold time
tDH8
10
ns
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Pin
Used
CSB
RS
WRB
(R/WB)
D0~D7
• 67
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85℃
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Address hold time
tAH8
0
ns
Address setup time
tAS8
0
ns
System cycle time in
tCYCWR8
write
500
ns
Write pulse “L” width tWRLW8
100
ns
Write pulse “H” width tWRHW8
350
ns
Data setup time
tDS8
100
ns
Data hold time
tDH8
20
ns
Pin
Used
CSB
RS
WRB
(R/WB)
D0~D7
11.2 80-Family MCU Read Timing
tAH8
tAS8
CSB
RS
tRDLW8
RDB
tRDHW8
tRDH8
tRDD8
D0-D7
tCYCRD8
Figure 11-2 80-Family MCU Read Timing Diagram
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85℃
68 •
Item
Symbol
Address hold time
tAH8
Address setup time
System cycle time
in read
Condition
Min.
Unit
Pin Used
0
ns
tAS8
0
ns
CSB
RS
tCYCRD8
380
ns
Read pulse “L”
width
tRDLW8
200
ns
Read pulse “H”
width
tRDHW8
170
ns
Data setup time
tRDD8
Data hold time
tRDH8
CL = 80 pF
Typ.
Max.
210
10
ns
ns
RDB(E)
D0~D7
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85℃
Item
Symbol
Address hold time
tAH8
Address setup time
System cycle time
in read
Condition
Min.
Typ.
Max.
Unit
Pin Used
0
ns
tAS8
0
ns
CSB
RS
tCYCRD8
540
ns
Read pulse “L”
width
tRDLW8
290
ns
Read pulse “H”
width
tRDHW8
230
ns
Data setup time
tRDD8
Data hold time
tRDH8
CL = 80 pF
300
10
ns
ns
RDB(E)
D0~D7
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85℃
Item
Symbol
Address hold time
tAH8
Address setup time
tAS8
Condition
Min.
Typ.
Max.
Unit
Pin Used
0
ns
CSB
RS
0
ns
System cycle time
tCYCRD8
in read
840
ns
Read pulse “L”
width
tRDLW8
440
ns
Read pulse “H”
width
tRDHW8
380
ns
Data setup time
tRDD8
Data hold time
tRDH8
CL = 80 pF
450
10
ns
ns
RDB(E)
D0~D7
11.3 68-Family MCU Write Timing
tAH6
tAS6
CSB
RS
R/WB
(WRB)
E
(RDB)
tELW6
tEHW6
tDS6
tDH6
D0-D7
tCYCWR6
Figure 11-3 68-Family MCU Write Timing Diagram
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 69
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
VSS=0V, VDD = 2.7 ~3.3V, Ta = -30~+85℃
Item
Symbol
Condition
Min.
Address hold time
tAH6
Address setup time
tAS6
200
ns
System cycle time in
tCYCWR6
write
Typ.
Max.
Unit
Pin Used
0
ns
0
ns
CSB
RS
Write pulse “L” width
tELW6
135
ns
Write pulse “H”
width
tEHW6
30
ns
Data setup time
tDS6
60
ns
Data hold time
tDH6
5
ns
RDB(E)
D0~D7
VSS=0V, VDD = 2.4 ~2.7V, Ta = -30~+85℃
Item
Symbol
Condition
Min.
Typ.
Max.
Unit Pin Used
Address hold time
tAH6
0
ns
Address setup time
tAS6
0
ns
System cycle time
in write
tCYCWR6
250
ns
Write pulse “L” width
tELW6
160
ns
Write pulse “H”
width
tEHW6
50
ns
Data setup time
tDS6
80
ns
Data hold time
tDH6
10
ns
CSB
RS
RDB(E)
D0~D7
VSS=0V, VDD = 2.2 ~2.4V, Ta = -30~+85℃
Item
Symbol
Address hold time
tAH6
Address setup time
tAS6
System cycle time
tCYCWR6
in write
Write pulse “L” width tELW6
Write pulse “H”
tEHW6
width
Data setup time
tDS6
Data hold time
tDH6
70 •
Condition
Min.
Typ.
Max.
Unit Pin Used
0
0
ns
ns
500
ns
350
ns
100
ns
100
20
ns
ns
CSB
RS
RDB(E)
D0~D7
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
11.4 68-Family MCU Read Timing
tAH6
tAS6
CSB
RS
R/WB
(WRB)
E
(RDB)
tELW6
tEHW6
tRDD6
tRDH6
D0-D7
tCYCRD6
Figure 11-4 68-Family MCU Read Timing Diagram
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85℃
Item
Symbol
Address hold time
tAH6
Address setup time
tAS6
System cycle time in
tCYCRD6
read
Write pulse “L” width tELW6
Write pulse “H”
tEHW6
width
Data setup time
tRDD6
Data hold time
tRDH6
Condition
CL=50pF
Min.
Typ.
Max.
Unit
0
ns
0
ns
380
ns
200
ns
170
ns
210
10
ns
ns
Pin
Used
CSB
RS
RDB(E)
D0~D7
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85℃
Item
Symbol
Address hold time
tAH6
Address setup time
tAS6
System cycle time
tCYCRD6
in read
Write pulse “L”
tELW6
width
Write pulse “H”
tEHW6
width
Data setup time
tRDD6
Data hold time
tRDH6
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Condition
CL=50pF
Min.
Typ.
Max.
Unit
Pin Used
0
ns
0
ns
CSB
RS
540
ns
290
ns
230
ns
300
10
ns
ns
RDB(E)
D0~D7
• 71
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85℃
Item
Symbol
Address hold time
tAH6
Condition
Min.
Typ.
Max.
Unit
Pin Used
CSB
RS
0
ns
Address setup time
tAS6
System cycle time in
tCYCRD6
read
Write pulse “L” width tELW6
0
ns
1000
ns
450
ns
Write pulse “H” width
tEHW6
500
ns
Data setup time
tRDD6
Data hold time
tRDH6
650
CL=50pF
10
ns
ns
RDB(E)
D0~D7
11.5 Serial Interface Timing Diagram
tCSH
tCSS
CSB
RS
tASS
tAHS
tSLW
tSHW
SCL
tDSS
SDA
tDHS
1st bit
7rd bit
tCYCS
Figure 11-5 Serial Interface Timing Diagram
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85℃
72 •
Item
Serial clock
period
SCL pulse “H”
width
SCL pulse “L”
width
Address setup
time
Address hold
time
Data setup
time
Data hold time
Symbol
Condition
Min.
Typ.
Max.
Unit
tCYCS
200
ns
tSHW
80
ns
tSLW
80
ns
tASS
40
ns
tAHS
40
ns
tDSS
80
ns
tDHS
80
ns
CSB-SCL time
tCSS
40
ns
CSB hold time
tCSH
40
ns
Pin Used
SCL
RS
SDA
CSB
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85℃
Item
Serial clock
period
SCL pulse “H”
width
SCL pulse “L”
width
Address setup
time
Address hold
time
Data setup
time
Data hold time
Symbol
Condition
Min.
Typ.
Max.
Unit
tCYCS
200
ns
tSHW
80
ns
tSLW
80
ns
tASS
50
ns
tAHS
50
ns
tDSS
80
ns
tDHS
80
ns
CSB-SCL time
tCSS
50
ns
CSB hold time
tCSH
60
ns
Pin Used
SCL
RS
SDA
CSB
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85℃
Item
Serial clock
period
SCL pulse “H”
width
SCL pulse “L”
width
Address setup
time
Address hold
time
Data setup
time
Data hold time
Symbol
Condition
Min.
Typ.
Max.
Unit Pin Used
tCYCS
230
ns
tSHW
100
ns
tSLW
100
ns
tASS
80
ns
tAHS
80
ns
tDSS
100
ns
tDHS
100
ns
SCL
RS
CSB-SCL time
tCSS
80
ns
CSB hold time
tCSH
100
ns
SDA
CSB
11.6 Clock Input Timing
tCKLW
CK
tCKHW
Figure 11-6 Clock Input Timing Diagram
VSS=0V, VDD = 2.4~3.3V, Ta = -30~+85℃
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
CK pulse “H”
width
tTCKHW2
5.4
6.5
µs
CK pulse “L”
width
tCKLW2
5.4
6.5
µs
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
Pin
Used
CK
※1
• 73
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85℃
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
CK pulse “H”
width
tCKHW2
5.4
6.5
µs
CK pulse “L”
width
tCKLW2
5.4
6.5
µs
Pin
Used
*
* CK pin. Applied when using the 16 gray scale gradation display mode
11.7 Reset Timing
tRW
RESB
tR
internal state
normal dsiplay
reset mode
Figure 11-7 Reset Timing Diagram
VSS=0V, VDD = 2.4~3.3V, Ta = -30~+85℃
Item
Reset time
Reset pulse “L”
width
Symbol
Condition
Min.
Typ.
tR
Max.
1
tRW
40
Unit Pin Used
µs
µs
RESB
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85℃
Item
Reset time
Reset pulse “L”
width
74 •
Symbol
Condition
Min.
tR
tRW
Typ.
Max.
1.5
40
Unit Pin Used
µs
µs
RESB
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
12 Application Circuit
VDD
VDD
EM65101
CAP3+ 1uF
VEE
CAP2+
CAP2-
1uF
CAP4+
1uF
CAP1+
CAP1V2X
VDD
P/S
M86
1uF
CAP3-
/RES
/CSB
R/S
/WR
/RD
DB0 ~ DB7
8051 or
80-Serial MPU
CAP5+
Parallel
Mode
80-Serial MPU
Internal OSC
CKS
VSS
TEST
1uF
1uF
VOUT
1uF
V0 1uF
CK
V1 1uF
INPUT Pad
CVREF
VPP
V2 1uF
VREF
V3 1uF
VBA
V4 1uF
Figure 12-1 EM65101 Application Circuit
NOTE
To obtain a stable voltage, it is recommended that you use VREF to connect a 0.1uF
capacitor CVREF to VSS.
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 75
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
13 Tray Information
Figure 13-1 EM65101 Tray Diagram
Tray Dimensions (Unit: mm):
76 •
Symbol
Dimensions (mm)
Symbol
Dimensions (mm)
L1
50.80
Z
0.61 ± 0.05
L2
45.50
Px
11.97
L3
45.80
Py
2.18
T
4.00
Nx
3
Sx
13.43
Ny
20
Sy
4.69
N
60
S
14.22
P1
1.76
X
10.97 ± 0.05
P2
1.60
Y
1.48 ± 0.05
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
• 77