INTEGRATED CIRCUITS DATA SHEET TDA1373H General Digital Input (GDIN) Product specification Supersedes data of 1995 Aug 28 File under Integrated Circuits, IC01 1996 Jul 17 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H FEATURES • Four operating modes: – Sample Rate Conversion (SRC) mode – AD/DA mode – SLAVE-VCO mode – SLAVE-VCXO mode • Full digital sample rate conversion over a wide range of input sample rates • 5 V power supply • Fast and automatic detection and locking to the input sample rate with continuous tracking • 0.7 µm double metal Complementary Metal Oxide Semiconductor (CMOS) • Digital Phase-Locked Loop (PLL) with adaptive bandwidth which removes jitter on the digital audio input • SRC THD + N: • Audio outputs (soft) muted during loop acquisition – −113 dB over the 0 to 20 kHz band (1 kHz, 20 bits input and output) (see Fig.3) • Full linear phase processing based on all-FIR filtering – −95 dB over the 0 to 20 kHz band (1 kHz, 16 bits input and output) • Integrated full digital IEC 958 demodulator for digital input signals (AES/EBU or SPDIF format) with intelligent error handling • Pass band ripple smaller than ±0.004 dB for up-sampling and down-sampling filters • Extended input sample frequency range • Stop band suppression: • IEC 958 Channel Status (CS) and User Channel (UC) outputs – selectable between 70 dB and 50 dB for 64× up-sampling filters • On-chip CS and/or UC demodulation and buffering (consumer and professional format) – 80 dB for 128× down-sampling filters • Dedicated subcode processing for Compact Disc (CD) • Microcontroller operated and stand-alone mode. • Final output quantization to 16, 18 or 20 bits with optional in-audio-band noise shaping APPLICATIONS • Bitstream input and output for coupling with 1-bit analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) • Professional audio equipment for: – mixing • I2S and Japanese serial input formats supported for SRC and DAC functions – recording • I2S – broadcasting – editing and Japanese serial output formats supported for SRC and ADC functions • CD-Recordable (CD-R) • I2S and Japanese 4× oversampled serial output available for SRC and ADC functions • Digital Speaker Systems (DSS) • Digital Compact Cassette recorders (DCC) • 8-bit digital gain/attenuation control • Digital Audio Tape (DAT) and MD recorders • Switchable Digital Signal Processor (DSP)-interface (I2S input and output) for additional audio processing • Digital amplifiers • Jitter killers. • Additional clock outputs available at 768, 384, 256 and 128fso • 3-line serial microcontroller interface, compatible with the Philips CD I.C. protocol (HCL) 1996 Jul 17 2 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H The GDIN digital filters can also be reused for Bitstream ADC and DAC conversion (AD/DA mode). The internal digital PLL can be reconfigured to operate the GDIN in a slave mode, where the output sample frequency of the device is locked to the incoming sample rate (SLAVE-VCO and SLAVE-VCXO modes). GENERAL DESCRIPTION The TDA1373H is a General Digital Input (GDIN) device for audio signals which is able to perform a high-quality sample rate conversion of digital audio signals (SRC mode). The device reads several serial input formats and signals in the IEC 958 digital audio format (also known as AES/EBU or SPDIF signals). For this purpose a full Audio Digital Input Circuit (ADIC) is present in the device. The combination of an ADIC function, sample rate conversion and Bitstream ADC and DAC results in a device with a highly versatile functionality and large replacement value in consumer and professional audio sets. An internal digital PLL results in extensive jitter removal from incoming digital audio signals without any analog loop electronics. The standard 20 bit output word length can be limited to 16 or 18 bits by means of ‘in-audio-band noise shaping’. QUICK REFERENCE DATA All inputs and outputs CMOS compatible; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage fso > 44.1 kHz 4.75 5 5.5 V fso ≤ 44.1 kHz 4.5 5 5.5 V IDD(tot) total supply current fso = 44.1 kHz − 155 − mA Ptot total power dissipation fso = 44.1 kHz − 775 − mW fso = 49 kHz; VDD = 5.5 V − 1030 − mW 0.2 − VDD V maximum output sample frequency VDD = 4.75 V 49 55 − kHz operating ambient temperature 0 70 °C IEC 958 input DI1S (high-sensitivity IEC input) Vi(p-p) AC input voltage (peak-to-peak value) Clock and timing fso(max) Temperature Tamb ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA1373H QFP64 1996 Jul 17 DESCRIPTION Plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.7 mm; high stand-off height 3 VERSION SOT319-1 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H BLOCK DIAGRAM EM LOCK SA DI1D DI1O DI1S VDDA1 VSSA1 32 39 BS 14 52 CUS 34 CEN 36 35 44 48 ADIC (IEC 958 DECODER) 43 62 63 47 45 USER CHANNEL EXTRACTION U 37 CL LD DA XTLI 46 MICROCONTROLLER INTERFACE/ STAND-ALONE CONTROL XTLO CLI 21 19 20 22 CLO1 CLO2 CLO3 CLO4 23 27 CRYSTAL OSCILLATOR 28 30 31 128f so MU 11 VDDD V 256f so 7 VDDD V SSA4 DDA4 VDDD 384f so handbook, full pagewidth VDDD VDDD 768f so VDDD CLOCK SHOP PV MM1 C CHANNEL STATUS EXTRACTION WS PO GENERAL CONTROL 64f so DI1 1 DATA SLICER DI2 3 PHASE DETECTOR 2 LOOP FILTER HOLD 25 VCO FSL MM0 4x UPSAMPLING FIFO AND GAIN 16 x UPSAMPLING VARIABLE HOLD 10 DO2 I2 S 16 OUT 6 DO2D DO2W DO2C TST1 TST2 RST AIL AIR 50 42 DO1D DSO 2 I S OUT 41 INS 38 DNI 32 x DOWNSAMPLING 4 5 49 51 IN-BAND NOISE SHAPER 4x DOWNSAMPLING DO1C stereo FOS 9 AOS DI2 BITSTREAM DIGITAL FILTER ATTENUATOR 15 DAC OUTPUT 18 TDA1373H I 2S OUT 55 56 I 2S IN 54 57 59 60 8 12 13 17 24 26 29 33 40 53 58 61 64 MLC334 - 2 FOD FOC FOW DI2D DI2W DI2C VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD Switches MM1 and MM0 are controlled indirectly via the mode selection. All other switches can be controlled directly by the user. Fig.1 Block diagram. 4 AOL1 AOR1 CLD HOLD 1996 Jul 17 DO1W Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H PINNING SYMBOL PIN DESCRIPTION TYPE DI1S 1 IEC 958 digital audio input ‘S’ (200 mV peak-to-peak value) E036A VSSA1 2 IEC 958 slicer analog ground E038A VDDA1 3 IEC 958 slicer analog supply voltage E037A AIL 4 Bitstream audio input left HPP01 AIR 5 Bitstream audio input right HPP01 DO2C 6 serial digital audio output 2; bit clock output (192fso) OPF40 VDDD 7 digital supply voltage; note 1 VSSD 8 digital ground; note 2 AOL1 9 Bitstream audio output left OPF40 DO2D 10 DLO = 0; serial digital audio output 2; data; DLO = 1; Bitstream audio output left inverted (AOL1); note 3 OPF40 − − VDDD 11 digital supply voltage; note 1 − VSSD 12 digital ground; note 2 − VSSD 13 digital ground; note 2 − VDDD 14 digital supply voltage; note 1 − AOR1 15 Bitstream audio output right OPF40 DO2W 16 DLO = 0; serial digital audio output 2; word select output (4fso); DLO = 1; Bitstream audio output right inverted (AOR1); note 3 OPF40 − VSSD 17 digital ground; note 2 CLD 18 Bitstream DAC clock (192 or 128fso) OPF43 VDDA4 19 oscillator analog supply voltage E037A VSSA4 20 oscillator analog ground E038A XTLI 21 crystal input 768fso OSX01 XTLO 22 crystal output OSX01 CLI 23 external VCO input (SLAVE-VCO mode only) HPP01 VSSD 24 digital ground; note 2 FSL 25 SA = 0 (microcontroller operated) external VCO output (slave modes only); SA = 1 (stand-alone control) DI11 control line; note 4 − HOF21 − VSSD 26 digital ground; note 2 CLO1 27 clock output 768fso OPF40 CLO2 28 clock output 384fso OPF40 VSSD 29 digital ground; note 2 − CLO3 30 clock output 256fso OPF40 CLO4 31 clock output 128fso; OPF40 VDDD 32 digital supply voltage; note 1 − − VSSD 33 digital ground; note 2 BS 34 block sync; channel status/user channel/CD subcode OPF40 CEN 35 data enable; channel status/user channel/CD subcode OPF40 CUS 36 data bit; channel status/user channel/CD subcode OPF40 EM 37 IEC 958 source pre-emphasis flag OPF20 1996 Jul 17 5 Philips Semiconductors Product specification General Digital Input (GDIN) SYMBOL PIN TDA1373H DESCRIPTION RST 38 power-on reset input (active LOW) TYPE HPP07 VDDD 39 digital supply voltage; note 1 − VSSD 40 digital ground; note 2 − TST2 41 test pin 2 (LOW for normal operation) HPP01 TST1 42 test pin 1 (LOW for normal operation) HPP01 SA 43 Stand-alone/microcontroller operated selection; SA = 1 for stand-alone operation HPP01 MU 44 mute flag (active HIGH) OPF40 LD 45 SA = 0 (microcontroller operated) microcontroller interface; load (read/write); SA = 1 (stand-alone control) NSD control line; note 4 HPP01 DA 46 SA = 0 (microcontroller operated) microcontroller interface (data); SA = 1 (stand-alone control) DI2 control line; note 4 HOF41 CL 47 SA = 0 (microcontroller operated) microcontroller interface (clock); SA = 1 (stand-alone control) QU1/QU0 control line; note 4 HPP01 LOCK 48 ADIC lock flag (active HIGH) OPF40 DO1W 49 serial digital audio output 1; word select input/output (fso) HOF41 DO1D 50 serial digital audio output 1; data OPF43 HOF41 DO1C 51 serial digital audio output 1; bit clock input/output (48fso) VDDD 52 digital supply voltage; note 1 − VSSD 53 digital ground; note 2 − FOW 54 serial digital audio feature output; word select FOD 55 serial digital audio feature output; data OPF43 FOC 56 serial digital audio feature output; bit clock (64fso) OPF43 DI2D 57 serial digital audio input 2; data HPP01 OPF43 − VSSD 58 digital ground; note 2 DI2W 59 serial digital audio input 2; word select HOF21 DI2C 60 serial digital audio input 2; bit clock output HOF21 − VSSD 61 digital ground; note 2 DI1D 62 SA = 0 (microcontroller operated) IEC 958 digital audio input ‘D’ (CMOS level); SA = 1 (stand-alone control) MSO control line; note 4 HPP01 DI1O 63 IEC 958 digital audio input ‘O’ (CMOS level) HPP01 VSSD 64 digital ground; note 2 − Notes 1. All VDDD pins are internally connected. 2. All VSSD pins are internally connected. 3. DLO is a command flag from register 4 (see Section “Command registers”). 4. SA is the stand-alone/microcontroller operated pin (pin 43). DI11, NSD, DI2, QU1, QU0 and MS0 are command flags to control the operation of the device. For more information see Section “Controlling the GDIN”. 1996 Jul 17 6 Philips Semiconductors Product specification 52 V DDD 53 V SSD 54 FOW 55 FOD 56 FOC 57 DI2D 58 V SSD 59 DI2W 60 DI2C TDA1373H 61 VSSD 62 DI1D handbook, full pagewidth 63 DI1O 64 V SSD General Digital Input (GDIN) DI1S 1 51 DO1C V SSA1 2 50 DO1D V DDA1 3 49 DO1W AIL 4 48 LOCK AIR 5 47 CL DO2C 6 46 DA V DDD 7 45 LD V SSD 8 44 MU AOL1 9 43 SA TDA1373H DO2D 10 42 TST1 V DDD 11 41 TST2 V SSD 12 40 V SSD V SSD 13 39 V DDD V DDD 14 38 RST AOR1 15 37 EM DO2W 16 36 CUS V SSD 17 35 CEN CLD 18 34 BS 33 V SSD Fig.2 Pin configuration. 1996 Jul 17 7 VDDD 32 CLO4 31 CLO3 30 CLO2 28 V SSD 29 CLO1 27 V SSD 26 FSL 25 VSSD 24 CLI 23 XTLO 22 XTLI 21 V SSA4 20 V DDA4 19 MLB955 - 2 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H FUNCTIONAL DESCRIPTION Data path (see Fig.4) Operating modes The input signal at sample frequency fsi comes in via one of the DI1 inputs (IEC 958) or via the serial input DI2X. The signal passes through the FIFO/GAIN part and is interpolated in the up-sampling filters. The actual sample rate conversion takes place in the variable hold block. The down-sampling filters decimate the sample frequency to fso and after in-band noise shaping, the output signal is present at serial output DO1. Additionally the converted signal is available at the ‘analog’ Bitstream outputs AOL, AOR and at the serial digital output DO2 (4fso). SAMPLE RATE CONVERSION (SRC) MODE The output sample rate is determined by a crystal and can be chosen up to 49 kHz. The range of input sample rates for a given output sample rate is given in Table 1. A pitch variation (‘Varispeed’) of ±12% around the nominal input sample rate can be tracked. Table 1 Input sample rates I2S INPUT (kHz) 0.3 to 1.7fso OUTPUT SAMPLE RATE (kHz) IEC 958 INPUT (kHz) 0.35 to 1.45fso 48 13 to 83 16 to 68 44.1 12 to 76 15 to 62 9 to 55 12 to 45 32 MLB956 60 handbook, full pagewidth THD N (dB) 80 100 120 140 160 10 10 2 10 3 10 4 Measurement done with ‘Audio Precision’. SRC mode; 48 to 44.1 kHz; 20-bit output. Fig.3 Total harmonic distortion plus noise as a function of frequency. 1996 Jul 17 8 f (Hz) 10 5 1996 Jul 17 9 DA DI2W LD GENERAL CONTROL DI2 MICROCONTROLLER INTERFACE FOS DI2D CL ADIC (IEC 958 DECODER) CEN CLOCK SHOP DI1 BS DI2C AIR AIL DI1D DI1O DI1S FSL MU 4 x AND 16 x UP-SAMPLING EM SA VARIABLE HOLD 768f so TDA1373H DNI RST LOCK BITSTREAM DAC e.g. TDA1547 CLO1 HOLD 32 x AND 4 x DOWNSAMPLING XTLO analog output 2 I S digital output fso AOS CLO2 XTLI IN-BAND NOISE SHAPER TST1 CLO4 BITSTREAM DIGITAL FILTER CLO3 INS CLI CLD DO2 DSO TST2 Example of additional path. Main path. MLC335 FOW FOD FOC AOR AOL DO2W DO2D DO2C DO1W DO1D DO1C General Digital Input (GDIN) Fig.4 Standard data path in the SRC mode. CS AND UC EXTRACTION DIGITAL PLL TDA1373H FIFO & GAIN CUS AES/EBU or I S 2 handbook, full pagewidth digital input f si Philips Semiconductors Product specification TDA1373H Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H SLAVE-VCO AND SLAVE-VCXO MODES AD/DA MODE In the SLAVE-VCO and SLAVE-VCXO modes, the GDIN can pass an exact copy of the incoming samples to the output, e.g. for storage on a digital medium such as CD-R. The output sample rate tracks any input sample rate within the frequency range of the external VC(X)O (fso = fsi). In this mode, the GDIN supports an economic realization of analog-to-digital and digital-to-analog conversion, in accordance with the Bitstream principle. This requires a Bitstream sigma-delta modulator and a Bitstream DAC, since the up-sampling and down-sampling filters of the sample rate convertor are reused. ADC and DAC can be simultaneously performed. In the SLAVE-VCO mode a pitch variation of ±12.5% around the nominal sample frequency can be tolerated. Data path DA conversion (see Fig.6) Data path (see Fig.5) The signal at sample frequency fso comes in via serial input DI2X or via one of the DI1 inputs (IEC 958). The signal passes through the FIFO/GAIN part and is interpolated in the up-sampling filters. A Bitstream digital filter converts this signal into a Bitstream signal at outputs AOL and AOR, after which it can be filtered by a Bitstream DAC like the TDA1547. The signal at input sample frequency fsi comes in via one of the DI1 inputs (IEC 958). The ADIC signal passes through the FIFO/GAIN block and can be fed through the IN-BAND NOISE SHAPER to the serial output DO1. Additionally, the signal is present at DO2 (4fso) and at the Bitstream outputs AOL and AOR. Exact copies for digital use (e.g. write to a disk) from the input signal can be retrieved at output FO (this signal might be affected by jitter since it has not passed through the FIFO/GAIN block). By means of data path switch DSO, this direct output of the ADIC block can also be fed to output DO1. Note that in this event the DO1 serial format becomes equal to the FO format (see Table 3). 1996 Jul 17 Data path AD conversion (see Fig.6) The Bitstream signal from the sigma-delta modulator enters the GDIN at inputs AIL and AIR. The down-sampling filters decimate this signal to fso and after in-band noise shaping (selectable), the output signal is present at serial output DO1. 10 1996 Jul 17 11 EM handbook, full pagewidth SA VARIABLE HOLD 768fso DNI RST LOCK BITSTREAM DAC e.g.TDA1547 BITSTREAM DAC e.g.TDA1547 2 HOLD CLO1 32 x AND 4 x DOWNSAMPLING XTLO analog output I S 2 digital output f si analog output I S TST1 CLO4 BITSTREAM DIGITAL FILTER IN-BAND NOISE SHAPER CLI CLO3 INS AOS CLO2 XTLI Fig.5 Standard data path in the SLAVE-VCO and SLAVE-VCXO modes. MU 4 x AND 16 x UP-SAMPLING CS AND UC EXTRACTION DIGITAL PLL TDA1373H FIFO & GAIN CUS TDA1373H VCO TDA1373H digital output f si CLD DO2 DSO TST2 Example of additional path. Main path. MLC336 FOW FOD FOC AOR AOL DO2W DO2D DO2C DO1W DO1D DO1C General Digital Input (GDIN) DA GENERAL CONTROL DI2W LD MICROCONTROLLER INTERFACE DI2 DI2D CL ADIC (IEC 958 DECODER) CEN CLOCK SHOP DI1 FOS BS DI2C AIR AIL DI1D DI1O DI1S FSL digital input f si AES/EBU or I2 S digital input f si AES/EBU or I2 S Philips Semiconductors Product specification TDA1373H 1996 Jul 17 12 DA DI2W LD GENERAL CONTROL DI2D DI2 MICROCONTROLLER INTERFACE CL ADIC (IEC 958 DECODER) CS AND UC EXTRACTION DIGITAL PLL TDA1373H FIFO & GAIN CUS MU 4 x AND 16 x UP-SAMPLING EM SA VARIABLE HOLD 768fso RST LOCK DNI BITSTREAM DAC e.g. TDA1547 HOLD CLO1 32 x AND 4 x DOWNSAMPLING XTLO analog output I S 2 digital output fso TST1 CLO4 BITSTREAM DIGITAL FILTER IN-BAND NOISE SHAPER CLI CLO3 INS AOS CLO2 XTLI CLD DO2 DSO TST2 DA OUT Example of additional path. Main path. MLC337 FOW FOD FOC AOR AOL DO2W DO2D DO2C DO1W AD OUT DO1D DO1C General Digital Input (GDIN) Fig.6 Standard data paths in the AD/DA mode. CEN CLOCK SHOP AIR DI1 FOS BS DI2C AD IN AIL DI1D DI1O DA IN DI1S FSL 2 AES/EBU or I S digital input fso TDA1373H handbook, full pagewidth analog input BITSTREAM ADC e.g. SAA7360 Philips Semiconductors Product specification TDA1373H Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H ADIC locks in less than 1 ms for a 44.1 kHz input signal. During this lock-in time the word clock is stopped and the audio bits are muted. Description of functional blocks IEC 958 AUDIO DIGITAL INPUT CIRCUIT The TDA1373H has three IEC 958 inputs: The validity flag (VA), pre-emphasis flag and pin (EM), lock flag (LCK) and lock pin (LOCK) are available to check the status of the ADIC. This validity flag is an OR-ing of the incoming validity (V) bit and the own error detection of the ADIC. The actions which take place in case of detected errors are listed in Table 2. 1. DI1S. 2. DI1O. 3. DI1D. DI1S accepts IEC 958 line signals (minimum 200 mV peak-to-peak value and maximum 5 V peak-to-peak value), DI1O and DI1D accept only CMOS level signals. The input sample rate range that can be handled depends on the output sample frequency (fso) of the device. SERIAL DIGITAL INPUTS DI2W, DI2D AND DI2C The serial digital input DI2 can be used as standard input instead of the DI1 IEC 958 input or can be used together with the FO-output to switch a DSP IC in the input data path. A third possibility is to use DI2 as direct input to the GDIN Bitstream digital filter. In that case the DI2 input signal should be 4× oversampled externally. The serial formats supported are shown in Fig.7 and Table 3. The maximum useful word length of the incoming samples is 20 bits. The internal ADIC retrieves the stereo audio samples, the V, U, C and P data bits, the ADIC word clock and the bit clock from the selected IEC 958 input signal. The digital Table 2 Error concealment in the IEC 958 decoder ERROR ACTION DATA Validity (V-bit) error pass sample Parity (P-bit) error repeat last correct sample ACTION WORD CLOCK no action Number of data bits ≠32 Missing pre-amble(s) Extra pre-amble(s) More than 4 pre-ambles missing or extra mute output; restart Table 3 stop ADIC word clock Serial input and output formats (see note 1) INPUT OUTPUT DI2 DO1 DO2 FO JAPANES JAPANESE JAPANESE 3-STATE E 16-BIT 18-BIT 20-BIT fWS fBCK I2S fsi ≤128fsi S 4fso 192fso M fso 48fso M ≤128fso S − − 4fso 192fso M M M − no DO2, DO21 and DO22 fsi 64fso M − − − yes FO and FO1 S S S no DI2, DI21 and DI22 S S S no DI2 M M − yes DO1S, DO11 and DO12 Note 1. S = slave; M = master. 1996 Jul 17 CONTROL BITS 13 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H RIGHT handbook, full pagewidth WS (W) RIGHT LEFT tr t HB LEFT t LB t hWS t suWS tf BCK (C) t suDAT TBCK DATA (D) DATA LSB LSB MSB t hDAT MSB LSB MSB BCK WS RIGHT LEFT a. LEFT WS (W) RIGHT tr t HB t LB tf t hWS t suWS BCK (C) t suDAT TBCK DATA (D) DATA LSB MSB t hDAT MSB LSB MSB LSB BCK WS LEFT RIGHT MLB960 a. I2S input format. b. Japanese input format. b. Fig.7 Timing diagram for the serial input and output formats. 1996 Jul 17 14 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H featuring IC in the data path before SRC (at fsi). See Table 3 for the formats supported. SERIAL DIGITAL OUTPUTS DO1W, DO1D AND DO1C Depending on the operating mode and data path switching, DO1 can contain the output of the in-band noise shaper or can be directly connected to the output of the internal ADIC. The supported serial formats and modes of this interface are given in Table 3. BITSTREAM INPUTS AIL AND AIR The Bitstream input receives data at 128fso from a 1-bit sigma-delta modulator. Possible Bitstream inputs at 64fso are held twice. The timing diagram for the Bitstream inputs and outputs is given in Fig.8. In case the GDIN goes out-of-lock the output data is muted and if the output is configured as master transmitter, the word clock slips half a word clock period. If this is undesirable, use the serial output as a slave transmitter. BITSTREAM OUTPUTS AOL1 AND AOR1 The Bitstream output generates a 128 (SRC and SLAVE modes) or 192 (AD/DA mode) times oversampled Bitstream and can be connected to a Bitstream DAC (e.g. TDA1547) for high-quality DAC. It is also possible to get the inverted Bitstream signals on the complementary Bitstream outputs AOL1 (pin DO2D) and AOR1 (pin DO2W) by setting the DLO control bit. By using a simple low-pass filter, this symmetrical Bitstream output can be used to make an inexpensive analog monitor output. In that event the serial digital output DO2 cannot be used. SERIAL DIGITAL OUTPUTS DO2W, DO2D AND DO2C The additional digital audio output DO2 operates at 4fso. DO2 can contain data of the up-sampling (not in SRC mode) or down-sampling filters. The formats supported are shown in Table 3. SERIAL FEATURE OUTPUTS FOW, FOD AND FOC The internal ADIC output is directly available in I2S format at this output. This makes it possible to switch a DSP handbook, full pagewidth FOC, CLO4 and DO2C CLOCK t d1 AIL and AIR DATA Tcy tf tr t CL CLD CLOCK t CH t d2 t d3 AOL1, AOL2, AOR1 and AOR2 DATA V DD 1 V 1.0 V MLB961 Fig.8 Timing diagram for the Bitstream inputs and outputs. 1996 Jul 17 15 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H as the up-sampling filter for a Bitstream digital-to-analog conversion in the AD/DA mode, in combination with the Bitstream digital filter and Bitstream DAC (e.g. TDA1547). Two filter characteristics can be chosen by the control bit SS (see Table 4). FIRST-IN FIRST-OUT (FIFO) The incoming samples are buffered in a FIFO. The depth of this FIFO determines the transients that can be allowed in the input frequency, as they may occur during pitch control. The FIFO has a depth of 8 samples, which makes GDIN support a tracking speed of up to 4 kHz/ms. FIFO overflow detection is provided to detect out-of-lock situations. The 50 dB stop band suppression mode is especially suited for 32 kHz input sources like Digital Satellite Radio (DSR), where a very narrow transition band is required to obtain 0 to 15 kHz pass band. GAIN CONTROL VARIABLE HOLD At the begin of the data path, the signal level can be controlled over a gain/attenuation range from 2 to 0 with a step size of 2E-7. This gain control can be used for volume control, gain correction and fade-in or fade-out. For normal operation, the gain level should be set to 1-2E-7 (−0.068 dB) to avoid pass band ripple clipping in the digital filters. Whenever a new gain value is set, the gain level is increased or decreased by one step per input sample until the new entered value is reached. In SRC mode, the variable hold is the interface between the 64× up-sampling filters (64fsi) and the 128× down-sampling filters (128fso). In SLAVE and AD/DA modes, the variable hold holds each sample twice from 64fsi to 128fsi (fsi = fso). 128× DOWN-SAMPLING FILTER (see Fig.10) After SRC, a 128× (32× + 4×) down-sampling filter decimates the signal to fso. In the AD/DA mode, this filter is used as the ADC down-sampling filter for a Bitstream sigma-delta modulator. The stop band suppression is 80 dB from 0.54648fso (e.g. 24.1 kHz at fso = 44.1 kHz). Setting the MMU control bit forces the GDIN to start a soft muting. The gain is decreased, by one step per input sample, to zero. Clearing the MMU bit will increase the gain back to its original value. Only those outputs, for which the signal passes through the ‘gain control’ part, are muted. 64× UP-SAMPLING FILTER A 64× (4× and 16×) oversampling filter is incorporated in the GDIN for the SRC process. This filter can also be used Table 4 Filter characteristics 64× up-sampling filter SS PASS BAND STOP BAND 0 0 to 0.45351fsi ±0.004 dB 0.54648fsi to 1fsi −70 dB 1 0 to 0.46875fsi ±0.004 dB 0.53125fsi to 1fsi −50 dB 1996 Jul 17 16 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H MLB962 0 stop band suppression (dB) handbook, full pagewidth 20 40 60 80 100 0 20 40 60 80 f (kHz) 100 SS = 0; 70 dB stop band suppression. Fig.9 Filter characteristic 64× up-sampling filter. MLB963 0 stop band suppression (dB) handbook, full pagewidth 20 40 60 80 100 0 20 40 60 Fig.10 Filter characteristic 128× down-sampling filter. 1996 Jul 17 17 80 f (kHz) 100 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H allows fast locking to the input frequency and a small bandwidth during steady-state. At start-up, the bandwidth of the 3-step digital loop filter is gradually reduced to 0.5 Hz. A difference frequency of 1 Hz is reached within 512 input samples (10 ms at 44.1 kHz), which allows to start the SRC. At this moment the outputs are de-muted, indicated at pin MU and status flag MUT. IN-BAND NOISE SHAPING (INS) The standard 20-bit output word length can be reduced to 16 or 18 bits to match digital consumer equipment. Normally 16 bit output re-quantization at audio-band sample rates drops the signal-to-noise ratio (S/N) inevitably to 95 dB, because of the re-quantization noise at −98 dB. The FIFO position is continuously monitored to control the adaptive loop filter. The loop filter switches back to a fast state when the FIFO tends to drift, e.g. during pitch control on the input signal. It is possible to fix the loop filter in one of the three states. In the adaptive mode, the actual state can be monitored by the microcontroller (ST1 and ST0). In SRC mode, the microcontroller can retrieve the exact input sample frequency via the status registers STS3 and STS4. It is possible however to shape the re-quantization noise in a psycho-acoustical way. This reduces the re-quantization noise at the frequencies where the human ear is most sensitive and stores the bulk of re-quantization noise at high frequencies, where the human ear is quite insensitive. The In-band Noise Shaping function (to 16 or 18 bits) results in a subjective quality improvement of about 2 bits below the actual quantization level. Table 6 It is also possible to re-quantize the 20 bit output to 16 bits without noise shaping but by a simple rounding operation. Table 5 gives an overview of the 4 possible settings. Table 5 Selectable output word lengths QU1 QU0 WORD LENGTH 0 0 16 bit (rounded) 0 1 20 bit 1 0 16 bit INS(1) 1 1 18 bit INS(1) PLL OPERATION PLL BANDWIDTH (Hz) LC1 LC0 0 0 adaptive 500, 50 or 0.5 0 1 state 1 fixed 500 1 0 state 2 fixed 50 1 1 state 3 fixed 0.5 In both SLAVE modes, a pulse modulated signal at pin FSL is present to control the external VC(X)O. In SLAVE-VCO mode, CLI is the clock input of the GDIN and in SLAVE-VCXO mode XTLI is the clock input. An external 1000 Hz low-pass filter retrieves the control voltage for the VC(X)O. To get the loop characteristics as described above, the centre frequency of the VCO should be at 1⁄ V 2 DD and the sensitivity should be: Note 1. INS = In-band Noise Shaping. BITSTREAM DIGITAL FILTER The Bitstream digital filter generates a Bitstream signal which should be filtered by a Bitstream DAC (e.g. TDA1547) to become a high-quality analog signal. The input for this block can be selected from the output of the up-sample path or directly from serial input DI2. In this case, the input signal applied to DI2 should be externally oversampled to 4fso and further oversampling will be carried out by the hold function. The Bitstream signal has a frequency of 128fso (SRC and SLAVE modes) or 192fso (AD/DA mode). 768f so ( c ) g v = ------------------------ Hz/V. 1 --- V DD 2 The maximum VCO frequency range is: (768 × 0.3)fso(c) < 768fsi (=fso) < (768 × 1.7)fso(c) (49 kHz). IEC 958 CHANNEL STATUS AND USER CHANNEL EXTRACTOR (CUP) The internal ADIC retrieves also the Channel Status (CS) and User Channel (UC) bits from the IEC 958 signal. The C/U processing function block can be programmed for 4 different functions (see Table 7). To prevent idle patterns in the audio band, it is strongly advised to add out-of-band dither by setting control bit NSD. DIGITAL PLL The digital PLL controls the variable hold function which steers the actual SRC process. An adaptive loop filter 1996 Jul 17 PLL operation modes 18 Philips Semiconductors Product specification General Digital Input (GDIN) Table 7 TDA1373H Overview of selectable CUP functions SM1 SM0 LR(1) 0 1 0 extract full C-block left (192 bits/block) 80H to 97H 0 1 1 extract full C-block right (192 bits/block) 80H to 97H 1 0 X extract full U-block (384 bits/block) 80H to AFH 0 0 X decode CD-Subcode Q-information (80 bits/CD frame) from U-bits 80H to 89H CUP FUNCTION RAM BUFFER Note 1. X = don’t care. Interrupt protocol (UIP = 0) The extracted or decoded information can be read in three ways: A C-block, a U-block or CD Subcode frame is read in the time between two Block Sync (output pin BS) pulses, which can be used as the interrupt for a microcontroller. At a sample rate of 44.1 kHz, the microcontroller must be 192 able to read a C-block or U-block within ---------------- = 4.35 ms. 44100 CD Subcode frames are received at a data rate of 75 Hz or 13.3 ms/frame. • From the internal RAM buffer by a microcontroller (see Section “The RAM buffer”) • At the output pins CUS, BS and CEN (see Fig.11) • In status registers STS5 and STS6 (permanent 16 ‘consumer mode’ C-bits, see Table 9). During CD subcode Q extraction, a 16-bit CRC is done over the Q-channel (CRC flag). This flag is only meaningful when the ADIC is locked (LCK flag). User request protocol (UIP = 1) The microcontroller requests for a C, U and CD-Q block or frame, which will then become available at the next block preamble, indicated by BS. The information is not updated until the next user request, which means the microcontroller can take any time to read the information. The CD Subcode CRC check flag always shows the CRC over the last received CD Subcode Q frame and is not stored with the present Q frame in the buffer. Figure 12 shows the user request read procedure. THE RAM BUFFER A double RAM buffer is present in the device. While reading one buffer, the other buffer is filled with the new incoming data. The RAM buffer can be read in two ways: 1. Interrupt protocol (UIP = 0). 2. User request protocol (UIP = 1). 1996 Jul 17 19 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H TcyBS handbook, full pagewidth BS t suBC t hBC CEN t suCC t hCC t LCEN LEFT CS0 or UC0 CUS t cyCEN RIGHT CS0 or UC1 LEFT CS191 or UC382 RIGHT CS191 or UC 383 a. BS t HBS(CD) t suBC(CD) TcyBS(CD) CEN t suCC(CD) CUS t HCEN(CD) t hCC(CD) Q1 R1 S1 Q98 R1 S1 MLB964 t cyCEN b. a. Channel Status (CS) or User Channel (UC) extraction. b. CD subcode demodulation. Fig.11 Timing of the CUS, CEN and BS output pins. 1996 Jul 17 Q1 20 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H handbook, full pagewidth Block Sync or CD subcode frame sync (BS) Buffer Contents Valid (BCV) OK, buffer valid Set Buffer Free (SBF) set buffer free again request to read (hold buffer) microcontroller data communication (LD, CL, DA) MLB965 start to read buffer buffer completely read Fig.12 C, U and CD-Q user request procedure. THE MICROCONTROLLER INTERFACE/ STAND-ALONE CONTROL BLOCK Read operations are at least two-byte operations with multi-byte reads possible. The address is sent to the GDIN and then one or more bytes are read from the GDIN with each additional byte coming from an incrementally higher address: If pin SA is LOW, a microcontroller controls and monitors the operation of the GDIN and reads C, U and CD-Q information. A 3-line bidirectional serial interface with data (DA), load (LD) and clock (CL) line is present. For both a write and read operation the microcontroller generates the clock and load signals. 1. Write Address. 2. Read Data byte. 3. Read Data byte. A single byte is written by setting the LD signal active HIGH during transmission of the serial data. At the rising edge of the serial clock, the GDIN clocks in the serial data. At the end of the 8-bit data word a ‘load pulse’ should be given to enable the internal serial-to-parallel conversion. 4. Read Data byte. 5. Etc. Multi-read operations continue to cycle through the given Register Address Range until the read operation is completed. Write operations are always two-byte operations. First, the register address is sent to the GDIN, then the corresponding data is send (see Fig.13): If pin SA is HIGH, the GDIN can operate without an external microcontroller. In this event, only the SRC mode and the AD/DA mode can be selected. A number of pins are reconfigured to control some of the internal switches of the device. For more information see Chapter “Pinning” and Section “Controlling the GDIN”. 1. Write Address. 2. Write Data byte. A single byte read-operation is initialized by pulling LD LOW. When the serial clock is started, the GDIN will transmit serial data on the DA line. The information is read by the microcontroller at the rising edges of the clock CL. 1996 Jul 17 21 Philips Semiconductors Product specification General Digital Input (GDIN) Table 8 TDA1373H TDA1373H memory map REGISTER ADDRESS RANGE REGISTER NAME TYPE 00H to 05H CMD1 to CMD6 command; read/write 40H to 45H STS1 to STS6 status; read 80H to 97H RAM buffer; C-block read 80H to AFH RAM buffer; U-block read 80H to 89H RAM buffer; CD-Q frame read Tcy handbook, full pagewidth t HCL CL t LCL t suLC t hLC LD t hDC t suDC DA 7 t LD1 0 7 0 a. CL t HLD LD t suLC DA 7 0 t hDC t suDC 7 0 MLB966 b. a. A complete write operation. b. A complete read operation. Fig.13 Timing for the microcontroller read and write operations. 1996 Jul 17 22 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H Controlling the GDIN MICROCONTROLLER OPERATED Status registers Table 9 Status registers REGISTER STS1 (40H) GDIN status information STS2 (41H) GDIN status information BIT FLAG 7 − reserved − 6 − reserved − 5 − reserved − 4 − reserved − 3 LCK 2 CRC 1 VA 0 BCV 7 6 DESCRIPTION internal ADIC lock status CD-Q channel; CRC check(1) EXPLANATION 0 = not locked; 1 = locked 0 = OK; 1 = error validity bit(2) 0 = valid; 1 = not valid RAM buffer contents 0 = valid; 1 = not valid − reserved − − reserved − 5 − reserved − 4 − reserved − 3 − reserved − status(3) 00 = reserved; 01 = state 1; 10 = state 2; 11 = state 3 2 and 1 ST1 and ST0 PLL operating 0 MUT mute status(4) 0 = mute OFF; 1 = mute ON STS3 (42H) 7 to 0 LF15 to LF8 fsi = fso × (1 − (0.75 × LF15 to LF0)) STS4 (43H) 7 to 0 LF7 to LF0 LF15 to LF0: input sample rate(5) 7 and 6 CA1 and CA0 clock accuracy 00 = level 2; 01 = level 1; 10 = level 3; 11 = reserved 5 and 4 FS1 and FS0 input sample rate 00 = 44.1 kHz; 01 = reserved; 10 = 48 kHz; 11 = 32 kHz 3 EM pre-emphasis 0 = OFF; 1 = ON 2 CPY 1 AN 0 CPF consumer or professional use 0 = consumer; 1 = professional 7 CAT7 6 CAT6 5 CAT5 4 CAT4 3 CAT3 2 CAT2 1 CAT1 CAT7 to CAT0: category code some examples: 00000000 = general 10000000 = CD 1100001L = DCC 1100000L = DAT 0100100L = mixer 0101100L = SRC 1001000L = MD 0 CAT0(7) (44H)(6) STS5 AES/EBU channel status (45H)(6) STS6 AES/EBU channel status copyright protection 0 = YES; 1 = NO audio or data 0 = audio; 1 = data Notes 1. Only valid when the internal ADIC is in lock (bit 3 of register STS1; LCK = 1). 1996 Jul 17 23 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H 2. VA = IEC 958 V-bit or ADIC error detector. 3. Only valid when the digital PLL works in adaptive mode. 4. After approximately 512 stereo input samples (approximately 10 ms when fsi = 44.1 kHz). 5. Only valid in SRC mode. LF15 to LF0 are in two’s complement notation. 6. Only valid when IEC 958 input format is consumer (bit 0 of register STS5; CPF = 0). When the input format is professional (CPF = 1) the STS5 and STS6 registers contain the first 16 bits of C-block. 7. Generation status (L-bit). Command registers Table 10 Command registers REGISTER BIT FLAG CMD1 (00H) ADIC control 7 and 6 DI12 and DI11 5 CMD2 (01H) loop and mode control CMD3 (02H) data path(5) 1996 Jul 17 DESCRIPTION EXPLANATION ADIC input selector 00 = DI1S; 01 = DI1O; 10 = DI1D; 11 = reserved UIP user interface protocol 0 = interrupt; 1 = user requirement 4 SBF set internal RAM buffer free 0 = hold buffer; 1 = set buffer free 3 and 2 SM1 and SM0 channel decoding 00 = CD-Q; 01 = C-block; 10 = U-block; 11 = reserved 1 LRS C-block left/right selector 0 = left; 1 = right 0 DBA RAM buffer mode 0 = normal; 1 = test 7 − reserved − 6 − reserved − 5 and 4 LC1 and LC0 PLL control; note 1 00 = adaptive; 01 = state 1 fixed; 10 = state 2 fixed; 11 = state 3 fixed 3 and 2 MS1 and MS0 mode selector; notes 1 and 2 00 = SRC mode; 01 = AD/DA mode; 10 = SLAVE-VCXO mode; 11 = SLAVE-VCO mode 1 RTR enable 3-state outputs; note 3 0 = 3-state; 1 = enabled 0 MRS reset (hardware reset); note 4 0 = no reset; 1 = reset 7 DSO 6 − 5 DO1 output selector 0 = INS; 1 = ADIC reserved − FOS FO output selector 0 = ADIC; 1 = 128× filter 4 DI2 FIFO input selector 0 = FOW, FOD and FOC; 1 = DI2W, DI2D and DI2C 3 DNI input selector 128× filter 0 = variable hold; 1 = AIL/AIR 2 INS In-band Noise Shaper input selector 0 = output 128× down; 1 = output FIFO/GAIN 1 AOS Bitstream digital filter input selector 0 = variable hold; 1 = DI2W, DI2D and DI2C 0 DO2 DO2 output selector 0 = 128× down; 1 = 64× up 24 Philips Semiconductors Product specification General Digital Input (GDIN) REGISTER CMD4 (03H) control CMD5 (04H) input/output formats CMD6 (05H) TDA1373H BIT FLAG DESCRIPTION EXPLANATION 7 − reserved − reserved − soft mute function; note 7 0 = OFF; 1 = ON in-band noise shaper 00 = 16-bit; 01 = 20-bit; 10 = 16-bit INS; 11 = 18-bit INS 6 − 5 MMU 4 and 3 QU1 and QU0 2 NSD dither Bitstream digital filter; note 8 0 = OFF; 1 = ON 1 DLO symmetrical Bitstream output 0 = OFF; 1 = ON 0 SSP stop band suppression 64× filter; 0 = 70 dB; 1 = 50 dB note 9 7 and 6 DI22 and DI21 5 and 4 serial format DI2 input 00 = I2S; 01 = Japanese 16-bit; 10 = Japanese 18-bit; 11 = Japanese 20-bit DO22 and DO21 serial format DO2 output 00 = I2S; 01 = Japanese 16-bit; 10 = Japanese 18-bit; 11 = reserved 3 and 2 DO12 and DO11 serial format DO1 output 00 = I2S; 01 = Japanese 16-bit; 10 = Japanese 18-bit; 11 = 3-stated 1 DO1M DO1 master/slave selector 0 = master; 1 = slave 0 FOT FO output 3-state selector 0 = I2S; 1 = 3-stated 7 GAIN7 6 GAIN6 5 GAIN5 GAIN7 to GAIN0: gain of the GCM block(10); maximum = 2; step = 1⁄128 4 GAIN4 some examples: 11111111 = ×2 (maximum) 10000000 = ×1 01111111 = ×0.992 00000001 = ×0.0078 3 GAIN3 2 GAIN2 1 GAIN1 0 GAIN0 Notes 1. In the SLAVE-VCXO mode, the PLL should be fixed in state 2 until locked. 2. A mode change will always invoke a restart of the GDIN. 3. At power-on the DO1 and FO outputs are ‘3-state’ to avoid I2S bus conflicts. This bit overrides the serial I/O control bits. 4. A MRS or hardware reset clears all command registers, also the MRS flag itself. 5. See Section “Data path switching” for possible settings of the data path switches in the different modes. 6. Set all reserved flags to 0. 7. Setting MMU starts a soft-mute from current gain value to 0 by 1⁄128 per input sample. Clearing MMU starts the inverse process from 0 to current gain value. 8. To prevent idle patterns in the audio band, it is strongly advised to add out-of-band dither by setting control bit NSD. 9. Set this bit for 32 kHz input sources. 10. Use ‘01111111’ for normal operation to avoid pass band ripple clipping. 1996 Jul 17 25 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H Data path switching All data path switches are freely controllable, although not all combinations make sense in the different operating modes. Table 11 shows the preferred settings of the CMD3 control register. Table 11 Preferred settings of the CMD3 control register REGISTER CMD3 (02H) data path BIT FLAG DATA PATH SWITCH 7 DSO DO1 output selector; note 2 SRC(1) SLAVE(1) AD/DA(1) 0 A A 6 − reserved − − − 5 FOS FO output selector; note 2 A A A 4 DI2 FIFO input selector A A A 3 DNI input selector 128× filter 0 1 1 2 − reserved − − − 1 AOS AOL and AOR output selector A A A 0 DO2 DO2 output selector 0 A A Notes 1. Level 0 or 1 indicates to set the flag in this position. A = application dependent. 2. When the output of the internal ADIC is fed directly to DO1 or FO, the serial output format is I2S, the word select jitters (by one 384fso clock cycle) and the number of bit clocks per word select is not fixed. STAND-ALONE CONTROL When pin SA is HIGH, the GDIN operates under stand-alone control. Some basic settings can be controlled in this event by changing the level at the control pins. Table 12 shows which command bits are pin-controllable during stand-alone operation. The command bits which are not pin-controllable are automatically set to their appropriate value in accordance with the selected mode (SRC or AD/DA). All control bits not shown get the value 0 in the event of stand-alone control. Table 12 Command registers REGISTER FLAG PIN CMD1 (00H) ADIC control DI11 FSL ADIC input selector 0 = DI1S; 1 = DI1O CMD2 (01H) loop and mode control MS0 DI1D mode selector; note 1 0 = SRC mode; 1 = AD/DA mode RTR − enable 3-state outputs; note 2 RTR is always 1 in stand-alone mode DI2 DA FIFO input selector 0 = FOW, FOD and FOC; 1 = DI2W, DI2D and DI2C DNI − input selector 128× filter SRC mode = 0: variable hold; AD/DA mode = 1: AIL/AIR CMD3 (02H) data path DESCRIPTION EXPLANATION CMD4 (03H) control QU0/QU1 CL in-band noise shaper 0 = 20 bit; 1 = 16 bit INS NSD LD dither Bitstream digital 0 = OFF; 1 = ON CMD6 (05H) GAIN − gain of the FIFO/GAIN block gain = 01111111 = ×0.992 Notes 1. When the device operates in stand-alone control, only the SRC mode and AD/DA mode are available. 2. This means that all 3-state outputs are permanently enabled during stand-alone operation. 1996 Jul 17 26 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage −0.5 − +6.5 V IDD supply current − − 200 mA Vi input voltage −0.5 − VDD + 0.5 V Ii(max) maximum input current − − 10 mA Io(max) maximum output current − − 10 mA Ptot total power dissipation − 1030 − mW Tstg storage temperature −65 − +150 °C Tamb operating ambient temperature Ves electrostatic handling 0 − +70 °C HBM; note 1 −3000 − +3000 V MM; note 2 −300 − +300 V Notes 1. Human Body Model (HBM): C = 100 pF; R = 1.5 kΩ; 3 zaps positive and 3 zaps negative. 2. Machine Model (MM): C = 200 pF; L = 2.5 µH; R = 25 Ω; 3 zaps positive and 3 zaps negative. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Jul 17 PARAMETER thermal resistance from junction to ambient in free air 27 VALUE UNIT 46 K/W Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H CHARACTERISTICS VDD = 5 V ±10%; Tamb = 0 to +70 °C; CL = 50 pF; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage −0.5 − 6.5 V IDDD digital supply current − 148 180 mA IDDA1 analog supply current IEC 958 data slicer − 0.65 1 mA IDDA4 analog supply current clock oscillator − 4 6 mA Ptot total power dissipation fso = 44.1 kHz − 775 − mW Iq(tot) total quiescent supply current Tamb = 25 °C; note 2 − − 10 µA DC characteristics INPUT PINS TYPE HPP01 (AIL, AIR, CLI, TST2, TST1, SA, LD, CL, DI2D, DI1D AND DI1O) VIL LOW level input voltage − − 0.3VDD V VIH HIGH level input voltage 0.7VDD − − V IIL input leakage current − − 1.0 µA INPUT PIN TYPE HPP07 (SCHMITT-TRIGGER; RST) VIL LOW level input voltage − − 0.2VDD V VIH HIGH level input voltage 0.8VDD − − V Vhys hysteresis voltage − 0.33VDD − V IIL input leakage current − − 1.0 µA INPUT PIN DI1S (IEC 958 INPUT) VIL LOW level input voltage − − 0.3VDD V VIH HIGH level input voltage 0.7VDD − − V Ii input current − − 1.9 mA OUTPUT PINS TYPE OPF40 (DO2C, AOL1, DO2D, AOR1, DO2W, CLO1, CLO2, CLO3, CLO4, BS, CEN, CUS, MU AND LOCK; 4 mA OUTPUTS) VOL LOW level output voltage − − 0.5 V VOH HIGH level output voltage VDD − 0.5 − − V OUTPUT PIN TYPE OPF20 (EM; 2 mA OUTPUT) VOL LOW level output voltage − − 0.5 V VOH HIGH level output voltage VDD − 0.5 − − V OUTPUT PINS TYPE OPF43 (CLD, DO1D, FOW, FOD AND FOC; 4 mA 3-STATE OUTPUTS) VOL LOW level output voltage − − 0.5 V VOH HIGH level output voltage VDD − 0.5 − − V IOZ 3-state leakage current − − 5.0 µA 1996 Jul 17 28 Philips Semiconductors Product specification General Digital Input (GDIN) SYMBOL PARAMETER TDA1373H CONDITIONS MIN. TYP. MAX. UNIT INPUT/OUTPUT PINS TYPE HOF21 (FSL, DI2W AND DI2C; 2 mA OUTPUTS) VIL LOW level input voltage − − 0.3VDD V VIH HIGH level input voltage 0.7VDD − − V IOZ 3-state leakage current − − 5.0 µA VOL LOW level output voltage − − 0.5 V VOH HIGH level output voltage VDD − 0.5 − − V INPUT/OUTPUT PINS TYPE HOF41 (DA, DO1W AND DO1C; 4 mA OUTPUTS) VIL LOW level input voltage − − 0.3VDD V VIH HIGH level input voltage 0.7VDD − − V IOZ 3-state leakage current − − 5.0 µA VOL LOW level output voltage − − 0.5 V VOH HIGH level output voltage VDD − 0.5 − − V Characteristics per block and pin; note 1 INPUT PINS TYPE HPP01 AND HPP07 Ci input capacitance − 10 − pF tr rise time (unless otherwise specified) − − Tcy ns tf fall time (unless otherwise specified) − − Tcy ns OUTPUT PINS TYPE OPF40 AND OPF43 tr rise time (unless otherwise specified) − 5 10 ns tf fall time (unless otherwise specified) − 5 10 ns CRYSTAL OSCILLATOR gm mutual conductance 0.007821 − 0.03913 mA/V ZO output impedance 405 − 3200 Ω IIL input leakage current − − 1.0 µA CI input capacitance − 3.1 − pF CO output capacitance − − 18 pF VIL LOW level input voltage − − 0.3VDD V VIH HIGH level input voltage 0.7VDD − − V IEC 958 INTERFACE (FOR TIMING SEE SECTION 13 OF REFERENCE 1 IN CHAPTER “References”) Vi(p-p) AC input voltage (peak-to-peak value) 0.2 − VDD V Ci input capacitance − 25 − pF 1996 Jul 17 29 Philips Semiconductors Product specification General Digital Input (GDIN) SYMBOL TDA1373H PARAMETER CONDITIONS MIN. TYP. MAX. UNIT SERIAL INPUT INTERFACES (see Fig.7) tr rise time (unless otherwise specified) − − 25 ns tf fall time (unless otherwise specified) − − 25 ns tsuDAT set-up time data (D) to clock (C) Tcy − − ns thDAT hold time data (D) to clock (C) 0 − − ns tsuWS set-up time word select (W) to clock (C) Tcy − − ns thWS hold time word select (W) to clock (C) 0 − − ns TBCK clock period time − 1/fBCK − ns tHB bit clock HIGH time Tcy − − ns tLB bit clock LOW time Tcy − − ns see Table 3 SERIAL OUTPUT INTERFACES tr rise time (unless otherwise specified) − − 10 ns tf fall time (unless otherwise specified) − − 10 ns tsuDAT set-up time data (D) to clock (C) 0.5tBCK − − ns thDAT hold time data (D) to clock (C) Tcy − − ns tsuWS set-up time word select (W) to clock (C) 0.5tBCK − − ns thWS hold time word select (W) to clock (C) TBCK clock period time tHB tLB Tcy − − ns − 1/fBCK − ns bit clock HIGH time 0.4tBCK − − ns bit clock LOW time 0.4tBCK − − ns − − 100 ns ns see Table 3 BITSTREAM INPUTS AIL AND AIR (see Fig.8) td1 delay time after HIGH-to-LOW clock transition BITSTREAM OUTPUTS AOL1, AOR1 AND CLD (see Fig.8) tr data output rise time − 10 15 tf data output fall time − 10 15 ns tsu data output set-up time 0 − − ns th data output hold time 25 − − ns tr clock output rise time − 5 10 ns tf clock output fall time − 5 10 ns tCH clock output HIGH time 40 − − ns tCL clock output LOW time 40 − − ns 1996 Jul 17 30 Philips Semiconductors Product specification General Digital Input (GDIN) SYMBOL PARAMETER TDA1373H CONDITIONS MIN. TYP. MAX. UNIT MICROCONTROLLER INTERFACE (see Fig.13) TcyCL CL cycle time 6Tcy − − ns tHCL CL HIGH time 3Tcy − − ns tLCL CL LOW time 3Tcy − − ns tsuLC set-up time LD to CL write operation 9Tcy − − ns thLC hold time LD to CL write operation 3Tcy − − ns tLD1 write pulse period LD 3Tcy − − ns TcyLD LD cycle time read operation 3Tcy − − ns thLC hold time LD to CL read operation 3Tcy − − ns tLD2 read enable LD pulse period 6Tcy − − ns tsuDC set-up time DA to CL write operation Tcy − − ns thDC hold time DA to CL write operation 3Tcy − − ns tsuDC set-up time DA to CL read operation Tcy − − ns thDC hold time DA to CL read operation 3Tcy − − ns 1 192 × ----f si − ms OUTPUT PINS CUS, CEN AND BS (see Fig.11) Channel status or channel mode TcyBS BS cycle time − tCEN CEN enable time − 1⁄ − µs tLCEN CEN LOW time 1.5 − − µs tsuBC set-up time BS to CEN 1.5 − − µs thBC hold time BS to CEN 8 − − µs tsuCC set-up time CUS to CEN 1.5 − − µs thCC hold time CUS to CEN 8 − − µs 2fsi CD-Q subcode demodulation mode TcyBS(CD) frame sync BS cycle time − 13.3 − ms tHBS(CD) frame sync BS HIGH time − 408 − µs tCEN CEN enable time − 136 − µs tHCEN(CD) CEN enable HIGH time − 1⁄ − ms tsuBSCEN set-up time BS to CEN 8 − − µs tsuCC(CD) set-up time CUS to CEN 1.5 − − µs thCC(CD) hold time CUS to CEN 8 − − µs 1996 Jul 17 31 2fsi Philips Semiconductors Product specification General Digital Input (GDIN) SYMBOL PARAMETER TDA1373H CONDITIONS MIN. TYP. MAX. UNIT RESET tPWRES reset pulse width 10Tcy − − ns tiRES internal reset time after reset pulse − − 40Tcy ns Notes 1. Most timing specifications are referenced to the system clock Tcy = 1⁄384fso. 2. The (IDD) quiescent current is checked on as much active gate area as possible, therefore outputs are chosen reference. Each output is IDD tested in HIGH and LOW state. The minimum number of test vectors on which IDD quiescent current is tested is 2 and the maximum is N + 1 (N = number of outputs). These test vectors also define fixed conditions in the core. IDD quiescent current test is not allowed on test vectors which may result in additional quiescent current caused by pull-up/down resistors, I/Os, internal bus-structures, etc. In total this IDD quiescent current test contributes highly to the (functional) fault coverage. QUALITY SPECIFICATION • General quality in accordance with “SNW-FQ-611 part E” and can be found in the “Quality Reference Handbook” (order number 9398 510 63011). REFERENCES 1. “Digital audio interface”, first edition 1989-03 International standard “IEC 958”. 2. “I2S bus specification”, release 2-86, Philips Export B.V. (order number 9398 332 10011). 1996 Jul 17 32 1996 Jul 17 J1 RCA C4 100 pF 33 VCC VCC VCC R1 75 Ω 6V 6V 4.7 Ω C22 47 µF C23 47 µF C20 100 nF C19 100 nF 41 42 5 4 13 12 14 2 11 C18 100 nF 4.7 Ω R6 6V C21 47 µF 3 1 62 63 43 37 44 R5 4.7 Ω R4 C3 100 nF C7 10 µF R3 10 kΩ VCC 34 BS 36 CUS 35 48 CEN LOCK 47 CL 46 DA 21 XTLI TDA1373H 45 LD 22 XTLO 23 CLI 28 30 31 VDDD VDDD VDDD VDDD CLO AOR1 AOL1 DO1C DO1W DO1D DO2C DO2W DO2D 55 54 56 59 60 8 33 40 53 26 29 Fig.14 Test diagram for the TDA1373H. 57 58 61 FSL VSSD VSSD VSSA4 VDDA4 CLO1 CLO2 CLO3 CLO4 27 R2 100 kΩ 64 FOD FOW FOC DI2D DI2W DI2C VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD TST2 TST1 AIR AIL VSSD VSSD VDDD VDDD VSSA1 VDDA1 DI1S DI1D DI1O SA EM MU 38 RST C2 100 nF 4 3 2 1 JP1 52 39 32 7 18 15 9 51 49 50 6 16 10 25 17 24 20 19 C11 100 nF C10 C8 100 nF R8 10 kΩ C5 100 nF 768f s 100 nF C9 100 nF R7 10 kΩ C16 22 pF Y1 4.7 Ω 1 nF C12 47 µF 6V C14 47 µF 6V C13 47 µF 6V C15 47 µF 6V L4 L3 L2 L1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 V CC V CC VCC VCC MLB967 - 1 JP2 VCC 2.2 µH L5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 IN 40 C6 47 µF DO1D 6 V DO1W DO1C DI2D DI2W DI2C AIL AIR AOL1 DO2D AOL2 AOR1 DO2W AOR2 CLD XTIN SDA R9 C17 22 pF C1 supply voltage ground General Digital Input (GDIN) handbook, full pagewidth Philips Semiconductors Product specification TDA1373H TEST DIAGRAM Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height SOT319-1 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 θ wM Lp pin 1 index bp L 20 64 detail X 19 1 w M bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.3 0.36 0.10 2.87 2.57 0.25 0.50 0.35 0.25 0.13 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.43 1.23 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-1 1996 Jul 17 EUROPEAN PROJECTION 34 o 7 0o Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9398 510 63011). Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Jul 17 35 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jul 17 36 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H NOTES 1996 Jul 17 37 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H NOTES 1996 Jul 17 38 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H NOTES 1996 Jul 17 39 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 708 296 8556 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 615 800, Fax. +358 615 80920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 52 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. +30 1 4894 339/911, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 648 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 83749, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 São Paulo, SÃO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com/ps/ (1) TDA1373H_3 June 26, 1996 11:51 am © Philips Electronics N.V. 1996 SCA50 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 517021/50/03/pp40 Date of release: 1996 Jul 17 Document order number: 9397 750 00927