RENESAS HD74BC573AP

HD74BC573A
Octal D Type Transparent Latches With 3 State Outputs
REJ03D0287–0300Z
(Previous ADE-205-021A (Z))
Rev.3.00
Jul.16.2004
Description
The HD74BC573A provides high drivability and operation equal to or better than high speed bipolar standard logic IC
by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC,
when the frequency is 10 MHz. The device has eight D type latches with three state outputs in a 20 pin package. When
the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D
inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the
output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs
and the state of the storage elements.
Features
• Input/Output are at high impedance state when power supply is off.
• Built in input pull up circuit can make input pins be open, when not used.
• TTL level input
• Wide operating temperature range
Ta = –40 to + 85°C
• Ordering Information
Part Name
Package Type
Package Code
HD74BC573AP
DILP-20 pin
HD74BC573AFPEL
SOP-20 pin (JEITA) FP-20DAV
DP-20N, -20NEV
Package
Abbreviation
Taping Abbreviation
(Quantity)
P
—
FP
EL (2,000 pcs/reel)
Note: Please consults the sales office for the above package availability.
Function Table
Output Control
Latch Enable
Data
Output Q
L
H
H
H
L
L
H
L
L
X
L
Q0
X
X
Z
H
H
L
X
Z
Q0
:
:
:
:
:
High leve
Low level
Immaterial
High impedance
Level of Q before the indicated steady input conditions were established
Rev.3.00, Jul.16.2004, page 1 of 8
HD74BC573A
Pin Arrangement
Output
Control
1
20
VCC
1D
2
19
1Q
2D
3
18
2Q
3D
4
17
3Q
4D
5
16
4Q
5D
6
15
5Q
6D
7
14
6Q
7D
8
13
7Q
8D
9
12
8Q
GND
10
11
Latch
Enable
(Top view)
Absolute Maximum Ratings
Item
Supply voltage
Input diode current
Input voltage
Output voltage
Off state output voltage
Symbol
VCC
Rating
–0.5 to +7.0
Unit
V
IIK
VIN
±30
–0.5 to +7.5
mA
V
VOUT
VOUT(off)
–0.5 to +7.5
–0.5 to +5.5
V
V
Storage temperature
Tstg
–65 to +150
°C
Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two
of which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
VCC
4.5
5.0
5.5
V
Input voltage
Output voltage
VIN
VOUT
0
0
—
—
VCC
VCC
V
V
Operating temperature
Input rise/fall time*1
Topr
tr, tf
–40
0
—
—
85
8
°C
ns/V
Note:
Symbol
Min
Typ
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Rev.3.00, Jul.16.2004, page 2 of 8
Max
Unit
HD74BC573A
Logic Diagram
Output
Control
D Q
1D
1Q
CK
2D
D Q
7D
D Q
2Q
CK
7Q
CK
D Q
8D
8Q
CK
Latch
Enable
Electrical Characteristics (Ta = –40°C to +85°C)
Item
Symbol
VCC (V)
Input voltage
VIH
Min
2.0
Max
—
Unit
V
Output voltage
VIL
VOH
4.5
—
2.4
0.8
—
V
V
IOH = –3 mA
VOL
4.5
4.5
2.0
—
—
0.4
V
V
IOH = –15 mA
IOL = 24 mA
Input diode voltage
VIK
4.5
4.5
—
—
0.5
–1.2
V
V
IOL = 48 mA
IIN = –18 mA
Input current
II
5.5
5.5
—
—
–250
1.0
µA
µA
VIN = 0 V
VIN = 5.5 V
—
–100
100
–225
µA
mA
VIN = 7.0 V
VIN = 0 or 5.5 V
VO = 2.7 V
VO = 0.5 V
VIN = 0 or 5.5 V
All outputs is “L”
VIN = 0 or 5.5 V
All outputs is “H”
VIN = 0 or 5.5 V
All outputs is “Z”
VIN = 3.4 or 0.5 V
Short circuit output current*
IOS
5.5
5.5
Off state output current
IOZH
IOZL
5.5
5.5
—
—
50
–50
µA
µA
Supply current
ICCL
5.5
—
29.5
mA
ICCH
5.5
—
2.5
mA
ICCZ
5.5
—
2.5
mA
ICCT*2
5.5
—
1.5
mA
1
Test Conditions
Notes: 1. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one
second.
2. When input by the TTL level, it shows ICC increase at per one input pin.
Rev.3.00, Jul.16.2004, page 3 of 8
HD74BC573A
Switching Test Method (CL = 50 pF)
Ta = 25°C
VCC = 5.0 V
Item
Propagation
Ta = –40 to 85°C
VCC = 5.0 V ±10%
D→Q
Symbol
Min
tPLH
3.0
Max
8.0
Min
3.0
Max
10.0
Unit
Test conditions
ns
See under figure
LE → Q
tPHL
tPLH
3.0
3.0
8.0
8.0
3.0
3.0
10.0
10.0
ns
Output enable time
tPHL
tZH
3.0
3.0
8.0
9.0
3.0
3.0
10.0
11.0
ns
Output disable time
tZL
tHZ
3.0
3.0
9.0
8.0
3.0
3.0
11.0
10.0
ns
Setup time
tLZ
tS(H)
3.0
2.0
8.0
—
3.0
2.0
10.0
—
ns
Hold time
tS(L)
th(H)
2.0
2.0
—
—
2.0
2.0
—
—
ns
Pulse width
th(L)
tw
2.0
6.0
—
—
2.0
6.0
—
—
Input capacitanse
Output capacitance
CIN
CO
3.0 (Typ)
15.0 (Typ)
delay time
—
—
ns
pF
pF
VIN = VCC or GND
VO = VCC or GND
Test Circuit
Input
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
Notes:
VCC
See Function Table
VCC
OC
500 Ω
1D to 8D
1Q to 8Q
LE
1. CL includes probe and jig capacitance.
2. OPEN: tPLH, tPHL, tZH, tHZ, th, tS, tw
7 V: tZL, tLZ
Rev.3.00, Jul.16.2004, page 4 of 8
Output
CL =
50 pF
450 Ω
50 Ω Scope
*2
OPEN
7V
HD74BC573A
Waveforms-1
tr
tf
90%
1.5 V
Input
LE
3V
90%
1.5 V
10%
10%
90%
Input
D
0V
tf
tr
3V
90%
10%
10%
t PLH
0V
t PHL
VOH
1.5 V
Output
Q
1.5 V
VOL
Waveforms-2
tr
3V
90%
Input
LE
10%
0V
tr
tf
90%
Input
D
3V
90%
1.5 V
1.5 V
10%
10%
t PHL
t PLH
0V
VOH
Output
Q
Rev.3.00, Jul.16.2004, page 5 of 8
1.5 V
1.5 V
VOL
HD74BC573A
Waveforms-3
tr
Input
LE
tf
90%
1.5 V
10%
3V
90%
1.5 V
tw
10%
ts
0V
th
3V
Input
D
Notes:
1.5 V
1.5 V
0V
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform: PRR =1 MHz, duty cycle 50%
Waveforms-4
tf
Output
Control
tr
90%
90%
1.5 V
3V
1.5 V
10%
10%
0V
t ZL
t LZ
3.5 V
1.5 V
Waveform–A
VOL + 0.3 V
t ZH
Waveform–B
VOL
t HZ
VOH – 0.3 V
VOH
1.5 V
0V
Notes:
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform: PRR = 1 MHz, duty cycle 50%
3. Waveform-A shows input conditions such that the output is “L” level when enable by the
output control.
4. Waveform-B shows input conditions such that the output is “H” level when enable by the
output control.
Rev.3.00, Jul.16.2004, page 6 of 8
HD74BC573A
Package Dimensions
As of January, 2003
Unit: mm
24.50
25.40 Max
1
7.00 Max
11
6.30
20
10
2.54 ± 0.25
0.51 Min
1.27 Max
0.48 ± 0.10
2.54 Min 5.08 Max
1.30
0.89
7.62
+ 0.11
0.25 – 0.05
0˚ – 15˚
Package Code
JEDEC
JEITA
Mass (reference value)
DP-20N
—
Conforms
1.26 g
Unit: mm
24.50
25.40 Max
1
7.00 Max
11
6.30
20
10
1.30
2.54 ± 0.25
*0.48 ± 0.08
0.51 Min
1.27 Max
2.54 Min 5.08 Max
0.89
7.62
*0.25 ± 0.06
0˚ – 15˚
*NI/Pd/AU Plating
Rev.3.00, Jul.16.2004, page 7 of 8
Package Code
JEDEC
JEITA
Mass (reference value)
DP-20NEV
—
Conforms
1.26 g
HD74BC573A
As of January, 2003
Unit: mm
12.6
13 Max
11
1
10
1.27
*0.40 ± 0.06
0.10 ± 0.10
0.80 Max
*0.20 ± 0.05
2.20 Max
5.5
20
0.20
7.80 +– 0.30
1.15
0˚ – 8 ˚
0.70 ± 0.20
0.15
0.12 M
*Ni/Pd/Au plating
Rev.3.00, Jul.16.2004, page 8 of 8
Package Code
JEDEC
JEITA
Mass (reference value)
FP-20DAV
—
Conforms
0.31 g
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