19-2456; Rev 0; 11/07 EVALUATION KIT AVAILABLE Low-Jitter, Precision Clock Generator with Two Outputs The MAX3622 is a low-jitter precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet and other networking applications. The proprietary PLL design features ultra-low jitter (0.36psRMS) and excellent power-supply noise rejection, minimizing design risk for network equipment. The MAX3622 has one LVPECL output and one LVCMOS output. It is available in a 16-pin TSSOP package and operates over the 0°C to +70°C temperature range. Features ♦ Crystal Oscillator Interface: 25MHz Typical ♦ Output Frequencies: 125MHz and 156.25MHz ♦ Low Jitter 0.14psRMS (1.875MHz to 20MHz) 0.36psRMS (12kHz to 20MHz) ♦ Excellent Power-Supply Noise Rejection ♦ No External Loop Filter Capacitor Required Ordering Information Applications Ethernet Networking Equipment Typical Application Circuit and Pin Configuration appear at end of data sheet. PART TEMP RANGE PINPACKAGE PKG CODE MAX3622CUE+ 0°C to +70°C 16 TSSOP U16-2 +Denotes a lead-free package. Block Diagram QAC_OE RESET LOGIC/POR MAX3622 RESET ÷5 LVCMOS BUFFER QA_C 27pF 625MHz X_IN 25MHz X_OUT CRYSTAL OSCILLATOR PFD FILTER RESET VCO RESET RESET ÷ 25 ÷4 QB_OE 33pF LVPECL BUFFER QB QB 1 MAX3622 General Description MAX3622 Low-Jitter, Precision Clock Generator with Two Outputs ABSOLUTE MAXIMUM RATINGS Current into QA_C ............................................................±50mA Current into QB, QB...........................................................-56mA Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 11.1mW/°C above +70°C) .......889mW Operating Junction Temperature Range ...........-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Supply Voltage Range VCC, VCCA, VDDO_A, VCCO_B ...............................................-0.3V to +4.0V Voltage Range at QAC_OE, QB_OE, RES1, RES2 ............................................-0.3V to (VCC + 0.3V) Voltage Range at X_IN Pin ....................................-0.3V to +1.2V Voltage Range at GNDO_A...................................-0.3V to +0.3V Voltage Range at X_OUT Pin ......................-0.3V to (VCC - 0.6V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER Power-Supply Current SYMBOL ICC CONDITIONS MIN (Note 3) TYP MAX UNITS 70 90 mA CONTROL INPUT CHARACTERISTICS (QAC_OE, QB_OE PINS) Input Capacitance Input Logic Bias Resistor CIN 2 pF RBIAS 50 k LVPECL OUTPUT SPECIFICATIONS (QB, QB PINS) Output High Voltage VOH VCC 1.13 VCC 0.98 VCC 0.83 V Output Low Voltage VOL VCC 1.85 VCC 1.7 VCC 1.55 V 0.6 0.72 0.9 VP-P 200 350 600 ps 48 50 52 % Peak-to-Peak Output-Voltage Swing (Single-Ended) Output Rise/Fall Time 20% to 80% Output Duty-Cycle Distortion LVCMOS/LVTTL INPUT SPECIFICATIONS (QAC_OE, QB_OE PINS) Input-Voltage High VIH 2.0 Input-Voltage Low VIL Input High Current I IH VIN = VCC Input Low Current I IL VIN = 0V V 0.8 V 80 μA -80 μA LVCMOS OUTPUT SPECIFICATIONS (QA_C PIN) Output High Voltage VOH QA_C sourcing 12mA Output Low Voltage VOL QA_C sinking 12mA 2.6 V 0.4 V Output Rise/Fall Time (Note 4) 250 500 1000 ps Output Duty-Cycle Distortion (Note 4) 42 50 58 % Output Impedance 2 14 _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Two Outputs (VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MHz CLOCK OUTPUT AC SPECIFICATIONS VCO Frequency Range 620 Random Jitter RJRMS 625 648 12kHz to 20MHz 0.36 1.0 1.875MHz to 20MHz 0.14 Deterministic Jitter Induced by Power-Supply Noise (Notes 5, 6) LVPECL output 4 LVCMOS output 19 Spurs Induced by Power-Supply Noise (Note 6) LVPECL output -57 LVCMOS output -47 psP-P Nonharmonic and Subharmonic Spurs -70 Clock Output SSB Phase Noise at 125MHz Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: psRMS f = 1kHz -124 f = 10kHz -126 f = 100kHz -130 f = 1MHz -145 f > 10MHz -153 dBc dBc dBc/Hz A series resistor of up to 10.5Ω is allowed between VCC and VCCA for filtering supply noise when system power-supply tolerance is VCC = 3.3V ±5%. See Figure 2. LVPECL terminated with 50Ω load connected to VTT = VCC - 2V. Both outputs enabled and unloaded. Measured using setup shown in Figure 1 with VCC = 3.3V ±5%. Measured with Agilent DSO81304A 40GS/s real-time oscilloscope. Measured with 40mVP-P, 100kHz sinusoidal signal on the supply with VCCA connected as shown in Figure 2. 36Ω MAX3622 499Ω OSCILLOSCOPE 0.1μF Z0 = 50Ω QA_C 4.7pF 50Ω Figure 1. LVCMOS Output Measurement Setup _______________________________________________________________________________________ 3 MAX3622 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Typical values are at VCC = +3.3V, TA = +25°C, crystal frequency = 25MHz.) OUTPUT WAVEFORM AT 125MHz (LVCMOS OUTPUT) DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz (LVPECL OUTPUT) SUPPLY CURRENT vs. TEMPERATURE MAX3622 toc03 MAX3622 toc02 MAX3622 toc01 150 MEASURED USING 50Ω OSCILLOSCOPE INPUT THROUGH NETWORK SHOWN IN FIGURE 1 BOTH OUTPUTS ACTIVE AND TERMINATED 100 75 BOTH OUTPUTS ACTIVE AND UNTERMINATED 50 AMPLITUDE (50mV/div) AMPLITUDE (200mv/div) 125 SUPPLY CURRENT (mA) 25 0 0 10 20 30 40 50 60 70 1ns/div 1ns/div AMBIENT TEMPERATURE (°C) QB PHASE NOISE (156.25MHz CLOCK FREQUENCY) QA_C PHASE NOISE (125MHz CLOCK FREQUENCY) -100 -110 -120 -130 -140 -150 -90 -100 -110 -120 -130 -140 -150 -160 -160 0.1 1 10 100 1000 10,000 100,000 OFFSET FREQUENCY (kHz) 4 MAX3622 toc05 -90 -80 NOISE POWER DENSITY (dBc/Hz) MAX3622 toc04 -80 NOISE POWER DENSITY (dBc/Hz) MAX3622 Low-Jitter, Precision Clock Generator with Two Outputs 0.1 1 10 100 1000 10,000 100,000 OFFSET FREQUENCY (kHz) _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Two Outputs PIN NAME 1 QAC_OE 2 GNDO_A 3 QA_C 4 5, 6 VDDO_A FUNCTION LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect pin high to enable QA_C. Connect low to set QA_C to a high-impedance state. Has internal 50k input impedance. Ground for QA_C Output. Connect to supply ground. LVCMOS Clock Output Power Supply for QA_C Clock Output. Connect to +3.3V. RES1, RES2 Reserved. Do not connect. 7 VCCA Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can connect to VCC through 10.5 as shown in Figure 2 (requires VCC = +3.3V ±5%). 8 VCC Core Power Supply. Connect to +3.3V. 9, 15 GND Supply Ground 10 X_OUT 11 X_IN 12 VCCO_B 13 QB LVPECL, Inverting Clock Output 14 QB LVPECL, Noninverting Clock Output 16 QB_OE Crystal Oscillator Output Crystal Oscillator Input Power Supply for QB Clock Output. Connect to +3.3V. LVCMOS/LVTTL Input. Enables/disables QB clock output. Connect pin high to enable LVPECL clock output QB. Connect low to set QB to a logic 0. Has internal 50k input impedance. Detailed Description The MAX3622 is a low-jitter clock generator designed to operate at Ethernet frequencies. It consists of an onchip crystal oscillator, PLL, LVCMOS output buffer, and an LVPECL output buffer. Using a 25MHz crystal as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance. Crystal Oscillator An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires a 25MHz crystal connected between X_IN and X_OUT. PLL The PLL takes the signal from the crystal oscillator and synthesizes a low-jitter, high-frequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO). The VCO output is connected to the PFD input through a feedback divider. The PFD compares the reference frequency to the divided-down VCO output (fVCO/25) and generates a control signal that keeps the VCO locked to the reference clock. The high-frequency VCO output clock is sent to the output dividers. To minimize noiseinduced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies. Output Dividers The output dividers are set to divide-by-five for the LVCMOS output QA_C and divide-by-four for the LVPECL output QB. LVPECL Driver The differential PECL buffer (QB) is designed to drive transmission lines terminated with 50Ω to VCC - 2.0V. The output goes to a logic 0 when disabled. LVCMOS Driver QA_C, the LVCMOS output, is designed to drive a single-ended high-impedance load. This output goes to a high-impedance state when disabled. Reset Logic/POR During power-on, the power-on reset (POR) signal is generated to synchronize all dividers. _______________________________________________________________________________________ 5 MAX3622 Pin Description Low-Jitter, Precision Clock Generator with Two Outputs MAX3622 Applications Information +3.3V ±5% Power-Supply Filtering The MAX3622 is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. In addition to excellent on-chip power-supply noise rejection, the MAX3622 provides a separate powersupply pin, VCCA, for the VCO circuitry. Figure 2 illustrates the recommended power-supply filter network for V CCA . The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. This network requires that the power supply is +3.3V ±5%. Decoupling capacitors should be used on all other supply pins for best performance. VCC 0.01μF 10.5Ω VCCA 0.01μF 10μF Figure 2. Analog Supply Filtering Crystal Selection The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 1 for recommended crystal specifications. See Figure 4 for external capacitor connection. Crystal Input Layout and Frequency Stability C9 The crystal, trace, and two external capacitors should be placed on the board as close as possible to the MAX3622’s X_IN and X_OUT pins to reduce crosstalk of active signals into the oscillator. Y1 25MHz CRYSTAL MAX3622 C 10 The layout shown in Figure 3 gives approximately 3pF of trace plus footprint capacitance per side of the crystal (Y1). The dielectric material is FR-4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C10 = 27pF and C9 = 33pF, the measured output frequency accuracy is -10ppm at +25°C ambient temperature. Figure 3. Crystal Layout Table 1. Crystal Selection Parameters PARAMETER Crystal Oscillation Frequency SYMBOL MIN TYP fOSC 25 Shunt Capacitance CO 2.0 Load Capacitance CL 18 Equivalent Series Resistance (ESR) RS Maximum Crystal Drive Level 6 MAX UNITS MHz 7.0 pF pF 50 300 μW _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Two Outputs 27pF X_IN 25MHz CRYSTAL (CL = 18pF) X_OUT 33pF Interface Models Figure 4. Crystal, Capacitors Connection Figure 7 and Figure 8 show examples of interface models. VCC +3.3V 130Ω MAX3622 QB Z0 = 50Ω QB Z0 = 50Ω 130Ω HIGH IMPEDANCE QB 82Ω 82Ω QB Figure 5. Thevenin Equivalent of Standard PECL Termination ESD STRUCTURES 0.1μF Z0 = 50Ω QB 100Ω MAX3622 0.1μF HIGH IMPEDANCE Figure 7. Simplified LVPECL Output Circuit Schematic Z0 = 50Ω QB 150Ω VDDO_A 150Ω DISABLE NOTE: AC-COUPLING IS OPTIONAL. Figure 6. AC-Coupled PECL Termination 10Ω IN QA_C 10Ω ESD STRUCTURES GNDO_A Figure 8. Simplified LVCMOS Output Circuit Schematic _______________________________________________________________________________________ 7 MAX3622 Interfacing with LVPECL Outputs The equivalent LVPECL output circuit is given in Figure 7. This output is designed to drive a pair of 50Ω transmission lines terminated with 50Ω to VTT = VCC - 2V. If a separate termination voltage (VTT) is not available, other termination methods can be used such as shown in Figures 5 and 6. Unused outputs should be disabled and may be left open. For more information on LVPECL terminations and how to interface with other logic families, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML. MAX3622 Low-Jitter, Precision Clock Generator with Two Outputs Layout Considerations The inputs and outputs are critical paths for the MAX3622, and care should be taken to minimize discontinuities on these transmission lines. Here are some suggestions for maximizing the MAX3622’s performance: • An uninterrupted ground plane should be positioned beneath the clock I/Os. • Supply and ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3622 and the receive devices. • Supply decoupling capacitors should be placed close to the MAX3622 supply pins. • Maintain 100Ω differential (or 50Ω single-ended) transmission line impedance out of the MAX3622. • Use good high-frequency layout techniques and a multilayer board with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3622 Evaluation Kit for more information. Typical Application Circuit VCC +3.3V ±5% 10.5Ω 0.1μF 0.1μF VCCO_B VCC 10μF 0.01μF VDDO_A ASIC MAX3622 QAC_OE QB Z0 = 50Ω QB_OE QB Z0 = 50Ω 156.25MHz X_OUT X_IN GND 25MHz (CL = 18pF) 33pF 8 Z0 = 50Ω 125MHz 0.01μF VCC 36Ω QA_C VCCA 0.1μF GNDO_A ASIC 50Ω 50Ω (VCC - 2V) 27pF _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Two Outputs Pin Configuration TRANSISTOR COUNT: 10,490 PROCESS: BiCMOS TOP VIEW QAC_OE + 16 QB_OE 2 15 GND QA_C 3 14 QB VDDO_A 4 13 QB RES1 5 12 VCCO_B RES2 6 11 X_IN VCCA 7 10 X_OUT VCC 8 9 GND GNDO_A 1 Chip Information MAX3622 TSSOP Package Information For the latest package outline information and land patterns (footprints), go to http://www.microsemi.com . PACKAGE TYPE DOCUMENT NO. 16 TSSOP 21-0066 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.