MAX3610 Data Sheet

19-3286; Rev 0; 5/04
EVALUATION KIT AVAILABLE
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
The MAX3610 is a low-jitter, high-performance, dual-rate
clock generator optimized for 1Gbps/2Gbps/4Gbps
Fibre-Channel applications. When connected with an
external AT-cut crystal, the device generates a precision
clock output by integrating a crystal oscillator with
Maxim’s low-noise phase-locked loop (PLL) providing a
low-cost solution. By coupling Maxim’s low-noise PLL
design featuring a low-jitter generation VCO with an
inexpensive fundamental mode crystal, the MAX3610
provides the optimum combination of low cost, flexibility,
and high performance.
The MAX3610 output frequency is selectable. When
using a 26.5625MHz crystal, the output clock rate can
be set to either 106.25MHz or 212.5MHz. When operating at 106.25MHz, the typical phase jitter is 0.7psRMS
from 12kHz to 20MHz. The MAX3610A has low-voltage
positive-emitter-coupled logic (LVPECL) clock output
drivers. The MAX3610B has low-voltage differential-signal (LVDS) clock output drivers. The MAX3610 output
drivers can also be disabled.
The MAX3610 operates from a single +3.3V supply.
The PECL version typically consumes 165mW, while the
LVDS version typically consumes 174mW. Both devices
are available in die form and have a 0°C to +85°C operating temperature range.
Applications
Features
♦ Clock Output Frequencies: 106.25MHz or
212.5MHz
♦ Phase Jitter: 0.7psRMS
♦ LVPECL or LVDS Output
♦ Excellent Power-Supply Noise Rejection
♦ Supply Current: 50mA at +3.3V Supply (LVPECL)
53mA at +3.3V Supply (LVDS)
♦ 0°C to +85°C Temperature Range
♦ Optional Output Disable
Ordering Information
PINPACKAGE
PART
TEMP RANGE
OUTPUTS
MAX3610AU/D
MAX3610BU/D
0°C to +85°C
Die
LVPECL
0°C to +85°C
Die
LVDS
Dice are designed to operate from 0°C to +85°C, but are tested
and guaranteed only at TA = +25°C.
Fibre-Channel Hard Disk Drives
Host Bus Adapters
Raid Controllers
Fibre-Channel Switches
Typical Operating Circuits
+3.3V
+3.3V
0.1µF
0.1µF
OE
VCC
FREQSET
OE
+3.3V
AT CUT
CRYSTAL
AT CUT
CRYSTAL
X1
MAX3610A
X1
OUT+
VCC
FREQSET
MAX3610B
OUT+
DEVICE WITH
LVPECL INPUTS
GND
100Ω
50Ω
50Ω
DEVICE WITH
LVDS INPUTS
OUT-
X2
OUT-
X2
+3.3V
GND
OPERATING AT 106.25MHz
LVPECL OUTPUTS
VCC -2V
OPERATING AT 106.25MHz
LVDS OUTPUTS
1
MAX3610
General Description
MAX3610
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................................................-0.5V to +5.0V
Voltage at FREQSET, OE............................-0.5V to (VCC + 0.5V)
Voltage at X1 .........................................................-0.5V to +0.8V
Voltage at X2 .....................................................................0 to 2V
PECL Output Current ..........................................................56mA
LVDS Output Voltage .................................-0.5V to (VCC + 0.5V)
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Processing Temperature..................................................+400°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1 )
PARAMETER
SYMBOL
Supply Current
ICC
CONDITIONS
(Note 2)
TYP
MAX
LVPECL
MIN
50
65
LVDS
53
67
UNITS
mA
LVPECL OUTPUT SPECIFICATIONS (Note 3)
Output High Voltage
VOH
0°C to +85°C
VCC 1.025
VCC 0.88
V
Output Low Voltage
VOL
0°C to +85°C
VCC 1.81
VCC 1.62
V
1.475
V
400
mV
25
mV
1.275
V
25
mV
140
Ω
12
mA
0.8
V
LVDS OUTPUT SPECIFICATIONS (Figure 1)
LVDS Output High Voltage
LVDS Output Low Voltage
LVDS Differential Output Voltage
LVDS Change in Magnitude of
Differential Output for
Complementary States
LVDS Offset Output Voltage
(Output Common-Mode Voltage)
LVDS Change in Magnitude of
Output Offset Voltage for
Complementary States
VOH
VOL
0.925
|VOD|
250
V
∆|VOD|
1.125
VOS
∆|VOS|
LVDS Differential Output
Impedance
80
LVDS Output Current
100
Outputs shorted together
CONTROL INPUT SPECIFICATIONS (FREQSET, OE)
TTL Control Input-Voltage High
VIH
TTL Control Input-Voltage Low
VIL
2
V
Input Current (Input High)
IIH
-10
+10
µA
Input Current (Input Low)
IIL
-50
+10
µA
CLOCK OUTPUT SPECIFICATIONS
Clock Output Frequency
Crystal Oscillation Circuit Input
Capacitance
2
FREQSET = TTL High, VCC, or NC
FREQSET = TTL Low or GND
106.25
212.5
12
_______________________________________________________________________________________
MHz
pF
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
(VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1 )
PARAMETER
SYMBOL
Phase Jitter
PJRMS
CONDITIONS
MIN
12kHz to 20MHz
Accumulated Deterministic Jitter
Due to Reference Spurs
MAX
UNITS
0.7
1.0
psRMS
3.0
Accumulated Deterministic Jitter
Due to Power-Supply Noise
Clock-Output Edge Speeds
TYP
(Note 4)
tR, tF
20% to 80%
10kHz
3.0
100kHz
27
69
200kHz
15
43
1MHz
7
LVPECL outputs
250
600
200
600
49
51
%
5
ms
(Note 5)
Clock-Output SSB Phase Noise
Measured at 106.25MHz
psP-P
LVDS outputs
Clock-Output Duty Cycle
Oscillation Startup Time
psP-P
100Hz
-90
1kHz
-112
10kHz
-115
100kHz
-123
1MHz
-142
10MHz
-147
ps
dBc/Hz
Note 1: AC parameters are guaranteed by design and characterization.
Note 2: Outputs are enabled and unloaded.
Note 3: When LVPECL output is disabled to high impedance, the typical output off-current is <100µA for nominal LVPECL signal
levels at the output.
Note 4: Measured with 50mVP-P sinusoidal signal on the supply, from 10kHz to 1MHz.
Note 5: Including oscillator startup time and PLL acquisition time, measured after VCC reaches 3.0V from power on.
OUT+
RL = 100Ω
D
V
VOD
OUTVOH
VOUT+
|VOD|
SINGLE-ENDED OUTPUT
VOS
VOL
VOUT-
+VOD
DIFFERENTIAL OUTPUT
0V (DIFF)
0V
VODP-P = VOUT+ - VOUT-VOD
Figure 1. LVDS Swing Definitions
_______________________________________________________________________________________
3
MAX3610
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
65
LVDS DEVICE
55
50
LVPECL DEVICE
45
40
70
100mVP-P NOISE
60
50mVP-P NOISE
50
40
30
20
10
10
20
30
40
50
60
70
80
SUPPLY VOLTAGE (V)
45
40
212, 5MHz CLOCK OUTPUT
50mVP-P SUPPLY NOISE
VOLTAGE AMPLITUDE
35
30
100kHz SUPPLY NOISE
25
20
15
10
5
200kHz SUPPLY NOISE
0
0
0
50
OUTPUT DETERMINISTIC JITTER (psP-P)
70
MAX3610 toc02
75
80
OUTPUT DETERMINISTIC JITTER (psP-P)
MAX3610 toc01
80
60
OUTPUT DETERMINISTIC JITTER DUE TO
POWER-SUPPLY NOISE vs. SUPPLY VOLTAGE
OUTPUT DETERMINISTIC JITTER DUE TO
POWER-SUPPLY NOISE vs. FREQUENCY
MAX3610 toc03
POWER-SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT (mA)
MAX3610
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
1
10
100
1000
FREQUENCY OF POWER-SUPPLY NOISE VOLTAGE (kHz)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE LEVEL (V)
Pin Description
PAD
NAME
1, 2, 3, 6, 7, 9,
10, 11, 15–18
N.C.
4
X1
Crystal Oscillator Input
5
X2
Crystal Oscillator Output
8
OE
Output Enable. On-chip pullup resistor. Connect OE to logic-high, VCC, or leave open to enable the
output clock. Connect OE to logic-low or GND to disable the output clock. LVPECL output clock is set
to high impedance when disabled. LVDS output clock is latched to a differential high when disabled.
12
OUT-
Negative Clock Output, LVPECL or LVDS
13
GND
Ground
14
OUT+
Positive Clock Output, LVPECL or LVDS
19
FREQSET
20
VCC
4
FUNCTION
No Connection
Output Frequency Select. On-chip pullup resistor. Connect FREQSET to logic-high, VCC, or leave open
to set the output clock rate to 106.25MHz. Connect FREQSET to logic-low or GND to set the output
clock rate to 212.5MHz.
+3.3V Supply
_______________________________________________________________________________________
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
FREQSET
MAX3610A
MAX3610B
X1
OSCILLATOR
GAIN CIRCUIT
PFD
LOOP
FILTER
VCO
X2
COUNTER
M
OUTPUT
BUFFER
OUT+
OUT-
PLL
COUNTER
N
OE
Figure 2. Functional Diagram
Detailed Description
The MAX3610 contains all of the blocks needed to form a
precision Fibre-Channel clock except for the external
crystal, which must be supplied separately. Figure 2
shows a functional block diagram of the MAX3610. The
MAX3610 consists of a crystal oscillator, a low-noise PLL,
selectable clock-divider circuitry, and an output buffer.
Optimal performance is achieved by integrating the
crystal oscillator with a low-noise PLL. The PLL consists
of a digital phase/frequency detector (PFD) and low-jitter generation VCO. The VCO signal is scaled by clockdivider circuitry and applied to the output buffer. The
MAX3610 is available with either LVPECL or LVDS output buffers (see the Ordering Information).
Oscillator Gain Circuit
The input capacitance of the oscillator gain circuit is
trimmed to 12pF of capacitance and produces oscillations at 26.5625MHz when interfaced with the appropriate external crystal (see Table 1 for the external crystal
specifications).
PLL
The PLL generates a 1.7GHz high-speed clock signal
based on the 26.5625MHz crystal oscillator output.
Clock-divider circuit M generates the output clock by
scaling the VCO output frequency. Clock-divider circuit
N applies a scaled version of the output clock signal to
the PFD. A TTL low applied to FREQSET, sets clockdivider M ratio to 16, and clock-divider N ratio to 8. With
FREQSET pulled low, the output clock rate is
212.5MHz. A TTL high applied to FREQSET sets the
clock-divider M ratio to 32, and clock-divider N ratio to
4. With FREQSET pulled high, the output clock rate is
106.25MHz.
Output Drivers
The MAX3610 is available with either LVPECL
(MAX3610A) or LVDS (MAX3610B) output buffers.
When not needed, the output buffers can be disabled.
When disabled, the LVPECL output buffer goes to a
high-impedance state. However, the LVDS outputs go
to a differential 1 (OUT+ latched high and OUT- latched
low) when the outputs are disabled.
Design Procedure
Crystal Resonator Specifications
The MAX3610 is designed to operate with an inexpensive fundamental mode crystal. Table 1 specifies the
characteristics of a typical crystal to be interfaced with
the MAX3610.
_______________________________________________________________________________________
5
MAX3610
Functional Diagram
MAX3610
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
Table 1. Crystal Resonator Specifications
PARAMETER
CO
VALUE
Crystal
Fundamental AT-cut
Nominal Oscillator Frequency
26.5625MHz
Shunt Capacitance (Co)
2pF
Co/Cs
280
Load Capacitance (Note 6)
12pF
Equivalent Series Resistance (ESR)
5Ω to 40Ω
Maximum Crystal Drive Level
500µW
X1
X2
CS
RS
LS
Figure 3. Equivalent Crystal Resonator Circuit Model
Note 6: The load capacitance includes the oscillation-circuit
input capacitance, as well as the parasitic capacitance caused
from the assembling/packaging of the blank crystal and IC.
Applications Information
VCC
VCC
OUT+
ESD
STRUCTURES
OUT+
OUT-
OUT-
ESD
STRUCTURES
Figure 4. LVPECL Output Stage
6
Figure 5. LVDS Output Stage
_______________________________________________________________________________________
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
COORDINATES
PAD
NAME
X (µm)
Y (µm)
BP1
N.C.
36.1
1362.4
BP2
N.C.
13.7
1193
BP3
N.C.
13.7
1060
BP4
X1
17.9
742.2
BP5
X2
16.5
613.4
BP6
N.C.
16.5
474.8
BP7
N.C.
16.5
344.6
BP8
OE
15.1
210.2
*BP9
N.C.
16.5
39.4
BP10
N.C.
167.7
33.8
BP11
N.C.
1119.7
36.6
BP12
OUT-
1613.9
50.6
BP13
GND
1613.9
187.8
BP14
OUT+
1613.9
325
BP15
N.C.
1612.5
613.4
BP16
N.C.
1611.1
753.4
BP17
N.C.
577.9
1366.6
BP18
N.C.
435.1
1369.4
BP19
FREQSET
306.3
1369.4
BP20
VCC
169.1
1366.6
Bond pad coordinates specify center pad location. All
bond pad coordinates are referenced to the lower
most left corner of the index pad (see Application Note
HFAN 9.0).
*Index pad
_______________________________________________________________________________________
7
MAX3610
Pad Information
Table 2. Bond Pad Coordinates
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel
Clock Generator
Package Information
Chip Topography
For the latest package outline information and land patterns
(footprints), go to http://www.microsemi.com
TRANSISTOR COUNT: 2920
SUBST ELECTRICALLY ISOLATED
PROCESS: SiGe BIPOLAR
DIE SIZE: 1.88mm x 1.63mm
1
N.C.
VCC
FREQSET
N.C.
N.C.
20
19
18
17
N.C.
2
N.C.
3
X1
4
16
X2
5
15
N.C.
N.C.
6
N.C.
7
14
OUT+
OE
8
13
GND
N.C.
9
N.C.
0.064"
1.63mm
10
N.C.
0.074"
1.88mm
11
12
N.C.
OUT-
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