19-4256; Rev 0; 8/10 EVALUATION KIT AVAILABLE +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs Applications Ethernet Networking Equipment Features ♦ Crystal Oscillator Interface: 25MHz ♦ OSC_IN Interface: PLL Enabled: 25MHz PLL Disabled: 20MHz to 320MHz ♦ Outputs: MAX3698A (Five LVDS Outputs at 125MHz) MAX3697A (Four LVDS Outputs at 125MHz, One LVDS Output at 125MHz/156.25MHz) Three LVCMOS Outputs at 125MHz One LVCMOS Output at 3.90625MHz ♦ Low Phase Jitter: 0.4psRMS (12kHz to 20MHz) ♦ PSNR: -57dBc at 100kHz Offset ♦ Operating Temperature Range: -40°C to +85°C Ordering Information Typical Operating Circuit PART +3.3V ±5% 0.1μF 0.1μF 0.1μF 10.5Ω VDD 10μF VDDO_DIFF VDDO_SE Q0 VDDA 0.01μF OSC_IN MAX3697A MAX3698A 33pF Z0 = 50Ω 125MHz/156.25MHz (MAX3697A ONLY) Q0 Z0 = 50Ω Q1 Z0 = 50Ω 125MHz Q1 Z0 = 50Ω Q2 Z0 = 50Ω 125MHz Q2 Z0 = 50Ω 100Ω ASIC 100Ω ASIC 100Ω ASIC 100Ω ASIC 100Ω ASIC TEMP RANGE PIN-PACKAGE MAX3697AETJ+ -40°C to +85°C 32 TQFN-EP* MAX3698AETJ+ -40°C to +85°C 32 TQFN-EP* +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad. X_OUT 25MHz (CL = 18pF) X_IN 27pF Q3 Z0 = 50Ω 125MHz VDD PLL_BP Q3 Q4 Z0 = 50Ω Z0 = 50Ω 125MHz GND OR VDD FSEL (MAX3697A ONLY) Q4 Z0 = 50Ω 33Ω Q5 125MHz Z0 = 50Ω ASIC 125MHz Z0 = 50Ω ASIC 125MHz Z0 = 50Ω ASIC 3.90625MHz Z0 = 50Ω ASIC GND 33Ω Q6 33Ω Q7 49.9Ω Q8 ________________________________________________________________ Maxim Integrated Products For information on other Maxim products, visit Maxim’s website at www.maxim-ic.com. 1 MAX3697A/MAX3698A General Description The MAX3697A/MAX3698A are low-jitter precision clock generators optimized for network applications. The devices integrate a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications. This proprietary PLL design features ultra-low jitter (0.4psRMS) and excellent power-supply noise rejection (PSNR), minimizing design risk for network equipment. The MAX3697A/MAX3698A contain five LVDS outputs and four LVCMOS outputs. The MAX3697A has a selectable output feature on channel Q0 that allows selection between 125MHz or 156.25MHz. MAX3697A/MAX3698A +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 32-Pin TQFN (derate 34.5mW/°C above +70°C) .......2759mW Operating Junction Temperature ......................-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Supply Voltage Range at VDD, VDDA, VDDO_SE, VDDO_DIFF ................................................-0.3V to +4.0V Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q6, Q7, Q8, PLL_BP, FSEL, OSC_IN..........................-0.3V to (VDD + 0.3V) Voltage at X_IN Pin................................................-0.3V to +1.2V Voltage at X_OUT Pin ........................................-0.3V to (VDD - 0.6V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT, input no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1) PARAMETER Power-Supply Current (Note 2) SYMBOL IDD TYP MAX PLL enabled CONDITIONS MIN 175 224 PLL bypassed 160 UNITS mA LVDS OUTPUTS (Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4 Pins) Output High Voltage VOH Output Low Voltage VOL Differential Output Voltage Amplitude Change in Magnitude of Differential Output for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States |VOD | 1.475 0.925 Figure 1 250 1.125 |VOS| Differential Output Impedance 80 Output Current Clock Output Rise/Fall Time V |VOD | VOS tr, tf Output Duty-Cycle Distortion V 105 Shorted together 5 Short to ground (Note 3) 8 400 mV 25 mV 1.275 V 25 mV 140 mA 20% to 80%, RL = 100 90 180 330 PLL enabled 48 50 52 ps PLL bypassed (Note 4) 46 50 54 2.4 2.7 3.3 V 0.4 V % LVCMOS/LVTTL OUTPUTS (Q5, Q6, Q7, Q8 Pins) Q8 Output High Voltage VOH IOH = -2mA Q8 Output Low Voltage VOL IOL = 2mA Q5, Q6, Q7 Output High Voltage VOH IOH = -12mA Q5, Q6, Q7 Output Low Voltage VOL IOL = 12mA 2 2.6 _______________________________________________________________________________________ VDD V 0.4 V +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs (VDD = 3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT, input no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1) PARAMETER SYMBOL Q5, Q6, Q7 Output Rise/Fall Time tr, tf Q8 Output Rise/Fall Time tr, tf Output Duty-Cycle Distortion Output Impedance CONDITIONS 20% to 80% at 125MHz (Note 5) MIN TYP MAX UNITS 0.15 0.5 0.8 ns ns 4.0 6.1 PLL enabled 20% to 80% at 3.90625MHz (Note 5) 45 50 55 PLL bypassed (Note 4) 43 50 57 ROUT % 15 INPUT SPECIFICATIONS (FSEL, PLL_BP Pins) Input-Voltage High VIH 2.0 VDD V Input-Voltage Low VIL 0 0.8 V Input High Current IIH VIN = VDD 82 μA Input Low Current IIL VIN = 0 -80 μA LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6) PLL enabled Input Clock Frequency Input Amplitude Range MHz PLL bypassed 20 320 (Note 7) 1.2 3.6 V 80 μA Input High Current IIH VIN = VDD Input Low Current IIL VIN = 0 Reference Clock Duty Cycle Input Capacitance 25 80 40 CIN μA 50 60 % 1.5 pF 625 MHz CLOCK OUTPUT AC SPECIFICATIONS VCO Center Frequency Output Frequency with PLL Enabled for MAX3697A FSEL = GND (Q0) 125 FSEL = VDD (Q0) 156.25 Q1 to Q7 125 Q8 output 3.90625 Q0 to Q7 MHz 125 Output Frequency with PLL Enabled for MAX3698A Q8 Output Frequency with PLL Disabled LVDS outputs 20 320 LVCMOS outputs Q5, Q6, Q7 20 160 Integrated Phase Jitter at 125MHz/156.25MHz RJRMS 12kHz to 20MHz, PLL_BP = high (Note 8) 0.4 12kHz to 20MHz, PLL_BP = high-Z (Note 9) 0.4 Power-Supply Noise Rejection (Note 10) LVDS output -57 LVCMOS output -47 Deterministic Jitter Due to Supply Noise (Note 11) LVDS output 7 LVCMOS output 23 MAX3697A -73 MAX3698A -87 Nonharmonic and Subharmonic Spurs (Note 12) MHz 3.90625 MHz psRMS dBc psP-P dBc _______________________________________________________________________________________ 3 MAX3697A/MAX3698A ELECTRICAL CHARACTERISTICS (continued) MAX3697A/MAX3698A +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT, input no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1) PARAMETER LVDS Clock Output SSB Phase Noise at 125MHz (Note 13) LVCMOS Clock Output SSB Phase Noise at 125MHz (Note 13) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: 4 SYMBOL CONDITIONS MIN TYP f = 100Hz -114 f = 1kHz -124 f = 10kHz -127 f = 100kHz -131 f = 1MHz -144 f > 10MHz -149 f = 100Hz -113 f = 1kHz -124 f = 10kHz -126 f = 100kHz -130 f = 1MHz -144 f > 10MHz -151 MAX UNITS dBc/Hz dBc/Hz A series resistor of up to 10.5Ω is allowed between VDD and VDDA for filtering supply noise when system power-supply tolerance is VDD = 3.3V ±5%. See Figure 5. All outputs unloaded. The current when an LVDS output is shorted to ground is the steady-state current after the detection circuitry has settled. It is expected that the LVDS output short to ground condition is short-term only. Measured with OSC_IN input with 50% duty cycle. Q5, Q6, and Q7 measured with a series resistor of 33Ω to a load capacitance of 3.0pF. Q8 is measured with a series resistor of 50Ω to a load capacitance of 15pF. See Figure 2. The OSC_IN input can be DC- or AC-coupled. Must be within the absolute maximum rating of VDD + 0.3V. Measured with 25MHz crystal (with OSC_IN left open). Measured with 25MHz signal applied to OSC_IN. Measured at 125MHz output with 40mVP-P sinusoidal signal on the supply at 100kHz. Measured with network in Figure 5. Parameter calculated based on PSNR. Measurement includes XTAL oscillator feedthrough, crosstalk, intermodulation spurs, etc. Measured with 25MHz XTAL oscillator. _______________________________________________________________________________________ +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3697A/MAX3698A Qx RL = 100Ω VOD V Qx Qx VOH IVODI SINGLE-ENDED OUTPUT VOS Qx VOL Qx - Qx DIFFERENTIAL OUTPUT 0 VODP-P = 2IVODI Figure 1. Driver Output Levels VCC MAX3697A MAX3698A 800Ω RL Qx Z0 = 50Ω CL 800Ω OSCILLOSCOPE 0.1μF Z0 = 50Ω Q5 TO Q7: RL = 33Ω, CL = 3pF Q8: RL = 49.9Ω, CL = 15pF 50Ω 50Ω Figure 2. LVCMOS Output Measurement Setup _______________________________________________________________________________________ 5 Typical Operating Characteristics (Typical values are at VDD = +3.3V, TA = +25°C, crystal frequency = 25MHz.) SUPPLY CURRENT vs. TEMPERATURE 125 100 75 50 -100 -110 -120 -130 -140 0 5 20 35 50 65 80 0.1 AMBIENT TEMPERATURE (°C) 1 10 100 -110 -120 -130 -140 0.1 1000 10,000 100,000 10 100 1000 10,000 100,000 DIFFERENTIAL OUTPUT WAVEFORM AT 125MHz (LVDS OUTPUT) MAX3697A/98A toc05 MAX3697A/98A toc04 -80 1 OFFSET FREQUENCY (kHz) OFFSET FREQUENCY (kHz) PHASE NOISE AT 125MHz CLOCK FREQUENCY (Q7) NOISE POWER DENSITY (dBc/Hz) -100 -160 -160 -40 -25 -10 -90 -150 -150 25 MAX3697A/98A toc03 -90 -80 NOISE POWER DENSITY (dBc/Hz) PLL_BP = LOW MAX3697A/98A toc02 175 NOISE POWER DENSITY (dBc/Hz) PLL_BP = HIGH 150 -80 MAX3697A/98A toc01 225 200 PHASE NOISE AT 125MHz CLOCK FREQUENCY (Q4) PHASE NOISE AT 156MHz CLOCK FREQUENCY (Q0) 250 SUPPLY CURRENT (mA) MAX3697A/MAX3698A +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs -90 -100 -110 100mV/div -120 -130 -140 -150 -160 0.1 1 10 100 1ns/div 1000 10,000 100,000 OFFSET FREQUENCY (kHz) OUTPUT WAVEFORM AT 125MHz (CMOS OUTPUT) OUTPUT WAVEFORM AT 3.90625MHz (CMOS OUTPUT) DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz (LVDS OUTPUT) MAX3697A/98A toc06 MAX3697A/98A toc08 MAX3697A/98A toc07 MEASURED USING SETUP IN FIGURE 2 15mV/div 20mV/div 100mV/div 1ns/div 6 MEASURED USING SETUP IN FIGURE 2 1ns/div _______________________________________________________________________________________ 40ns/div +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs -30 -40 -50 -60 -20 -30 -40 -50 -60 -70 -70 -80 -80 -90 -90 10 100 10,000 1000 100 10 NOISE FREQUENCY (kHz) 1000 10,000 NOISE FREQUENCY (kHz) Q8 VDDO_SE Q7 GND Q6 VDDO_SE Q5 GND Pin Configuration 24 23 22 21 20 19 18 17 TOP VIEW VDDA 25 16 RESERVED PLL_BP 26 15 RESERVED VDD 27 FSEL (GND) 28 14 Q4 13 Q4 12 VDDO_DIFF MAX3697A MAX3698A OSC_IN 29 X_IN 30 X_OUT 31 EP + 3 4 5 6 7 8 Q1 Q1 VDDO_DIFF Q2 Q2 2 GND 1 Q0 GND 32 Q0 SPUR AMPLITUDE (dBc) fC = 125MHz OUTPUT = Q0 NOISE AMPLITUDE = 40mVP-P -10 SPUR AMPLITUDE (dBc) fC = 125MHz OUTPUT = Q5 NOISE AMPLITUDE = 40mVP-P -20 0 MAX3697A/98A toc09 0 -10 MAX3697A/98A toc10 SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY 11 Q3 10 Q3 9 GND THIN QFN (5mm × 5mm) ( )MAX3698A ONLY. _______________________________________________________________________________________ 7 MAX3697A/MAX3698A Typical Operating Characteristics (continued) (Typical values are at VDD = +3.3V, TA = +25°C, crystal frequency = 25MHz.) +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs MAX3697A/MAX3698A Pin Description PIN FUNCTION MAX3698A 1 Q0 Q0 LVDS, Noninverting Clock Output 2 Q0 Q0 LVDS, Inverting Clock Output 3, 9, 17, 21, 32 GND GND Supply Ground 4 Q1 Q1 LVDS, Noninverting Clock Output 5 Q1 Q1 LVDS, Inverting Clock Output 6, 12 VDDO_DIFF VDDO_DIFF 7 Q2 Q2 LVDS, Noninverting Clock Output 8 Q2 Q2 LVDS, Inverting Clock Output Power Supply for Q0, Q1, Q2, Q3, and Q4 Clock Outputs. Connect to +3.3V. 10 Q3 Q3 LVDS, Noninverting Clock Output 11 Q3 Q3 LVDS, Inverting Clock Output 13 Q4 Q4 LVDS, Noninverting Clock Output 14 Q4 Q4 LVDS, Inverting Clock Output 15 RESERVED RESERVED Reserved. Connect to GND. 16 RESERVED RESERVED Reserved. Connect to VDD. 18, 20, 22, 24 Q5, Q6, Q7, Q8 Q5, Q6, Q7, Q8 19, 23 VDDO_SE VDDO_SE 25 VDDA VDDA Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can connect to VDD through a 10.5 resistor as shown in Figure 5. Three-State LVCMOS/LVTTL Input (Active Low). When connected to logic-high, the PLL locks to the crystal interface (25MHz typical at X_IN and X_OUT). When left open (high-Z) the PLL locks to the OSC_IN input (25MHz typical). When connected to logic-low, the PLL is bypassed and the OSC_IN input is selected. When bypass mode is selected, the VCO/PLL is disabled to save power and eliminate intermodulation spurs. LVCMOS Clock Output Power Supply for Q5, Q6, Q7, and Q8 Clock Outputs. Connect to +3.3V. 26 PLL_BP PLL_BP 27 VDD VDD Core Power Supply. Connect to +3.3V. 28 FSEL GND LVCMOS/LVTTL Input. Controls the Q0 output divider on the MAX3697A. For the MAX3697A, connect to logic-low for 125MHz output or connect to logic high for 156.25MHz output. For the MAX3698A, connect to GND. OSC_IN LVCMOS Input. Self-biased to allow AC- or DC-coupling. When PLL_BP is open, the OSC_IN input frequency should be 25MHz. When the PLL is in bypass mode (PLL_BP = low), the OSC_IN input frequency can be between 20MHz and 320MHz. When PLL_BP is high, the OSC_IN should be disconnected. 29 8 NAME MAX3697A OSC_IN 30 X_IN X_IN 31 X_OUT X_OUT — EP EP Crystal Oscillator Input Crystal Oscillator Output Exposed Pad. Connect to GND for proper electrical and thermal performance. _______________________________________________________________________________________ +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs VDDA PLL_BP MAX3697A/MAX3698A VDD VDDO_DIFF PLL_BP LOGIC 125MHz 0 OSC_IN CMOS 0/OPEN PFD FILTER VCO DIVIDE 5 LVDS BUFFER 1/OPEN 1 X_IN LVDS BUFFER CRYSTAL OSCILLATOR X_OUT Q0 Q0 Q1 Q1 DIVIDE 25 LVDS BUFFER LVDS BUFFER LVDS BUFFER Q2 Q2 Q3 Q3 Q4 Q4 MAX3698A 125MHz DIVIDE 32 3.90625MHz LVCMOS BUFFER Q5 LVCMOS BUFFER Q6 LVCMOS BUFFER Q7 LVCMOS BUFFER Q8 VDDO_SE Figure 3. MAX3698A Functional Diagram _______________________________________________________________________________________ 9 MAX3697A/MAX3698A +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs VDD VDDA FSEL PLL_BP VDDO_DIFF PLL_BP LOGIC 125/156.25MHz 0 OSC_IN CMOS 0/OPEN PFD FILTER VCO DIVIDE 5 OR 4 CRYSTAL OSCILLATOR DIVIDE 25 Q0 125MHz LVDS BUFFER X_OUT Q0 1/OPEN 1 X_IN LVDS BUFFER 0 DIVIDE 5 Q1 Q1 125MHz 1/OPEN LVDS BUFFER Q2 Q2 125MHz LVDS BUFFER Q3 Q3 125MHz LVDS BUFFER Q4 Q4 MAX3697A 125MHz LVCMOS BUFFER Q5 125MHz LVCMOS BUFFER Q6 125MHz DIVIDE 32 3.90625MHz LVCMOS BUFFER Q7 LVCMOS BUFFER Q8 VDDO_SE Figure 4. MAX3697A Functional Diagram 10 ______________________________________________________________________________________ +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs The MAX3697A/MAX3698A are frequency generators designed to operate at Ethernet frequencies. They consist of an on-chip crystal oscillator, PLL, LVCMOS output buffers, and LVDS output buffers. Using a low-frequency clock (crystal or CMOS input) as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance. The MAX3697A comes with a selector pin (FSEL) that allows the Q0 output to be switched between 125MHz and 156.25MHz. Crystal Oscillator An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between X_IN and X_OUT. The crystal frequency is 25MHz. Applications Information Power-Supply Filtering The MAX3697A/MAX3698A are mixed analog/digital ICs. The PLL contains analog circuitry susceptible to random noise. To take full advantage of on-board filtering and noise attenuation, in addition to excellent onchip power-supply rejection, these parts provide a separate power-supply pin, VDDA, for the VCO circuitry. The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. Figure 5 illustrates the recommended power-supply filter network for VDDA. This network requires that the power supply is +3.3V ±5%. Decoupling capacitors should be used on all other supply pins for best performance. OSC_IN Buffer The LVCMOS OSC_IN buffer is internally biased to allow AC- or DC-coupling. This input is internally ACcoupled, and is designed to operate at 25MHz when the PLL is enabled (PLL_BP is left open). When the PLL is bypassed (PLL_BP is set low), the OSC_IN buffer can be operated from 20MHz to 320MHz. +3.3V ±5% VDD 0.1μF 10.5Ω VDDA 0.01μF 10μF PLL The PLL takes the signal from the crystal oscillator or reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO) that operates at 625MHz. The VCO output is connected to the PFD input through a feedback divider that divides the VCO frequency by 25 to lock onto the 25MHz reference clock or oscillator. With the VCO locked onto the input reference, a stable 125MHz output clock is provided through a final output divider. The MAX3697A includes an extra control pin (FSEL) that selects either 125MHz or 156.25MHz output frequency at Q0. To minimize noise-induced jitter, the VCO supply (VDDA) is isolated from the core logic and output buffer supplies. LVDS Drivers The high-frequency outputs—Q0, Q1, Q2, Q3, and Q4— are differential LVDS buffers designed to drive 100Ω. LVCMOS Driver LVCMOS outputs Q5, Q6, Q7, and Q8 are provided on the MAX3697A/MAX3698A. They are designed to drive single-ended high-impedance loads. The maximum data rate for Q5, Q6, and Q7 is 160MHz. Q8 output frequency is equal to the frequency of Q5, Q6, or Q7 divided by 32. Figure 5. Analog Supply Filtering Crystal Input Layout and Frequency Stability The MAX3697A/MAX3698A feature an integrated onchip crystal oscillator to minimize system implementation cost. The integrated crystal oscillator is a Pierce-type that uses the crystal in its parallel resonance mode. It is recommended to use a 25MHz crystal with a load specification of CL = 18pF. See Table 1 for the recommended crystal specifications. The crystal, trace, and two external capacitors should be placed on the board as close as possible to the X_IN and X_OUT pins to reduce crosstalk and active signals into the oscillator. The layout shown in Figure 6 gives approximately 2pF of trace plus footprint capacitors per side of the crystal (Y1). The dielectric material is FR-4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C45 = 27pF and C46 = 33pF, the measured output frequency accuracy is -1ppm at +25°C ambient temperature. ______________________________________________________________________________________ 11 MAX3697A/MAX3698A Detailed Description MAX3697A/MAX3698A +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs Table 1. Crystal Selection Parameters PARAMETER Crystal Oscillation Frequency SYMBOL fOSC Shunt Capacitance CO Load Capacitance CL Equivalent Series Resistance (ESR) RS MIN TYP MAX 25 UNITS MHz 7.0 pF 18 pF Maximum Crystal Drive Level 50 300 μW Crystal Selection The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 1 for recommended crystal specifications. See Figure 7 for external capacitance connection. 27pF X_IN CRYSTAL (CL = 18pF) X_OUT 33pF Figure 7. Crystal, Capacitors Connection Figure 6. Crystal Layout 12 ______________________________________________________________________________________ +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs 1.4V VDD 180kΩ • Supply decoupling capacitors should be placed close to the supply pins, preferably on the same layer as the MAX3697A/MAX3698A. OSC_IN • Take care to isolate crystal input traces from the MAX3697A/MAX3698A outputs. • The crystal, trace, and two external capacitors should be placed on the board as close as possible to the X_IN and X_OUT pins to reduce crosstalk and active signals into the oscillator. ESD STRUCTURES Figure 8. Simplified OSC_IN Pin Circuit Schematic Vx plane under the crystal should be removed to minimize capacitance. • Ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3697A/MAX3698A and the receive devices. VDDO_SE • Maintain 100Ω differential (or 50Ω single-ended) transmission line impedance into and out of the part. • Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3697A and MAX3698A evaluation kits for more information. ROUT Exposed-Pad Package Q5 TO Q8 ROUT ESD STRUCTURES The exposed pad on the 32-pin TQFN package provides a very low inductance path for return current traveling to the PCB ground plane. The pad is also electrical ground on the MAX3697A/MAX3698A and must be soldered to the circuit board ground for proper electrical performance. Chip Information Vx = 2.7V FOR Q8 Vx = VDDO_SE FOR Q5 TO Q7 ROUT = 50Ω FOR Q8 ROUT = 10Ω FOR Q5 TO Q7 TRANSISTOR COUNT: 13,768 PROCESS: BiCMOS Package Information Figure 9. Simplified LVCMOS Output Circuit Schematic Layout Considerations The inputs and outputs are the most critical paths for the MAX3697A/MAX3698A and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the MAX3697A/MAX3698A: • An uninterrupted ground plane should be positioned beneath the clock outputs. The ground For the latest package outline information and land patterns (footprints), go to http://www.microsemi.com . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 32 TQFN-EP T3255+5 21-0140 90-0013 ______________________________________________________________________________________ 13 MAX3697A/MAX3698A Interface Models Figures 8 and 9 show examples of interface models. MAX3697A/MAX3698A +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs Revision History REVISION NUMBER REVISION DATE 0 8/10 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 14 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. 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