RENESAS 4551

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER
4500 SERIES
4551
Group
User’s Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
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● The prior written approval of Mitsubishi Electric Corporation is necessary to
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● If these products or technologies are subject to the Japanese export control
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Any diversion or reexport contrary to the export control laws and regulations of
JAPAN and/or the country of destination is prohibited.
● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
Preface
This user’s manual describes the hardware and
instructions of Mitsubishi’s 4551 Group CMOS 4-bit
microcomputer.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 4551 Group and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting
examples of related registers.
● CHAPTER 3 APPENDIX
This chapter includes precautions for systems development using the microcomputer, the mask ROM
confirmation forms (mask ROM version), ROM programming confirmation forms (One Time PROM version)
and mark specification forms which are to be submitted when ordering.
Be sure to refer to this chapter because this chapter also includes necessary information for systems
development.
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-3
FEATURES ...................................................................................................................................... 1-3
PIN CONFIGURATION (TOP VIEW) ........................................................................................... 1-3
APPLICATION ................................................................................................................................ 1-3
BLOCK DIAGRAM ......................................................................................................................... 1-4
PERFORMANCE OVERVIEW ....................................................................................................... 1-5
DEFINITION OF CLOCK AND CYCLE ....................................................................................... 1-5
PIN DESCRIPTION ........................................................................................................................ 1-6
MULTIFUNCTION ................................................................................................................... 1-7
CONNECTIONS OF UNUSED PINS ................................................................................... 1-7
PORT FUNCTION .................................................................................................................. 1-7
PORT BLOCK DIAGRAMS .................................................................................................. 1-8
FUNCTIONAL BLOCK OPERATIONS ...................................................................................... 1-10
CPU ........................................................................................................................................ 1-10
PROGRAM MEMORY (ROM) ............................................................................................. 1-13
DATA MEMORY (RAM) ...................................................................................................... 1-14
INTERRUPT FUNCTION ..................................................................................................... 1-15
EXTERNAL INTERRUPTS .................................................................................................. 1-18
TIMERS ................................................................................................................................. 1-20
WATCHDOG TIMER ............................................................................................................ 1-24
CARRIER GENERATING CIRCUIT ................................................................................... 1-25
LCD FUNCTION ................................................................................................................... 1-28
RESET FUNCTION .............................................................................................................. 1-32
VOLTAGE DROP DETECTION CIRCUIT ......................................................................... 1-34
POWER DOWN FUNCTION ............................................................................................... 1-35
CLOCK CONTROL .............................................................................................................. 1-38
ROM ORDERING METHOD ....................................................................................................... 1-39
LIST OF PRECAUTIONS ............................................................................................................ 1-40
SYMBOL ........................................................................................................................................ 1-41
LIST OF INSTRUCTION FUNCTION ........................................................................................ 1-42
INSTRUCTION CODE TABLE .................................................................................................... 1-44
MACHINE INSTRUCTIONS ........................................................................................................ 1-46
CONTROL REGISTERS .............................................................................................................. 1-60
BUILT-IN PROM VERSION ........................................................................................................ 1-64
PIN CONFIGURATION (TOP VIEW) ......................................................................................... 1-64
4551 Group User’s Manual
i
Table of contents
CHAPTER 2 APPLICATION
2.1 I/O pins .................................................................................................................................... 2-2
2.1.1 I/O ports .......................................................................................................................... 2-2
2.1.2 Related registers ............................................................................................................ 2-4
2.1.3 Port application examples ............................................................................................. 2-6
2.1.4 Notes on use .................................................................................................................. 2-8
2.2 Interrupts ................................................................................................................................. 2-9
2.2.1 Interrupt functions .......................................................................................................... 2-9
2.2.2 Related registers .......................................................................................................... 2-10
2.2.3 Interrupt application examples .................................................................................... 2-12
2.2.4 Notes on use ................................................................................................................ 2-16
2.3 Timers .................................................................................................................................... 2-17
2.3.1 Timer functions ............................................................................................................. 2-17
2.3.2 Related registers .......................................................................................................... 2-17
2.3.3 Timer application examples ........................................................................................ 2-20
2.3.4 Notes on use ................................................................................................................ 2-24
2.4 Carrier generating circuit .................................................................................................. 2-25
2.4.1 Carrier functions ........................................................................................................... 2-25
2.4.2 Related registers .......................................................................................................... 2-26
2.4.3 Carrier wave output application examples ................................................................ 2-28
2.4.4 Notes on use ................................................................................................................ 2-32
2.5 LCD function ......................................................................................................................... 2-33
2.5.1 Operation description ................................................................................................... 2-33
2.5.2 Related registers .......................................................................................................... 2-34
2.5.3 LCD application examples .......................................................................................... 2-36
2.5.4 Notes on use ................................................................................................................ 2-38
2.6 Power down function .......................................................................................................... 2-39
2.6.1 Clock control function .................................................................................................. 2-41
2.6.2 Power down function ................................................................................................... 2-41
2.6.3 Related register ............................................................................................................ 2-44
2.6.4 Power down function application example ............................................................... 2-45
2.6.5 Notes on use ................................................................................................................ 2-45
2.7 Reset ....................................................................................................................................... 2-46
2.7.1 Reset circuit .................................................................................................................. 2-46
2.7.2 Internal state at reset .................................................................................................. 2-48
2.7.3 Voltage drop detection circuit ..................................................................................... 2-49
2.8 Oscillation circuit ................................................................................................................ 2-50
2.8.1 Oscillation circuit .......................................................................................................... 2-50
2.8.2 Oscillation operation .................................................................................................... 2-51
2.8.3 Notes on use ................................................................................................................ 2-51
ii
4551 Group User’s Manual
Table of contents
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-3
3.1.3 Electrical characteristics ................................................................................................ 3-4
3.1.4 Basic timing diagram ..................................................................................................... 3-5
3.2 Typical characteristics ......................................................................................................... 3-6
3.2.1 VDD–IDD characteristics ................................................................................................. 3-6
3.2.2 VOH–I OH characteristics (port CARR) .......................................................................... 3-9
3.2.3 V OL–IOL characteristics (Ports P0, P1, D 0 –D7, CARR, RESET) ............................ 3-10
3.2.4 Voltage drop detection circuit temperature characteristics .................................... 3-11
3.3 List of precautions .............................................................................................................. 3-12
3.4 Notes on noise ..................................................................................................................... 3-13
3.4.1 Shortest wiring length .................................................................................................. 3-13
3.4.2 Connection of bypass capacitor across VSS line and VCC line ............................ 3-15
3.4.3 Oscillator concerns ....................................................................................................... 3-16
3.4.4 setup for I/O ports ....................................................................................................... 3-17
3.4.5 providing of watchdog timer function by software ................................................... 3-17
3.5 Mask ROM order confirmation form ............................................................................... 3-18
3.6 ROM programming order confirmation form ................................................................ 3-20
3.7 Mark specification form ..................................................................................................... 3-21
3.8 Package outline ................................................................................................................... 3-22
4551 Group User’s Manual
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig.
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iv
1 AMC instruction execution example ............................................................................... 1-10
2 RAR instruction execution example ............................................................................... 1-10
3 Registers A, B and register E ........................................................................................ 1-10
4 TABP p instruction execution example .......................................................................... 1-10
5 Stack registers (SKs) structure ....................................................................................... 1-11
6 Example of operation at subroutine call ....................................................................... 1-11
7 Program counter (PC) structure ..................................................................................... 1-12
8 Data pointer (DP) structure ............................................................................................. 1-12
9 SD instruction execution example .................................................................................. 1-12
10 ROM map of M34551E8 ................................................................................................ 1-13
11 Interrupt address page (addresses 0080 16 to 00FF16) structure ............................ 1-13
12 RAM map ......................................................................................................................... 1-14
13 Program example of interrupt processing ................................................................... 1-16
14 Internal state when interrupt occurs ............................................................................ 1-16
15 Interrupt system diagram ............................................................................................... 1-16
16 Interrupt sequence .......................................................................................................... 1-17
17 External interrupt circuit structure ................................................................................ 1-18
18 Auto-reload function ....................................................................................................... 1-20
19 Timers structure .............................................................................................................. 1-21
20 Watchdog timer function ................................................................................................ 1-24
21 Program example to enter the RAM back-up mode when using the watchdog timer .... 1-24
22 Carrier wave selection register ..................................................................................... 1-25
23 Carrier wave output auto-control by timer 1 .............................................................. 1-27
24 LCD clock control circuit structure ............................................................................... 1-28
25 LCD controller/driver structure ...................................................................................... 1-29
26 LCD RAM map ................................................................................................................ 1-30
27 LCD controller/driver structure ...................................................................................... 1-31
28 Reset release timing ...................................................................................................... 1-32
29 RESET pin input waveform and reset operation ....................................................... 1-32
30 Power-on reset circuit example .................................................................................... 1-32
31 Internal state at reset .................................................................................................... 1-33
32 Voltage drop detection reset circuit ............................................................................. 1-34
33 Voltage drop detection circuit operation waveform .................................................... 1-34
34 Set source and clear source of the P flag ................................................................. 1-36
35 Start condition identified example using the SNZP instruction .............................. 1-36
36 State transition ................................................................................................................ 1-37
37 Clock control circuit structure ....................................................................................... 1-38
38 Ceramic resonator external circuit ............................................................................... 1-39
39 Quartz-crystal oscillator external circuit ...................................................................... 1-39
40 External 0 interrupt program example ......................................................................... 1-40
41 Pin configuration of built-in PROM version ................................................................ 1-64
42 PROM memory map ....................................................................................................... 1-65
43 Flow of writing and test of the product shipped in blank ......................................... 1-65
4551 Group User’s Manual
List of figures
CHAPTER 2 APPLICATION
Fig.
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2.1.1
2.1.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3.1
2.3.2
2.3.3
2.3.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.6.1
2.6.2
2.6.3
2.6.4
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.8.1
2.8.2
2.8.3
Key input by key scan ................................................................................................. 2-6
Input timing of key scan ............................................................................................. 2-7
External interrupt operation example ....................................................................... 2-12
External interrupt setting example ........................................................................... 2-13
Timer 1 constant period interrupt setting example ................................................ 2-14
Timer 2 constant period interrupt setting example ................................................ 2-15
Watchdog timer function............................................................................................ 2-20
Constant period measurement setting example ..................................................... 2-21
Constant period counter by timer 2 setting example ............................................ 2-22
Watchdog timer setting example .............................................................................. 2-23
Carrier wave selection register ................................................................................ 2-26
Carrier wave auto-control setting example 1 ......................................................... 2-28
Carrier wave auto-control setting example 2 ......................................................... 2-29
Carrier wave output interval setting example ......................................................... 2-30
Carrier wave by software generating example ...................................................... 2-31
LCD clock control circuit structure ........................................................................... 2-33
LCD RAM map ........................................................................................................... 2-34
LCD display panel example ...................................................................................... 2-36
Segment assignment example .................................................................................. 2-36
LCD RAM assignment example ............................................................................... 2-36
Initial setting example ................................................................................................ 2-37
State transition ............................................................................................................ 2-39
Oscillation stabilizing time in each mode ............................................................... 2-40
Start condition identified example ............................................................................ 2-43
Software setting example .......................................................................................... 2-45
Power-on reset circuit example ................................................................................ 2-46
Reset circuit example when the supply voltage rising time exceeds 100 ms .. 2-47
Oscillation stabilizing time after system is released from reset .......................... 2-47
Internal state at reset ................................................................................................ 2-48
Voltage drop detection reset circuit ......................................................................... 2-49
Voltage drop detection circuit operation waveform ............................................... 2-49
Oscillation circuit example connecting ceramic resonator externally .................. 2-50
Oscillation circuit example connecting quartz-crystal externally .......................... 2-50
Structure of clock control circuit .............................................................................. 2-51
CHAPTER 3 APPENDIX
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
40 External 0 interrupt program example ......................................................................... 3-12
3.4.1 Selection of packages ............................................................................................... 3-13
3.4.2 Wiring for the RESET input pin ............................................................................... 3-13
3.4.3 Wiring for clock I/O pins ........................................................................................... 3-14
3.4.4 Wiring for CNV SS pin ............................................................................................... 3-14
3.4.5 Wiring for the VPP pin of the One Time PROM version ...................................... 3-15
3.4.6 Bypass capacitor across the V SS line and the V CC line ...................................... 3-15
3.4.7 Wiring for a large current signal line ...................................................................... 3-16
3.4.8 Wiring to a signal line where potential levels change frequently ....................... 3-16
3.4.9 V SS pattern on the underside of an oscillator ....................................................... 3-16
3.4.10 Watchdog timer by software ................................................................................... 3-17
4551 Group User’s Manual
v
List of tables
List of tabels
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Selection of system clock .................................................................................................. 1-5
1 ROM size and pages .................................................................................................... 1-13
2 RAM size ........................................................................................................................ 1-14
3 Interrupt sources ............................................................................................................ 1-15
4 Interrupt request flag, interrupt enable bit and skip instruction .............................. 1-15
5 Interrupt enable bit function ......................................................................................... 1-15
6 Interrupt control register ............................................................................................... 1-17
7 External interrupt activated condition ......................................................................... 1-18
8 External interrupt control register ................................................................................ 1-19
9 Function related timers ................................................................................................. 1-20
10 Timer control registers ................................................................................................ 1-22
11 Carrier generating circuit control register and control flag .................................... 1-26
12 Duty and maximum number of displayed pixels ..................................................... 1-28
13 LCD control registers .................................................................................................. 1-30
14 Port state at reset ....................................................................................................... 1-33
15 Functions and states retained at power down ........................................................ 1-35
16 Return source and return condition .......................................................................... 1-36
17 Pull-up control register ............................................................................................... 1-36
18 Clock control register .................................................................................................. 1-38
19 Product of built-in PROM version ............................................................................. 1-64
20 Programming adapter .................................................................................................. 1-65
CHAPTER 2 APPLICATION
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
vi
2.1.1
2.1.2
2.1.3
2.1.4
2.2.1
2.2.2
2.3.1
2.3.3
2.3.2
2.3.4
2.4.1
2.4.2
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.8.1
Pull-up control register PU0 .................................................................................... 2-4
LCD control register L2 ............................................................................................ 2-4
Clock control register MR ........................................................................................ 2-5
connections of unused pins ..................................................................................... 2-8
Interrupt control register V1 ................................................................................... 2-10
Interrupt control register I1 .................................................................................... 2-11
Interrupt control register V1 ................................................................................... 2-17
Timer control register W2 ...................................................................................... 2-18
Timer control register W1 ...................................................................................... 2-18
Timer control register W3 ...................................................................................... 2-19
Carrier wave output control register C2 .............................................................. 2-27
Carrier wave generating control flag CR ............................................................. 2-27
Duty and maximum number of displayed pixels ................................................. 2-33
LCD control register L1 .......................................................................................... 2-34
LCD control register L2 .......................................................................................... 2-35
Timer control register W3 ...................................................................................... 2-35
Frame frequency ..................................................................................................... 2-38
Functions and states retained at RAM back-up mode and the clock operating mode .... 2-42
Return source and return condition ...................................................................... 2-43
Start condition identification................................................................................... 2-43
Clock control register MR ...................................................................................... 2-44
Pull-up control register PU0 .................................................................................. 2-44
Maximum value of oscillation frequency and supply voltage ............................ 2-50
4551 Group User’s Manual
List of tables
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2
Table 3.1.2 Recommended operating conditions ....................................................................... 3-3
Table 3.1.3 Electrical characteristics ........................................................................................... 3-4
4551 Group User’s Manual
vii
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
BLOCK DIAGRAM
PERFORMANCE OVERVIEW
PIN DESCRIPTION
FUNCTIONAL BLOCK OPERATIONS
ROM ORDERING METHOD
LIST OF PRECAUTIONS
SYMBOL
LIST OF INSTRUCTION FUNCTION
INSTRUCTION CODE TABLE
MACHINE INSTRUCTIONS
CONTROL REGISTERS
BUILT-IN PROM VERSION
HARDWARE
MEMO
1-2
4551 Group User’s Manual
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
● LCD control circuit
Segment output .................................................................. 20
Common output ....................................................................4
● Carrier wave frequency switch function
System clock, system clock/2, system clock/8,
system clock/12, system clock/16, system clock/24, “H” fixed
● Timers
Timer 1 ................................ 8-bit timer with a reload register
Timer 2 ............... 14-bit timer also used as a watchdog timer
Timer LC ............................. 4-bit timer with a reload register
● Interrupt ................................................................... 3 sources
● Voltage drop detection circuit ............................................... 1
● Clock generating circuit (ceramic resonance and quartz-crystal
oscillation)
The 4551 Group is a 4-bit single-chip microcomputer designed
with CMOS technology. Its CPU is that of the 4500 series using
a simple, high-speed instruction set. The computer is equipped
with an 8-bit timer with a reload register, a 14-bit timer which is
also used as a watchdog timer, a 4-bit timer with a reload register,
a carrier wave output circuit and an LCD control circuit.
The mask ROM version and built-in PROM version of 4551 Group
are produced as shown in the table below.
FEATURES
● Minimum instruction execution time ............................ 1.5 µs
(f(XIN)=8.0 MHz, VDD=5.0 V, system clock = f(XIN)/4)
● Supply voltage
............................. 2.5 V to 5.5 V (One Time PROM version)
....................................... 2.2 V to 5.5 V (Mask ROM version)
● System clock switch function
........................................... Clock divided by 4 or not divided
Remote control transmitter
RAM size
ROM (PROM) size
(✕ 10 bits)
Product
APPLICATION
(✕ 4 bits)
280 words
Package
ROM type
48P6S-A
Mask ROM
280 words
48P6S-A
Mask ROM
280 words
M34551E8-XXXFP
(Note 2)
Notes 1: Under development (Aug. 1998)
2: Shipped after writing (shipped in blank: M34551E8FP)
48P6S-A
One Time PROM
M34551M4-XXXFP
M34551M8-XXXFP
4096 words
(Note 1)
8192 words
8192 words
SEG2
SEG1
SEG0
COM3
COM2
32
31
30
29
28
RESET
SEG3
25
SEG4
34
33
26
SEG5
35
COM1
SEG6
36
COM0
SEG7
27
SEG8
37
M34551Mx-XXXFP
38
PIN CONFIGURATION (TOP VIEW)
SEG9
39
24
D7/XCOUT
SEG10
40
23
D6/XCIN
SEG11
41
22
CNVSS
SEG12
42
21
XOUT
VSS
43
20
XIN
SEG13
44
19
VSS
SEG14
45
18
VDD
SEG15
46
17
CARR
P20 / SEG16
47
16
D5 / INT
P21 / SEG17
48
15
D4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P22 / SEG18
P23 / SEG19
P00
P01
P02
P03
P10
P11
P12
P13
D0
D1
D2
D3
M34551Mx-XXXFP
Outline 48P6S-A
4551 Group User’s Manual
1-3
1-4
Port P0
Port P1
4
4
Port P2
4551 Group User’s Manual
20
Segment output
4
Common output
LCD drive control circuit
(max. 20 segments ✕ 4 common)
Register B (4 bits)
Register A (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack registers SKs (8 levels)
Interrupt stack register SDP(1 level)
ALU(4 bits)
4500 Series
CPU core
Remote control carrier wave output
Note: PROM 8192 words ✕ 10 bits
280 words ✕ 4 bits
(LCD RAM
20 words ✕ 4 bits included)
RAM
4096 to 8192 words ✕ 10 bits
ROM (Note)
Memory
XIN –XOUT
(Main clock)
XCIN –XCOUT
(Sub-clock)
Timer 1 (8 bits)
Timer 2 (14 bits)
Timer LC (4 bits)
System clock generating circuit
Port D
8
Timers
Internal peripheral functions
I/O port
4
HARDWARE
BLOCK DIAGRAM
BLOCK DIAGRAM
HARDWARE
PERFORMANCE OVERVIEW
PERFORMANCE OVERVIEW
Parameter
Function
Number of basic instructions
92
Minimum instruction execution time 1.5 µs (f(XIN) = 8.0 MHz:system clock = f(XIN)/4: VDD = 5.0 V)
Memory sizes ROM
M34551M4 4096 words ✕ 10 bits
RAM
Input/Output
ports
Timers
Interrupt
M34551M8 8192 words ✕ 10 bits
M34551E8 8192 words ✕ 10 bits
280 words ✕ 4 bits (LCD RAM 20 words ✕ 4 bits included)
Output
P00–P03 I/O
P10–P13 I/O
P20–P23 Input
Output
CARR
D0–D7
Eight independent output ports
4-bit I/O port; each pin is equipped with a pull-up function.
4-bit I/O port; each pin is equipped with a pull-up function.
4-bit input port
Timer 1
1-bit output port (CMOS output)
8-bit timer with a reload register
Timer 2/
14-bit timer/
Watchdog timer
Timer LC
Fixed dividing frequency timer
4-bit timer with a reload register
Sources
3 (one for external and two for timer)
Nesting
Subroutine nesting
1 level
8 levels (however, only 7 levels can be used when an interrupt is used or the TABP p instruction
is executed)
LCD
Selective bias value 1/2, 1/3 bias
Selective duty value 2, 3, 4 duty
4
Common output
20
Segment output
Internal resistor for 200 kΩ ✕ 3
power supply
Device structure
CMOS silicon gate
Package
48-pin plastic molded QFP
Operating temperature range
Supply voltage
–20 °C to 70 °C
2.2 V to 5.5 V (One Time PROM version: 2.5 V to 5.5 V)
Power
2.5 mA (f(XIN) = 8.0 MHz system clock = f(XIN)/4, VDD=5 V)
at active
dissipation
at clock operating
(typical value)
at RAM back-up
27.5 µA (at main clock oscillation stop, sub-clock oscillation frequency: 32.0 kHz, Ta=25°C,
VDD=5 V)
0.1 µA (at main clock oscillation stop, sub-clock oscillation stop, Ta=25 °C, VDD=5V)
DEFINITION OF CLOCK AND CYCLE
● System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock can be selected by bits 0 and 3 of the clock
control register MR as shown in the table below.
Table Selection of system clock
Register MR
System clock (STCK)
MR3 MR0
f(XIN)
0
0
0
1
1
● Instruction clock (INSTK)
The instruction clock is the standard clock for controlling CPU.
The instruction clock is a signal derived from dividing the
system clock by 3. The one cycle of the instruction clock is
equivalent to the one machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute
the instruction.
f(XCIN)
f(XIN)/4
0
f(XCIN)/4
1
1
Note: f(XIN)/4 is selected immediately after system is released
from reset.
4551 Group User’s Manual
1-5
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
VDD
Name
Power supply
VSS
Ground
CNVSS
CNVSS
Reset input
Pin
RESET
Input/Output
Function
—
Connected to a plus power supply.
—
Connected to a 0 V power supply.
Input
I/O
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. A pull-up resistor is built-in
this pin. When the watchdog timer causes the system to be reset or the lowsupply voltage is detected, the RESET pin outputs “L” level.
XIN
Main clock input
Input
I/O pins of the main clock generating circuit. A ceramic resonator can be connected
XOUT
Main clock output
Output
D0–D4
Output port D
Output
between XIN pin and XOUT pin. A feedback resistor is built-in between them.
Each pin of port D has an independent 1-bit wide output function. The output
D5/INT
Output port D/
I/O
structure is N-channel open-drain.
Interrupt input
1-bit output port. Port D5 is also used as an INT input pin. When D5/INT pin is
used as the INT input pin, set the output latch to “1.” The output structure is Nchannel open-drain.
D6/XCIN
Output port D/
I/O
Sub-clock input
D7/XCOUT
Output port D/
Output
Sub-clock output
P00–P03
I/O port P0
I/O
Each pin of port D has an independent 1-bit output function. Ports D6 and D7 are
also used as pins XCIN and XCOUT for the sub-clock generating circuit, respectively.
When pins D6/XCIN and D7/XCOUT are used as the pins for the sub-clock generating
circuit, a 32.0 kHz quartz-crystal oscillator can be connected between XCIN pin
and XCOUT pin. A feedback resistor is built-in between them.
4-bit I/O port. It can be used as an input port when the output latch is set to “1.”
The output structure is N-channel open-drain. Every pin of the ports has a key-on
wakeup function and a pull-up function.
P10–P13
I/O port P1
I/O
4-bit I/O port. It can be used as an input port when the output latch is set to “1.”
The output structure is N-channel open-drain. Every pin of the ports has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
I/O
4-bit input port. Ports P20–P23 are also used as the segment output pins SEG16–
SEG19, respectively.
Output
Carrier wave output pin for remote control transmit. The output structure is the
for remote control
SEG0–SEG15 Segment output
Output
CMOS circuit.
LCD segment output pins.
COM0–COM3 Common output
Output
LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0–
P20/SEG16– Input port P2/
P23/SEG19 Segment output
CARR
Carrier wave output
COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty.
1-6
4551 Group User’s Manual
HARDWARE
PIN DESCRIPTION
MULTIFUNCTION
Pin
Multifunction
Pin
Multifunction
D5
INT
INT
D5
D6
XCIN
D7
P20
XCOUT
SEG16
XCIN
XCOUT
D6
D7
SEG16
P20
P21
SEG17
SEG17
P22
SEG18
SEG18
P23
SEG19
SEG19
Notes 1: Pins except above have just single function.
2: The ports D5–D7 are the output port and ports P20–P23 are the input ports.
P21
P22
P23
CONNECTIONS OF UNUSED PINS
Pin
Connection
Pin
Connect to VSS, or set the output latch to CARR
“0” and open.
SEG0–SEG15
Select ports D6 and D7 and connect to VSS, COM0–COM3
or set the output latch to “0” and open.
P00–P03
D0–D4
D5/INT
D6/XCIN
D7/XCOUT
P 2 0 / S E G 1 6 – P 2 3 / Select port P2 and connect to VSS, or select P10–P13
SEG19
the segment output function and open.
Connection
Open
Open
Open
Set the output latch to “1” and open.
Open or connect to VSS (Note)
Note: In order to connect ports P10–P13 to VSS, turn off their pull-up transistors (Pull-up control register PU0i=“0”) by software. In
order to make these pins open, turn on their pull-up transistors (register PU0 i=“1”) by software, or turn off their pull-up
transistors (register PU0i=“0”) and set the output latch to “0” (i = 0, 1, 2, or 3).
Be sure to select the key-on wakeup function and the pull-up function with every one port.
(Note in order to set the output latch to “0” and make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software.
Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away
(caused by noise).
(Note in order to connect unused pins to VSS or VDD)
• To avoid noise, connect the unused pins to VSS or VDD at the shortest distance using a thick wire.
PORT FUNCTION
Port
Port D
Pin
D0–D4, D5/INT,
D6/XCIN,
Input/
Output
Output structure
Output
N-channel open-drain
Control
bits
1
(8)
Control
Control
instructions registers
SD
MR
Remark
RD
D7/XCOUT
Port P0
P00–P03
I/O
N-channel open-drain
4
Port P1
P10–P13
(4)
I/O
N-channel open-drain
4
CLD
OP0A
Pull-up functions
IAP0
(4)
OP1A
IAP1
PU0
Key-on wakeup functions
Pull-up functions
(programmable)
Key-on wakeup functions
(programmable)
Port P2
P20/SEG16–
P23/SEG19
Input
4
IAP2
(4)
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1-7
HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS
Pull-up
transistor
Key-on wakeup
input
(Note 1)
IAP0 instruction
Register A
P00–P03
Ai
Ai
D Q
OP0A instruction
T
Pull-up
transistor
PU0i
Key-on wakeup
input
(Note 1)
IAP1 instruction
Register A
P10–P13
Ai
Ai
D Q
OP1A instruction
T
(Note 1)
LCD power supply
LCD control signal
Connected to
when selecting SEG
P20/SEG16–P23/SEG19
L2i
LCD
power
supply
IAP2 instruction
Register A
Register Y
Decoder
(Note 1)
CLD
instruction
S
SD instruction
D0–D4
R Q
RD instruction
(Note 1)
Register Y
Decoder
INT input
D5/INT
CLD instruction
S
SD instruction
R Q
RD instruction
Register Y
(Note 1)
Decoder
MR2
CLD
instruction
S
0
R Q
1
D6/XCIN
SD instruction
RD instruction
MR2
MR2
XCIN clock
Register Y
(Note 1)
Decoder
MR2
CLD
instruction
SD instruction
RD instruction
0
S
R Q
1
Notes 1:
This symbol represents a parasitic diode.
2: i represents bit 0, 1, 2 or 3.
1-8
4551 Group User’s Manual
D7/XCOUT
HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
To timer 1
TC1A instruction
CR flag
STCR instruction
S Q
SPCR instruction
R
CARRY
Register C1
(Note)
Carrier wave
output circuit
Timer LC underflow signal
CARR
W31
F/F
W30
Timer 1 underflow signal
F/F
C20
W20
LCD power supply
LCD control signal
Pch
SEG0–SEG15
LCD control signal
Nch
LCD power supply
LCD power supply
LCD control signal
Pch
COM0–COM3
LCD control signal
Pch
LCD power supply
LCD power supply
LCD control signal
LCD control signal
Nch
Nch
Note:
This symbol represents a parasitic diode.
4551 Group User’s Manual
1-9
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
FUNCTIONAL BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, AND operation, OR
operation, and bit manipulation.
(2) Register A and carry flag (CY)
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).
(M(DP))
Addition
ALU
(A)
<Result>
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
Register B TAB instruction Register A
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
B3 B2 B1 B0
Register B
A3 A2 A1 A0
TBA instruction
Register A
Fig. 3 Registers A, B and register E
ROM
TABP p instruction
Specifying address
p6 p5
PCH
p4 p3 p2 p1 p0
PCL
DR2 DR1DR0 A3 A2 A1 A0
8
4
0
Low-order 4 bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents of The contents of
register D
register A
Fig. 4 TABP p instruction execution example
1-10
4551 Group User’s Manual
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the
contents of program counter (PC) just before branching until
returning to the original routine when;
• branching to an interrupt service routine (referred to as
an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that
subroutines can be nested up to 8 levels. However, one of
stack registers is used when using an interrupt service routine
or when executing a table reference instruction. Accordingly,
be careful not to stack over when performing these operations
together. The contents of registers SKs are destroyed when
8 levels are exceeded.
The register SK nesting level is pointed automatically by 3bit stack pointer (SP). The contents of the stack pointer (SP)
can be transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an
interrupt occurs, this register (SDP) is used to temporarily
store the contents of data pointer, carry flag, skip flag, register
A, and register B just before an interrupt until returning to the
original routine. Multiple interrupts cannot be used.
Unlike the stack registers (SKs), this register (SDP) is not
used when executing the subroutine call instruction and the
table reference instruction.
Program counter (PC)
Executing the subroutine
Executing the return or
call or table reference
table reference instruction
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP)
(SK0)
(PC)
0
000116
SUB1
Subroutine
Main program
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions. When
an interrupt occurs, the contents of skip flag is stored
automatically in the interrupt stack register (SDP) and the
skip condition is retained.
Address
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC)
(SP)
(SK0)
7
Note: Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
4551 Group User’s Manual
1-11
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments
the number of instruction bytes each time an instruction is
executed. However, the value changes to a specified address
when branch instructions, subroutine call instructions, return
instructions, or the table reference instruction (TABP p) is
executed.
Program counter consists of PCH (most significant bit to bit
7) which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the
next page (Figure 7).
Make sure that the PCH does not specify after the last page
of the built-in ROM.
Program counter (PC)
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a 2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and
consists of registers Z, X, and Y. Register Z specifies a RAM
file group, register X specifies a file, and register Y specifies
a RAM digit (Figure 8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD or RD instruction (Figure 9).
Register Y (4)
Register X (4)
Register Z (2)
Specifying
RAM digit
Specifying RAM file
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D7
0
1
0
1
Register Y (4)
D6
D5
Port D output latch
Fig. 9 SD instruction execution example
1-12
4551 Group User’s Manual
D4
1
D0
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
PROGRAM MEMORY (ROM)
1 word of ROM is composed of 10 bits. ROM is separated every
128 words by the unit of page (addresses 0 to 127). Table 1
shows the ROM size and pages. Figure 10 shows the ROM map
of M34551E8.
Table 1 ROM size and pages
Product
M34551M4
M34551M8
M34551E8
ROM size
(✕ 10 bits)
4096 words
8192 words
8192 words
Pages
9 8
000016
007F16
008016
00FF16
010016
017F16
018016
7
6
5
4
3 2
1 0
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
32 (0 to 31)
64 (0 to 63)
64 (0 to 63)
A top part of page 1 (addresses 008016 to 00FF16) is reserved
for interrupt addresses (Figure 11). When an interrupt occurs,
the address (interrupt address) corresponding to each interrupt
is set in the program counter, and the instruction at the interrupt
address is executed. When using an interrupt service routine,
write the instruction generating the branch to that routine at an
interrupt address.
Page 2 (addresses 0100 16 to 017F 16) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data
areas with the TABP p instruction.
0FFF16
Page 31
1FFF16
Page 63
Fig. 10 ROM map of M34551E8
008016
9 8 7 6 5 4 3 2 1 0
External 0 interrupt address
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
00FF16
Fig. 11 Interrupt address page (addresses 008016 to 00FF16) structure
4551 Group User’s Manual
1-13
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers Z, X, and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM. Also, be sure to set a value to the data pointer
certainly when returning from power down.
RAM includes the area corresponding to the LCD. A segment is
turned on automatically when “1” is written in the bit
corresponding to the segment.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Table 2 RAM size
Product
M34551M4
RAM size
M34551M8
280 words ✕ 4 bits (1120 bits)
M34551E8
RAM 280 words ✕ 4 bits (1120 bits)
Register Z
0
Register X 0 1 2 3 ••• 6 7 •••••• 15
0
1
0
1
1
2
6
7
8
9
0
1
8
9
16
17
10
11
12
13
2
3
4
5
10
11
12
13
18
19
14
15
6
7
14
15
Register Y
2
3
4
5
280 words
Notes 1: The area marked “–” (Z = 1, X = 0 to 2, Y = 0 to 7) is not a memory area.
2: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig. 12 RAM map
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4551 Group User’s Manual
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source.
An interrupt occurs when the following 3 conditions are satisfied.
• Interrupt enable flag (INTE) = “1” (Interrupt enabled)
• Interrupt enable bit = “1” (Interrupt request occurrence enabled)
• An interrupt activated condition is satisfied
(request flag = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every
interrupt enable/disable. Interrupts are enabled when INTE
flag is set to “1” with the EI instruction and disabled when
INTE flag is cleared to “0” with the DI instruction. When any
interrupt occurs, the INTE flag is automatically cleared to “0,”
so that other interrupts are disabled until the EI instruction is
executed.
(2) Interrupt enable bits (V10–V13)
Use an interrupt enable bit of interrupt control register V1 to
select the corresponding interrupt request or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit
and skip instruction.
Table 5 shows the interrupt enable bit function.
Table 3 Interrupt sources
Interrupt
Priority
Activated condition
Interrupt name
address
level
Address 0
1
External 0 interrupt Level change of
in page 1
INT pin
2
Timer 1 underflow Address 4
Timer 1 interrupt
in page 1
3
Timer 2 interrupt
Timer 2 underflow
Address 6
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip
instruction
Request flag Enable bit Skip instruction
Interrupt name
V10
EXF0
SNZ0
External 0 interrupt
Timer 1 interrupt
T1F
V12
SNZT1
Timer 2 interrupt
T2F
V13
SNZT2
Table 5 Interrupt enable bit function
Occurrence of
Interrupt enable bit
interrupt request
1
0
Enabled
Disabled
Skip instruction
Invalid
Valid
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied,
the corresponding interrupt request flag is set to “1.” Each
interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition
is satisfied even if the interrupt is disabled by the INTE flag or
its interrupt enable bit. Once set, the interrupt request flag
retains set until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable
state is released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt
disable state is released, the interrupt priority level is as follows
shown in Table 3.
4551 Group User’s Manual
1-15
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is
as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The
address to be executed when returning to the main routine
is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is
cleared to “0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address
is executed after a branch to a sequence for storing data into
stack register is performed. Write the branch instruction to
an interrupt service routine at an interrupt address.
Use the RTI instruction to return to main routine.
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed
just before the RTI instruction, interrupts are enabled after
returning to the main routine. (Refer to Figure 13)
Main
routine
•Program counter (PC)
........................................................ Each interrupt address
•Stack register (SK)
.......... The address of main routine to be executed when returning
•Interrupt enable flag (INTE)
........................................................... 0 (Interrupt disabled)
•Interrupt request flag (only the flag for the current interrupt source)
........................................................................................... 0
•Data pointer, carry flag, registers A and B, skip flag
...... Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
INT pin
(L → H or
H → L input)
V10
Timer 1
underflow
T1F
V12
Timer 2
underflow
T2F
V13
INTE
Activated
condition
Request
flag
(state retained)
Enable
bit
Enable
flag
Interrupt
service routine
Interrupt
occurs
Interrupt
is enabled
Fig. 15 Interrupt system diagram
EI
RTI
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
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Address 0 in
page 1
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4551 Group User’s Manual
Address 4 in
page 1
Address 6 in
page 1
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(6) Interrupt control register
● Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are
assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1
instruction can be used to transfer the contents of register
V1 to register A.
Table 6 Interrupt control register
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
1
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
0
R/W
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
Note: “R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V10–V13), and interrupt request flags (EXF0, T1F,
T2F) are “1.” The interrupt actually occurs 2 to 3 machine
cycles after the cycle in which all three conditions are satisfied.
The interrupt occurs after 3 machine cycles only when the
three interrupt conditions are satisfied on execution of other
than one-cycle instructions (Refer to Figure 16).
● When an interrupt request flag is set after its interrupt is enabled
1 machine cycle
System clock (STCK)
Interrupt enable
flag (INTE)
INT pin
External
interrupt
EXF0
flag
“1”
“0”
EI instruction
execution cycle
Interrupt disabled state
Interrupt enabled state
“H”
“L”
Retaining level for 4 cycles or
more of STCK is necessary.
“1”
“0”
Interrupt activated
condition is satisfied.
Timer 1
and
Timer 2
interrupts
“1”
T1F, T2F “0”
flags
Flag cleared
Software starts from the
interrupt address.
2 to 3 machine cycles
(Note 1, 2)
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated
condition is satisfied.
Fig. 16 Interrupt sequence
4551 Group User’s Manual
1-17
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
EXTERNAL INTERRUPTS
An external interrupt request occurs when a valid waveform (=
waveform causing the external 0 interrupt) is input to an interrupt
input pin (edge detection).
The external 0 interrupt can be controlled with the interrupt control
register I1.
Table 7 External interrupt activated condition
Name
External 0 interrupt
D5/INT
Valid waveform
Valid waveform
Input pin
selection bit (I12)
0
1
Falling waveform (“H”→“L”)
Rising waveform (“L”→“H”)
I12
Falling
0
One-sided edge
detection circuit
D5/INT
EXF0
1
Rising
SNZI0
instruction
Fig. 17 External interrupt circuit structure
1-18
4551 Group User’s Manual
Skip
External 0
interrupt
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a
valid waveform is input to D5/INT pin.
The valid waveforms causing the interrupt must be retained
at their level for 4 cycles or more of the system clock (Refer
to Figure 16).
The state of EXF0 flag can be examined with the skip
instruction (SNZ0). Use the interrupt control register V1 to
select the interrupt or the skip instruction. The EXF0 flag is
cleared to “0” when an interrupt occurs or when the next
instruction is skipped with the skip instruction.
The D5/INT pin need not be selected the external interrupt
input INT function or the normal output port D5 function.
However, the EXF0 flag is set to “1” when a valid waveform
output from port D5 is input to INT pin even if it is used as an
output port D5.
(2) External interrupt control register
● Interrupt control register I1
Register I1 controls the valid waveform for the external 0
interrupt. Set the contents of this register through register A
with the TI1A instruction. The TAI1 instruction can be used
to transfer the contents of register I1 to register A.
● External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a
valid waveform is input to D5/INT pin.
The valid waveform can be selected from rising waveform or
falling waveform. An example of how to use the external 0
interrupt is as follows.
➀ Select the valid waveform with the bit 2 of register I1.
➁ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➂ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➃ Set both the external 0 interrupt enable bit (V10) and the
INTE flag to “1.”
The external 0 interrupt is now enabled. Now when a valid
waveform is input to the D5/INT pin, the EXF0 flag is set to
“1” and the external 0 interrupt occurs.
Table 8 External interrupt control register
Interrupt control register I1
I13
I12
at reset : 00002
0
1
Not used
Interrupt valid waveform for INT pin
selection bit (Note 2)
at power down : state retained
R/W
This bit has no function, but read/write is enabled.
0
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)
1
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)
I11
Not used
I10
Not used
0
1
This bit has no function, but read/write is enabled.
0
This bit has no function, but read/write is enabled.
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of D5/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of
I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after
executing at least one instruction.
4551 Group User’s Manual
1-19
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
TIMERS
The 4551 Group has the following timers.
● Programmable timer
The programmable timer has a reload register and enables
the frequency dividing ratio to be set. It is decremented from a
set value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).
● Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency
dividing ratio (n). An interrupt request flag is set to “1” every n
count of a count pulse.
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer 1 interrupt “1”
request flag
“0”
An interrupt occurs or
a skip instruction is executed.
Fig. 18 Auto-reload function
The 4551 Group timer consists of the following circuits.
• Prescaler : frequency divider
• Timer 1 : 8-bit programmable timer
• Timer 2 : 14-bit fixed dividing frequency timer
• Timer LC : 4-bit programmable timer
(Timers 1 and 2 have the interrupt function, respectively)
Prescaler, timer 1, timer 2 and timer LC can be controlled with
the timer control registers W1, W2 and W3.
Each function is described below.
Table 9 Function related timers
Circuit
Prescaler
Timer 1
Timer 2
Frequency divider
• Instruction clock (INSTCK)
8-bit programmable
• Prescaler output (ORCLK)
binary down counter
• Carrier generating circuit
output (CARRY, CARRY/2)
14-bit fixed dividing • Prescaler output (ORCLK)
frequency
Timer LC
Frequency
dividing ratio
4, 8
1 to 256
16384
• f(XCIN)
Use of output signal
Control
register
• Timer 1 and 2 count sources
W1
• Timer 1 interrupt
• Port CARR output control
W1
W2
• Timer 2 interrupt
W2
• Divider for LCD
• Watchdog timer
4-bit programmable • Bit 3 of timer 2
binary down counter
1-20
Count source
Structure
1 to 16
• System clock (STCK)
4551 Group User’s Manual
• Divider for LCD
• Carrier output
W3
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
INSTCK
Frequency
dividing circuit
(divided by 4)
MR0
XIN
XCIN
MR3
Frequency
dividing circuit
(divided by 3)
1
0
0
Prescaler
W13
W12
0
1/4
0
1
1/8
1
ORCLK
1
STCK
W11, W10
W2 0 (Note 1)
00,01
ORCLK
0
10
CARRY
1
Timer 1
interrupt
T1F
Timer 1 (8)
1
11
2
Reload register R1 (8)
(T1AB) (Note 2)
(TAB1)
Register B
Carrier wave
output control
Register A
To port CARR
W3 0 (Note 1)
W3 1
STCK
1
0
Count source
Timer LC (4)
Reload register RLC (4)
1
1
2
LCD clock
0
WRST instruction
S
WEF
W23 (Note 3)
Reset signal
Q
R
0
ORCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13
1
Count
source
Timer 2
WDF
D
System
reset
Q
T
W22, W2 1
00
01
T2F
Timer 2
interrupt
Not available
10,11
Notes 1: Count source is stopped by setting to “0.”
2: When the T1AB instruction is executed after
setting W2 0 to “1,” data is written only to
reload register R1.
3: When the contents of W2 3 changes from “0”
to “1,” the count value of timer 2 is initialized.
Fig. 19 Timers structure
4551 Group User’s Manual
1-21
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
Table 10 Timer control registers
at reset : 00002
Timer control register W1
W13
Prescaler control bit
W12
Prescaler dividing ratio selection bit
0
1
Stop (prescaler state initialized)
Operating
0
Instruction clock (INSTCK) divided by 4
1
Instruction clock (INSTCK) divided by 8
Count source
W11 W10
W11
Timer 1 count source selection bits
W10
0
0
0
1
1
Prescaler output (ORCLK)
at reset : 10002
Timer control register W2
0
1
Timer 2 count source selection bit
at power down : – – – 02
Timer 2 count value selection bits
W21
W20
Timer 1 control bit
0
0
Count source
W31
Timer LC count source selection bit
W30
Timer LC control bit
14
0
Underflow occur every 2 count
1
1
0
Underflow occur every 213 count
Not available
1
1
Not available
Stop (timer 1 state retained)
Operating
0
1
at reset : 002
Timer control register W3
at power down : state retained
R/W
0
Bit 3 of timer 2 is output (timer 2 count source divided by 16)
1
0
System clock (STCK)
Stop (timer LC state retained)
1
Operating
Note: “R” represents read enabled, and “W” represents write enabled.
“–” represents state retained.
(1) Timer control registers
● Timer control register W1
Register W1 controls the count source of timer 1, the
frequency dividing ratio and count operation of prescaler.
Set the contents of this register through register A with
the TW1A instruction. The TAW1 instruction can be used
to transfer the contents of register W1 to register A.
● Timer control register W2
Register W2 controls the count operation of timer 1 and
count operation and count source of timer 2. Set the
contents of this register through register A with the TW2A
instruction. The TAW2 instruction can be used to transfer
the contents of register W2 to register A.
● Timer control register W3
Register W3 controls the count operation and count source
of timer LC. Set the contents of this register through
register A with the TW3A instruction. The TAW3 instruction
can be used to transfer the contents of register W3 to
register A.
1-22
R/W
f(XCIN)
Prescaler output (ORCLK)
W22 W21
W22
R/W
0 Carrier output (CARRY)
1 Carrier output divided by 2 (CARRY/2)
1
W23
at power down : 00002
4551 Group User’s Manual
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(2) Precautions
Note the following for the use of timers.
● Prescaler
Stop the prescaler operation to change its frequency
dividing ratio.
● Count source
Stop timer 1 or timer LC counting to change its count
source. When timer 2 count source changes from f(XCIN)
to ORCLK (W23 = “0” → W23 = “1”), the count value of
timer 2 is initialized. However, when timer 2 count source
changes from ORCLK to f(XCIN) (W23 = “1” → W23 = “0”)
or the same count source is set again (W23 = “0” → W23
= “0” or W23 = “1” → W23 = “1”), the count value of timer
2 is not initialized.
● Timer 2
Timer 2 has the watchdog timer function (WDT). When
timer 2 is used as the WDT, note that the processing to
initialize the count value and the execution of the WRST
instruction.
● Reading the count value
Stop the prescaler and then execute the TAB1 instruction
to read timer 1 data.
● Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio
can be selected. The count source of prescaler is the
instruction clock (INSTCK).
Use the bit 2 of register W1 to select the prescaler dividing
ratio and the bit 3 to start and stop its operation. When the bit
3 of register W1 is cleared to “0,” prescaler is initialized, and
the output signal (ORCLK) stops.
(4) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1). When timer 1 stops, data can be set
simultaneously in timer 1 and the reload register (R1) with
the T1AB instruction. When timer 1 is operating, data can be
set only in the reload register (R1) with the T1AB instruction.
When setting the next count data to reload register R1 while
timer 1 is operating, be sure to set data before timer 1
underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1,
➁ select the count source with bits 0 and 1 of register W1,
➂ set the bit 0 of register W2 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 interrupt request flag (T1F) is set to “1,” new data is
loaded from reload register R1, and count continues (autoreload function).
When a value set in reload register R1 is n, timer 1 divides
the count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 1 to registers A and B. Stop
counting and then execute the TAB1 instruction to read its
data.
(5) Timer 2 (interrupt function)
Timer 2 is a 14-bit binary down counter.
Timer 2 starts counting after the following process;
➀ select the count source with the bit 3 of register W2, and
➁ the clock as a count source is supplied.
Timer 2 stops counting and its count value is retained when
supply of a clock as a count source stops. Timer 2 is initialized
at reset and when the count source changes from f(XCIN)
(W23=“0”) to ORCLK (W23=“1”).
The count value to set the timer 2 interrupt request flag (T2F)
to “1” can be selected from every 8192 count or every 16384
count with bits 1 and 2 of register W2. The count source signal
divided by 16 is output from timer 2.
Timer 2 can be used as a counter for clock in the clock
operating mode (POF instruction executed).
(6) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC
reload register (RLC). Data can be set simultaneously in timer
LC and the reload register (RLC) with the TLCA instruction.
Timer LC starts counting after the following process;
➀ set data in timer LC,
➁ select the count source with the bit 1 of register W3,
➂ set the bit 0 of register W3 to “1.”
Timer LC is the timer for LCD clock generating. Also, it can
be used as the multi-carrier generator by setting the bit 1 of
register W3 to “1” and selecting the system clock (STCK) as
a count source. When the multi-carrier generator is selected,
the waveform which is the timer LC underflow signal divided
by 2 can be output as a carrier wave from port CARR. At this
time, stop the carrier generating circuit and LCD control circuit.
When the multi-carrier generator (duty ratio: 1/2 fixed) is used,
the enable/stop of the carrier wave output from port CARR
can be set by the stop of timer LC or the carrier wave output
auto-control function by timer 1.
(7) Timer interrupt request flags (T1F and T2F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with
the skip instructions (SNZT1 and SNZT2).
Use the interrupt control register V1 to select an interrupt or
a skip instruction.
An interrupt request flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with a skip
instruction.
4551 Group User’s Manual
1-23
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a
program runs wild. Watchdog timer consists of timer 2, watchdog
timer enable flag (WEF), and watchdog timer flag (WDF).
When the WRST instruction is executed after system is released
from reset, the WEF flag is set to “1.” At this time, the watchdog
timer starts operating. When the WEF flag is set to “1,” it cannot
be cleared to “0” until system reset is performed. Also, when the
WRST instruction is not executed once, watchdog timer does
not operate because the WEF flag retains “0.”
When the watchdog timer is operating, the WDF flag is set to “1”
every time the bit 12 of timer 2 is cleared from “1” to “0.” This
means that count is performed 8192 times. When the bit 12 of
timer 2 is cleared from “1” to “0” while the WDF flag is set to “1,”
the internal reset signal is generated and system reset is
performed.
The WDF flag can be cleared to “0” with the WRST instruction.
In the RAM back-up mode, though timer 2 count operation stops,
its count value is retained and the WDF flag is initialized.
In the clock operating mode, timer 2 count operation is continued
and the WDF flag is initialized.
When using the watchdog timer, execute the WRST instruction
at a certain cycle which consists of timer 2’s 8191 counts or less
to keep the microcomputer operation normal.
3FFF16
Value of timer 2
0000 16
WEF flag
“1”
“0”
WDF flag
“1”
“0”
Internal reset signal
“H”
“L”
System reset
WRST instruction WRST instruction
execution
execution
Fig. 20 Watchdog timer function
The contents of the WDF flag are initialized in the RAM back-up
mode.
If the WDF flag is set to “1” at the same time that the
microcomputer enters the RAM back-up mode, system reset may
be performed.
When using the watchdog timer and the RAM back-up mode,
initialize the WDF flag with the WRST instruction just before the
microcomputer enters the RAM back-up mode (refer to Figure
21).
•
••
•
•
•
WRST
; Clear WDF flag
EPOF
; POF instruction execution enabled
POF2
Oscillation stop (RAM back-up mode)
Fig. 21 Program example to enter the RAM back-up mode
when using the watchdog timer
1-24
4551 Group User’s Manual
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
CARRIER GENERATING CIRCUIT
The 4551 Group has a carrier generating circuit that generates
the transfer waveform by dividing the system clock (STCK) for
each remote control carrier wave. Each carrier waveform can be
output by setting the carrier wave selection register (C1).
Also, timer 1 can auto-control the carrier wave output from port
CARR by setting the carrier wave output control register (C2).
Carrier wave selection register C1
Register C1
Setting value
STCR instruction
(at reset: 0 1 1 1 2, at power down: 0 1 1 1 2, W)
Output waveform
0
0
Carrier wave
Frequency
C13 C12 C11 C10
0
SPCR instruction
Duty
0
“H”
“L”
1/2
1/4
1/3
STCK/24
0
0
0
1
“H”
“L”
0
0
1
0
“H”
“L”
STCK/16
0
0
1
1
“H”
“L”
0
1
0
0
“H”
“L”
0
1
0
1
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
1/2
STCK/2
“H”
“L”
1/2
No carrier wave
No available
“H”
“L”
“L” fixed
“H”
“L”
1/3
STCK/12
1
0
0
1
“H”
“L”
1/2
1
0
1
0
“H”
“L”
1/4
STCK/8
1
0
1
1
“H”
“L”
1
1
0
0
“H”
“L”
1/2
STCK
1/2
Note:“W” represents write enabled.
Fig. 22 Carrier wave selection register
4551 Group User’s Manual
1-25
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
Table 11 Carrier generating circuit control register and control flag
Carrier wave output control register C2
C20
Carrier wave output auto-control bit
at reset : 02
CR
Carrier wave generating control
W
Auto-control output by timer 1 is invalid
Auto-control output by timer 1 is valid
0
1
Carrier wave generating control flag CR
at power down : 02
at reset : 02
0
1
at power down : 02
W
Carrier wave generating stop (SPCR instruction)
Carrier wave generating start (STCR instruction)
Note: “W” represents write enabled.
(1) Carrier generating circuit related registers
● Carrier wave selection register C1
Each carrier waveform can be selected by setting the register
C1. Set the contents of this register through register A with
the TC1A instruction.
● Carrier wave output control register C2
Timer 1 can auto-control the output enable interval and the
output disable interval of the carrier wave output from port
CARR by setting the register C2. Set the contents of this
register through register A with the TC2A instruction.
The setting of the output enable/disable interval is described
below.
➀ Validate the carrier wave output auto-control function
(C20=“1”).
➁ Select the carrier wave or the carrier wave divided by 2
as the timer 1 count source.
➂ Set the count value (the output enable interval of carrier
wave from port CARR) to timer 1.
➃ Operate timer 1 (W20=“1”).
➄ Operate the carrier generating circuit (STCR instruction
executed).
➅ Set the next count value (the output disable interval of
carrier wave from port CARR) to reload register R1 before
timer 1 underflow occurs.
The carrier wave is output from port CARR until the first timer
1 underflow occurs. The output of the carrier wave from port
CARR is disabled and the next count value is loaded from
reload register R1 to timer 1 by the first timer 1 underflow.
Then, the output of carrier wave is disabled until the second
timer 1 underflow. Also, the next enable interval of the carrier
wave output can be set by setting the third count value to
timer 1 reload register before the second timer 1 underflow
occurs. If the carrier wave output auto-control function is
invalidated (C20=“0”) while the carrier wave output is autocontrolled, the output of port CARR retains the state when
the auto-control is invalidated regardless of timer 1 underflow.
This state can be terminated by timer 1 stop (W20=“0”). When
the carrier wave output auto-control function is validated
(C20=“1”) again after it is invalidated (C20=“0”), the autocontrol of carrier wave output is started again when the next
timer 1 underflow occurs.
1-26
(2) Carrier wave generating control flag (CR)
The CR flag is used to control the carrier wave generating
operation of the carrier generating circuit. The CR flag is “1”
and the carrier wave generating is started by executing the
STCR instruction. The CR flag is “0” and the carrier wave
generating is stopped by executing the SPCR instruction. The
CR flag is “0” at system reset.
(3) Note on the carrier generating circuit stop
In order to stop the carrier wave which has the cycle longer
than that of the instruction clock with the SPCR instruction,
stop it at the point when the carrier wave outputs “L” level in
the SPCR instruction execution cycle.
If this condition is not satisfied, the last “H” output interval of
carrier wave is shortened.
(4) Notes when using the carrier wave output auto-control function
● Execute the STCR instruction after setting the timer 1 and
register C2 in order to start the carrier generating circuit
operation.
● Stop the timer 1 (W2 0 =“0”) after stopping the carrier
generating circuit (SPCR instruction executed) while the
carrier wave output is disabled in order to stop the carrier
wave output auto-control operation.
● If the carrier wave output auto-control function is invalidated
(C20=“0”) while the carrier wave output is auto-controlled,
the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow. This
state can be terminated by timer 1 stop (W20=“0”).
When the carrier wave output auto-control function is
validated (C2 0=“1”) again after it is invalidated (C20=“0”),
the auto-control of carrier wave output is started again when
the next timer 1 underflow occurs. However, when the carrier
wave output auto-control bit is changed during timer 1
underflow, the error-operation may occur.
● Use the carrier wave or the carrier wave divided by 2 as the
timer 1 count source when the carrier wave output autocontrol function is selected.
If the ORCLK is used as the count source, a hazard may
occur in port CARR output because ORCLK is not
synchronized with the carrier wave.
● When “no carrier wave” is selected with register C1
((C13C12C11C10 ) = (0101), (1101)), the enable/disable of
the carrier wave output cannot be controlled by the carrier
wave output auto-control function.
4551 Group User’s Manual
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
Timer 1 start
Timer 1
underflow
“1”
“0”
Port CARR
output
“H”
“L”
a
b
c
d
(C20)←1
Set the interval Set the interval “b” to
“a” to timer 1. reload register R1.
Set the interval “c” to
reload register R1.
Set the interval “d” to
reload register R1.
Carrier wave output start
Timer 1 underflow
“1”
“0”
Port CARR output
“H”
“L”
Register C20
“1”
“0”
(C20)←0
Carrier wave output start
(C20)←1 (C20)←0
(C20)←1
Fig. 23 Carrier wave output auto-control by timer 1
4551 Group User’s Manual
1-27
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
LCD FUNCTION
The 4551 Group has an LCD (Liquid Crystal Display) controller/
driver. When data are set in timer control registers (W2, W3),
timer LC, LCD control registers (L1, L2), and LCD RAM, the LCD
controller/driver automatically reads the display data and controls
the LCD display by setting duty and bias.
4 common signal output pins and 20 segment signal output pins
can be used to drive the LCD. By using these pins, up to 80
segments (when 1/4 duty and 1/3 bias are selected) can be
controlled to display. When the required number of segment pins
is 19 or less, pins SEG16–SEG19 (4) can be used as input ports
P20–P23.
The LCD clock is determined by the timer 2 count source
selection bit (W23), timer LC control bit (W30), and timer LC.
Accordingly, the frequency (F) of the LCD clock is obtained
by the following formula. Numbers (➀ to ➄) shown below the
formula correspond to numbers in Figure 24, respectively.
● When using the prescaler output (ORCLK) as timer 2 count
source (W23=“1”)
F = ORCLK ✕
➀
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data
on the LCD. Use bits 0 and 1 of LCD control register (L1) to
select the proper display method for the LCD panel being
used.
COM0, COM1 (Note)
COM0–COM2 (Note)
40 segments
60 segments
1/4
80 segments
Note: Leave unused COM pins open.
➀
W23
F = f(XCIN) ✕
✕
1
➀
1
16
LC + 1
➁➂
➃
0
Frame frequency =
Frame period =
n
F
F
n
➄
✕
1
2
➄
[LC: 0 to 15]
➂
➁
STCK
1/16
W31
1
(Hz)
(s)
F: LCD clock frequency
1/n: Duty
COM0–COM3
(Note)
W30
0
1
➃
Timer LC
0
1
Note: Count source is stopped by clearing to “0.”
Fig. 24 LCD clock control circuit structure
1-28
➃
1
2
The frame frequency and frame period for each display
method can be obtained by the following formula:
Table 12 Duty and maximum number of displayed pixels
(2) LCD clock control
Duty Maximum number of displayed pixels Used COM pins
XCIN
ORCLK
➁➂
✕
1
LC + 1
● When using the f(XCIN) as timer 2 count source (W23=“0”)
● 1/2 duty, 1/2 bias
● 1/3 duty, 1/3 bias
● 1/4 duty, 1/3 bias
1/2
1/3
✕
1
16
4551 Group User’s Manual
➄
1/2
LCD clock
4551 Group User’s Manual
L13 L12 L11 L10
LCD on/off
control
1/2, 1/3, 1/4
Counter
Decoder
Common driver
COM0 COM2
COM1
COM3
LCD clock
(from timer block)
Bias control
Control
signal
Multiplexer
(Note)
VLC3
Selector
...
...
Register A
RAM
SEG15
RAM
Selector
Segment
driver
.................
–
Segment
...
driver
SEG0
– P23/SEG19
RAM
Selector
Segment
driver
Multiplexer
.................
P20/SEG16
Note: VLC3=VDD.
L23 L22 L21 L20
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
Fig. 25 LCD controller/driver structure
1-29
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(4) LCD drive waveform
When “1” is written to a bit in the LCD RAM data, the voltage
difference between common pin and segment pin which
correspond to the bit automatically becomes lVLC3l and the
display pixel at the cross section turns on.
When returning from reset, and in the RAM back-up mode, a
display pixel turns off because every segment output pin and
common output pin becomes VLC3 level (=VDD).
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel
corresponding to the bit is automatically displayed.
Z
X
Bit
Y
1
1
0
8
9
10
11
12
13
14
15
COM
3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM3
2
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM2
Note: The area marked “
1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM1
0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM0
3
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM3
2
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM2
1
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM1
0
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM0
3
SEG16
SEG17
SEG18
SEG19
2
2
1
SEG16 SEG16
SEG17 SEG17
SEG18 SEG18
SEG19 SEG19
0
SEG16
SEG17
SEG18
SEG19
COM3 COM2 COM1 COM0
” is not the LCD display RAM.
Fig. 26 LCD RAM map
Table 13 LCD control registers
at reset : 00002
LCD control register L1
L13
Not used
L12
LCD on/off bit
0
Off
On
1
0
LCD duty and bias selection bits
0
1
1
L10
Duty
L23
P23/SEG19 pin function switch bit
L22
P22/SEG18 pin function switch bit
L21
P21/SEG17 pin function switch bit
L20
P20/SEG16 pin function switch bit
1/2
1/2
0
1/3
1/3
1
1/4
1/3
Not available
0
SEG19
1
P23
0
1
SEG18
P22
0
SEG17
1
0
P21
SEG16
1
P20
Note: “R” represents read enabled, and “W” represents write enabled.
1-30
Bias
0
1
at reset : 11112
LCD control register L2
R/W
This bit has no function, but read/write is enabled
1
0
L11 L10
L11
at power down : state retained
4551 Group User’s Manual
at power down : state retained
W
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 8) in RAM.
1 frame (2/F)
M (1, 2, 8)
COM0
0 (bit 0)
COM1
1
X
1/F
Voltage level
VLC3
VLC1=VLC2
COM1
VSS
COM0
X (bit 3)
VLC3
VLC1=VLC2
VSS
SEG16
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 8) in RAM.
1 frame (3/F)
M (1, 2, 8)
COM0
1/F
Voltage level
1 (bit 0)
COM1
0
COM2
1
X (bit 3)
VLC3
VLC2
VLC1
VSS
COM2
COM1
SEG16
COM0
SEG16
COM2
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
ON
VLC3
VLC2
VLC1
VSS
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 8) in RAM.
1 frame (4/F)
M (1, 2, 8)
COM0
COM1
COM2
COM3
1/F
Voltage level
0 (bit 0)
1
VLC3
VLC2
VLC1
VSS
COM3
0
1 (bit 3)
COM2
SEG16
COM1
COM0
F: LCD clock frequency
X: Set an arbitrary value.
(These bits are not
related to set the drive
waveform at each duty.)
SEG16
COM3
SEG16
COM2
SEG16
ON
OFF
COM1
SEG16
ON
COM0
SEG16
VLC3
VLC2
VLC1
VSS
OFF
Fig. 27 LCD controller/driver structure
4551 Group User’s Manual
1-31
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
RESET FUNCTION
____________
System reset is performed by applying “L” level to RESET pin
for 1 machine cycle or more when the following condition is
satisfied;
• the value of supply voltage is the minimum value or more of
the recommended operating conditions.
____________
Then when “H” level is applied to RESET pin, software starts
from address 0 in page 0.
f(XIN)
RESET
“H”
“L”
(Note)
f(XIN) is counted
10757 to 10786 times
Software start
(Address 0 in page 0)
Note: The number of clock cycles depends on the internal state of
the microcomputer when reset is performed.
Fig. 28 Reset release timing
Reset input
=
1machine cycle or more
f(XIN) is counted
10757 to 10786 times
0.85VDD
Software start
(Address 0 in page 0)
RESET
0.3VDD
Note: Keep the value of supply voltage the minimum value or more
of the recommended operating conditions.
(Note)
Fig. 29 RESET pin input waveform and reset operation
(1) Power-on reset
Reset can be automatically performed at power on (poweron reset) by the built-in power-on reset circuit. When the builtin power-on reset circuit is used, the time for the supply voltage
to reach the minimum operating voltage must be set to 100
µ s or less. If the rising time exceeds 100 µ s, connect a
capacitor between the RESET pin and VSS at the shortest
distance, and input “L” level to RESET pin until the value of
supply voltage reaches the minimum operating voltage.
VDD
Pull-up
transistor
RESET
pin
Internal reset
signal
Power-on
reset circuit
Voltage drop detection circuit
(Note)
This symbol represents a parasitic
diode.
Applied potential to RESET pin must
Power-on
be VDD or less.
Fig. 30 Power-on reset circuit example
1-32
Reset state
Watchdog timer
output
WEF
Note:
Power-on reset circuit
output voltage
4551 Group User’s Manual
Internal reset signal
Reset released
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(2) Internal state at reset
Table 14 shows port state at reset, and Figure 31 shows
internal state at reset (they are retained after system is
released from reset).
The contents of timers, registers, flags and RAM except those
shown in Figure 31 are undefined, so set the initial values to
them.
Table 14 Port state at reset
Name
D0–D4, D5/INT
D6/XCIN, D7/XCOUT
P00–P03
P10–P13
P20/SEG16–P23/SEG19
SEG0–SEG15
COM0–COM3
CARR
Function
State
D0–D4, D5
D 6 , D7
High impedance (Note 1)
P00–P03
“H” (VDD) level (Note 1)
P10–P13
P20–P23
(Notes 1, 2)
High impedance
SEG0–SEG15
VLC3 (VDD) level
COM0–COM3
CARR
“L” (VSS) level
Notes 1: Output latch is set to “1.”
2: The pull-up transistor is turned off.
• Program counter (PC) ............................................................................................
0 0 0 0 0 0
0
0
0
0
0
0
0
0
Address 0 in page 0 is set to program counter.
0
• Interrupt enable flag (INTE) ...................................................................................
• Power down flag (P) ...............................................................................................
0
(Interrupt disabled)
• External 0 interrupt request flag (EXF0) ................................................................
0
0 0 0 0
• Interrupt control register V1 ...................................................................................
• Interrupt control register I1 ....................................................................................
0 0 0 0
(Interrupt disabled)
• Timer 1 interrupt request flag (T1F) ......................................................................0
• Timer 2 interrupt request flag (T2F) ......................................................................0
• Watchdog timer flag (WDF) ...................................................................................
0
0
• Watchdog timer enable flag (WEF) .......................................................................
0 0 0 0
• Timer control register W1 ......................................................................................
• Timer control register W2 ......................................................................................
0 0 0 0
0 0
• Timer control register W3 ......................................................................................
(Prescaler stopped)
(Timer 1 stopped)
(Timer LC stopped)
1 0 0 0
• Clock control register MR ......................................................................................
• Carrier wave selection register C1 ........................................................................
0 1 1 1
• Carrier wave output control register C2 .................................................................0
0
• Carrier wave generating control flag CR ...............................................................
• LCD control register L1 ..........................................................................................
0 0 0 0
1 1 1 1
• LCD control register L2 ..........................................................................................
(Carrier wave output disabled)
(LCD off)
(Port P2 selected)
0 0 0 0
• Pull-up control register PU0 ...................................................................................
• General-purpose register V2 .................................................................................
0 0 0 0
0
• Carry flag (CY) .......................................................................................................
0 0 0 0
• Register A ..............................................................................................................
• Register B ..............................................................................................................
0 0 0 0
✕ ✕ ✕
• Register D ..............................................................................................................
• Register E ..............................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Data pointer X ........................................................................................................
0 0 0 0
0 0 0 0
• Data pointer Y ........................................................................................................
✕ ✕
• Data pointer Z ........................................................................................................
• Stack pointer (SP) ..................................................................................................
1 1 1
“✕” represents undefined.
Fig. 31 Internal state at reset
4551 Group User’s Manual
1-33
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply
voltage drops below a set value.
Pull-up transistor
Internal reset signal
RESET pin
Power-on
reset circuit
Voltage drop detection circuit
Watchdog timer output
WEF
Fig. 32 Voltage drop detection reset circuit
VDD
Reset voltage
The microcomputer starts operation
after the f(XIN) is counted 10757 to
10786 times.
Internal reset
signal
Fig. 33 Voltage drop detection circuit operation waveform
1-34
4551 Group User’s Manual
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
POWER DOWN FUNCTION
Table 15 Functions and states retained at power down
The 4551 Group has 2-type power down functions.
Function
● Clock operating mode ................................... POF instruction
● RAM back-up mode .................................... POF2 instruction
Power down is performed by executing each instruction. Above
power down functions are different from reset in start conditions.
Table 15 shows the function and states retained at power down.
Figure 36 shows the state transition.
operating back-up
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Clock control register MR
● Return from power down state ............. Warm start condition
● Return from reset state ........................... Cold start condition
Timer control register W1
(1) Clock operating mode
The following functions and states are retained.
● RAM
● Reset circuit
● XCIN–XCOUT oscillation
● LCD display
● Timer 2
Interrupt control register I1
Timer control registers W2, W3
Interrupt control register V1
Carrier wave control registers and flag (C1, C2, CR)
LCD display function
LCD control registers L1, L2
Timer LC
Timer 1 function
Timer 2 function
(2) RAM back-up mode
The following functions and states are retained.
● RAM
● Reset circuit
Unlike the clock operating mode, all oscillations stop in the
RAM back-up mode.
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Watchdog timer flag (WDF)
Watchdog timer enable flag (WEF)
Interrupt enable flag (INTE)
(3) Warm start condition
The system returns from the power down state when;
● the external wakeup signal is input or the timer 2 underflow
occurs
in the clock operating mode, or when;
● the external wakeup signal is input
in the RAM back-up mode.
In either case, the CPU starts executing the software from
address 0 in page 0. In this case, the P flag is “1.”
Power down
Clock
RAM
✕
✕
O
O
O
O
✕
O
✕
O
✕
O
O
O
✕
O
✕
✕
O
O
O
O
✕
O
✕
O
✕
(Note 3)
O
(Note 4)
✕
O
✕
✕
O
O
✕
O
✕
✕
✕
✕
General-purpose register V2
Notes 1: “O” represents that the function can be retained, and
“✕” represents that the function is initialized.
Registers and flags other than the above are undefined
at power down, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack
register and is initialized to “1112” at power down.
3: LCD is turned off.
4: The state of the timer is undefined.
(4) Cold start condition
The CPU starts executing the software from address 0 in
page 0 when;
● reset pulse is input to RESET pin,
● reset by watchdog timer is performed, or
● reset by the voltage drop detection circuit is performed.
In this case, the P flag is “0.”
4551 Group User’s Manual
1-35
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(5) Identification of the start condition
Warm start or cold start can be identified by examining the
state of the power down flag (P) with the SNZP instruction.
The warm start condition (timer 2 or external wakeup signal)
can be identified by examining the state of T2F flag.
POF instruction
or
POF2 instruction
Reset input
Software start
Powerdown flag P
S
Q
Yes
P = “1”
?
No
R
Yes
T2F = “1”
?
Cold start
● Set source
POF or POF2 instruction executed
● Clear source
Reset input
No
Return by timer 2
underflow
Return by external
wakeup signal
Fig. 34 Set source and clear source of the P flag
Fig. 35 Start condition identified example using the SNZP instruction
(6) Return signal
An external wakeup signal or timer 2 interrupt request flag is
used to return from the clock operating mode.
An external wakeup signal is used to return from the RAM
back-up mode because the oscillation is stopped. Table 16
shows the return condition for each return source.
(7) Port P1 control register
● Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P1 pull-up
transistor and the ON/OFF of the key-on wakeup function.
Set the contents of this register through register A with
the TPU0A instruction. In addition, the TAPU0 instruction
can be used to transfer the contents of register PU0 to
register A.
Table 16 Return source and return condition
External wakeup
signal
Return source
Return condition
Remarks
Ports P0, P1 Returns by an external falling Port P0 shares the falling edge detection circuit with port P1. The key-on
edge input (“H”→“L”).
wakeup function of port P0 is always valid. The only key-on wakeup
function of the port P1 bit of which the pull-up transistor is turned on is
valid. Set all the port using the key-on wakeup function to “H” level before
going into the power down state.
Timer 2 interrupt Returns by timer 2 underflow and The timer 2 interrupt request flag (T2F) can be used only when system
setting T2F to “1.”
returns from the clock operating mode (POF instruction execution).
request flag
However, if the POF and POF2 instructions are executed while the T2F =
“1”, its operation is recognized as the return condition and system returns
from the clock operating mode.
Note: P1 pin has the pull-up transistor which can be turned on/off by software.
Table 17 Pull-up control register
Pull-up control register PU0
PU03
PU02
PU01
Port P13 pull-up transistor
control bit
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
at reset : 00002
at power down : state retained
0
1
Pull-up transistor OFF, no key-on wakeup
0
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
1
0
1
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
0
Pull-up transistor ON, key-on wakeup
control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
PU00
1-36
4551 Group User’s Manual
R/W
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
(8) State transition
State transition is described using Figure 36.
Reset
POF execution
C,G
Return input 1, 2
C,G
POF execution
D,H
Return input 1, 2
D,H
(Stabilizing time c )
(Note 1)
(Note 2)
M
1
MRR0 ←
0← 0
R
←
3
M R0
← 0
M
1
1
MR
3← 0
M 0←
MR 3 ← (Note 2) R3
← 1
MR
0
C
System clock;
f(XCIN)/4
MR=(11012)
d)
MR3 ← 0
f(XIN):Oscillation
f(XCIN):Oscillation
MR1 ← 1
(Stabilizing time c )
(Note 1)
MR3 ← 1
MR3 ← 0
tim
e
1
c)
1← 1
MR 3 ←
MR
D
f(XIN):Stop
f(XCIN):Oscillation
System clock;
f(XCIN)/4
MR=(11112)
0
1← 0
R
←
M R3 time
M ing
iliz
ab
(St
M
MR R1 ←
3
← 1
0
MR3 ← 1
MR3 ← 0
MR2 ← 0
System clock;
f(XIN)
MR=(01002)
Return input 1
A,E
(Stabilizing time a )
RAM
back-up
mode
f(XIN):Stop
f(XCIN):Stop
POF2 execution
B,F
Return input 1
B,F
(Stabilizing time a )
POF2 execution
G
System clock;
f(XCIN)
MR=(01012)
c)
A,E
(Note 2)
f(XIN):Oscillation
f(XCIN):Oscillation
MR3 ← 1
M
MRR1 ←
(S
3
tab
← 0
iliz
ing
1
f(XIN):Oscillation
f(XCIN):Oscillation
(Stabilizing time c )
System clock;
f(XIN)/4
MR=(11002)
(
MR0 ← 0
f(XIN):Stop
f(XCIN) :
Oscillation
f(XIN):Oscillation
f(XCIN):Oscillation
F
MR0 ← 1
(Stabilizing time a )
Clock
operating
mode
im
e
K
System clock;
f(XIN)
MR=(00002)
MR1 ← 1
Return input 1, 2
B,F
gt
ab
St
(Stabilizing time c )
J
B,F
0
M
MRR2 ←
2← 0
R
←
2
← 0 MMR3
1
(Note 2)
M
1
MRR3 ←
3
2← 1
)
← 1
MRR3 ← ime d (Stab
0
t
i
l
izi
M
n
ing
iliz
B
MR0 ← 1
POF execution
MR2 ← 0
MR2 ← 1
f(XCIN):Stop
MR3 ← 0
MR1 ← 0
(Note 2)
POF2 execution
f(XIN):Oscillation
f(XCIN):Stop
MR2 ← 1
System clock;
f(XIN)/4
MR=(10002)
MR0 ← 0
(Stabilizing time a ) f(XIN):Stop
E
MR3 ← 1
MR1 ← 0
Clock
operating
mode
A
f(XIN):Oscillation
f(XCIN):Stop
(Stabilizing time d )
Return input 1
A,E
I
(Stabilizing time d )
POF execution
A,E
H
f(XIN):Stop
f(XCIN):Oscillation
System clock;
f(XCIN)
MR=(01112)
C,G
Return input 1
C,G
(Stabilizing time b )
POF2 execution
D,H
Return input 1
D,H
(Stabilizing time b )
Stabilizing time a : An interval required to stabilize the f(XIN) oscillation is automatically generated by hardware.
Stabilizing time b : An interval required to stabilize the f(XCIN) oscillation is automatically generated by hardware.
Stabilizing time c : Generate an interval required to stabilize the f(XIN) oscillation in state C or G by software at the
transition D→C, D→G, H→C, H→G, J→C, or J→G.
Stabilizing time d : Generate an interval required to stabilize the f(XCIN) oscillation in state B, F by software at the
transition A→B, E→F, A→F, or E→B.
Return input 1: External wakeup signal (P00–P03, P10–P13)
Return input 2: Timer 2 interrupt request flag
Notes 1. MR3=“1”→The microcomputer starts its operation after counting f(XCIN) clock signal 59 to 70 times.
MR3=“0”→The microcomputer starts its operation after counting f(XCIN) clock signal 32 to 43 times.
2. When the following 2 conditions are satisfied, the transition A→E, B→F, A→F, C→F, G→F represented
by “
” can be executed.
(1) VDD = 2.2 V to 5.5 V (One Time PROM version: VDD = 2.5 V to 5.5 V), f(XIN) ≤ 1.0 MHz
(2) VDD = 4.5 V to 5.5 V, f(XIN) ≤ 2.0 MHz
Fig. 36 State transition
4551 Group User’s Manual
1-37
HARDWARE
FUNCTIONAL BLOCK OPERATIONS
CLOCK CONTROL
The clock control circuit consists of the following circuits.
● Clock generating circuit
● Control circuit to stop the clock oscillation
● System clock (STCK) selection circuit
● Instruction clock (INSTCK) generating circuit
● Control circuit to return from the power down state
MR0
XIN
XOUT
OSC
Multiplexer
Frequency
dividing
circuit
(divided by 4)
MR3
Internal clock
1
0
generating circuit
INSTCK
(divided by 3)
STCK
MR1
XCIN
OSC
XCOUT
POF instruction
R
Q
S
POF2 instruction
R
S
RESET
Q
T2F flag
Falling detected
Ports P0, P1
Fig. 37 Clock control circuit structure
(1) Clock control register
● Clock control register MR
Register MR controls the system clock. Set the contents
of this register through register A with the TMRA
instruction. In addition, the TAMR instruction can be used
to transfer the contents of register MR to register A.
Table 18 Clock control register
Clock control register MR
at reset : 10002
0
MR3
System clock (STCK) selection bit
1
MR2
f(XCIN) oscillation circuit control bit
MR1
f(XIN) oscillation circuit control bit
0
1
0
1
MR0=0 f(XIN)
MR0=1 f(XCIN)
MR0=0 f(XIN)/4
MR0=1 f(XCIN)/4
f(XCIN) oscillation stop, ports D6 and D7 selected
f(XCIN) oscillation enabled, ports D6 and D7 not selected
Oscillation enabled
Oscillation stop
f(XIN)
0
f(XCIN)
1
Note: “R” represents read enabled, and “W” represents write enabled.
MR0
1-38
at power down : state retained
Clock selection bit
4551 Group User’s Manual
R/W
HARDWARE
FUNCTIONAL BLOCK OPERATIONS/ROM ORDERING METHOD
(2) f(XIN) clock generating circuit
Clock signal f(XIN) is obtained by externally connecting a
ceramic resonator. Connect this external circuit to pins XIN
and XOUT at the shortest distance. A feedback resistor is built
in between pins XIN and XOUT.
(3) f(XCIN) clock generating circuit
Clock signal f(XCIN) is obtained by externally connecting a
quartz-crystal oscillator. Connect this external circuit to pins
XCIN and XCOUT at the shortest distance. A feedback resistor
is built in between pins XCIN and XCOUT.
M34551
XIN
CIN
Note: Externally connect a
damping resistor Rd
depending on the
XOUT
oscillation frequency.
(A feedback resistor is
built-in.)
Rd
Use the resonator
manufacturer’s
recommended value
COUT
because constants such
as capacitance depend
on the resonator.
ROM ORDERING METHOD
Please submit the information described below when ordering
Mask ROM.
(1) M34551M4-XXXFP Mask ROM Order Confirmation Form
..............................................................................................1
(2) Data to be written into mask ROM
• EPROM (three sets containing the identical data)
(3) Mark Specification Form .................................................... 1
Fig. 38 Ceramic resonator external circuit
Note: Externally connect a
damping resistor Rd
depending on the
XCOUT
oscillation frequency.
(A feedback resistor is
built-in.)
Rd
Use the quartz-crystal
oscillator manufacturer’s
recommended value
COUT
because constants such
as capacitance depend
on the quartz-crystal
oscillator.
M34551
XCIN
CIN
Fig. 39 Quartz-crystal oscillator external circuit
4551 Group User’s Manual
1-39
HARDWARE
LIST OF PRECAUTIONS
LIST OF PRECAUTIONS
• Use the carrier wave or the carrier wave divided by 2 as the
timer 1 count source when the carrier wave output autocontrol function is selected.
If the ORCLK is used as the count source, a hazard may
occur in port CARR output because ORCLK is not
synchronized with the carrier wave.
• When “no carrier wave” is selected with register C1
((C13C12C11C10) = (0101), (1101)), the enable/disable of
the carrier wave output cannot be controlled by the carrier
wave output auto-control function.
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins
VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
In the built-in PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to V SS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
➇ D5/INT pin
When the interrupt valid waveform of D5/INT pin is changed
with the bit 2 of register I1 in software, be careful about the
following notes.
• Clear the bit 0 of register V1 to “0” and then change the
interrupt valid waveform of D5/INT pin with the bit 2 of register
I1 (refer to Figure 40➀).
• Clear the bit 2 of register I1 to “0” and execute the SNZ0
instruction to clear the EXF0 flag after executing at least
one instruction (refer to Figure 40➁). Depending on the input
state of the D5/INT pin, the external 0 interrupt request flag
(EXF0) may be set to “1” when the interrupt valid waveform
is changed.
➁ Prescaler
Stop the prescaler operation to change its frequency dividing
ratio.
➂ Count source
Stop timer 1 or timer LC counting to change its count source.
When timer 2 count source changes from f(X CIN) to ORCLK
(W23 = “0” → W23 = “1”), the count value of timer 2 is initialized.
However, when timer 2 count source changes from ORCLK to
f(XCIN) (W23 = “1” → W23 = “0”) or the same count source is
set again (W23 = “0” → W23 = “0” or W23 = “1” → W23 = “1”),
the count value of timer 2 is not initialized.
...
LA
➃ Timer 2
Timer 2 has the watchdog timer function (WDT). When timer 2
is used as the WDT, note that the processing to initialize the
count value and the execution of the WRST instruction.
4
TV1A
LA
SNZ0
NOP
...
➅ Writing to reload register R1
Write the data to reload register R1 while timer 1 is operating,
avoid a timing when timer 1 underflows.
➆ Notes when using the carrier wave output auto-control function
• Execute the STCR instruction after setting the timer 1 and
register C2 in order to start the carrier generating circuit
operation.
• Stop the timer 1 (W2 0 =“0”) after stopping the carrier
generating circuit (SPCR instruction executed) while the
carrier wave output is disabled in order to stop the carrier
wave output auto-control operation.
• If the carrier wave output auto-control function is invalidated
(C20 =“0”) while the carrier wave output is auto-controlled,
the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow. This
state is released by timer 1 stop (W20=“0”).
When the carrier wave output auto-control function is
validated (C20=“1”) again after it is invalidated (C20=“0”),
the auto-control of carrier wave output is started again when
the next timer 1 underflow occurs. However, when the carrier
wave output auto-control bit is changed during timer 1
underflow, the error-operation may occur.
1-40
; Change of the interrupt valid waveform
➁
NOP
Stop the prescaler and then execute the TAB1 instruction to
read timer 1 data.
➀
4
TI1A
➄ Reading the count value
; (✕✕✕02)
; The SNZ0 instruction is valid
;The SNZ0 instruction is executed
✕ : this bit is not related to the setting of INT.
Fig. 40 External 0 interrupt program example
➈ One Time PROM version
The operating power voltage of the One Time PROM version
is within the range of 2.5 V to 5.5 V.
➉ Multifunction
Note that the port D5 output function can be used even when
INT function is selected.
11
Power down instruction (POF instruction, POF2 instruction)
Execute the POF or POF2 instruction immediately after
executing the EPOF instruction to enter the power down state.
Note that system cannot enter the power down state when
executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction
before executing the EPOF instrcution.
12 Program
counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
4551 Group User’s Manual
HARDWARE
SYMBOL
SYMBOL
The symbols shown below are used in the following list of instruction function and machine instructions.
Contents
Symbol
A
B
Register A (4 bits)
DR
Register D (3 bits)
Register E (8 bits)
E
V1
V2
I1
W1
W2
W3
C1
C2
CR
L1
L2
PU0
MR
X
Y
Z
Symbol
WDF
INTE
Register B (4 bits)
EXF0
P
General-purpose register V2 (4 bits)
Interrupt control register I1 (4 bits)
Timer control register W1 (4 bits)
R2
RLC
STCK
INSTK
T1
T2
TLC
P0
P1
Port D (8 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (4 bits)
Carrier wave selection register C1 (4 bits)
x
Hexadecimal variable
Carrier wave output control register C2 (1 bit)
Carrier wave generating control flag
y
Hexadecimal variable
Hexadecimal variable
LCD control regiser L1
z
p
Hexadecimal variable
LCD control register L2
Pull-up control register PU0 (4 bits)
n
Hexadecimal constant which represents the
immediate value
Clock control register MR (4 bits)
i
Hexadecimal constant which represents the
j
immediate value
Hexadecimal constant which represents the
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
immediate value
Program counter (14 bits)
High-order 7 bits of program counter
CY
R1
D
P2
PC
SP
External 0 interrupt request flag
Power down flag
Timer control register W2 (4 bits)
Timer control register W3 (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
PCL
SK
Interrupt enable flag
Interrupt control register V1 (4 bits)
DP
PCH
Contents
Watchdog timer flag
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
Carry flag
Timer 1 reload register
Timer 2 reload register
Timer LC reload register
System clock
Instruction clock
Timer 1
Timer 2
Timer LC
A3A2A1A0
Binary notation of hexadecimal variable A
(same for others)
←
Direction of data movement
↔
?
Data exchange between a register and memory
( )
Decision of state shown before “?”
Contents of registers and memories
—
Negate, Flag unchanged after executing
M(DP)
instruction
RAM address pointed by the data pointer
a
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0
C
+
Hex. C + Hex. number x (also same for others)
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p5 p4 p3 p2 p1 p0
x
Timer 1 interrupt request flag
T1F
Timer 2 interrupt request flag
T2F
Note : The 4551 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not
increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count
becomes “1” if the TABP p, RT, or RTS instruction is skipped.
4551 Group User’s Manual
1-41
HARDWARE
LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION
(A) ← (B)
TBA
(B) ← (A)
TYA
TEAB
(A) ← (Y)
(Y) ← (A)
Grouping
Function
Mnemonic
(A) ← → (M(DP))
XAMI j
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
SB j
(Mj(DP)) ← 1
j = 0 to 3
RB j
(Mj(DP)) ← 0
j = 0 to 3
SZB j
j = 0 to 15
LA n
(A) ← n
n = 0 to 15
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
Function
Mnemonic
(Mj(DP)) = 0 ?
j = 0 to 3
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
Grouping
Bit operation
TAB
TAY
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(DR2–DR0) ← (A2–A0)
SEAM
(A) = (M(DP)) ?
SEA n
(A) = n ?
n = 0 to 15
Ba
(PCL) ← a6–a0
BL p, a
(PCH) ← p
(PCL) ← a6–a0
BLA p
(PCH) ← p
(PC L ) ← (DR 2 –DR 0 ,
(PC L ) ← (DR 2 –DR 0 ,
TAD
(A2–A0) ← (DR2–DR0)
(A3) ← 0
A3–A0)
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
TAZ
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
(A) ← (X)
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Branch operation
Register to register transfer
Function
Comparison
operation
Mnemonic
RAM to register transfer
Grouping
A3–A0)
LZ z
INY
DEY
TAM j
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
(A) ← (A) + (M(DP))
BM a
AMC
(A) ← (A) + (M(DP))
+ (CY)
(SK(SP)) ← (PC)
(CY) ← Carry
An
(A) ← (A) + n
n = 0 to 15
(Z) ← z, z = 0 to 3
AND
(A) ← (A)AND(M(DP))
OR
(A) ← (A)OR(M(DP))
SC
(CY) ← 1
RC
(CY) ← 0
SZC
(CY) = 0 ?
CMA
(A) ← (A)
RAR
→ CY → A3A2A1A0
(Y) ← (Y) + 1
BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
BMLA p
(Y) ← (Y) – 1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
(SP) ← (SP) + 1
(PCH) ← 2
(PCL) ← a6–a0
Subroutine operation
RAM addresses
LXY x, y
(A2–A0) ← (SP2–SP0)
(A3) ← 0
Arithmetic operation
TASP
AM
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0,
A3–A0)
XAM j
(X) ← (X)EXOR(j)
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
1-42
(PC) ← (SK(SP))
(SP) ← (SP) – 1
j = 0 to 15
XAMD j
RTI
(A) ← → (M(DP))
4551 Group User’s Manual
Return operation
RAM to register transfer
j = 0 to 15
RT
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
HARDWARE
LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION (CONTINUED)
(INTE) ← 0
EI
(INTE) ← 1
(EXF0) = 1 ?
Interrupt operation
After skipping the next
instruction,
(EXF0) ← 0
SNZI0
I12 = 1 : (INT0) = “H” ?
I12 = 0 : (INT0) = “L” ?
TAV1
(A) ← (V1)
TV1A
(V1) ← (A)
TAI1
(I1) ← (A)
TAW1
(A) ← (W1)
TAW2
Function
TLCA
(TLC) ← (A)
(RLC) ← (A)
SNZT1
(T1F) = 1 ?
After skipping the next
Grouping Mnemonic
(W1) ← (A)
(A) ← (W2)
TW2A
(W2) ← (A)
TAW3
(A1, A0) ← (W31, W30)
TC1A
Function
(C1) ← (A)
STCR
Carrier wave
generating start
SPCR
Carrier wave
generating stop
TC2A
(C20) ← (A0)
(T2F) ← 0
NOP
(PC) ← (PC) + 1
IAP0
(A) ← (P0)
POF
Transition to clock
OP0A
(P0) ← (A)
IAP1
(A) ← (P1)
OP1A
(P1) ← (A)
IAP2
(A) ← (P2)
CLD
(D) ← 1
RD
(D(Y)) ← 0
instruction,
(T1F) ← 0
SNZT2
(T2F) = 1 ?
After skipping the next
instruction,
operating mode
(A) ← (I1)
TI1A
TW1A
Mnemonic
POF2
SD
Transition to RAM
back-up mode
EPOF
Other operation
SNZ0
Grouping
Carrier wave generating operation
Function
DI
Timer operation
Mnemonic
Input/Output operation
Grouping
Power down instruction
(POF, POF2) valid
SNZP
(P) = 1 ?
WRST
(WDF) ← 0, (WEF) ← 1
(Y) = 0 to 7
TAMR
(A) ← (MR)
(D(Y)) ← 1
TMRA
(MR) ← (A)
TAV2
(A) ← (V2)
TV2A
(V2) ← (A)
(Y) = 0 to 7
TAB1
T1AB
(W31, W30) ← (A1, A0)
TPU0A
(PU0) ← (A)
(A) ← (T13–T10)
TAPU0
(A) ← (PU0)
at timer 1 stop (W20=0)
TL1A
(L1) ← (A)
TAL1
(A) ← (L1)
TL2A
(L2) ← (A)
(B) ← (T17–T14)
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
At timer 1 operating
(W20=1),
(R17–R14) ← (B)
(R13–R10) ← (A)
LCD control operation
Timer operation
TW3A
4551 Group User’s Manual
1-43
HARDWARE
INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE
D9–D4 000000 000001 000010 000011 000100 000101000110 000111001000001001 001010 001011 001100 001101001110 001111
010000 011000
010111 011111
D3 –
D0
Hex.
notation
00
01
0000
0
NOP
BLA
0001
1
–
0010
2
POF
0011
3
0100
4
DI
RD
0101
5
EI
SD SEAn
0110
6
RC
–
0111
7
SC
1000
8
1001
9
1010
A
1011
B
AMC
1100
C
1101
D
1110
1111
0E
0F
TABP TABP TABP TABP
0
16
32* 48* BML BML
BL
BL
BM
B
LA
1
TABP TABP TABP TABP
BML BML
1
17
33* 49*
BL
BL
BM
B
A
2
LA
2
TABP TABP TABP TABP
BML BML
2
18
34* 50*
BL
BL
BM
B
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML BML
3
19
35* 51*
BL
BL
BM
B
TAV1
A
4
LA
4
TABP TABP TABP TABP
4
20
36* 52* BML BML
BL
BL
BM
B
–
RTS TAV2
A
5
LA
5
TABP TABP TABP TABP
5
21
37* 53* BML BML
BL
BL
BM
B
SEAM
–
RTI
–
A
6
LA
6
TABP TABP TABP TABP
BML
6
22
38* 54* BML
BL
BL
BM
B
DEY
–
–
–
–
A
7
LA
7
TABP TABP TABP TABP
7
23
39* 55* BML BML
BL
BL
BM
B
POF2 AND
–
SNZ0
LZ
0
–
A
8
LA
8
TABP TABP TABP TABP
8
40* 56* BML BML
24
BL
BL
BM
B
TDA
–
LZ
1
–
A
9
LA
9
TABP TABP TABP TABP
BML BML
9
25
41* 57*
BL
BL
BM
B
LZ
2
–
A
10
LA
10
TABP TABP TABP TABP
10
42* 58* BML BML
26
BL
BL
BM
B
04
05
06
07
SZB
BMLA
0
–
TASP
A
0
LA
0
CLD
SZB
1
–
–
TAD
A
1
–
SZB
2
–
–
TAX
SZB
3
–
–
–
–
RT
SNZP INY
OR
–
03
02
AM TEAB TABE SNZI0
08
09
0A
0B
0C
0D
10–17 18–1F
–
–
LZ
3
EPOF
A
11
LA
11
TABP TABP TABP TABP
11
43* 59* BML BML
27
BL
BL
BM
B
TYA CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
12
28
44* 60* BML BML
BL
BL
BM
B
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
BML BML
13
45* 61*
29
BL
BL
BM
B
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
BML BML
14
30
46* 62*
BL
BL
BM
B
F
–
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
15
31
47* 63* BML BML
BL
BL
BM
B
–
The above table shows the relationship between machine language codes and machine language instructions. D 3–D0 show
the low-order 4 bits of the machine language code, and D 9–D4 show the high-order 6 bits of the machine language code. The
hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only
the first word of each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below. * cannot be used at M34551M4.
The second word
1-44
BL
10
paaa
aaaa
BML
10
paaa
aaaa
BLA
10
pp00
pppp
BMLA
10
pp00
pppp
SEA
00
0111
nnnn
4551 Group User’s Manual
HARDWARE
INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (CONTINUED)
110000
D9–D4 100000 100001100010 100011100100 100101100110 100111101000 101001101010 101011101100 101101101110 101111
111111
D 3–
D0
Hex.
notation
20
0000
0
–
0001
1
–
0010
2
0011
21
22
23
24
25
TW3A OP0A T1AB
–
–
–
OP1A
–
–
–
–
–
–
–
–
3
–
–
–
–
–
TAI1
0100
4
–
–
–
–
–
0101
5
–
–
–
–
0110
6
–
TMRA
–
0111
7
–
TI1A
1000
8
–
1001
9
1010
26
27
28
2C
2D
2E
2F
30–3F
29
2A
IAP0 TAB1 SNZT1
–
WRST
TMA TAM XAM XAMI XAMD
LXY
0
0
0
0
0
IAP1
–
SNZT2
–
–
TMA TAM XAM XAMI XAMD
LXY
1
1
1
1
1
TAMR IAP2
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
2
2
2
2
2
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
3
3
3
3
3
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
4
4
4
4
4
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
5
5
5
5
5
–
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
6
6
6
6
6
–
–
–
TAPU0
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
7
7
7
7
7
–
–
–
–
–
–
–
–
STCR TC1A
TMA TAM XAM XAMI XAMD
LXY
8
8
8
8
8
–
–
–
–
–
–
–
–
–
SPCR TC2A
TMA TAM XAM XAMI XAMD
LXY
9
9
9
9
9
A
TL1A
–
–
–
TAL1
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
10
10
10
10
10
1011
B
TL2A
–
–
–
TAW1
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
11
11
11
11
11
1100
C
–
–
–
–
TAW2
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
12
12
12
12
12
1101
D
TLCA
–
TPU0A
–
TAW3
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
13
13
13
13
13
1110
E
TW1A
–
–
–
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
14
14
14
14
14
1111
F
TW2A
–
–
–
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
15
15
15
15
15
2B
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the
low-order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The
hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the
first word of each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
BL
10
paaa
aaaa
BML
10
paaa
aaaa
BLA
10
pp00
pppp
BMLA
10
pp00
pppp
SEA
00
0111
nnnn
4551 Group User’s Manual
1-45
HARDWARE
MACHINE INSTRUCTIONS
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register to register transfer
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS
Function
TAB
0
0
0
0
0
1
1
1
1
0
0
1
E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0
0
E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0
1
F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0
0
C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0
1
A
1
1
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0
2
9
1
1
(DR2–DR0) ← (A2–A0)
TAD
0
0
0
1
0
1
0
0
0
1
0
5
1
1
1
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0
5
3
1
1
(A1, A0) ← (Z1, Z0)
RAM addresses
(A3, A2) ← 0
1-46
TAX
0
0
0
1
0
1
0
0
1
0
0
5
2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0
5
0
1
1
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
x
y
1
1
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
LZ z
0
0
0
0
4
8
1
1
(Z) ← z, z = 0 to 3
1
0
0
1
0
z1 z0
+z
INY
0
0
0
0
0
1
0
0
1
1
0
1
3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0
1
7
1
1
(Y) ← (Y) – 1
4551 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of registers A and B to register E.
–
–
Transfers the contents of register E to registers A and B.
–
–
Transfers the contents of register A to register D.
–
–
Transfers the contents of register D to register A.
–
–
Transfers the contents of register Z to register A.
–
–
Transfers the contents of register X to register A.
–
–
Transfers the contents of stack pointer (SP) to register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register
Y.
Detailed description
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
4551 Group User’s Manual
1-47
HARDWARE
MACHINE INSTRUCTIONS
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAM j
1
0
1
1
0
0
j
j
j
j
Hexadecimal
notation
2 C
j
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D
j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
RAM to register transfer
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2 F
j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2 E
j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2 B
j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
LA n
0
0
0
1
1
1
n
n
n
n
0 7
n
1
1
(A) ← n
Arithmetic operation
n = 0 to 15
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
0 8
p
1
+p
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(Note)
Note: p is 0 to 31 for M34551M4 and p is 0 to 63 for M34551M8 and M34551E8.
1-48
4551 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
Detailed description
performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
Continuous
–
Loads the value n in the immediate field to register A.
description
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
and other LA instructions coded continuously are skipped.
–
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, 1 stage of stack register is used.
4551 Group User’s Manual
1-49
HARDWARE
MACHINE INSTRUCTIONS
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Function
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP))+ (CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
Comparison
operation
Bit operation
Arithmetic operation
n = 0 to 15
1-50
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A)AND(M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A)OR(M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
SB j
0
0
0
1
0
1
1
1
j
j
0 5
C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0 4
C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0 2
j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
0
0
0
0
1
0
0
1
1
0
0 2
6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0 2
5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0 7
n
4551 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
–
Overflow = 0
Detailed description
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag
CY.
–
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
–
–
Performs the AND operation between the contents of register A and the contents of M(DP), and stores
the result in register A.
–
–
Performs the OR operation between the contents of register A and the contents of M(DP), and stores
the result in register A.
–
1
Sets carry flag CY to “1.”
–
0
Clears carry flag CY to “0.”
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one’s complement for register A’s contents in register A.
–
0/1 Rotates the contents of register A including the contents of carry flag CY to the right by 1 bit.
–
–
Sets the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “1.”
–
–
Clears the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “0.”
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field)
of M(DP) is “0.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
4551 Group User’s Manual
1-51
HARDWARE
MACHINE INSTRUCTIONS
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Branch operation
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Function
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
BL p, a
0
0
1
1
p4 p3 p2 p1 p0
0 E p
+p
2
2
(PCH) ← p
(PCL) ← a6–a0
1
0
p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+a
0
0
0
0
1
0
0 1
0
1
0
p5 p4 0
0
p3 p2 p1 p0
2 p
p
0
1
0
a6 a5 a4 a3 a2 a1 a0
1 a
a
1
(Note)
BLA p
BM a
0
0
0
0
2
2
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(Note)
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
Subroutine operation
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
1
0
p4 p3 p2 p1 p0
0 C p
+p
0
0
1
1
0
p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+a
0
0
0
1
1
0
0 3
0
1
0
p5 p4 0
0
p3 p2 p1 p0
2 p
p
2
2
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
BMLA p
0
0
0
0
(PCL) ← a6–a0
(Note)
2
2
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
Return operation
(PCL) ← (DR2–DR0, A3–A0)
(Note)
RTI
0
0
0
1
0
0
0
1
1
0
0 4
6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
1
0
0
0
1
0
0
0 4
4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4
5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Note: p is 0 to 31 for M34551M4 and p is 0 to 63 for M34551M8 and M34551E8.
1-52
4551 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and
A in page p.
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers
D and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous
Detailed description
description of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip unconditionally
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction unconditionally.
4551 Group User’s Manual
1-53
HARDWARE
MACHINE INSTRUCTIONS
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Function
DI
0
0
0
0
0
0
0
1
0
0
0 0
4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0 0
5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3
8
1
1
(EXF0) = 1 ?
After skipping the next instruction,
Interrupt operation
(EXF0) ← 0
SNZI0
0
0
0
0
1
1
1
0
1
0
0 3
A
1
1
I12 = 1 : (INT) = “H” ?
I12 = 0 : (INT) = “L” ?
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
SNZT1
1
0
1
0
0
0
0
0
0
0
2 8 0
1
1
(T1F) = 1 ?
After skipping the next instruction
(T1F) ← 0
SNZT2
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
(T2F) = 1 ?
After skipping the next instruction
Timer operation
(T2F) ← 0
1-54
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
TAW3
1
0
0
1
0
0
1
1
0
1
2 4 D
1
1
(A1, A0) ← (W31, W30)
TW3A
1
0
0
0
0
1
0
0
0
0
2 1 0
1
1
(W31, W30) ← (A1, A0)
4551 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Clears the interrupt enable flag INTE to “0,” and disables the interrupt.
–
–
Sets the interrupt enable flag INTE to “1,” and enables the interrupt.
(EXF0) = 1
–
Skips the next instruction when the contents of EXF0 flag is “1.”
After skipping, clears the EXF0 flag to “0.”
(INT) = “H”
–
When bit 2 (I12) of register I1 is “1” : Skips the next instruction when the level of INT pin is “H.”
–
When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT pin is “L.”
–
–
Transfers the contents of interrupt control register V1 to register A.
–
–
Transfers the contents of register A to interrupt control register V1.
–
–
Transfers the contents of interrupt control register I1 to register A.
–
–
Transfers the contents of register A to interrupt control register I1.
(T1F) = 1
–
Skips the next instruction when the contents of T1F flag is “1.”
After skipping, clears T1F flag.
(T2F) =1
–
Skips the next instruction when the contents of T2F flag is “1.”
Detailed description
However, I12 = 1
(INT) = “L”
However, I12 = 0
After skipping, clears T2F flag.
–
–
Transfers the contents of timer control register W1 to register A.
–
–
Transfers the contents of register A to timer control register W1.
–
–
Transfers the contents of timer control register W2 to register A.
–
–
Transfers the contents of register A to timer control register W2.
–
–
Transfers the contents of timer control register W3 to register A.
–
–
Transfers the contents of register A to timer control register W3.
4551 Group User’s Manual
1-55
HARDWARE
MACHINE INSTRUCTIONS
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAB1
1
0
0
1
1
1
0
0
0
0
Hexadecimal
notation
2 7 0
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(B) ← (T17–T14)
(A) ← (T13–T10)
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
At timer 1 stop (W20=0),
Timer operation
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
At timer 1 operating (W20=1),
(R17–R14) ← (B)
(R13–R10) ← (A)
TLCA
1
0
0
0
0
0
1
1
0
1
2 0 D
1
1
(TLC) ← (A)
Input/Output operation
(RLC) ← (A)
1-56
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A) ← (P2)
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 7
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
TAPU0
1
0
0
1
0
1
0
1
1
1
2 5 7
1
1
(A) ← (PU0)
4551 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
–
–
Detailed description
Transfers the contents of timer 1 to registers A and B.
When stopping (W2 0=0), transfers the contents of registers A and B to timer 1 and timer 1 reload
register.
When operating (W20=1), transfers the contents of registers A and B only to timer 1 reload register.
–
–
Transfers the contents of register A to timer LC and timer LC reload register.
–
–
Transfers the input of port P0 to register A.
–
–
Outputs the contents of register A to port P0.
–
–
Transfers the input of port P1 to register A.
–
–
Outputs the contents of register A to port P1.
–
–
Transfers the input of port P2 to register A.
–
–
Sets port D to “1.”
–
–
Clears a bit of port D specified by register Y to “0.”
–
–
Sets a bit of port D specified by register Y to “1.”
–
–
Transfers the contents of register A to pull-up control register PU0.
–
–
Transfers the contents of pull-up control register PU0 to register A.
4551 Group User’s Manual
1-57
HARDWARE
MACHINE INSTRUCTIONS
Instruction code
Parameter
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Other operation
Carrier generating circuit
operation
LCD control
operation
instructions
1-58
Hexadecimal
notation
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Function
TL1A
1
0
0
0
0
0
1
0
1
0
2 0 A
1
1
(L1) ← (A)
TAL1
1
0
0
1
0
0
1
0
1
0
2 4 A
1
1
(A) ← (L1)
TL2A
1
0
0
0
0
0
1
0
1
1
2 0 B
1
1
(L2) ← (A)
TC1A
1
0
1
0
1
0
1
0
0
0
2 A 8
1
1
(C1) ← (A)
STCR
1
0
1
0
0
1
1
0
0
0
2 9 8
1
1
Carrier wave generating start
SPCR
1
0
1
0
0
1
1
0
0
1
2 9 9
1
1
Carrier wave generating stop
TC2A
1
0
1
0
1
0
1
0
0
1
2 A 9
1
1
(C20) ← (A0)
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
0
0
0
1
0
0 0 2
1
1
Transition to clock operating mode
POF2
0
0
0
0
0
0
1
0
0
0
0 0 8
1
1
Transition to RAM back-up mode
EPOF
0
0
0
1
0
1
1
0
1
1
5 B
1
1
Power down instruction (POF, POF2) valid
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF) ← 0, (WEF) ← 1
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
0
4551 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Transfers the contents of register A to LCD control register L1.
–
–
Transfers the contents of register L1 to register A.
–
–
Transfers the contents of register A to LCD control register L2.
–
–
Transfers the contents of register A to carrier wave selection register C1.
–
–
Starts generating carrier wave.
–
–
Stops generating carrier wave.
–
–
Transfers the contents of register A to carrier wave output control register C2.
–
–
No operation
–
–
Puts the system in clock operating mode state by executing the POF instruction after executing the
EPOF instruction.
Detailed description
f(XCIN) oscillation, LCD, timer LC and timer 2 are operated.
–
–
Puts the system in RAM back-up mode state by executing the POF2 instruction after executing the
EPOF instruction.
Oscillation is stopped.
–
–
Validates the power down instruction (POF, POF2) which is executed after the EPOF instruction by
executing the EPOF instruction.
(P) = 1
–
Skips the next instruction when P flag is “1.”
After skipping, P flag remains unchanged.
–
–
Operates the watchdog timer and initializes the watchdog timer flag (WDF).
–
–
Transfers the contents of clock control register MR to register A.
–
–
Transfers the contents of register A to clock control register MR.
–
–
Transfers the contents of general-purpose register V2 to register A.
–
–
Transfers the contents of register A to general-purpose register V2.
4551 Group User’s Manual
1-59
HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
0
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
1
This bit has no function, but read/write is enabled.
0
Prescaler control bit
W12
Prescaler dividing ratio selection bit
at reset : 00002
at power down : 00002
0
Stop (prescaler state initialized)
1
Operating
0
1
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 8
Timer 1 count source selection bits
0
0
0
Prescaler output (ORCLK)
1
0 Carrier output (CARRY)
1 Carrier output divided by 2 (CARRY/2)
1
W10
1
at reset : 10002
Timer control register W2
W23
Timer 2 count source selection bit
f(XCIN)
1
Prescaler output (ORCLK)
0
Timer 2 count value selection bits
W20
0
1
1
W21
Timer 1 control bit
0
1
Timer LC count source selection bit
Underflow occur every 214 count
Underflow occur every 213 count
0
Not available
1
Not available
Stop (timer 1 state retained)
Operating
at power down : state retained
R/W
0
Bit 3 of timer 2 is output (timer 2 count source divided by 16)
1
System clock (STCK)
0
Stop (timer LC state retained)
Timer LC control bit
W30
1
Operating
Note: “R” represents read enabled, and “W” represents write enabled.
“–” represents state retained.
1-60
R/W
Count source
0
1
at reset : 002
Timer control register W3
W31
at power down : – – – 02
0
W22 W21
W22
R/W
Count source
W11 W10
W11
R/W
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
1
Timer control register W1
W13
at power down : 00002
4551 Group User’s Manual
HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS (CONTINUED)
Interrupt control register I1
I13
I12
at reset : 00002
0
Not used
1
R/W
This bit has no function, but read/write is enabled.
0
Falling waveform (“L” level of INT pin is recognized with the SNZI0
1
instruction)
Rising waveform (“H” level of INT pin is recognized with the SNZI0
Interrupt valid waveform for INT pin
selection bit (Note 2)
at power down : state retained
instruction)
I11
Not used
I10
Not used
0
1
0
1
Pull-up control register PU0
PU03
PU02
PU01
PU00
Port P13 pull-up transistor
0
1
0
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
1
0
1
0
1
Clock control register MR
System clock (STCK) selection bit
1
MR2
f(XCIN) oscillation circuit control bit
MR1
f(XIN) oscillation circuit control bit
0
1
0
1
at power down : state retained
R/W
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
at reset : 10002
0
MR3
This bit has no function, but read/write is enabled.
at reset : 00002
control bit
Port P12 pull-up transistor
control bit
This bit has no function, but read/write is enabled.
at power down : state retained
R/W
MR0=0 f(XIN)
MR0=1 f(XCIN)
MR0=0 f(XIN)/4
MR0=1 f(XCIN)/4
f(XCIN) oscillation stop, ports D6 and D7 selected
f(XCIN) oscillation enabled, ports D6 and D7 not selected
Oscillation enabled
Oscillation stop
f(XIN)
0
f(XCIN)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of D5/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of
I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after
executing at least one instruction.
MR0
Clock selection bit
4551 Group User’s Manual
1-61
HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS (CONTINUED)
Carrier wave selection register C1
at reset : 01112
C13 C12 C11 C10
Carrier wave selection bits
Carrier wave output auto-control bit
0
0
STCK/24
1/3
0
0
0
0
0
1
1
0
STCK/24
STCK/16
1/2
1/4
0
0
1
1
STCK/16
1/2
0
0
1
1
0
0
0
1
STCK/2
No carrier wave
1/2
0
1
1
0
Not available
0
1
1
0
1
0
1
0
“L” fixed
STCK/12
1/3
1
0
0
1
STCK/12
1/2
1
1
0
0
1
1
0
1
STCK/8
STCK/8
1/4
1/2
1
1
0
0
STCK
1/2
1
1
1
1
0
1
1
0
No carrier wave
Not available
1
1
1
1
“L” fixed
at reset : 02
Carrier wave generating control
Auto-control output by timer 1 is invalid
1
Auto-control output by timer 1 is valid
0
1
at power down : 02
Carrier wave generating stop (SPCR instruction)
Carrier wave generating start (STCR instruction)
Note: “W” represents write enabled.
1-62
at power down : 02
0
at reset : 02
4551 Group User’s Manual
W
Duty
0
Carrier wave generating control flag CR
CR
Carrier wave frequency
0
Carrier wave output control register C2
C20
at power down : 01112
W
W
HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS (CONTINUED)
at reset : 00002
LCD control register L1
L13
Not used
L12
LCD on/off bit
0
LCD duty and bias selection bits
Off
On
1
Duty
L10
0
0
1
0
1/2
1/3
1/2
1/3
1
1/4
1/3
P23/SEG19 pin function switch bit
L22
P22/SEG18 pin function switch bit
L21
P21/SEG17 pin function switch bit
L20
P20/SEG16 pin function switch bit
General-purpose register V2
Not available
at reset : 11112
LCD control register L2
L23
Bias
0
1
1
R/W
This bit has no function, but read/write is enabled
1
0
L11 L10
L11
at power down : state retained
0
1
SEG19
P23
0
SEG18
1
0
P22
SEG17
1
P21
0
1
SEG16
P20
at reset : 00002
at power down : state retained
W
at power down : 00002
R/W
4-bit general-purpose register.
The data transfer between register A and this register is performed with the TV2A and TAV2 instructions.
Note: “R” represents read enabled, and “W” represents write enabled.
4551 Group User’s Manual
1-63
HARDWARE
BUILT-IN PROM VERSION
BUILT-IN PROM VERSION
Table 19 shows the product of built-in PROM version. Figure 41
shows the pin configurations of built-in PROM version. The One
Time PROM version has pin-compatibility with the mask ROM
version.
In addition to the mask ROM version, the 4551 Group has the
programmable ROM version software compatible with mask
ROM. The One Time PROM version has PROM which can only
be written to and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM version, but it has a PROM mode that enables writing
to built-in PROM.
Table 19 Product of built-in PROM version
Product
PROM size
RAM size
(✕ 10 bits)
(✕ 4 bits)
8192 words
280 words
ROM type
Package
M34551E8-XXXFP
One Time PROM [shipped after writing]
(shipped after writing and test in factory)
48P6S-A
One Time PROM [shipped in blank]
M34551E8FP
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
RESET
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PIN CONFIGURATION (TOP VIEW)
SEG9
39
24
D7/XCOUT
SEG10
40
23
D6/XCIN
SEG11
41
22
CNVSS
SEG12
42
21
XOUT
VSS
43
20
XIN
SEG13
44
19
VSS
SEG14
45
18
VDD
SEG15
46
17
CARR
P20 / SEG16
47
16
D5 / INT
P21 / SEG17
48
15
D4
8
9
10
11
12
13
14
P12
P13
D0
D1
D2
D3
P02
P11
5
P01
P10
4
P00
7
3
P23 / SEG19
6
2
P03
1
P22 / SEG18
M34551E8-XXXFP
Outline 48P6S-A
Fig. 41 Pin configuration of built-in PROM version
1-64
4551 Group User’s Manual
HARDWARE
BUILT-IN PROM VERSION
(1) PROM mode
The built-in PROM version has a PROM mode in addition to
a normal operation mode. The PROM mode is used to write
to and read from the built-in PROM.
In the PROM mode, the programming adapter can be used
with a general-purpose PROM programmer to write to or read
from the built-in PROM as if it were M5M27C256K.
Programming adapter is listed in Table 20. Contact addresses
at the end of this book for the appropriate PROM programmer.
• Writing and reading of built-in PROM
Programming voltage is 12.5 V. Write the program in the
PROM of the built-in PROM version as shown in Figure
42.
(2) Notes on handling
➀ A high-voltage is used for writing. Take care that
overvoltage is not applied. Take care especially at turning
on the power.
➁ For the One Time PROM version shipped in blank,
Mitsubishi Electric corp. does not perform PROM writing
test and screening in the assembly process and following
processes. In order to improve reliability after writing,
performing writing and test according to the flow shown in
Figure 43 before using is recommended.
Table 20 Programming adapter
Microcomputer
M34551E8-XXXFP, M34551E8FP
Address
000016
Programming adapter
PCA7414
AAAAAAAAA
AAAAAAAAA
AAAAAAAAA
AAAAAAAAA
AAAAAAAAA
1
1
1
D2
D1
D0
Low-order 5 bits
1FFF16
400016
D4 D3
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
5FFF16
7FFF16
Set “FF16” to the shaded area.
Fig. 42 PROM memory map
( Products shipped in blank: PROM contents is not written in
factory when shipped)
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 43 Flow of writing and test of the product shipped in
blank
4551 Group User’s Manual
1-65
HARDWARE
BUILT-IN PROM VERSION
MEMO
1-66
4551 Group User’s Manual
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
I/O pins
Interrupts
Timers
Carrier generating circuit
Liquid crystal display
Power down function
Reset
Oscillation circuit
APPLICATION
2.1 I/O pins
2.1 I/O pins
The 4551 Group has the eight I/O pins, four input pins and eight output pins. (Ports P20–P2 3, D5 –D 7 are
also used as segment output pins SEG 16–SEG 19, INT input pin, X CIN, and X COUT, respectively).
This section describes each port I/O function, related registers, application example using each port function
and notes.
2.1.1 I/O ports
(1) Port P0
Port P0 is a 4-bit I/O port.
Port P0 has the key-on wakeup function and pull-up transistor.
■ Input/output of port P0
● Data input to port P0
Set the output latch of specified port P0i (i=0 to 3) to “1” with the OP0A instruction. If the output
latch is set to “0,” “L” level can be input.
The state of port P0 is transferred to register A when the IAP0 instruction is executed.
● Data output from port P0
The contents of register A is output to port P0 with the OP0A instruction.
The output structure is an N-channel open-drain (built-in pull-up resistor).
(2) Port P1
Port P1 is a 4-bit I/O port.
Port P1 has the key-on wakeup function and pull-up transistor which turn ON/OFF by setting register
PU0.
■ Input/output of port P1
● Data input to port P1
Set the output latch of specified port P1i (i=0 to 3) to “1” with the OP1A instruction. If the output
latch is set to “0,” “L” level can be input.
The state of port P1 is transferred to register A when the IAP1 instruction is executed.
● Data output from port P1
The contents of register A is output to port P1 with the OP1A instruction.
The output structure is an N-channel open-drain.
Note: When the pull-up function becomes valid, simultaneously, the key-on wakeup function becomes
valid.
Accordingly, be careful when using the key-on wakeup function. (Refer to the Table 2.1.1 and
notes for the power down function.)
2-2
4551 Group User’s Manual
APPLICATION
2.1 I/O pins
(3) Port P2
Port P2 is a 4-bit input port.
■ Input of port P2
Port P2 is also used as SEG16–SEG 19. Accordingly, when ports P2 0/SEG 16–P23/SEG19 are used
as port P2, set the corresponding bits of the LCD control register L2 to “1.”
● Data input to port P2
The state of port P2 is transferred to register A when the IAP2 instruction is executed.
(4) Port D
D 0–D 7 are eight independent output ports.
■ Output of port D
Each pin of port D has an independent 1-bit wide output function. For output of ports D0–D7, select
one of port D with the register Y of the data pointer first.
● Data output from port D
Set the output level to the output latch with the SD and RD instructions.
The state of pin enters the high-impedance state when the SD instruction is executed.
The states of all port D enter the high-impedance state when the CLD instruction is executed.
The state of pin becomes “L” level when the RD instruction is executed.
The output structure is an N-channel open-drain.
Notes 1: When the SD and RD instructions are used, do not set “10002 ” or more to register Y.
2: Port D 6 is also used as X CIN, and port D7 is also used as XCOUT. Accordingly, when using
port D6 and D7 functions, set the clock control register MR2 to “0.”
4551 Group User’s Manual
2-3
APPLICATION
2.1 I/O pins
2.1.2 Related registers
(1) Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P1 0–P13 pull-up transistor and the ON/OFF of the keyon wakeup function.
Set the contents of this register through register A with the TPU0A instruction.
The contents of register PU0 is transferred to register A with the TAPU0 instruction.
Table 2.1.1 shows the pull-up control register PU0.
Table 2.1.1 Pull-up control register PU0
Pull-up control register PU0
PU03
PU02
PU01
PU00
at reset : 0000 2
at power down : state retained
R/W
Port P1 3
0
pull-up transistor control bit
Port P1 2
1
0
pull-up transistor control bit
1
Pull-up transistor ON, key-on wakeup function
Port P1 1
0
Pull-up transistor OFF, no key-on wakeup function
pull-up transistor control bit
1
Pull-up transistor ON, key-on wakeup function
Port P1 0
0
Pull-up transistor OFF, no key-on wakeup function
Pull-up transistor ON, key-on wakeup function
Pull-up transistor OFF, no key-on wakeup function
Pull-up transistor ON, key-on wakeup function
Pull-up transistor OFF, no key-on wakeup function
pull-up transistor control bit
1
Note: “R” represents read enabled, “W” represents write enabled.
(2) LCD control register L2
Register L2 is used to select the port P2 function or segment output pin function.
Set the contents of this register through register A with the TL2A instruction.
Table 2.1.2 shows the LCD control register L2.
Table 2.1.2 LCD control register L2
LCD control register L2
L23
P23/SEG 19 function switch bit
L22
P2 2/SEG 18 function switch bit
L21
P2 1/SEG 17 function switch bit
L20
P2 0/SEG 16 function switch bit
at reset : 1111 2
0
1
SEG 19
0
1
SEG 18
P22
0
SEG 17
1
P21
0
1
SEG 16
P23
P20
Note: “W” represents write enabled.
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4551 Group User’s Manual
at power down : state retained
W
APPLICATION
2.1 I/O pins
(3) Clock control register MR
The oscillation circuit control bit is assigned to the bit 2 of the clock control register MR.
Set the contents of this register through register A with the TMRA instruction.
The contents of register MR is transferred to register A with the TAMR instruction.
Table 2.1.3 shows the clock control register MR.
Table 2.1.3 Clock control register MR
Clock control register MR
MR 3
MR 2
MR 1
System clock (STCK) selection
bit
at reset : 10002
0
1
f(X CIN) oscillation circuit control 0
1
bit
f(XIN) oscillation circuit control bit
at power down : state retained
MR 0 = 0
f(XIN)
MR 0 = 1
f(XCIN)
MR 0 = 0
f(XIN)/4
MR 0 = 1
f(XCIN)/4
R/W
(X CIN) oscillation stop, ports D6, D7 selected
0
(X CIN) oscillation enabled, ports D6, D7 not selected
Oscillation enabled
1
Oscillation stop
0 f(XIN)
1 f(XCIN)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When setting ports, MR3 , MR 1, MR 0 are not used.
3: Do not stop the oscillation circuit selected with the clock selection bit (MR0).
Note the stop of the oscillation circuit selected with the clock selection bit (MR0) if the following
setting is performed.
Example 1: (MR 3MR 2MR 1MR 0) = ✕0✕1 (f(XCIN) selected, f(X CIN) oscillation stop)
Example 2: (MR 3MR 2MR 1MR 0) = ✕✕10 (f(XIN) selected, f(X IN) oscillation stop)
✕: “0” or “1.”
MR 0
Clock selection bit
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APPLICATION
2.1 I/O pins
2.1.3 Port application examples
(1) Key input by key scan
Key matrix can be set up by connecting keys externally because port D output structure is an Nchannel open-drain and port P0 has the pull-up resistor.
Outline: The connecting required external part is just keys.
Specifications: Port D is used to output “L” level and port P0 is used to input 16 keys. Multiple key
inputs are not detected.
Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing.
M34551
SW4
SW3
SW2
SW1
SW8
SW7
SW6
SW5
SW12
SW11
SW10
SW9
SW16
SW15
SW14
SW13
D0
D1
D2
D3
P00
P01
P02
P03
Fig. 2.1.1 Key input by key scan
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APPLICATION
2.1 I/O pins
Switch of key input selection port (D0→D1)
Waiting time for stabilizing until input
Reading of port (key input)
Key input cycle
High
D0
Low
High
D1
Low
High
D2
Low
High
D3
Low
IAP0
IAP0
Input of
SW1–SW4
Input of
SW5–SW8
IAP0
Input of
SW9–SW12
IAP0
Input of
SW13–SW16
IAP0
Input of
SW1–SW4
Note: Output from port D is high-impedance state.
Fig. 2.1.2 Input timing of key scan
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APPLICATION
2.1 I/O pins
2.1.4 Notes on use
(1) Note when an I/O port is used as an input port
Set the output latch to “1” and input the port value before input. If the output latch is set to “0,” “L”
level can be input.
(2) Noise and latch-up prevention
Connect an approximate 0.1 µF bypass capacitor directly to the VSS line and the VDD line with the
thickest possible wire at the shortest distance, and equalize its wiring in width and length.
The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the One Time PROM
version.
Connect the CNVSS/V PP pin to V SS through an approximate 5 kΩ resistor which is connected to the
CNV SS/V PP pin at the shortest distance.
(3) Note on multifunction
Port D 5 is also used as the INT pin.
Note that the port D 5 output function can be used even when INT pin function is selected.
(4) Connection of unused pins
Table 2.1.4 shows the connections of unused pins.
(5) SD, RD instructions
When the SD and RD instructions are used, do not set “10002” or more to register Y.
Table 2.1.4 connections of unused pins
Connection
Pin
Connect to V SS pin, or set the output latch to “0.”
D0 –D 4 , D 5/INT
Select D 6 and D 7 and connect to V SS , or set the output latch to “0” and open.
D6 /X CIN , D 7 /XCOUT
P20/SEG16–P23/SEG19 Select P2 and connect to V SS , or select segment output function and open.
Open.
CARR
Open.
SEG 0–SEG 15
Open.
COM0 –COM 3
Set the output latch to “1” and open.
P00 –P03
Open or connect to V SS (Note).
P10 –P13
Note: In order to connect ports P10–P1 3 to V SS , turn off their pull-up transistors (Pull-up control register
PU0i=“0”) by software. In order to make these pins open, turn on their pull-up transistors (register
PU0i=“1”) by software, or turn off their pull-up transistors (register PU0i=“0”) and set the output latch
to “0” (i = 0, 1, 2, or 3).
Be sure to select the key-on wakeup function and the pull-up function with every one port.
(Note in order to set the output latch to “0” and make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port
is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply
current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by
noise or a program run away (caused by noise).
(Note in order to connect unused pins to V SS or V DD)
• To avoid noise, connect the unused pins to V SS or V DD at the shortest distance using a thick wire.
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APPLICATION
2.2 Interrupts
2.2 Interrupts
The 4551 Group has three interrupt sources : external interrupt (INT), timer 1 interrupt and timer 2 interrupt.
This section describes individual types of interrupts, related registers, application examples using interrupts
and notes.
2.2.1 Interrupt functions
(1) External interrupt (INT)
The interrupt request occurs by the change of input level of INT pin.
The interrupt valid waveform can be selected by the bit 2 of the interrupt control register I1.
■ External interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the external interrupt occurs, the interrupt processing
is executed from address 0 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZ0 instruction is valid when the bit 0 of register V1 is set
to “0.”
(2) Timer 1 interrupt
The interrupt request occurs by the timer 1 underflow.
■ Timer 1 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 1 interrupt occurs, the interrupt processing
is executed from address 4 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set
to “0.”
(3) Timer 2 interrupt
The interrupt request occurs by the timer 2 underflow.
■ Timer 2 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 2 interrupt occurs, the interrupt processing
is executed from address 6 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set
to “0.”
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APPLICATION
2.2 Interrupts
2.2.2 Related registers
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable.
Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE
flag is cleared to “0” with the DI instruction.
When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are
disabled until the EI instruction is executed.
Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more
instruction.
(2) Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1.
Set the contents of this register through register A with the TV1A instruction.
In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A.
Table 2.2.1 shows the interrupt control register V1.
Table 2.2.1 Interrupt control register V1
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
1
Interrupt disabled (SNZT1 instruction is valid)
0
1
R/W
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt
enabled (SNZ0 instruction is invalid)
1
Note: “R” represents read enabled, and “W” represents write enabled.
V10
External 0 interrupt enable bit
0
(3) Interrupt request flag
The activated condition for each interrupt is examined. Each interrupt request flag is set to “1” when
the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt
enable bit.
Each interrupt request flag is cleared to “0” when either;
•an interrupt occurs, or
•the next instruction is skipped with a skip instruction.
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APPLICATION
2.2 Interrupts
(4) Interrupt control register I1
The interrupt valid waveform for INT pin is assigned to the bit 2 of register I1.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.2.2 shows the interrupt control register I1.
Table 2.2.2 Interrupt control register I1
Interrupt control register I1
I13
I12
Not used
Interrupt valid waveform for INT
pin selection bit(Note 2)
I11
Not used
I10
Not used
at reset : 00002
0
1
at power down : state retained
R/W
This bit has no function, but read/write is enabled.
0
Falling waveform (“L” level of INT pin is recognized with
the SNZI0 instruction)
1
Rising waveform (“H” level of INT pin is recognized with
the SNZI0 instruction)
0
1
This bit has no function, but read/write is enabled.
0
This bit has no function, but read/write is enabled.
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of D 5/INT pin, the external interrupt request flag (EXF0) may be set
to “1” when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of
register I1, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least
one instruction.
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APPLICATION
2.2 Interrupts
2.2.3 Interrupt application examples
(1) External interrupt
The INT pin is used for external interrupts, of which valid waveforms can be chosen, which can
recognize the change of both edges (“H”→“L” or “L”→“H”).
Outline: An external interrupt can be used by dealing with the change of edge (“H”→“L” or “L”→“H”)
in both directions as a trigger.
Specifications: An interrupt occurs by the change of an external signals edge (“H”→“L” or “L”→“H”).
Figure 2.2.1 shows an operation example of an external interrupt, and Figure 2.2.2 shows a setting
example of an external interrupt.
(2) Timer 1 interrupt
Constant period interrupts by a setting value to timer 1 can be used.
Outline: The constant period interrupts by the timer 1 underflow signal can be used.
Specifications: Prescaler and timer 1 divide the system clock frequency f(XIN) = 3.6 MHz, and the
timer 1 interrupt occurs every 1 ms.
Figure 2.2.3 shows a setting example of the timer 1 constant period interrupt.
(3) Timer 2 interrupt
Timer 2 is the fixed dividing frequency, and the constant period interrupts which the count source is
divided by 213 or 2 14 can be used.
Outline: The constant period interrupts by the timer 2 underflow signal can be used.
Specifications: Timer 2 divides the sub-clock frequency f(X CIN) = 32.768 kHz, and the timer 2
interrupt occurs every 0.5 sec.
Figure 2.2.4 shows a setting example of the timer 2 constant period interrupt.
INT valid waveform
Falling
Falling
Rising
Rising
Falling
Rising
“H”
D5/INT
“L”
Setting of valid waveform by I12
“1”
“0”
“H”
D5/INT
I12
“L”
“1”
“0”
Interrupt occurs after setting the valid waveform to “falling.”
The valid waveform of the next interrupt is set to “rising.”
When the interrupt which valid waveform is set to “rising” occurs,
the opposite of the above processing is performed.
Fig. 2.2.1 External interrupt operation example
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APPLICATION
2.2 Interrupts
➀ Disable Interrupts
External interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
b3
Interrupt control register V1
All interrupts disabled (DI instruction)
b0
✕ ✕ ✕ 0 External interrupt occur disabled (TV1A instruction)
➁ Set Port
Port used for external interrupt is set to input port.
Port D5 output latch “1”
Set to input (SD instruction)
➂ Set Valid Waveform
Valid waveform of INT pin is selected.
b3
b0
Interrupt control register I1 ✕ 1 ✕ ✕
b3
Rising waveform selected (TI1A instruction)
b0
Interrupt control register I1 ✕ 0 ✕ ✕
Falling waveform selected (TI1A instruction)
❈ Note when interrupt valid waveform is changed
When ➂ is executed, depending on the input state of INT pin, the interrupt request
flag EXF0 may be set to “1.”
Accordingly, insert the NOP instruction after the TI1A instruction.
➃ Clear Interrupt Request
External interrupt activated condition is cleared.
External interrupt request flag EXF0 “0”
Clear the external interrupt activated condition
(SNZ0 instruction)
❈ Note when interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
➄ Enable Interrupts
External interrupt which is temporarily disabled is enabled.
b3
b0
Interrupt control register V1 ✕ ✕ ✕ 1
Interrupt enable flag INTE “1”
External interrupt occur enabled (TV1A instruction)
All interrupts enabled (EI instruction)
External interrupt execution started
“✕” : it can be “0” or “1.”
Fig. 2.2.2 External interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
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APPLICATION
2.2 Interrupts
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
b3
All interrupts disabled ( DI instruction)
b0
Interrupt control register V1 ✕ 0 ✕ ✕ Timer 1 interrupt occur disabled ( TV1A instruction)
➁ Stop Timer Operation
Timer 1 operation is temporarily stopped.
b3
b0
Timer control register V1 ✕ ✕ ✕ 0
Timer 1 operation stop ( TW2A instruction)
➂ Set Timer Value
Timer 1 count time is set. (The formula is shown ✽A below.)
b3
b0
Timer control register W1 1 0 0 0
Timer 1 reload register R1 “4A16”
Prescaler divided by 4 selected ( TW1A instruction)
Timer count value 74 set ( T1AB instruction)
➃ Clear Interrupt Request
The timer 1 interrupt activated condition is cleared.
Clear the timer 1 interrupt activated condition
Timer 1 interrupt request flag T1F “0”
(SNZT1 instruction)
❈ Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
➄ Start Timer 1 Operation
The timer 1 operation which is temporarily stopped is restarted.
b3
b0
Timer control register W2 ✕ ✕ ✕ 1
Timer 1operation start ( TW2A instruction)
➅ Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled.
b3
b0
Interrupt control register V1 ✕ 1 ✕ ✕
Interrupt enable flag INTE “1”
Timer 1 interrupt occur enabled ( TV1A instruction)
All interrupts enabled ( EI instruction)
Constant period interrupt execution started
✽A The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 1ms are set as follows:
1ms = (3.6 MHz) – 1✕ 4 ✕ 3 ✕
4
✕
System clock Instruction Prescaler
clock
dividing
ratio
(74 + 1)
Timer 1
count
value
“✕” : it can be “0” or “1.”
Fig. 2.2.3 Timer 1 constant period interrupt setting example
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APPLICATION
2.2 Interrupts
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
b3
All interrupts disabled (DI instruction)
b0
Interrupt control register V1 0 ✕ ✕ ✕
Timer 1 interrupt occur disabled (TV1A instruction)
➁ Set Timer Value
Timer 2 count time is set. (Only when timer count value is 213or 214, the formula is shown ✽A below.)
b3
b0
When timer count value = 213, 0 1
✕
✕
Timer count value 213 set (TW2A instruction)
timer control register W2
b3
b0
When timer count value = 214,
14
timer control registerW2 ✕ 0 0 ✕ Timer count value 2 set (TW2A instruction)
➂ Reset Timer Value and Set Count Source
Timer 2 counter is initialized. (Initialization is performed only by setting W23 from 0 to 1.)
b3
Timer control register W2
This processing and setting timer value
shown ➁ can be executed simultaneously.
Timer control register W2
Timer 2 reset
b3
b0
1 ✕ ✕✕
b3
Timer control register W2
b0
0 ✕ ✕✕
b0
0 ✕ ✕✕
Timer 2 count source is returned to XCIN.
(TW2A instruction)
➃ Clear Interrupt Request
The timer 2 interrupt activated condition is cleared.
Clear the timer 2 interrupt activated condition
g0 h
Timer 2 interrupt request flag T2F “0”
(SNZT2 instruction)
❈ Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
➅ Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
b3
b0
Interrupt control register V1 1 ✕ ✕ ✕
Interrupt enable flag INTE “1”
Timer 2 interrupt occur enabled (TV1A instruction)
All interrupts enabled (EI instruction)
Constant period interrupt execution started
✽ A The timer 2 count value to make the interrupt occur every 0.5s is set as follows:
–1
14
0.5s = (32.768kHz) ✕ 2
Sub-clock
Timer 2 count value
“✕” : it can be “0” or “1.”
Fig. 2.2.4 Timer 2 constant period interrupt setting example
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APPLICATION
2.2 Interrupts
2.2.4 Notes on use
(1) Setting of external interrupt valid waveform
Depending on the input state of D5/INT pin, the external interrupt request flag (EXF0) may be set to
“1” when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register I1,
and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction.
(2) Multiple interrupts
Multiple interrupts cannot be used in the 4551 Group.
(3) Notes on interrupt processing
When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt
disable state). In order to enable the interrupt at the same time when system returns from the
interrupt, write EI and RTI instructions continuously.
(4) D 5/INT pin
The D 5/INT pin need not be selected the external interrupt input INT function or the normal output
port D5 function. However, the EXF0 flag is set to “1” when a valid waveform output from port D5
is input to INT pin even if it is used as an output port D5 .
(5) Power down instruction
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
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APPLICATION
2.3 Timers
2.3 Timers
The 4551 Group has an 8-bit timer with a reload register, a 4-bit timer and the 14-bit fixed dividing frequency
timer which has the watchdog timer function.
This section describes individual types of timers, related registers, application examples using timers and
notes.
2.3.1 Timer functions
(1) Timer 1
■ Timer operation
■ Carrier wave output auto-control function
(Refer to section “2.4 Carrier generating circuit” for details.)
(2) Timer 2
■ Timer operation
(Timer 2 has the function to return from clock operation mode (POF instruction execution))
■ Watchdog function
Watchdog timer provides a method to reset the system when a program runs wild.
When the WRST instruction is executed after system is released from reset, in this time, the
watchdog timer starts operating. System reset is performed if the WRST instruction is not performed
while timer 2 counts 2 13.
(3) Timer LC
■ LCD frame clock generating
2.3.2 Related registers
(1) Interrupt control register V1
The timer 1 interrupt enable bit is assigned to the bit 2, and the timer 2 interrupt enable bit is
assigned to the bit 3.
Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 2.3.1 shows the interrupt control register V1.
Table 2.3.1 Interrupt control register V1
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
1
0
1
0
R/W
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When timer is used, V1 0 is not used.
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APPLICATION
2.3 Timers
(2) Timer control register W1
The timer 1 count source selection bits are assigned to bits 0 and 1, and the prescaler dividing ratio
selection bit is assigned to the bit 2, and the prescaler control bit is assigned to the bit 3.
Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction
can be used to transfer the contents of register W1 to register A.
Table 2.3.2 shows the timer control register W1.
Table 2.3.2 Timer control register W1
Timer control register W1
W1 3
Prescaler control bit
W1 2
Prescaler dividing ratio selection
bit
W1 1
W1 0
at reset : 00002
at power down : 00002
0
Stop (prescaler state initialized)
1
Operating
0
Instruction clock (INSTCK) divided by 4
1
W11 W10
0
0
Timer 1 count source selection
0
1
bits
1
0
1
1
R/W
Instruction clock (INSTCK) divided by 8
Count source
Prescaler output (ORCLK)
Carrier output (CARRY)
Carrier output/2 (CARRY/2)
Note: “R” represents read enabled, and “W” represents write enabled.
(3) Timer control register W2
The timer 1 control bit is assigned to the bit 0, and timer 2 count value selection bits are assigned
to bits 1 and 2, and the timer 1 control bit is assigned to the bit 3.
Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction
can be used to transfer the contents of register W2 to register A.
Table 2.3.3 shows the timer control register W2.
Table 2.3.3 Timer control register W2
Timer control register W2
W23
W22
W21
W20
Timer 2 count source selection
bit
at reset : 10002
0
f(X CIN)
1
Prescaler output (ORCLK)
W22
0
Timer 2 count value selection bits 0
1
1
Timer 1 control bit
at power down : – – – 0 2
W21
0
1
0
1
0
Count source
Underflow occur every 214 count
Underflow occur every 213 count
Not available
Not available
Stop (timer 1 state retained)
Operating
1
Note: “R” represents read enabled, and “W” represents write enabled.
“–” represents state retained.
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R/W
APPLICATION
2.3 Timers
(4) Timer control register W3
The timer LC control bit is assigned to the bit 0, and timer LC count source selection bit is assigned
to the bit 1.
Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction
can be used to transfer the contents of register W3 to register A.
Table 2.3.4 shows the timer control register W3.
Table 2.3.4 Timer control register W3
Timer control register W3
W3 1
Timer LC count source selection
bit
W3 0
Timer LC control bit
at reset : 002
at power down : state retained
R/W
0
1
Bit 3 of timer 2 is output (timer 2 count source divided by 16)
0
Stop (timer LC state retained)
1
Operating
System clock (STCK)
Note: “R” represents read enabled, and “W” represents write enabled.
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APPLICATION
2.3 Timers
2.3.3 Timer application examples
(1) Timer operation: measurement of constant period
The constant period by the setting timer count value can be measured.
Outline: The constant period by the timer 1 underflow signal can be measured.
Specifications: Timer 1 and prescaler divides the system clock frequency f(X IN) = 3.6 MHz, and the
timer 1 interrupt request occurs every 4 ms.
Figure 2.3.2 shows the setting example of the constant period measurement.
(2) Timer operation: constant period counter by timer 2
The constant period by the setting timer count value can be measured.
Outline: The correct time can be measured and the clock which has high-accuracy can be set up
by using a 32.768 kHz quartz-crystal oscillator.
Specifications: Timer 2 divides the sub-clock frequency f(X CIN) = 32.768 kHz, and the timer 2
interrupt request occurs every 250 ms.
Figure 2.3.3 shows the setting example of constant period counter by timer 2.
(3) Watchdog timer
Watchdog timer provides a method to reset the system when a program run-away occurs.
In the 4551 Group, the bit 12 of timer 2 is used for the watchdog timer.
Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at
a certain cycle which consists of timer 2’s 8191 counts or less.
Outline: Execute the WRST instruction in timer 2’s 8192 count at the normal operation. If program
runs wild, the WRST instruction is never executed and system reset occurs.
Specifications: System clock frequency f(X IN) = 3.6 MHz, sub-clock frequency f(X CIN) = 32.768 kHz
are used, and program run-away is detected by executing the WRST instruction in
250 ms.
Figure 2.3.1 shows the watchdog timer function, and Figure 2.3.4 shows the example of watchdog
timer.
Timer 2 value
3FFF16
1FFF16
0000 16
“1”
WEF flag
WDF flag
“0”
“1”
“0”
“H”
Internal reset signal
“L”
WRST
instruction
execution
WRST
instruction
execution
Fig. 2.3.1 Watchdog timer function
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4551 Group User’s Manual
System reset
APPLICATION
2.3 Timers
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
All interrupts disabled ( DI instruction)
Interrupt enable flag INTE “0”
b3
b0
Interrupt control register V1 ✕ 0 ✕ ✕
Timer 1 interrupt occur disabled ( TV1A instruction)
➁ Stop Timer Operation
Timer 1 operation is temporarily stopped.
b3
b0
Timer control register W2 ✕ ✕ ✕ 0
Timer 1 operation stop ( TW2A instruction)
➂ Set Timer Value
Timer 1 count time is set. (The formula is shown ✽A below.)
b3
b0
Timer control register W1 1 1 0 0
Timer 1 reload register R1 “9516”
Prescaler divided by 8 selected ( TW1A instruction)
Timer count value 149 set ( T1AB instruction)
➃ Clear Interrupt Request
The timer 1 interrupt activated condition is cleared.
g0 timer
h
1 interrupt activated condition
Timer 1 interrupt request flag T1F “0” Clear the
(SNZT1 instruction)
❈ Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
➄ Start Timer 1 Operation
The timer 1 operation which is temporarily stopped is restarted.
b3
b0
Timer control register W2 ✕ ✕ ✕ 1
Timer 1 operation start ( TW2A instruction)
➅ Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled.
b3
b0
Interrupt control register V1 ✕ 1 ✕ ✕
Interrupt enable flag INTE “1”
Timer 1 interrupt occur enabled ( TV1A instruction)
All interrupts enabled ( EI instruction)
Constant period interrupt execution started
✽A The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 4ms are set as follows:
4ms = (3.6 MHz)
–1
✕4✕3
System clock
✕
Instruction
clock
8
✕
Prescaler
dividing
ratio
(149 + 1)
Timer 1
count
value
“✕” : it can be “0” or “1.”
Fig. 2.3.2 Constant period measurement setting example
4551 Group User’s Manual
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APPLICATION
2.3 Timers
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
b3
b0
Interrupt control register V1 0 ✕ ✕ ✕
Timer 2 interrupt occur disabled (TV1A instruction)
➁ Set Timer Value
13
14
Timer 2 count time is set. (Only when timer count value is 2 or 2 , the formula is shown ✽A below.)
13 b3
b0
When timer count value = 2 , ✕ 0 1 ✕
timer control register W2
14 b3
b0
When timer count value = 2 ,
✕0 0 ✕
timer control register W2
13
Timer count value 2 set (TW2A instruction)
14
Timer count value 2 set (TW2A instruction)
➂ Reset Timer Value and Set Count Source
Timer 2 counter is initialized. Initialization is performed only by setting W23 from 0 to 1.
b3
Timer control register W2
This processing and setting timer value
shown ➁ can be executed simultaneously.
Timer control register W2
Timer 2 reset
b3
b0
1 ✕✕ ✕
b3
Timer control register W2
b0
0 ✕✕ ✕
b0
0 ✕✕ ✕
Timer 2 count source is returned to XCIN.
➃ Clear Interrupt Request
The timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F “0”
g0 Clear
h
the timer 2 interrupt activated condition
(SNZT2 instruction)
❈ Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
➄ Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
b3
b0
Interrupt control register V1 1 ✕ ✕ ✕
Interrupt enable flag INTE “1”
Timer 2 interrupt occur enabled (TV1A instruction)
All interrupts enabled (EI instruction)
Constant period interrupt execution started
✽ A The timer 2 count value to make the interrupt occur every 0.25s is set as follows:
0.25s = (32.768kH z)
Sub-clock
–1
✕ 213
Timer 2 count value
“✕” : it can be “0” or “1.”
Fig. 2.3.3 Constant period counter by timer 2 setting example
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4551 Group User’s Manual
APPLICATION
2.3 Timers
➀ Set Timer 2 Count Source
Timer 2 countsource is set.
b3
b0
Timer control register W2 0 ✕ ✕ ✕
XCIN selected (TW2A instruction)
➁ Activate Watchdog Timer
Watchdog timer is activated.
Watchdog timer enable flag WEF “1”
Watchdog timer enable flag WEF set
(WRST instruction)
Main routine (every 20 ms)
WDF Flag Reset
Watchdog timer flag WDF is reset. “0”
g0 h
Watchdog timer flag WDF cleared
(WRST instruction)
Main routine execution
Repeat
Do not perform the interrupt processing for reset of watchdog timer flag WDF.
Interrupt may keep operating even when a program runs wild.
When going into RAM back-up mode
••
••
••
WRST;
WDF flag cleared
EPOF;
POF instruction enabled
POF2
Oscillation (RAM back-up mode)
stop
In the RAM back-up mode, the value of WDF flag is initialized.
However, when the WDF flag is “1,” at the same time, a microcomputer may be reset.
When the watchdog timer and RAM back-up mode are used, execute the WRST instruction
before system enters into the RAM back-up mode in order to initialize the WDF flag.
“✕” : it can be “0” or “1.”
Fig. 2.3.4 Watchdog timer setting example
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APPLICATION
2.3 Timers
2.3.4 Notes on use
(1) Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
(2) Count source
• Stop timer 1 or timer LC counting to change its count source.
• When timer 2 count source changes from f(XCIN ) to ORCLK (W23 = “0” → W2 3 = “1”), the count
value of timer 2 is initialized. However, when timer 2 count source changes from ORCLK to f(X CIN)
(W23 = “1” → W2 3 = “0”) or the same count source is set again (W2 3 = “0” → W23 = “0” or W2 3
= “1” → W23 = “1”), the count value of timer 2 is not initialized.
(3) Timer 2
Timer 2 has the watchdog timer function (WDT). When timer 2 is used as the WDT, note that the
processing to initialize the count value and the execution of the WRST instruction.
(4) Reading the count value
Stop the prescaler and then execute the TAB1 instruction to read timer 1 data.
(5) Writing to reload register R1
When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1
underflows.
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4551 Group User’s Manual
APPLICATION
2.4 Carrier generating circuit
2.4 Carrier generating circuit
The 4551 Group has a carrier generating circuit that generates the transfer waveform by dividing the system
clock (STCK) for each remote control carrier wave.
Also, the 4551 Group has the function to control the carrier wave output from port CARR by using timer 1.
This section describes carrier functions, related registers, application examples using each carrier output
and notes.
2.4.1 Carrier functions
(1) Carrier wave output
Carrier wave is selected by the carrier wave selection register C1.
Carrier output is started with the STCR instruction, and carrier output is stopped with the SPCR
instruction.
(2) Carrier wave output auto-control function
Timer 1 can auto-control the output enable/disable interval of port CARR carrier wave by setting
register C2.
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APPLICATION
2.4 Carrier generating circuit
2.4.2 Related registers
(1) Carrier wave selection register C1
The output waveform of carrier wave is selected.
Set the contents of this register through register A with the TC1A instruction.
Figure 2.4.1 shows the relationship between register C1 and carrier wave.
Carrier wave selection register C1
Register C1
Setting value
(at reset: 0 1 1 1 2, at power down: 0 1 1 1 2, W)
Output waveform
STCR instruction
0
0
0
Carrier wave
Frequency
C13 C12 C11 C10
0
SPCR instruction
Duty
“H”
“L”
1/3
STCK/24
0
0
0
1
“H”
“L”
0
0
1
0
“H”
“L”
1/2
1/4
STCK/16
0
0
1
1
“H”
“L”
0
1
0
0
“H”
“L”
0
1
0
1
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
1/2
STCK/2
“H”
“L”
1/2
No carrier wave
No available
“H”
“L”
“L” fixed
“H”
“L”
1/3
STCK/12
1
0
0
1
“H”
“L”
1/2
1
0
1
0
“H”
“L”
1/4
STCK/8
1
0
1
1
“H”
“L”
1
1
0
0
“H”
“L”
1/2
STCK
Note:“W” represents write enabled.
Fig. 2.4.1 Carrier wave selection register
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APPLICATION
2.4 Carrier generating circuit
(2) Carrier wave output control register C2
The carrier wave output auto-control bit is assigned to the bit.
Set the contents of this register through register A with the TC2A instruction.
Table 2.4.1 shows the carrier wave output control register C2.
Table 2.4.1 Carrier wave output control register C2
Carrier wave output control register C2
C20
Carrier wave output auto-control
bit
at reset : 02
at power down : 0 2
0
Auto-control output by timer 1 is invalid
1
Auto-control output by timer 1 is valid
W
Note: “W” represents write enabled.
(3) Carrier wave generating control flag CR
Execute the SPCR instruction to set the carrier wave generating control flag CR to “0.”
Execute the STCR instruction to set the carrier wave generating control flag CR to “1.”
Table 2.4.2 shows the carrier wave generating control flag CR.
Table 2.4.2 Carrier wave generating control flag CR
Carrier wave generating control flag CR
CR
Carrier wave generation control
at reset : 02
0
1
at power down : 02
W
Carrier wave generating stop (SPCR instruction)
Carrier wave generating start (STCR instruction)
Note: “W” represents write enabled.
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APPLICATION
2.4 Carrier generating circuit
2.4.3 Carrier wave output application examples
(1) Remote control waveform output by carrier wave output auto-control function
The carrier wave output auto-control function can be used to turn carrier wave ON/OFF automatically
by counting carrier waveform.
Outline: ➀ CARRY is selected as the timer 1 count source and port CARR can be controlled.
➁ Output of waveform can be controlled by the bit C2 0.
➂ OFF interval can be output.
Specifications: The 37.9 kHz carrier wave is output from port CARR by using system clock frequency
f(X IN) = 3.64 MHz.
Also, the timer 1 interrupt occurs, and at the same time, setting the next output
interval is performed.
Figure 2.4.2 and Figure 2.4.3 show the setting example of carrier wave auto-control, Figure 2.4.4
shows the setting example of carrier wave output interval.
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
b3
b0
Interrupt control register V1 ✕ 0 ✕ ✕ Timer 1 interrupt occur disabled (TV1A instruction)
➁ Stop Timer Operation and Carrier Operation
Timer 1 operation and carrier operation is temporarily stopped.
b3
b0
Timer control register W2 ✕ ✕ ✕ 0
Carrier wave generation control flag CR “0”
Timer 1 operation stopped (TW2A instruction)
Carrier wave generation stop (SPCR instruction)
➂ Change of Count Source
Timer 1 count source is changed.
b3
b0
Timer control register W1 ✕ ✕ 1 0
Count source CARRY selected (TW1A instruction)
➃ Set Timer Value
Timer 1 count time is set. (The formula is shown ✽A below.)
Reload register R1 “1416”
Timer count value 20 is set (T1AB instruction)
➄ Set Carrier Generation Circuit
Carrier wave frequency and duty ratio are set.
Carrier wave selectionr register C1
b3
b0
0 0 0 0
Frequency STCK/24, duty ratio 1/3 selected
(TC1A instruction)
Continue to Figure 2.4.3 on the next page.
Fig. 2.4.2 Carrier wave auto-control setting example 1
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APPLICATION
2.4 Carrier generating circuit
From preceding Figure 2.4.2.
➅ Set Carrier Wave Output Auto-control
Carrier wave output auto-control is set to be valid.
Carrier wave output cotrol register C2 0 “1”
Auto-control valid by timer 1 ( TC2A instruction)
➆ Clear Interrupt Request
The timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F “0” Clear the timer 1 interrupt activated condition
(SNZT1 instruction)
❈ Note when the interrupt request is cleared
When ➆ is executed, considering the skip of the next instruction according to the
interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
➇ Start Timer 1 Operation
The timer 1 operation which is temporarily stopped is restarted.(Timer is stopped because count
source is not operating.)
b3
Timer control register W2
b0
✕ ✕ ✕ 1 Timer 1 operation start ( TW2A instruction)
➈ Enable Interrupts
Timer 1 interrupt which is temporarily disabled is enabled.
b3
b0
Interrupt control register V1 ✕ 1 ✕ ✕ Timer 1 interrupt occur enabled ( TV1A instruction)
➉ Start Carrier Output
Carrier output is started. (In this time, timer 1 operation is started simultaneously.)
Carrier wave generating control flag CR “1”
Carrier wave generating started ( STCR instruction)
Carrier output started
Setting the Next Output Waveform
11
Set Next Waveform Data
The next carrier output length is set to bit C2 0 and reload register R1.
Interrupt occurs
12
Set Next Waveform Data
The next carrier output length is set to bit C2 0 and reload register R1.
Interrupt occurs
12
Refer to Figure 2.4.4 for the detail
of setting output data.
repeated
✽A The carrier wave which duty ratio is 1/3 is output with a 3.64 MHz oscillator for the 0.55 ms.
8.77 µs
37.9 kHz = 3.64 MHz ✕ 1/4 ✕ 1/24
System clock
26.3 µs
Carrier wave
dividing ratio
-1
0.55 ms = (37.9 kHz) ✕ (20+1)
Carrier wave
frequency
0.55 ms
Timer 1 count value
“✕” : it can be “0” or “1.”
Fig. 2.4.3 Carrier wave auto-control setting example 2
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APPLICATION
2.4 Carrier generating circuit
Timer 1 start
▼
Timer 1 underflow
Reload register R1
a
a
a
a
a
a
a
a
b
c
d
aa
a
a
a
a
a
b
c
d
a
a
b
c
d
a
C2 0
Port CARR output
16a
➀ ➁
➂
8a
➃
➄
➅
➆
➇
▲
Carrier wave output start ( STCR)
➀ Initial value “a” is set to timer 1.
➁ The carrier wave output is started with the STCR instruction.
C20 is set to “0” to continue the carrier wave output.
➂ After timer 1 underflow is counted to 15 times by software, C20 is set to “1.”
➃ After CARR output is turned OFF by timer 1 underflow, C20 is set to “0.”
➄ After timer 1 underflow is counted to 7 times by software, C20 is set to “1.”
➅ The next CARR OFF interval “b” is set to reload register R1.
➆ The next CARR output interval “c” is set to reload register R1.
➇ The next CARR OFF interval “d” is set to reload register R1.
➈ The next CARR output interval “a” is set to reload register R1.
Fig. 2.4.4 Carrier wave output interval setting example
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4551 Group User’s Manual
➈
a
APPLICATION
2.4 Carrier generating circuit
(2) Carrier wave generating by software
Carrier wave generating can be output by software count.
Outline: The carrier wave generating circuit is set to “no carrier wave” and carrier wave is generated
by software.
Specifications: The 37.9 kHz carrier wave is generated by using main clock frequency f(X IN) = 3.64
MHz.
Figure 2.4.5 shows the generating example of carrier wave by software.
➀ Set Carrier Wave Output Auto-control
Carrier wave output auto-control is set to be invalid.
Carrier wave output control register C20
Auto-control by timer 1 invalid (TC2A instruction)
“0”
➁ Set Carrier Generation Circuit
Carrier wave frequency and duty ratio is set.
b3
b0
Carrier wave selection register C1 0 1 0 1 No carrier wave (TC1A instruction)
➂ Start Carrier Output
Carrier output is started.
1.10 µs
1 instruction (3.30µs)
STCK
CARR output
Description
instruction
example
8.79 µs
STCR NOP
17.58 µs
NOP SPCR NOP
NOP
NOP
NOP
STCR NOP
NOP SPCR NOP
Fig. 2.4.5 Carrier wave by software generating example
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APPLICATION
2.4 Carrier generating circuit
2.4.4 Notes on use
(1) Note on the carrier generating circuit stop
In order to stop the carrier wave which has the cycle longer than that of the instruction clock with
the SPCR instruction, stop it at the point when the carrier wave outputs “L” level in the SPCR
instruction execution cycle.
If this condition is not satisfied, the last “H” output interval of carrier wave is shortened.
(2) Notes when using the carrier wave output auto-control function
● Execute the STCR instruction after setting the timer 1 and register C2 in order to start the carrier
generating circuit operation.
● Stop the timer 1 (W20=“0”) after stopping the carrier generating circuit (SPCR instruction executed)
while the carrier wave output is disabled in order to stop the carrier wave output auto-control
operation.
● If the carrier wave output auto-control function is invalidated (C20 =“0”) while the carrier wave
output is auto-controlled, the output of port CARR retains the state when the auto-control is
invalidated regardless of timer 1 underflow. This state can be terminated by timer 1 stop (W20=“0”).
When the carrier wave output auto-control function is validated (C20=“1”) again after it is invalidated
(C20=“0”), the auto-control of carrier wave output is started again when the next timer 1 underflow
occurs. However, when the carrier wave output auto-control bit is changed during timer 1 underflow,
the error-operation may occur.
● Use the carrier wave or the carrier wave divided by 2 as the timer 1 count source when the carrier
wave output auto-control function is selected.
If the ORCLK is used as the count source, a hazard wave may occur in port CARR output because
ORCLK is not synchronized with the carrier wave.
● When “no carrier wave” is selected with register C1 ((C1 3 C1 2 C1 1 C1 0 ) = (0101), (1101)), the
disable/enable of the carrier wave output cannot be controlled by the carrier wave output autocontrol function.
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4551 Group User’s Manual
APPLICATION
2.5 LCD function
2.5 LCD function
The 4551 Group has an LCD (Liquid Crystal Display) controller/driver.
4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using
these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display.
This section describes the LCD operation description, related registers, application examples using the LCD
and notes.
2.5.1 Operation description
(1) LCD duty and bias control
Table 2.5.1 shows the duty and maximum number of displayed pixels. Use bits 0 and 1 of LCD
control register (L1) to select the proper display method for the LCD panel being used. Also, when
using segment pins are 19 or less, SEG 16 –SEG 19 can be used as an I/O port with register L2.
Table 2.5.1 Duty and maximum number of displayed pixels
Maximum number
Used COM pins
Duty Bias
of displayed pixels
1/2 1/2
1/3 1/3
1/4 1/3
Note: Leave
COM 0, COM 1 (Note)
COM0 –COM2 (Note)
COM0 –COM3 (Note)
80 segments
unused COM pins open.
40 segments
60 segments
(2) LCD drive timing
The frequency (F) of the LCD clock generating the LCD drive timing and frame frequency are shown
below. Figure 2.5.1 shows the structure of the LCD clock circuit.
● When the prescaler output (ORCLK) is used for the timer 2 count source (W2 3 = “1”)
F = ORCLK ✕
➀
1
16
✕
1
✕
LC + 1
➁➂
➃
1
2
➄
● When f(X CIN) is used for the timer 2 count source (W2 3 = “0”)
F = f(X CIN)
✕
➀
1
16
✕
1
1
✕
LC + 1
2
➁➂
➃
➄
The frame frequency for each display method can be obtained by the following formula.
Frame frequency =
F
n
Frame period = n
F
(Hz)
(s)
[F: Frame frequency, 1/n: Duty]
Timer 2
(Note 1)
➀
W23
XCIN
0
ORCLK
1
➁
STCK
➂ (Note 2) W30
W31
0
1
➃
Timer LC
1
1/16
➄
1/2
LCD clock
0
Notes 1: Count source is stopped by clearing W30 to “0.”
2: When the LCD function is used, set W31 to “0.”
Fig. 2.5.1 LCD clock control circuit structure
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APPLICATION
2.5 LCD function
(3) LCD display method
The 4551 Group has the LCD RAM area for the LCD display.
When “1” is written to a bit in the LCD RAM data, the display pixel which correspond to the bit
automatically turns on.
Figure 2.5.2 shows the LCD RAM map.
Z
X
Bit
Y
8
9
10
11
12
13
14
15
COM
Note:
1
1
0
3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM3
2
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM2
1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM1
0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM0
3
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM3
2
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM2
1
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM1
0
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM0
3
SEG16
SEG17
SEG18
SEG19
2
2
1
SEG16 SEG16
SEG17 SEG17
SEG18 SEG18
SEG19 SEG19
0
SEG16
SEG17
SEG18
SEG19
COM3 COM2 COM1 COM0
LCD display RAM is not assigned.
Fig. 2.5.2 LCD RAM map
2.5.2 Related registers
(1) LCD control register L1
The LCD duty and bias selection bits are assigned to bits 0 and 1. The LCD on/off bit is assigned
to the bit 2.
Set the contents of this register through register A with the TL1A instruction. The TAL1 instruction
can be used to transfer the contents of register L1 to register A.
Table 2.5.2 shows the LCD control register L1.
Table 2.5.2 LCD control register L1
LCD control register L1
L1 3
Not used
L1 2
LCD on/off bit
L1 1
at reset : 00002
0
at power down : state retained
This bit has no function, but read/write is enabled.
1
0
Off
1
On
L11 L10
0
0
LCD duty and bias selection bits 0
1
1
2-34
Bias
Duty
Not available
1/2
0
1/3
1
1
1/4
Note: “R” represents read enabled, and “W” represents write enabled.
L1 0
R/W
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APPLICATION
2.5 LCD function
(2) LCD control register L2
Port P2 function and segment pin function of pins P2 0/SEG16–P23/SEG19 can be switched by setting
register L2.
Set the contents of this register through register A with the TL2A instruction.
Table 2.5.3 shows the LCD control register L2.
Table 2.5.3 LCD control register L2
LCD control register L2
L2 3
P23/SEG 19 function switch bit
L2 2
P2 2/SEG 18 function switch bit
L2 1
P2 1/SEG 17 function switch bit
L2 0
P2 0/SEG 16 function switch bit
at reset : 11112
0
1
SEG 19
0
SEG 18
1
P2 2
0
SEG 17
1
P2 1
SEG 16
0
1
at power down : state retained
W
P2 3
P2 0
Note: “W” represents write enabled.
(3) Timer control register W3
The timer LC control bit is assigned to the bit 0, and the timer LC count source selection bit is
assigned to the bit 1.
When the LCD display function is used, set the bit 1 to “0.”
Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction
can be used to transfer the contents of register W3 to register A.
Table 2.5.4 shows the timer control register W3.
Table 2.5.4 Timer control register W3
Timer control register W3
W3 1
Timer LC count source selection
bit
W3 0
Timer LC control bit
at reset : 002
at power down : state retained
R/W
0
Bit 3 of timer 2 is output (timer 2 count source divided by 16)
1
System clock (STCK)
0
Stop (timer LC state retained)
Operating
1
Note: “R” represents read enabled, “W” represents write enabled.
4551 Group User’s Manual
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APPLICATION
2.5 LCD function
2.5.3 LCD application examples
(1) LCD display
LCD display function can be used to display 80 pixels (maximum 4 common ✕ 20 segment).
Outline: LCD can be displayed easily by using the LCD display function.
Specifications: 1/4 duty and 1/3 bias LCD is displayed by using LCD display panel example. Timer
2 is used for the LCD clock source, the sub-clock f(XCIN) = 32.768 kHz is used for
the timer 2 clock source, and the frame frequency is set to 85 Hz.
Figure 2.5.3 shows the LCD display panel example, Figure 2.5.4 shows the segment assignment example,
Figure 2.5.5 shows the LCD RAM assignment example, and Table 2.5.5 shows the frame frequency.
Every
Program Su. Mo. Tu. We. Th. Fr. Sa. weeks SP EP
Start Stop
BS
A.M.
CH
P.M.
Fig. 2.5.3 LCD display panel example
Every
Program Su. Mo. Tu. We. Th. Fr. Sa. weeks SP EP
Start Stop
BS
A.M.
P.M.
CH
➀
➁
➂
➃
➄
➅
➆
➇
Fig. 2.5.4 Segment assignment example
Z
X
Y
8
9
10
11
12
13
14
15
COM
Note:
1
0
Bit
a
1
2
3
2
1
0
3
2
1
0
➀-g
➁-g
➂-g
➃-g
➄-g
➅-g
➆-g
➇-g
➀-e
➁-e
➂-f
➃-e
➄-e
➅-e
➆-e
➇-e
➀-d
➁-d
➂-d
➃-d
➄-d
➅-d
➆-d
➇-d
➀-c
➁-c
➂-c
➃-c
➄-c
➅-c
➆-c
➇-c
Start
Stop
➀-f
➁-f
➂-f
➃-f
➄-f
➅-f
➆-f
➇-f
➀-b
➁-b
➂-b
➃-b
➄-b
➅-b
➆-b
➇-b
➀-a
➁-a
➂-a
➃-a
➄-a
➅-a
➆-a
➇-a
•
•
Unused
•
•
Unused
Unused
Unused
3
We.
Every
weeks
BS
1
0
Mo.
Su.
Fr.
Tu.
EP
SP
A.M. Program
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
LCD display RAM is not assigned.
Fig. 2.5.5 LCD RAM assignment example
2-36
2
Tu.
Sa.
CH
P.M.
4551 Group User’s Manual
f
g
e
d
b
c
APPLICATION
2.5 LCD function
Initialization
➀ Operate Timer 2
(Refer to section “2.3 Timer.”)
Timer 2 count source is set to f(XCIN).
➁ Set SEG16–SEG19
P20/SEG16–P23/SEG19 are set to output.
b3
b0
LCD control register L2 0 0 0 0 SEG16–SEG19 selected (TL2A instruction)
➂ Stop Timer LC
Timer LC operation is stopped.
b1 b0
✕ 0 Timer LC stopped (TW3A instruction)
Timer control register W3
➃ Set Timer LC
Timer LC value is set. (The formula is shown ✽A below.)
Timer LC reload register RLC
Timer LC TLC “216” Timer count value 2 is set. (TLCA instruction)
➄ Initialization of LCD Display RAM
LCD display RAM is initialized.
LCD display RAM
Initial data is set.
➅ Set LCD Display Method
LCD duty and bias are set.
b3
b0
LCD control register L1 ✕ ✕ 1 1
1/4 duty and 1/3 bias set. (TL1A instruction)
➆ Set Timer LC Count Source
Timer LC count source is changed.
b1 b0
Timer control register W3
Count source is set to bit 3 of timer 2 .
0 1 Timer LC start (TW3A instruction)
➇ Display LCD
LCD display function is set to be valid.b3
b0
LCD control register LC ✕ 1 ✕ ✕ LCD turned ON (TL1A instruction)
to normal program
Display changed by rewriting LCD display RAM
✽ A The timer LC count value when the frame frequency is set to 85.3 Hz is set as follows:
1
1
1
1
85.3 Hz = (32.768 kHz) ✕
✕
✕
✕
2
4
16
(2+1)
Sub-clock
Bit 3 of
Timer
Duty
timer 2
LC
ratio
“✕” : it can be “0” or “1.”
Fig. 2.5.6 Initial setting example
4551 Group User’s Manual
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APPLICATION
2.5 LCD function
Table 2.5.5 Frame frequency
LCD clock = X CIN : 32.768 kHz
LCD clock = ORCLK: 910 kHz/12 LCD clock = ORCLK: 910 kHz/24
or
or
= ORCLK:3.64 MHz/48
= ORCLK:3.64 MHz/96
LCD timer
Duty
Duty
Duty
LCD timer
LCD timer
1/2
1/3
1/4
value
1/2
1/3
1/4
value
1/2
1/3
1/4
value
512 Hz 341 Hz 256 Hz
0
1185 Hz 790 Hz 592 Hz
0
592 Hz 395 Hz 296 Hz
0
256 Hz 170 Hz 128 Hz
1
592 Hz 395 Hz 296 Hz
1
296 Hz 197 Hz 148 Hz
1
171 Hz 114 Hz 85 Hz
2
395 Hz 263 Hz 197 Hz
2
197 Hz 132 Hz 99 Hz
2
128 Hz 85 Hz 64 Hz
3
296 Hz 197 Hz 148 Hz
3
148 Hz 99 Hz 74 Hz
3
102 Hz 68 Hz 51 Hz
4
237 Hz 158 Hz 118 Hz
4
118 Hz 79 Hz 59 Hz
4
85 Hz 57 Hz 43 Hz
5
197 Hz 132 Hz 99 Hz
5
99 Hz 66 Hz 49 Hz
5
73 Hz 49 Hz 37 Hz
6
169 Hz 113 Hz 85 Hz
6
85 Hz 56 Hz 42 Hz
6
64 Hz 42 Hz 32 Hz
7
148 Hz 99 Hz 74 Hz
7
74 Hz 49 Hz 37 Hz
7
57 Hz 38 Hz 28 Hz
8
131 Hz 88 Hz 66 Hz
8
66 Hz 44 Hz 33 Hz
8
51 Hz 34 Hz 27 Hz
9
118 Hz 79 Hz 59 Hz
9
59 Hz 39 Hz 30 Hz
9
47 Hz 31 Hz 23 Hz
10
108 Hz 72 Hz 54 Hz
10
54 Hz 36 Hz 27 Hz
10
43 Hz 28 Hz 21 Hz
11
99 Hz 66 Hz 49 Hz
11
49 Hz 33 Hz 25 Hz
11
39 Hz 26 Hz 20 Hz
12
91 Hz 61 Hz 46 Hz
12
46 Hz 30 Hz 23 Hz
12
37 Hz 24 Hz 18 Hz
13
85 Hz 56 Hz 42 Hz
13
42 Hz 28 Hz 21 Hz
13
34 Hz 23 Hz 17 Hz
14
79 Hz 53 Hz 39 Hz
14
39 Hz 26 Hz 20 Hz
14
32 Hz 21 Hz 16 Hz
15
74 Hz 49 Hz 37 Hz
15
37 Hz 25 Hz 18 Hz
15
Note: Values in the table shows the frame frequency (however, the values are rounded off to the decimal
points).
2.5.4 Notes on use
(1) Timer LC count source
Stop each timer counting to change timer LC count source.
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4551 Group User’s Manual
APPLICATION
2.6 Power down function
2.6 Power down function
The 4551 Group has the clock operation mode and RAM back-up mode for the power down function. The
4551 Group enters 12 kinds of state which includes the reset state to reduce the power dissipation. Figure
2.6.1 shows the state transition, and Figure 2.6.2 shows the oscillation stabilizing time.
In this section, the clock control function, each power down function, related register and application example
for the power down function are described.
Reset
System clock;
f(XIN)/4
MR=(1100 2)
MR3 ← 1
Return input 1, 2
D,H
(Stabilizing time c )
(Note 1)
(Note 2)
MR0 ← 0
M
1
MRR0 ←
0← 0
R
←
3
M R0
← 0
1
M
MR
1
←
0
3
MR 0 ←
R
←
M 3
(Note 2) 3 ← 1
MR
0
MR2 ← 0
F
f(XIN):Oscillation
f(XCIN):Oscillation
System clock;
f(XIN)
MR=(0100 2)
C
M
MR R1 ←
(S
3
tab
0
iliz ←
1
ing
tim
e
1
c)
1← 1
MR 3 ←
MR
0
1← 0
MRR3 ←g time
M in
iliz
ab
(St
MR
MR 1 ←
3
← 1
0
System clock;
f(XCIN)
MR=(0101 2)
c)
D
(Stabilizing time c )
MR3 ← 0
H
f(XIN):Stop
f(XCIN):Oscillation
System clock;
f(XCIN)/4
MR=(1111 2)
MR3 ← 1
MR3 ← 0
Return input 1
A,E
(Stabilizing time a )
RAM
back-up
mode
f(XIN):Stop
f(XCIN):Stop
POF2 execution
B,F
Return input 1
B,F
(Stabilizing time a )
POF2 execution
f(XIN):Oscillation
f(XCIN):Oscillation
MR3 ← 1
A,E
(Note 2)
G
System clock;
f(XCIN)/4
MR=(1101 2)
POF execution
D,H
MR3 ← 0
f(XIN):Oscillation
f(XCIN):Oscillation
MR1 ← 1
(Stabilizing time c )
(Note 1)
d)
MR1 ← 1
Return input 1, 2
C,G
tim
MR1 ← 0
POF execution
C,G
ing
e
(
IN):Oscillation
MR1 ← 0
f(XIN):Stop
f(XCIN) :
Oscillation
liz
iliz
ab
St
f(XCIN):Oscillation
Clock
operating
mode
0
2← 0
MRR3 ←
M
M
MR R3 ←
3
← 1
d )(S
tab
0
i
K
System clock;
f(XIN)
MR=(0000 2)
MR0 ← 1
1
2← 1
MRR3 ← ime
t
M
ing
(Stabilizing time c )
B,F
(Stabilizing time a )
f(X
MR0 ← 1
Return input 1, 2
J
M
MRR2 ←
2
← 0
1
(Note 2)
B
POF execution
B,F
MR3 ← 0
MR0 ← 0
(Note 2)
f(XIN):Oscillation
f(XCIN):Stop
MR2 ← 1
System clock;
f(XIN)/4
MR=(1000 2)
MR2 ← 0
f(XIN):Stop
f(XCIN):Stop
MR3 ← 1
MR2 ← 1
(Stabilizing time a )
Clock
operating
mode
POF2 execution
E
f(XIN):Oscillation
f(XCIN):Stop
(Stabilizing time d )
Return input 1
A,E
A
I
(Stabilizing time d )
POF execution
A,E
f(XIN):Stop
f(XCIN):Oscillation
System clock;
f(XCIN)
MR=(0111 2)
C,G
Return input 1
C,G
(Stabilizing time b )
POF2 execution
D,H
Return input 1
D,H
(Stabilizing time b )
Stabilizing time a : An interval required to stabilize the f(X IN) oscillation is automatically generated by hardware.
Stabilizing time b : An interval required to stabilize the f(X CIN) oscillation is automatically generated by hardware.
Stabilizing time c : Generate an interval required to stabilize the f(X IN) oscillation in state C or G by software at the
transition D →C, D→G, H→C, H→G, J→C, or J→G.
Stabilizing time d : Generate an interval required to stabilize the f(X CIN) oscillation in state B, F by software at the
transition A →B, E→F, A→F, or E→B.
Return input 1: External wakeup signal (P0 0–P0 3, P1 0–P1 3)
Return input 2: Timer 2 interrupt request flag
Notes 1. MR 3=“1”→The microcomputer starts its operation after counting f(X CIN) clock signal 59 to 70 times.
MR 3=“0”→The microcomputer starts its operation after counting f(X CIN) clock signal 32 to 43 times.
2. When the following 2 conditions are satisfied, the transition A →E, B→F, A→F, C→F, G→F represented
by “
” can be executed.
(1) V DD = 2.2 V to 5.5 V (One Time PROM version: V DD = 2.5 V to 5.5 V), f(X IN) ≤ 1.0 MHz
(2) V DD = 4.5 V to 5.5 V, f(X IN) ≤ 2.0 MHz
Fig. 2.6.1 State transition
4551 Group User’s Manual
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APPLICATION
2.6 Power down function
● Oscillation stabilizing time a
f(XIN)
(Note)
f(XIN) is counted 10757 to 10786 times.
Software start
(address 0 in page 0)
Oscillation condition satisfied
● Oscillation stabilizing time b
f(XCIN)
(Note)
f(XIN) is counted 10757 to 10786 times.
Oscillation condition satisfied
Software start
(address 0 in page 0)
● Oscillation stabilizing time c (software operating)
f(XIN)
f(XCIN)
f(XIN) oscillation
f(XIN) available
stabilizing time is
generated by software.
Oscillation condition satisfied
● Oscillation stabilizing time c (when returning from clock operating mode to state C, G)
f(XIN)
f(XCIN)
MR3=“1”: f(XCIN) is counted 59 to 70 times. f(XIN) oscillation wait f(XIN) available
MR3=“0”: f(XCIN) is counted 32 to 43 times. time by software
Software start
(address 0 in page 0)
Return input
● Oscillation stabilizing time d
f(XIN)
f(XCIN)
f(XCIN) oscillation
f(XCIN) available
stabilizing time is
generated by software.
Oscillation condition satisfied
Note : Time until 4551 Group recognize oscillation.
expresses system clock.
Fig. 2.6.2 Oscillation stabilizing time in each mode
2-40
4551 Group User’s Manual
APPLICATION
2.6 Power down function
2.6.1 Clock control function
The 4551 Group can reduce the power dissipation by controlling oscillation with the clock control register MR.
Refer to section “3.1 Electrical characteristics” for the oscillation frequency and power dissipation.
In Figure 2.6.1, directions in which state transition can be executed are expressed by the arrow. For
example, execute the transition A → B → ((X CIN ) oscillation stabilizing wait) → G → H to execute the
transition from the state A (MR3MR2MR 1MR0 = 1000) after reset to the state H (MR3MR2MR 1MR0 = 0111).
Note: Do not stop the oscillation circuit selected by clock selection bit (MR 0).
Note the stop of the oscillation circuit selected with the clock selection bit (MR 0) if the following
setting is performed.
Example 1: (MR3MR 2MR 1MR 0) = (✕0✕1) (f(XCIN ) selected, f(XCIN ) oscillation stop)
Example 2: (MR3MR 2MR 1MR 0) = (✕✕10) (f(X IN) selected, f(XIN) oscillation stop)
✕: “0” or “1.”
2.6.2 Power down function
When the POF instruction or POF2 instruction is executed just after the EPOF instruction, system enters
the power down state. Table 2.6.1 shows the internal state at each mode. Also, Table 2.6.2 shows the
return source from this state.
(1) Clock operating mode
In this mode, current dissipation can be reduced by stopping XIN-XOUT oscillation and system clock
with the states of RAM, reset circuit, XCIN –XCOUT oscillation, LCD display and timer 2 retained.
(2) RAM back-up mode
As oscillation stops with RAM, the state of reset circuit retained, current dissipation can be reduced
without losing the contents of RAM.
4551 Group User’s Manual
2-41
APPLICATION
2.6 Power down function
Table 2.6.1 Functions and states retained at RAM back-up mode and the clock operating mode
Clock operating
Function
RAM back-up
Program counter (PC), registers A, B,
✕
✕
Contents of RAM
Port level
O
O
O
O
Clock control register MR
O
O
Timer control register W1
✕
✕
Timer control registers W2, W3
O
O
Interrupt control register V1
✕
O
✕
O
✕
✕
LCD display function
O
(Note 3)
LCD control registers L1, L2
O
O
Timer LC
O
(Note 4)
Timer 1 function
✕
O
✕
O
✕
✕
carry flag (CY), stack pointer (SP) (Note 2)
Interrupt control register I1
Carrier wave control registers and flag (C1, C2, CR)
Timer 2 function
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
✕
✕
Timer 2 interrupt request flag (T2F)
O
O
Watchdog timer flag (WDF)
O
✕
Watchdog timer enable flag (WEF)
O
✕
O
✕
Interrupt enable flag (INTE)
General-purpose register V2
✕
✕
Notes 1: “O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at power down, and set an initial value
after returning from power down state.
2: The stack pointer (SP) points the level of the stack register and is initialized to “1112” at power down.
3: LCD is turned off.
4: The state of timer is undefined.
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4551 Group User’s Manual
APPLICATION
2.6 Power down function
Table 2.6.2 Return source and return condition
External wakeup
signal
Return source
Ports P0, P1
Return condition
Remarks
Returns by an external falling Port P0 shares the falling edge detection circuit with
edge input (“H”→“L”).
port P1. The key-on wakeup function of port P0 is always
valid. The only key-on wakeup function of the port P1
bit of which the pull-up transistor is turned on is valid.
Set all the port using the key-on wakeup function to “H”
level before going into the power down state.
Timer 2 interrupt Returns by timer 2 underflow The timer 2 interrupt request flag (T2F) can be used
and setting T2F flag to “1.” only when system returns from the clock operating mode
request flag
(POF instruction execution). However, if the POF and
POF2 instructions are executed while the T2F flag = “1”,
its operation is recognized as the return condition and
system returns from the clock operating mode.
Note: P1 pin has the pull-up transistor which can be turned on/off by software.
(3) Start condition identification
When system returns from both power down and reset, software is started from address 0 in page
0.
The start condition (warm start or cold start) can be identified by examining the state of the power
down flag (P) with the SNZP instruction. Also, warm start condition (timer 2 or external wakeup
signal) can be identified by the state of the T2F flag. Table 2.6.3 shows the start condition identification,
and Figure 2.6.3 shows the start condition identified example.
Table 2.6.3 Start condition identification
Return condition
T2F flag
P flag
External wakeup signal input
1
1
Timer 2 interrupt request flag
1
1
Reset
0
0
Software start
P = “1”
?
No
Yes
Yes
Cold start
T2F = “1”
?
No
Return by timer 2
underflow
Return by external
wakeup signal
Fig. 2.6.3 Start condition identified example
4551 Group User’s Manual
2-43
APPLICATION
2.6 Power down function
2.6.3 Related register
(1) Clock control register MR
Clock control register MR controls the system clock.
Set the contents of this register through register A with the TMRA instruction. The TAMR instruction
can be used to transfer the contents of register MR to register A.
Table 2.6.4 shows the clock control register MR.
Table 2.6.4 Clock control register MR
Clock control register MR
at reset : 10002
0
System clock (STCK) selection
bit
MR 3
1
f(XCIN) oscillation circuit control
bit
MR 2
MR 1
f(XIN) oscillation circuit control bit
MR 0
Clock selection bit
at power down : state retained
MR0=0
f(XIN)
MR0=1
f(XCIN)
MR0=0
f(XIN)/4
R/W
MR0=1
0
f(XCIN)/4
f(XCIN ) oscillation stop, ports D6 and D 7 selected
1
f(XCIN) oscillation enabled, ports D6 and D7 not selected
0
Oscillation enabled
1
0
Oscillation stop
f(XIN)
1
f(XCIN)
Note: “R” represents read enabled, and “W” represents write enabled.
(2) Pull-up control register PU0
Pull-up control register PU0 controls the pull-up function and key-on wakeup function.
Set the contents of this register through register A with the TPU0A instruction. The TAPU0 instruction
can be used to transfer the contents of register PU0 to register A.
Table 2.6.5 shows the pull-up control register PU0.
Table 2.6.5 Pull-up control register PU0
Pull-up control register PU0
PU03
PU02
PU01
PU00
at reset : 00002
at power down : state retained
Port P1 3 pull-up transistor
0
Pull-up transistor OFF, no key-on wakeup
control bit
Port P1 2 pull-up transistor
1
0
Pull-up transistor ON, key-on wakeup
control bit
1
Pull-up transistor ON, key-on wakeup
Port P1 1 pull-up transistor
0
control bit
1
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
Port P1 0 pull-up transistor
0
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor OFF, no key-on wakeup
Pull-up transistor ON, key-on wakeup
control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
2-44
4551 Group User’s Manual
R/W
APPLICATION
2.6 Power down function
2.6.4 Power down function application example
(1) Clock display
A clock which is high-accuracy and low-power dissipation can be set up by using a 32.768 kHz
quartz-crystal as a sub-clock and executing the POF instruction.
Outline: The power dissipation can be reduced by using the POF instruction.
Specifications: Time is displayed by the LCD and a 32.768 kHz quartz-crystal oscillator. The main
routine is executed by key input.
Figure 2.6.4 shows the software setting example.
Address 0 in page 0
Software start
Initialization of register Z
Yes
P = “1” ?
No
Cold start initial setting
T2F = “1” ?
Warm start initiai setting
Yes
No
Clock counter + 1
Time display renewed
Key input ?
No
Yes
Main routine initial setting
DI
EPOF
POF
To main routine
Fig. 2.6.4 Software setting example
2.6.5 Notes on use
(1) Key-on wakeup function
After setting ports (P1 specified with register PU0 and P0) which key-on wakeup function is valid to
“H,” execute the POF or POF2 instruction.
“L” level is input to the falling edge detection circuit even if one of ports which key-on wakeup
function is valid is in the “L” level state, and the edge is not detected.
(2) Power down instruction
Execute the POF or POF2 instruction immediately after executing the EPOF instruction to enter the
power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
(3) POF2 instruction
If the POF and POF2 instructions are executed while the T2F flag = “1,” its operation is recognized
as the return condition and system returns from power down state.
4551 Group User’s Manual
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APPLICATION
2.7 Reset
2.7 Reset
System reset is performed by applying “L” level to the RESET pin for 1 machine cycle or more when the
following conditions are satisfied;
● the value of supply voltage is the minimum value or more of the recommended operating conditions,
● oscillation is stabilized.
Then when “H” level is applied to the RESET pin, the software starts from address 0 in page 0 after elapsing
the internal oscillation stabilizing time (f(X IN ) is counted 10757 to 10786 machine cycles). Figure 2.7.3
shows the oscillation stabilizing time.
2.7.1 Reset circuit
The 4551Group has the power-on reset circuit and voltage drop detection circuit.
(1) Power-on reset
Reset can be performed automatically at power on (power-on reset) by the built-in power-on reset
circuit. When the built-in power-on reset circuit is used, set the time until the supply voltage rises to
the minimum operation voltage to 100 µs or less. When the rising time exceeds 100 µs, connect a
capacitor between the RESET pin and VSS at the shortest distance, input “L” level to RESET pin until
the supply voltage reaches the minimum operation voltage.
Figure 2.7.1 shows the power-on reset example and Figure 2.7.2 shows the reset circuit example
when the supply voltage rising time exceeds 100 µs.
VDD
Pull-up
transistor
RESET
pin
Internal reset
signal
Power-on
reset circuit
Voltage drop detection circuit
(Note)
Watchdog timer
output
WEF
Note:
This symbol represents a parasitic
diode.
Applied potential to RESET pin must
Power-on
be VDD or less.
Fig. 2.7.1 Power-on reset circuit example
2-46
Power-on reset circuit
output voltage
4551 Group User’s Manual
Reset
state
Internal reset signal
Reset released
APPLICATION
2.7 Reset
Calculate the capacitor value to input “L” level until the supply voltage
reaches the minimum operation voltage.
RESET
pin
Pull-up
transistor
A
Internal reset
signal
Power-on
reset circuit
Voltage drop detection circuit
(Note)
Watchdog timer
output
WEF
Note:
This symbol represents a parasitic
diode.
Applied potential to RESET pin must
be VDD or less.
Fig. 2.7.2 Reset circuit example when the supply voltage rising time exceeds 100 µs
Reset input
=
1machine cycle or more
f(XIN) is counted
10757 to 10786 times
0.85VDD
Software start
(Address 0 in page 0)
RESET
0.3VDD
(Note)
Note: Keep the value of supply voltage the minimum value or more
of the recommended operating conditions.
Fig. 2.7.3 Oscillation stabilizing time after system is released from reset
4551 Group User’s Manual
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APPLICATION
2.7 Reset
2.7.2 Internal state at reset
Figure 2.7.4 shows the internal state at reset. The contents of timers, registers, flags and RAM other than
shown in Figure 2.7.4 are undefined, so set them to initial values.
• Program counter (PC) ............................................................................................
0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
0
• Interrupt enable flag (INTE) ...................................................................................
0
(Interrupt disabled)
0
0
0
0
0
0
0
• Power down flag (P) ...............................................................................................
0
• External 0 interrupt request flag (EXF0) ................................................................
0
• Interrupt control register V1 ...................................................................................
0 0 0 0
(Interrupt disabled)
• Interrupt control register I1 ....................................................................................
0 0 0 0
• Timer 1 interrupt request flag (T1F) ......................................................................0
• Timer 2 interrupt request flag (T2F) ......................................................................0
• Watchdog timer flag (WDF) ...................................................................................
0
• Watchdog timer enable flag (WEF) .......................................................................
0
• Timer control register W1 ......................................................................................
0 0 0 0
(Prescaler stopped)
• Timer control register W2 ......................................................................................
0 0 0 0
• Timer control register W3 ......................................................................................
0 0
• Clock control register MR ......................................................................................
1 0 0 0
(Timer 1 stopped)
(Timer LC stopped)
• Carrier wave selection register C1 ........................................................................
0 1 1 1
• Carrier wave output control register C2 .................................................................0
• Carrier wave generating control flag CR ...............................................................
0
(Carrier wave output disabled)
• LCD control register L1 ..........................................................................................
0 0 0 0
• LCD control register L2 ..........................................................................................
1 1 1 1
(LCD off)
(Port P2 selected)
• Pull-up control register PU0 ...................................................................................
0 0 0 0
• General-purpose register V2 .................................................................................
0 0 0 0
• Carry flag (CY) .......................................................................................................
0
• Register A ..............................................................................................................
0 0 0 0
• Register B ..............................................................................................................
0 0 0 0
• Register D ..............................................................................................................
✕ ✕ ✕
• Register E ..............................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Data pointer X ........................................................................................................
0 0 0 0
• Data pointer Y ........................................................................................................
0 0 0 0
• Data pointer Z ........................................................................................................
✕ ✕
• Stack pointer (SP) ..................................................................................................
1 1 1
Fig. 2.7.4 Internal state at reset
2-48
4551 Group User’s Manual
“✕” represents undefined.
APPLICATION
2.7 Reset
2.7.3 Voltage drop detection circuit
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer
if the supply voltage drops below a set value.
Figure 2.7.5 shows the voltage drop detection reset circuit, and Figure 2.7.6 shows the operation waveform
example of the voltage drop detection circuit.
Pull-up transistor
Internal reset signal
RESET pin
Power-on
reset circuit
Voltage drop detection circuit
Watchdog timer output
WEF
Fig. 2.7.5 Voltage drop detection reset circuit
VDD
Reset voltage
(Note)
The microcomputer starts operation
after the f(XIN) is counted 10757 to
10786 times.
Internal reset
signal
Note: Refer to section “3.1 Electrical characteristics” for the reset voltage
of the voltage drop detection circuit.
Fig. 2.7.6 Voltage drop detection circuit operation waveform
4551 Group User’s Manual
2-49
APPLICATION
2.8 Oscillation circuit
2.8 Oscillation circuit
The 4551 Group has an internal oscillation circuit to produce the clock required for microcomputer operation.
The clock signal f(X IN) is obtained by connecting a ceramic resonator to X IN pin and X OUT pin. The clock
signal f(X CIN) is obtained by connecting a quartz-crystal oscillator to X CIN pin and X COUT pin.
2.8.1 Oscillation circuit
(1) f(X IN) clock generating circuit
The clock signal f(XIN) is obtained by connecting a ceramic resonator externally.
Connect this external circuit to pins XIN and X OUT at the shortest distance. A feed-back resistor is
built-in between XIN pin and X OUT pin.
Figure 2.8.1 shows an example of an oscillation circuit connecting a ceramic resonator externally.
Keep the maximum value of oscillation frequency within the range listed Table 2.8.1.
(2) f(X CIN) clock generating circuit
The clock signal f(X CIN) is obtained by connecting a quartz-crystal externally.
Connect this external circuit to pins XCIN and X COUT at the shortest distance. A feed-back resistor
is built-in between XCIN pin and X COUT pin.
Figure 2.8.2 shows an example of an oscillation circuit connecting a quartz-crystal externally.
Table 2.8.1 Maximum value of oscillation frequency
and supply voltage
Oscillation
frequency
Supply voltage
(System clock)
4.5 V to 5.5 V
4.5 V to 5.5 V
(f(XIN)/4)
(f(XIN))
8.0 MHz
2.0 MHz
2.2 V to 5.5 V (Note)
(f(XIN)/4)
4.0 MHz
2.5 V to 5.5 V (Note)
(f(XIN))
1.0 MHz
Note: 2.5 V to 5.5 V for the One Timer PROM version.
M34551
XIN
CIN
Note: Externally connect a
damping resistor Rd depending on the oscillaXOUT
tion frequency. (A feedback resistor is built-in.)
Rd
Use the resonator
manufacturer’s recommended value because
COUT
constants such as capacitance depend on the
resonator.
Fig. 2.8.1 Oscillation circuit example connecting
ceramic resonator externally
2-50
M34551
XCIN
XCOUT
Rd
CIN
COUT
Note: Externally connect a
damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.)
Use the quartz-crystal
oscillator manufacturer’s
recommended value because constants such as
capacitance depend on
the oscillator.
Fig. 2.8.2 Oscillation circuit example connecting
quartz-crystal externally
4551 Group User’s Manual
APPLICATION
2.8 Oscillation circuit
2.8.2 Oscillation operation
System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer
operation. For the 4551 Group, the clock (f(XIN)), (f(XIN)/4), (f(XCIN)), or (f(XCIN))/4 which is supplied from
the oscillation circuit is selected with the register MR.
Figure 2.8.3 shows the structure of the clock control circuit.
MR0
XIN
XOUT
OSC
Multiplexer
Frequency
dividing
circuit
(divided by 4)
MR3
Internal clock
1
0
generating circuit
INSTCK
(divided by 3)
STCK
MR1
XCIN
OSC
XCOUT
POF instruction
R
Q
S
POF2 instruction
R
S
RESET
Q
T2F flag
Falling detected
Ports P0, P1
Fig. 2.8.3 Structure of clock control circuit
2.8.3 Notes on use
(1) Value of a part connected to an oscillator
Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and
the board. Accordingly, consult the oscillator manufacturer for values of each part connected the
oscillator.
4551 Group User’s Manual
2-51
APPLICATION
2.8 Oscillation circuit
MEMO
2-52
4551 Group User’s Manual
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Typical characteristics
3.3 List of precautions
3.4 Notes on noise
3.5 Mask ROM confirmation form
3.6 ROM programming confirmation form
3.7 Mark specification form
3.8 Package outline
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
VDD
VI
VO
VO
VO
Pd
Topr
Tstg
3-2
Conditions
Parameter
Supply voltage
Input voltage P0, P1, P2, RESET, XIN, XCIN
Output voltage P0, P1, D
Output transistors in cut-off state
Output voltage CARR, XOUT, XCOUT
Output voltage SEG, COM
Power dissipation
Operating temperature range
Storage temperature range
4551 Group User’s Manual
Ratings
–0.3 to 7.0
Unit
V
–0.3 to VDD+0.3
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
V
V
–0.3 to VDD+0.3
V
300
–20 to 70
mW
°C
–40 to 125
°C
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions
(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Min.
Typ.
Max.
Unit
f(XIN) ≤ 4.0 MHz, ceramic resonator,
Mask ROM version
STCK=f(XIN)/4
2.2
5.5
2.5
5.5
4.5
5.5
2.0
5.5
V
0.8VDD
VDD
V
V
“H” level input voltage XIN
0.7VDD
“H” level input voltage RESET
“H” level input voltage INT
0.85VDD
0.8VDD
VDD
VDD
f(XIN) ≤ 1.0 MHz, ceramic resonator,
STCK=f(XIN)
f(XIN) ≤ 4.0 MHz, ceramic resonator,
VDD
STCK=f(XIN)/4
Supply voltage One Time PROM version
f(XIN) ≤ 1.0 MHz, ceramic resonator,
V
STCK=f(XIN)
f(XIN) ≤ 8.0 MHz, ceramic resonator,
STCK=f(XIN)/4
f(XIN) ≤ 2.0 MHz, ceramic resonator,
VRAM
VSS
VIH
VIH
VIH
VIH
VIL
VIL
VIL
RAM back-up voltage
Supply voltage
“H” level input voltage P0, P1, P2
0
“L” level input voltage P0, P1, P2
0
“L” level input voltage XIN
“L” level input voltage RESET
0
0
“L” level input voltage INT
VIL
IOL(peak) “L” level peak output current
P0, P1, D0–D7, CARR
IOL(avg)
STCK=f(XIN)
RAM back-up
“L” level average output current
0.3VDD
0
0.2VDD
10
VDD=5.0 V
VDD=3.0 V
VDD=5.0 V
P0, P1, D0–D7, CARR (Note)
IOH(peak) “H” level peak output current
CARR
VDD=3.0 V
IOH(avg) “H” level average output current
CARR (Note)
VDD=5.0 V
f(XCIN)
VDET
VDD
0.3VDD
0.3VDD
V
V
V
V
V
V
mA
4
5
2
VDD=5.0 V
VDD=3.0 V
–30
–15
–15
f(XCIN) clock frequency
VDD=3.0 V
Quartz-crystal oscillator
Voltage drop detection circuit
Mask ROM version
1.15
1.30
One Time PROM version
1.00
mA
mA
mA
–7
1.15
VDD = 0 to 2.2 V
Valid power supply rising time for Mask ROM version
One Time PROM version VDD = 0 to 2.5 V
power-on reset circuit
Note: The average output current is the average current value at the 100 ms interval.
50
2.15
1.65
2.00
1.50
2.00
1.85
TPON
4551 Group User’s Manual
V
100
kHz
V
µs
3-3
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.3 Electrical characteristics
(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
“L” level output voltage
IOL = 5 mA
VDD = 5.0 V
0.9
P0, P1, D0–D7, CARR, RESET
IOL = 2 mA
VDD = 3.0 V
0.9
VOH
“H” level output voltage CARR
IOH = –15 mA
IOH = –7 mA
VDD = 5.0 V
VDD = 3.0 V
IIH
IIL
“H” level input current P0, P1, P2, RESET
“L” level input current P1, P2
IOZ
Output current at off-state D0–D7
VOL
2.4
1.0
1
–1
1
VDD = 5.0 V, f(XCIN) = 32 kHz, f(XIN) = 8 MHz
2.5
5.0
2.3
4.6
f(XIN) = 1 MHz
STCK = f(XIN)
VDD = 3.0 V, f(XCIN) = 32 kHz, f(XIN) = 4 MHz
1.4
2.8
STCK = f(XIN)/4
0.7
1.4
STCK = f(XIN)/4
VDD = 5.0 V
at active high-speed mode
while LCD is operating
(SEG0–SEG15)
IDD
Supply current
(Note 2)
at active low-speed mode
while LCD is operating
(SEG0–SEG15)
at clock operating mode
while LCD is operating
(SEG0–SEG15)
RPH
mA
VDD = 3.0 V
f(XCIN) = 32 kHz
f(XIN) = 1 MHz
0.6
1.2
STCK = f(XIN)
f(XIN) = 500 kHz
0.4
0.8
VDD = 5.0 V
f(XIN) = stop
STCK = f(XCIN)/4
70
140
STCK = f(XCIN)
90
180
VDD = 3.0 V
f(XIN) = stop
STCK = f(XCIN)/4
30
60
f(XCIN) = 32 kHz
STCK = f(XCIN)
40
80
f(XIN) = stop
f(XCIN) = 32 kHz
VDD = 5.0 V
27.5
60
Ta=25 °C
VDD = 3.0 V
10
17.5
f(XIN) = stop
f(XCIN) = 32 kHz
VDD = 5.0 V
f(XCIN) = 32 kHz
µA
P0, P1
f(XIN) = stop, f(XCIN) = stop
VDD = 5.0 V, VI = 0 V
20
VDD = 3.0 V, VI = 0 V
40
VDD = 5.0 V, VI = 0 V
VDD = 3.0 V, VI = 0 V
12
25
INT
VDD = 5.0 V
RESET
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
COM output impedance
RSEG
SEG output impedance
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
LCD power supply internal resistor value
VDD = 3.0 V
Impedance between VLC3 and VSS
µA
65
20
VDD = 3.0 V
f(XIN) = stop, f(XCIN) = stop, Ta = 25 °C
RCOM
µA
µA
µA
f(XCIN) = 32 kHz
at RAM back-up mode
Pull-up resistor
RESET
value
VT+ – VT– Hysteresis
f(XIN) = 2 MHz
V
V
VI = VDD (Note 1)
VI = 0 V (Note 1)
VO = VDD
Unit
0.1
50
100
30
60
0.5
1.0
10
125
250
70
130
1.5
0.6
1.6
1.8
2.2
kΩ
kΩ
V
0.4
1.3
µA
V
6.5
8
9
11
kΩ
kΩ
600 1200 kΩ
300
Ta=25 °C
(Note 3)
Notes 1: In this case, the pull-up transistor of port P1 is turned off and the port P2 function is selected by software.
2: The current value includes the current dissipation of the LCD power supply internal resistor (RVLC).
3: VLC3=VDD.
RVLC
3-4
4551 Group User’s Manual
APPENDIX
3.1 Electrical characteristics
3.1.4 Basic timing diagram
Machine cycle
Mi
Parameter
Mi+1
Pin name
System clock
STCK
Port D output
D0–D7
Ports P0, P1 output
P00–P03
P10–P13
Ports P0, P1 and
P2 input
P00–P03
P10–P13
P20–P23
Interrupt input
INT
4551 Group User’s Manual
3-5
APPENDIX
3.2 Typical characteristics
3.2 Typical characteristics
3.2.1 VDD–IDD characteristics
(1) CPU high-speed operating (system clock: f(X IN))
[measurement condition]
X IN: operating, X CIN: 32 kHz, timer 2 count source: X CIN, system clock: f(X IN), LCD clock: 1 kHz,
duty: 1/4, bias: 1/3
Ta = 25°C
5.0
4.5
4.0
I DD (mA)
3.5
f(X IN ) = 2 MHz
3.0
2.5
f(X IN) = 1 MHz
2.0
1.5
f(X IN ) = 500 kHz
1.0
0.5
0.0
2
1
0
3
4
5
6
7
VDD (V)
(2) CPU high-speed operating (system clock: f(X IN)/4)
[measurement condition]
XIN: operating, X CIN: 32 kHz, timer 2 count source: X CIN, system clock: f(XIN)/4, LCD clock: 1 kHz,
duty: 1/4, bias: 1/3
Ta = 25°C
5.0
4.5
4.0
3.5
f(X IN ) = 8 MHz
I DD (mA)
3.0
2.5
f(X IN) = 4 MHz
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
VDD (V)
3-6
4551 Group User’s Manual
5
6
7
APPENDIX
3.2 Typical characteristics
(3) CPU low-speed operating (system clock: f(X CIN))
[measurement condition]
XIN : stop, XCIN : 32 kHz, timer 2 count source: XCIN , system clock: f(XCIN ), LCD clock: 1 kHz,
duty: 1/4, bias: 1/3
Ta = 25 °C
150
I DD (µA)
100
50
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VDD (V)
(4) CPU low-speed operating (system clock: f(XCIN)/4)
[measurement condition]
XIN : stop, XCIN : 32 kHz, timer 2 count source: XCIN, system clock: f(X CIN )/4, LCD clock: 1 kHz,
duty: 1/4, bias: 1/3
Ta = 25 °C
150
I DD (µA)
100
50
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VDD (V)
4551 Group User’s Manual
3-7
APPENDIX
3.2 Typical characteristics
(5) Clock operating
[measurement condition]
XIN : stop, XCIN : 32 kHz, timer 2 count source: XCIN , system clock: stop, LCD clock: 1 kHz,
duty: 1/4, bias: 1/3
Ta = 25 °C
100
I DD (µA)
80
60
40
20
0
0.0
1.0
2.0
3.0
4.0
VDD (V)
3-8
4551 Group User’s Manual
5.0
6.0
7.0
APPENDIX
3.2 Typical characteristics
3.2.2 VOH–I OH characteristics (port CARR)
(1) V DD = 3.0 V
Ta = 25 ºC
-50.0
-45.0
-40.0
IOH (mA)
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VOH (V)
(2) V DD = 5.0 V
Ta = 25 ºC
-100.0
-90.0
-80.0
IOH (mA)
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOH (V)
4551 Group User’s Manual
3-9
APPENDIX
3.2 Typical characteristics
3.2.3 VOL–I OL characteristics (Ports P0, P1, D 0 –D7, CARR, RESET)
(1) V DD = 3.0 V
Ta = 25 ºC
50.0
45.0
40.0
IOL (mA)
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VOL (V)
(2) V DD = 5.0 V
Ta = 25 ºC
100.0
90.0
80.0
IOL (mA)
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (V)
3-10
4551 Group User’s Manual
3.5
4.0
4.5
5.0
APPENDIX
3.2 Typical characteristics
3.2.4 Voltage drop detection circuit temperature characteristics
(1) M34551Mx-XXXFP
Supply voltage (V)
2.5
2
1.5
1
-20
-10
0
10
20
30
40
50
60
70
40
50
60
70
Operating temperature range (°C)
(2) M34551E8-XXXFP
Supply voltage (V)
2.5
2
1.5
1
-20
-10
0
10
20
30
Operating temperature range (°C)
4551 Group User’s Manual
3-11
APPENDIX
3.3 List of precautions
3.3 List of precautions
• Use the carrier wave or the carrier wave divided by 2 as the
timer 1 count source when the carrier wave output autocontrol function is selected.
If the ORCLK is used as the count source, a hazard may
occur in port CARR output because ORCLK is not
synchronized with the carrier wave.
• When “no carrier wave” is selected with register C1
((C13C12C11C10) = (0101), (1101)), the enable/disable of
the carrier wave output cannot be controlled by the carrier
wave output auto-control function.
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins
VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
In the built-in PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to V SS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
➇ D5/INT pin
When the interrupt valid waveform of D5/INT pin is changed
with the bit 2 of register I1 in software, be careful about the
following notes.
• Clear the bit 0 of register V1 to “0” and then change the
interrupt valid waveform of D5/INT pin with the bit 2 of register
I1 (refer to Figure 40➀).
• Clear the bit 2 of register I1 to “0” and execute the SNZ0
instruction to clear the EXF0 flag after executing at least
one instruction (refer to Figure 40➁). Depending on the input
state of the D5/INT pin, the external 0 interrupt request flag
(EXF0) may be set to “1” when the interrupt valid waveform
is changed.
➁ Prescaler
Stop the prescaler operation to change its frequency dividing
ratio.
➂ Count source
Stop timer 1 or timer LC counting to change its count source.
When timer 2 count source changes from f(X CIN) to ORCLK
(W23 = “0” → W23 = “1”), the count value of timer 2 is initialized.
However, when timer 2 count source changes from ORCLK to
f(XCIN) (W23 = “1” → W23 = “0”) or the same count source is
set again (W23 = “0” → W23 = “0” or W23 = “1” → W23 = “1”),
the count value of timer 2 is not initialized.
➃ Timer 2
...
LA
Timer 2 has the watchdog timer function (WDT). When timer 2
is used as the WDT, note that the processing to initialize the
count value and the execution of the WRST instruction.
LA
TI1A
➄ Reading the count value
Write the data to reload register R1 while timer 1 is operating,
avoid a timing when timer 1 underflows.
3-12
➀
4
SNZ0
NOP
...
➅ Writing to reload register R1
• Execute the STCR instruction after setting the timer 1 and
register C2 in order to start the carrier generating circuit
operation.
• Stop the timer 1 (W2 0 =“0”) after stopping the carrier
generating circuit (SPCR instruction executed) while the
carrier wave output is disabled in order to stop the carrier
wave output auto-control operation.
• If the carrier wave output auto-control function is invalidated
(C20 =“0”) while the carrier wave output is auto-controlled,
the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow. This
state is released by timer 1 stop (W20=“0”).
When the carrier wave output auto-control function is
validated (C20=“1”) again after it is invalidated (C20=“0”),
the auto-control of carrier wave output is started again when
the next timer 1 underflow occurs. However, when the carrier
wave output auto-control bit is changed during timer 1
underflow, the error-operation may occur.
; (✕✕✕02)
; The SNZ0 instruction is valid
; Change of the interrupt valid waveform
➁
NOP
Stop the prescaler and then execute the TAB1 instruction to
read timer 1 data.
➆ Notes when using the carrier wave output auto-control function
4
TV1A
;The SNZ0 instruction is executed
✕ : this bit is not related to the setting of INT.
Fig. 40 External 0 interrupt program example
➈ One Time PROM version
The operating power voltage of the One Time PROM version
is within the range of 2.5 V to 5.5 V.
➉ Multifunction
Note that the port D5 output function can be used even when
INT function is selected.
11
Power down instruction (POF instruction, POF2 instruction)
Execute the POF or POF2 instruction immediately after
executing the EPOF instruction to enter the power down state.
Note that system cannot enter the power down state when
executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction
before executing the EPOF instrcution.
12 Program
counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
4551 Group User’s Manual
APPENDIX
3.4 Notes on noise
3.4 Notes on noise
Countermeasures against noise are described below.
The following countermeasures are effective against
noise in theory, however, it is necessary not only to
take measures as follows but to evaluate before actual
use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function
as an antenna which feeds noise into the
microcomputer.
The shorter the total wiring length (by mm unit), the
less the possibility of noise insertion into a
microcomputer.
(1) Package
Select the smallest possible package to make
the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package,
for example QFP and not DIP, makes the
total wiring length short to reduce influence
of noise.
(2) Wiring for RESET input pin
Make the length of wiring which is connected
to the RESET input pin as short as possible.
Especially, connect a capacitor across the
RESET input pin and the V SS pin with the
shortest possible wiring (within 20mm).
● Reason
The width of a pulse input into the RESET
pin is determined by the timing necessary
conditions. If noise having a shorter pulse
width than the standard is input to the
RESET input pin, the reset is released before
the internal state of the microcomputer is
completely initialized. This may cause a
program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
DIP
Reset
circuit
SDIP
SOP
VSS
RESET
VSS
QFP
O.K.
Fig. 3.4.2 Wiring for the RESET input pin
Fig. 3.4.1 Selection of packages
4551 Group User’s Manual
3-13
APPENDIX
3.4 Notes on noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected
to clock I/O pins as short as possible.
• Make the length of wiring across the
grounding lead of a capacitor which is
connected to an oscillator and the V SS pin
of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation
from other V SS patterns.
Noise
(4) Wiring to CNV SS pin
Connect the CNV SS pin to the V SS pin with
the shortest possible wiring.
● Reason
The processor mode of a microcomputer is
influenced by a potential at the CNVSS pin.
If a potential difference is caused by the
noise between pins CNVSS and V SS , the
processor mode may become unstable. This
may cause a microcomputer malfunction or
a program runaway.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
CNVSS
CNVSS
VSS
VSS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
● Reason
If noise enters clock I/O pins, clock
waveforms may be deformed. This may
cause a program failure or program runaway.
Also, if a potential difference is caused by
the noise between the V SS level of a
microcomputer and the V SS level of an
oscillator, the correct clock will not be input
in the microcomputer.
3-14
O.K.
Fig. 3.4.4 Wiring for CNV SS pin
4551 Group User’s Manual
APPENDIX
3.4 Notes on noise
(5) Wiring to VPP pin of One Time PROM version
● When the V PP pin is also used as the
CNV SS pin
Connect an approximately 5 kΩ resistor to
the VPP pin the shortest possible in series
and also to the VSS pin. When not
connecting the resistor, make the length of
wiring between the V PP pin and the V SS
pin the shortest possible (refer to Figure
3.4.5)
Note: Even when a circuit which included an
approximately 5 kΩ resistor is used in the
Mask ROM version, the microcomputer
operates correctly.
● Reason
The VPP pin of the One Time PROM version is the power source input pin for the
built-in PROM. When programming in the
built-in PROM, the impedance of the VPP
pin is low to allow the electric current for
writing flow into the PROM. Because of
this, noise can enter easily. If noise enters
the VPP pin, abnormal instruction codes or
data are read from the built-in PROM, which
may cause a program runaway.
3.4.2 Connection of bypass capacitor across VSS
line and V CC line
Connect an approximately 0.1 µF bypass capacitor
across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the VSS pin
and the V CC pin at equal length.
• Connect a bypass capacitor across the V SS pin
and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal
lines for VSS line and V CC line.
• Connect the power source wiring via a bypass
capacitor to the V SS pin and the VCC pin.
AA
AA
AA
AA
AA
VCC
VSS
N.G.
AA
AA
AA
AA
AA
VCC
VSS
O.K.
Fig. 3.4.6 Bypass capacitor across the VSS line
and the VCC line
When the VPP pin is also used as the CNVSS pin
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.5 Wiring for the VPP pin of the One Time
PROM version
4551 Group User’s Manual
3-15
APPENDIX
3.4 Notes on noise
3.4.3 Oscillator concerns
Take care to prevent an oscillator that generates
clocks for a microcomputer operation from being
affected by other signals.
(1) Keeping oscillator away from large current
signal lines
Install a microcomputer (and especially an
oscillator) as far as possible from signal lines
where a current larger than the tolerance of
current value flows.
● Reason
In the system using a microcomputer, there
are signal lines for controlling motors, LEDs,
and thermal heads or others. When a large
current flows through those signal lines,
strong noise occurs because of mutual
inductance.
Microcomputer
N.G.
Do not cross
XIN
XOUT
VSS
Fig. 3.4.8 Wiring to a signal line where potential
levels change frequently
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print
a VSS pattern on the underside (soldering side)
of the position (on the component side) where
an oscillator is mounted.
Connect the VSS pattern to the microcomputer
V SS pin with the shortest possible wiring.
Besides, separate this VSS pattern from other
VSS patterns.
Mutual inductance
M
An example of VSS patterns on the
underside of a printed circuit board
XIN
XOUT
VSS
Large
current
AAAAAAA
AAA
AAAAAA
AAA
Oscillator wiring
pattern example
GND
XIN
XOUT
VSS
Fig. 3.4.7 Wiring for a large current signal line
(2) Installing oscillator away from signal lines
where potential levels change frequently
Install an oscillator and a connecting pattern
of an oscillator away from signal lines where
potential levels change frequently. Also, do
not cross such signal lines over the clock lines
or the signal lines which are sensitive to noise.
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.9 V SS pattern on the underside of an
oscillator
● Reason
Signal lines where potential levels change
frequently (such as the CARR pin signal
line) may affect other lines at signal rising
edge or falling edge. If such lines cross
over a clock line, clock waveforms may be
deformed, which causes a microcomputer
failure or a program runaway.
3-16
CNTR
4551 Group User’s Manual
APPENDIX
3.4 Notes on noise
3.4.4 Setup for I/O ports
Setup I/O ports using hardware and software as
follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port
in series.
<Software>
• As for an input port, read data several times by
a program for checking whether input levels are
equal or not.
• As for an output port or an I/O port, since the
output data may reverse because of noise, rewrite
data to its output latch at fixed periods.
• Rewrite data to pull-up control registers at fixed
periods.
3.4.5 Providing of watchdog timer function by
software
If a microcomputer runs away because of noise or
others, it can be detected by a software watchdog
timer and the microcomputer can be reset to normal
operation. This is equal to or more effective than
program runaway detection by a hardware watchdog
timer. The following shows an example of a watchdog
timer provided by software.
In the following example, to reset a microcomputer
to normal operation, the main routine detects errors
of the interrupt processing routine and the interrupt
processing routine detects errors of the main routine.
This example assumes that interrupt processing is
repeated multiple times in a single main routine
processing.
<The main routine>
• Assigns a single byte of RAM to a software
watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the
main routine. The initial value N should satisfy
the following condition:
N+1 ≥
initialization routine for recovery processing in the
following case:
If the SWDT contents do not change after interrupt
processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each
interrupt processing.
• Determines that the main routine operates normally
when the SWDT contents are reset to the initial
value N at almost fixed cycles (at the fixed interrupt
processing count).
• Detects that the main routine has failed and
determines to branch to the program initialization
routine for recovery processing in the following
case:
If the SWDT contents are not initialized to the
initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
EI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
≤0
>0
RTI
Return
Main routine
errors
Fig. 3.4.10 Watchdog timer by software
(Counts of interrupt processing executed in
each main routine)
As the main routine execution cycle may change
because of an interrupt processing or others, the
initial value N should have a margin.
• Watches the operation of the interrupt processing
routine by comparing the SWDT contents with
counts of interrupt processing after the initial value
N has been set.
• Detects that the interrupt processing routine has
failed and determines to branch to the program
4551 Group User’s Manual
3-17
APPENDIX
3.5 Mask ROM order confirmation form
3.5 Mask ROM order confirmation form
GZZ-SH10-66B <63A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34551M4-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽.
✽ Customer
TEL (
Date
issued
Issuance
signature
Company
name
)
Date:
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✽1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
EPROM Type:
(hexadecimal notation)
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
4.00K
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
0FFF 16
400016
4.00K
4FFF 16
7FFF 16
Low-order
5-bit data
High-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
0000 16
4.00K
0FFF 16
4000 16
4.00K
4FFF 16
FFFF 16
Set “FF 16 ” in the shaded area.
of low-order and high-order 5-bit data.
Set “111 2 ” in the area
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (48P6S-A for M34551M4-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✽ 3. Comments
3-18
4551 Group User’s Manual
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-94B <85A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34551M8-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽.
✽ Customer
TEL (
Date
issued
Issuance
signature
Company
name
)
Date:
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✽ 1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
EPROM Type:
(hexadecimal notation)
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
8.00K
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1FFF 16
400016
8.00K
5FFF 16
7FFF 16
Low-order
5-bit data
High-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
0000 16
8.00K
1FFF 16
4000 16
8.00K
5FFF 16
FFFF 16
Set “FF 16 ” in the shaded area.
of low-order and high-order 5-bit data.
Set “111 2 ” in the area
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (48P6S-A for M34551M4-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✽ 3. Comments
4551 Group User’s Manual
3-19
APPENDIX
3.6 ROM programming order confirmation form
3.6 ROM programming order confirmation form
GZZ-SH10-69B <64A0>
ROM number
Please fill in all items marked ✽.
Date:
Receipt
4500 SERIES ROM PROGRAMMING ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34551E8-XXXFP
MITSUBISHI ELECTRIC
Company
name
Responsible
Supervisor
officer
TEL (
)
Issuance
signature
✽ Customer
Date
issued
Section head S u p e r v i s o r
signature
signature
Date:
✽ 1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
programming based on this data. We shall assume the responsibility for errors only if the ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
EPROM Type:
(hexadecimal notation)
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
8.00K
1FFF16
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
400016
8.00K
5FFF16
7FFF16
Low-order
5-bit data
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
8.00K
1FFF16
400016
8.00K
5FFF16
FFFF16
Set “FF 16 ” in the shaded area.
of low-order and high-order 5-bit data.
Set “111 2 ” in the area
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (48P6S-A for M34551E8-XXXFP) and attach to the
ROM Programming Order Confirmation Form.
✽ 3. Comments
3-20
4551 Group User’s Manual
APPENDIX
3.7 Mark specification form
3.7 Mark specification form
48P6S-A (48-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
38
25
24
39
Mitsubishi IC catalog name
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
15
48
1
14
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
38
25
39
24
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
15
Mitsubishi IC catalog name
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s parts number can be up to 9 characters: Only 0 to
9, A to Z, +, –, /, (, ), &, , . (periods), , (commas) are usable.
4 : If the Mitsubishi logo
is not required, check the box below.
Mitsubishi logo is not required
Mitsubishi lot number
(6-digit or 7-digit)
48
1
14
C. Special Mark Required
38
25
39
24
48
15
1
Notes1 : If Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi lot number (6-digit, or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the cunstomer’s trade mark logo must be used in the
Special Mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
Special logo required
14
4551 Group User’s Manual
3-21
APPENDIX
3.8 Package outline
3.8 Package outline
48P6S-A
Plastic 48pin 7✕10mm body QFP
EIAJ Package Code
QFP48-P-710-0.65
Weight(g)
0.29
JEDEC Code
–
Lead Material
Alloy 42
MD
e
HD
D
48
1
b2
ME
39
38
I2
HE
E
Recommended Mount Pad
Symbol
25
14
15
A
24
b
y
F
A1
e
c
A2
L1
Detail F
3-22
4551 Group User’s Manual
L
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
2.15
0.1
0.2
0
1.85
–
–
0.2
0.25
0.35
0.13
0.15
0.2
6.8
7.0
7.2
9.8
10.0
10.2
0.65
–
–
8.7
9.0
9.3
11.7
12.0
12.3
0.3
0.5
0.7
1.0
–
–
0.1
–
–
0°
10°
–
–
–
0.35
1.0
–
–
–
–
7.4
–
–
10.4
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
4551 Group
Sep. First Edition 1998
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1998 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
4551 Group
© 1998 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Jul. 1997.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
4551 Group User’s Manual
Revision Description
First Edition
Rev.
date
980930
(1/1)