RENESAS 4514

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER
4500 SERIES
4513/4514
Group
User’s Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
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● The prior written approval of Mitsubishi Electric Corporation is necessary to
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● If these products or technologies are subject to the Japanese export control
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Any diversion or reexport contrary to the export control laws and regulations of
JAPAN and/or the country of destination is prohibited.
● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
Preface
This user’s manual describes the hardware and
instructions of Mitsubishi’s 4513/4514 Group CMOS
4-bit microcomputer.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 4513/4514 Group and should be able to fully
utilize the product. The manual starts with specifications
and ends with application examples.
In this manual, the 4514 Group is mainly described.
The differences from the 4513 Group are described
at the related points.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting
examples of related registers.
CHAPTER 3 APPENDIX
This chapter includes precautions for systems development using the microcomputer, the mask ROM
confirmation forms (mask ROM version), and mark specification forms which are to be submitted when
ordering.
Be sure to refer to this chapter because this chapter also includes necessary information for systems
development.
Note: In this manual, the 4514 Group is mainly described. The differences from the 4513 Group are
described at the related points.
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-3
FEATURES ...................................................................................................................................... 1-3
APPLICATION ................................................................................................................................ 1-3
PIN CONFIGURATION .................................................................................................................. 1-4
BLOCK DIAGRAM ......................................................................................................................... 1-6
PERFORMANCE OVERVIEW ....................................................................................................... 1-8
PIN DESCRIPTION ........................................................................................................................ 1-9
MULTIFUNCTION ................................................................................................................... 1-10
CONNECTIONS OF UNUSED PINS ................................................................................... 1-10
PORT FUNCTION .................................................................................................................. 1-11
DEFINITION OF CLOCK AND CYCLE ............................................................................... 1-11
PORT BLOCK DIAGRAMS ................................................................................................... 1-12
FUNCTION BLOCK OPERATIONS ........................................................................................... 1-17
CPU .......................................................................................................................................... 1-17
PROGRAM MEMOY (ROM) .................................................................................................. 1-20
DATA MEMORY (RAM) ......................................................................................................... 1-21
INTERRUPT FUNCTION ....................................................................................................... 1-22
EXTERNAL INTERRUPTS .................................................................................................... 1-26
TIMERS ................................................................................................................................... 1-29
WATCHDOG TIMER .............................................................................................................. 1-35
SERIAL I/O.............................................................................................................................. 1-36
A-D CONVERTER .................................................................................................................. 1-41
VOLTAGE COMPARATOR.................................................................................................... 1-47
RESET FUNCTION ................................................................................................................ 1-49
VOLTAGE DROP DETECTION CIRCUIT ........................................................................... 1-52
RAM BACK-UP MODE .......................................................................................................... 1-53
CLOCK CONTROL ................................................................................................................. 1-57
ROM ORDERING METHOD ....................................................................................................... 1-58
LIST OF PRECAUTIONS ............................................................................................................ 1-59
SYMBOL ........................................................................................................................................ 1-62
LIST OF INSTRUCTION FUNCTION ........................................................................................ 1-63
INSTRUCTION CODE TABLE.................................................................................................... 1-66
MACHINE INSTRUCTIONS ........................................................................................................ 1-70
CONTROL REGISTERS .............................................................................................................. 1-84
BUILT-IN PROM VERSION ........................................................................................................ 1-88
4513/4514 Group User’s Manual
i
Table of contents
CHAPTER 2 APPLICATION
2.1 I/O pins .................................................................................................................................... 2-2
2.1.1 I/O ports .......................................................................................................................... 2-2
2.1.2 Related registers ............................................................................................................ 2-4
2.1.3 Port application examples ............................................................................................. 2-7
2.1.4 Notes on use .................................................................................................................. 2-9
2.2 Interrupts ............................................................................................................................... 2-11
2.2.1 Interrupt functions ........................................................................................................ 2-11
2.2.2 Related registers .......................................................................................................... 2-13
2.2.3 Interrupt application examples.................................................................................... 2-16
2.2.4 Notes on use ................................................................................................................ 2-25
2.3 Timers .................................................................................................................................... 2-26
2.3.1 Timer functions ............................................................................................................. 2-26
2.3.2 Related registers .......................................................................................................... 2-27
2.3.3 Timer application examples ........................................................................................ 2-30
2.3.4 Notes on use ................................................................................................................ 2-39
2.4 Serial I/O ................................................................................................................................ 2-40
2.4.1 Carrier functions ........................................................................................................... 2-40
2.4.2 Related registers .......................................................................................................... 2-41
2.4.3 Operation description ................................................................................................... 2-42
2.4.4 Serial I/O application example ................................................................................... 2-45
2.4.5 Notes on use ................................................................................................................ 2-48
2.5 A-D converter ....................................................................................................................... 2-49
2.5.1 Related registers .......................................................................................................... 2-50
2.5.2 A-D converter application examples .......................................................................... 2-51
2.5.3 Notes on use ................................................................................................................ 2-52
2.6 Voltage comparator ............................................................................................................. 2-54
2.6.1 Voltage comparator function ....................................................................................... 2-54
2.6.2 Related registers .......................................................................................................... 2-54
2.6.3 Notes on use ................................................................................................................ 2-55
2.7 Reset....................................................................................................................................... 2-56
2.7.1 Reset circuit .................................................................................................................. 2-56
2.7.2 Internal state at reset .................................................................................................. 2-57
2.8 Voltage drop detection circuit.......................................................................................... 2-58
2.9 RAM back-up ........................................................................................................................ 2-59
2.9.1 RAM back-up mode ..................................................................................................... 2-59
2.9.2 Related register ............................................................................................................ 2-60
2.9.3 Notes on use ................................................................................................................ 2-62
2.10 Oscillation circuit .............................................................................................................. 2-63
2.10.1 Oscillation circuit ........................................................................................................ 2-63
2.10.2 Oscillation operation .................................................................................................. 2-64
2.10.3 Notes on use .............................................................................................................. 2-64
ii
4513/4514 Group User’s Manual
Table of contents
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-3
3.1.3 Electrical characteristics ................................................................................................ 3-5
3.1.4 A-D converter recommended operating conditions.................................................... 3-6
3.1.5 Voltage drop detection circuit characteristics............................................................. 3-6
3.1.6 Voltage comparator characteristics .............................................................................. 3-7
3.1.7 Basic timing diagram ..................................................................................................... 3-7
3.2 Typical characteristics ......................................................................................................... 3-8
3.2.1 VDD–I DD characteristics ................................................................................................. 3-8
3.2.2 VOL –IOL characteristics ................................................................................................ 3-11
3.2.3 VOH–I OH characteristics (Port P5) ............................................................................. 3-13
3.2.4 VDD –RPU characteristics (Ports P0, P1) ................................................................... 3-13
3.2.5 A-D converter typical characteristics ......................................................................... 3-14
3.2.6 Analog input current characteristics pins A IN0–A IN7 ............................................................ 3-17
3.2.7 VDD–V IH/VIL characteristics ......................................................................................... 3-19
3.2.8 Detection voltage temperature characteristics of voltage drop detection circuit . 3-20
3.3 List of precautions .............................................................................................................. 3-21
3.4 Notes on noise ..................................................................................................................... 3-24
3.4.1 Shortest wiring length .................................................................................................. 3-24
3.4.2 Connection of bypass capacitor across VSS line and VDD line ............................ 3-26
3.4.3 Wiring to analog input pins ........................................................................................ 3-27
3.4.4 Oscillator concerns....................................................................................................... 3-27
3.4.5 Setup for I/O ports ....................................................................................................... 3-28
3.4.6 Providing of watchdog timer function by software .................................................. 3-28
3.5 Mask ROM order confirmation form ............................................................................... 3-30
3.6 Mark specification form ..................................................................................................... 3-36
3.7 Package outline ................................................................................................................... 3-39
4513/4514 Group User’s Manual
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
PIN CONFIGURATION (TOP VIEW) 4513 Group ..................................................................... 1-4
PIN CONFIGURATION (TOP VIEW) 4514 Group ..................................................................... 1-5
BLOCK DIAGRAM (4513 Group) ................................................................................................. 1-6
BLOCK DIAGRAM (4514 Group) ................................................................................................. 1-7
PORT BLOCK DIAGRAMS ......................................................................................................... 1-12
External interrupt circuit structure .............................................................................................. 1-16
Fig. 1 AMC instruction execution example ............................................................................... 1-17
Fig. 2 RAR instruction execution example ............................................................................... 1-17
Fig. 3 Registers A, B and register E ........................................................................................ 1-17
Fig. 4 TABP p instruction execution example .......................................................................... 1-17
Fig. 5 Stack registers (SKs) structure ....................................................................................... 1-18
Fig. 6 Example of operation at subroutine call ....................................................................... 1-18
Fig. 7 Program counter (PC) structure ..................................................................................... 1-19
Fig. 8 Data pointer (DP) structure ............................................................................................. 1-19
Fig. 9 SD instruction execution example .................................................................................. 1-19
Fig. 10 ROM map of M34514M8/E8 ......................................................................................... 1-20
Fig. 11 Page 1 (addresses 0080 16 to 00FF 16 ) structure ....................................................... 1-20
Fig. 12 RAM map ......................................................................................................................... 1-21
Fig. 13 Program example of interrupt processing ................................................................... 1-23
Fig. 14 Internal state when interrupt occurs ............................................................................ 1-23
Fig. 15 Interrupt system diagram ............................................................................................... 1-23
Fig. 16 Interrupt sequence .......................................................................................................... 1-25
Fig. 17 External interrupt circuit structure ................................................................................ 1-26
Fig. 18 Auto-reload function ....................................................................................................... 1-29
Fig. 19 Timers structure .............................................................................................................. 1-31
Fig. 20 Watchdog timer function ................................................................................................ 1-35
Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer .... 1-35
Fig. 22 Serial I/O structure ......................................................................................................... 1-36
Fig. 23 Serial I/O register state when transferring.................................................................. 1-37
Fig. 24 Serial I/O connection example...................................................................................... 1-38
Fig. 25 Timing of serial I/O data transfer ................................................................................. 1-39
Fig. 26 A-D conversion circuit structure ................................................................................... 1-41
Fig. 27 A-D conversion timing chart.......................................................................................... 1-44
Fig. 28 Setting registers .............................................................................................................. 1-44
Fig. 29 Comparator operation timing chart............................................................................... 1-45
Fig. 30 Definition of A-D conversion accuracy ........................................................................ 1-46
Fig. 31 Voltage comparator structure ........................................................................................ 1-47
Fig. 32 Reset release timing ...................................................................................................... 1-49
Fig. 33 RESET pin input waveform and reset operation ....................................................... 1-49
Fig. 34 Power-on reset circuit example .................................................................................... 1-50
Fig. 35 Internal state at reset .................................................................................................... 1-51
Fig. 36 Voltage drop detection reset circuit ............................................................................. 1-52
Fig. 37 Voltage drop detection circuit operation waveform.................................................... 1-52
Fig. 38 State transition ................................................................................................................ 1-55
Fig. 39 Set source and clear source of the P flag ................................................................. 1-55
Fig. 40 Start condition identified example using the SNZP instruction ................................ 1-55
Fig. 41 Clock control circuit structure ....................................................................................... 1-57
iv
4513/4514 Group User’s Manual
List of figures
Fig.
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42
43
44
45
46
47
48
49
50
51
52
Ceramic resonator external circuit ............................................................................... 1-58
External clock input circuit ............................................................................................ 1-58
External 0 interrupt program example ......................................................................... 1-59
External 1 interrupt program example ......................................................................... 1-59
A-D converter operating mode program example ...................................................... 1-60
Analog input external circuit example-1 ...................................................................... 1-60
Analog input external circuit example-2 ...................................................................... 1-60
Pin configuration of built-in PROM version of 4513 Group...................................... 1-88
Pin configuration of built-in PROM version of 4514 Group...................................... 1-88
PROM memory map ....................................................................................................... 1-89
Flow of writing and test of the product shipped in blank......................................... 1-89
CHAPTER 2 APPLICATION
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2.1.1 Key input by key scan................................................................................................. 2-7
2.1.2 Key scan input timing .................................................................................................. 2-8
2.2.1 INT0 interrupt operation example ............................................................................ 2-17
2.2.2 INT0 interrupt setting example ................................................................................. 2-18
2.2.3 INT1 interrupt operation example ............................................................................ 2-19
2.2.4 INT1 interrupt setting example ................................................................................. 2-20
2.2.5 Timer 1 constant period interrupt setting example................................................ 2-21
2.2.6 Timer 2 constant period interrupt setting example................................................ 2-22
2.2.7 Timer 3 constant period interrupt setting example................................................ 2-23
2.2.8 Timer 4 constant period interrupt setting example................................................ 2-24
2.3.1 Peripheral circuit example ......................................................................................... 2-30
2.3.2 Watchdog timer function............................................................................................ 2-31
2.3.3 Constant period measurement setting example ..................................................... 2-32
2.3.4 CNTR0 output setting example ................................................................................ 2-33
2.3.5 CNTR1 input setting example .................................................................................. 2-34
2.3.6 CNTR0 output control setting example ................................................................... 2-35
2.3.7 Timer start by external input setting example (1) ................................................. 2-36
2.3.8 Timer start by external input setting example (2) ................................................. 2-37
2.3.9 Watchdog timer setting example .............................................................................. 2-38
2.4.1 Serial I/O block diagram ........................................................................................... 2-40
2.4.2 Serial I/O connection example ................................................................................. 2-42
2.4.3 Serial I/O register state when transmitting/receiving ............................................ 2-42
2.4.4 Serial I/O transfer timing ........................................................................................... 2-43
2.4.5 Master serial I/O setting example ............................................................................ 2-46
2.4.6 Slave serial I/O example ........................................................................................... 2-47
2.4.7 Input waveform of external clock ............................................................................. 2-48
2.5.1 A-D converter structure ............................................................................................. 2-49
2.5.2 A-D conversion mode setting example ................................................................... 2-51
2.5.3 Analog input external circuit example-1 .................................................................. 2-52
2.5.4 Analog input external circuit example-2 .................................................................. 2-52
2.5.5 A-D converter operating mode program example.................................................. 2-52
2.7.1 Power-on reset circuit example ................................................................................ 2-56
2.7.2 Oscillation stabilizing time after system is released from reset .......................... 2-56
2.7.3 Internal state at reset ................................................................................................ 2-57
2.8.1 Voltage drop detection reset circuit ......................................................................... 2-58
2.8.2 Voltage drop detection circuit operation waveform ............................................... 2-58
2.9.1 Start condition identified example ............................................................................ 2-60
2.10.1 Oscillation circuit example connecting ceramic resonator externally................ 2-63
2.10.2 Structure of clock control circuit ............................................................................ 2-64
4513/4514 Group User’s Manual
v
List of figures
CHAPTER 3 APPENDIX
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vi
3.2.1 A-D conversion characteristics data ........................................................................ 3-14
44 External 0 interrupt program example ......................................................................... 3-21
45 External 1 interrupt program example ......................................................................... 3-21
46 A-D converter operating mode program example ...................................................... 3-22
47 Analog input external circuit example-1 ...................................................................... 3-22
48 Analog input external circuit example-2 ...................................................................... 3-22
3.4.1 Selection of packages ............................................................................................... 3-24
3.4.2 Wiring for the RESET input pin ............................................................................... 3-24
3.4.3 Wiring for clock I/O pins ........................................................................................... 3-25
3.4.4 Wiring for CNVSS pin ................................................................................................. 3-25
3.4.5 Wiring for the VPP pin of the One Time PROM version ...................................... 3-26
3.4.6 Bypass capacitor across the VSS line and the VDD line ...................................... 3-26
3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-27
3.4.8 Wiring for a large current signal line ...................................................................... 3-27
3.4.9 Wiring to a signal line where potential levels change frequently ....................... 3-28
3.4.10 VSS pattern on the underside of an oscillator ..................................................... 3-28
3.4.11 Watchdog timer by software ................................................................................... 3-29
4513/4514 Group User’s Manual
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Selection of system clock ................................................................................................ 1-11
1 ROM size and pages .................................................................................................... 1-20
2 RAM size ........................................................................................................................ 1-21
3 Interrupt sources ............................................................................................................ 1-22
4 Interrupt request flag, interrupt enable bit and skip instruction.............................. 1-22
5 Interrupt enable bit function ......................................................................................... 1-22
6 Interrupt control registers ............................................................................................. 1-24
7 External interrupt activated conditions........................................................................ 1-26
8 External interrupt control registers .............................................................................. 1-28
9 Function related timers ................................................................................................. 1-30
10 Timer control registers ................................................................................................ 1-32
11 Serial I/O pins .............................................................................................................. 1-36
12 Serial I/O mode register ............................................................................................. 1-36
13 Processing sequence of data transfer from master to slave ................................ 1-40
14 A-D converter characteristics ..................................................................................... 1-41
15 A-D control registers ................................................................................................... 1-42
16 Change of successive comparison register AD during A-D conversion .............. 1-43
17 Voltage comparator characteristics ........................................................................... 1-47
18 Voltage comparator control register Q3 ................................................................... 1-48
19 Port state at reset ....................................................................................................... 1-50
20 Functions and states retained at RAM back-up ..................................................... 1-53
21 Return source and return condition .......................................................................... 1-54
22 Key-on wakeup control register, pull-up control register, and interrupt control . 1-56
23 Clock control register MR .......................................................................................... 1-57
24 Maximum value of external clock oscillation frequency ......................................... 1-58
25 Product of built-in PROM version ............................................................................. 1-88
26 Programming adapters ................................................................................................ 1-89
CHAPTER 2 APPLICATION
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.2.1
2.2.2
2.2.3
2.2.4
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4.1
2.4.2
Pull-up control register PU0 .................................................................................... 2-4
Key-on wakeup control register K0 ........................................................................ 2-5
A-D control register Q2 ............................................................................................ 2-5
Direction register FR0 .............................................................................................. 2-6
Timer control register W6 ........................................................................................ 2-6
connections of unused pins ................................................................................... 2-10
Interrupt control register V1................................................................................... 2-14
Interrupt control register V2................................................................................... 2-14
Interrupt control register I1 .................................................................................... 2-15
Interrupt control register I2 .................................................................................... 2-15
Interrupt control register V1................................................................................... 2-27
Interrupt control register V2................................................................................... 2-27
Timer control register W1 ...................................................................................... 2-28
Timer control register W2 ...................................................................................... 2-28
Timer control register W3 ...................................................................................... 2-29
Timer control register W4 ...................................................................................... 2-29
Serial I/O mode register J1 ................................................................................... 2-41
Recommended operating conditions (serial I/O) ................................................. 2-48
4513/4514 Group User’s Manual
vii
List of tables
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2.5.1 A-D control register Q1 .......................................................................................... 2-50
2.5.2 A-D control register Q2 .......................................................................................... 2-50
2.5.3 Recommended operating conditions (when using A-D converter) ................... 2-53
2.6.1 Voltage comparator control register Q3 ............................................................... 2-54
2.9.1 Functions and states retained at RAM back-up mode ...................................... 2-59
2.9.2 Return source and return condition ...................................................................... 2-60
2.9.3 Start condition identification................................................................................... 2-60
2.9.4 Key-on wakeup control register K0 ...................................................................... 2-60
2.9.5 Pull-up control register PU0 .................................................................................. 2-61
2.9.6 Interrupt control register I1 .................................................................................... 2-61
2.9.7 Interrupt control register I2 .................................................................................... 2-62
2.10.1 Maximum value of oscillation frequency and supply voltage ......................... 2-63
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
viii
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
Absolute maximum ratings ....................................................................................... 3-2
Recommended operating conditions 1 ................................................................... 3-3
Recommended operating conditions 2 ................................................................... 3-4
Electrical characteristics ........................................................................................... 3-5
A-D converter recommended operating conditions............................................... 3-6
A-D converter characteristics .................................................................................. 3-6
Voltage drop detection circuit characteristics........................................................ 3-6
Voltage comparator recommended operating conditions ..................................... 3-7
Voltage comparator characteristics ......................................................................... 3-7
4513/4514 Group User’s Manual
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
BLOCK DIAGRAM
PERFORMANCE OVERVIEW
PIN DESCRIPTION
FUNCTION BLOCK OPERATIONS
ROM ORDERING METHOD
LIST OF PRECAUTIONS
SYMBOL
LIST OF INSTRUCTION FUNCTION
INSTRUCTION CODE TABLE
MACHINE INSTRUCTIONS
CONTROL REGISTERS
BUILT-IN PROM VERSION
HARDWARE
1-2
4513/4514 Group User’s Manual
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
The 4513/4514 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series
using a simple, high-speed instruction set. The computer is
equipped with serial I/O, four 8-bit timers (each timer has a reload
register), and 10-bit A-D conver ter.
The various microcomputers in the 4513/4514 Group include variations of the built-in memory type and package as shown in the
table below.
FEATURES
●Minimum instruction execution time ................................ 0.75 µ s
(at 4.0 MHz oscillation frequency, in high-speed mode, V DD = 4.0
V to 5.5 V)
●Supply voltage
• Middle-speed mode
...... 2.5 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask
ROM version and One Time PROM version)
...... 2.0 V to 5.5 V (at 3.0 MHz oscillation frequency, for Mask
ROM version)
(Operation voltage of A-D conversion: 2.7 V to 5.5 V)
• High-speed mode
...... 4.0 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask
ROM version and One Time PROM version)
...... 2.5 V to 5.5 V (at 2.0 MHz oscillation frequency, for Mask
ROM version and One Time PROM version)
...... 2.0 V to 5.5 V (at 1.5 MHz oscillation frequency, for Mask
ROM version)
(Operation voltage of A-D conversion: 2.7 V to 5.5 V)
Product
M34513M2-XXXSP/FP
M34513M4-XXXSP/FP
M34513E4SP/FP (Note)
M34513M6-XXXFP
M34513M8-XXXFP
M34513E8FP (Note)
M34514M6-XXXFP
M34514M8-XXXFP
M34514E8FP (Note)
ROM (PROM) size
(✕ 10 bits)
2048 words
4096 words
4096 words
6144 words
8192 words
8192 words
6144 words
8192 words
8192 words
●Timers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ...................................... 8-bit timer with a reload register
Timer 3 ...................................... 8-bit timer with a reload register
Timer 4 ...................................... 8-bit timer with a reload register
●Interrupt ........................................................................ 8 sources
●Serial I/O ....................................................................... 8 bit-wide
●A-D converter .................. 10-bit successive comparison method
●Voltage comparator ........................................................ 2 circuits
●Watchdog timer ................................................................. 16 bits
●Voltage drop detection circuit
●Clock generating circuit (ceramic resonator)
●LED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office automation equipment, etc.
RAM size
(✕ 4 bits)
128 words
256 words
256 words
384 words
384 words
384 words
384 words
384 words
384 words
Package
ROM type
SP: 32P4B FP: 32P6B-A
SP: 32P4B FP: 32P6B-A
SP: 32P4B FP: 32P6B-A
32P6B-A
32P6B-A
32P6B-A
42P2R-A
42P2R-A
42P2R-A
Mask ROM
Mask ROM
One Time PROM
Mask ROM
Mask ROM
One Time PROM
Mask ROM
Mask ROM
One Time PROM
Note: shipped in blank
4513/4514 Group User’s Manual
1-3
HARDWARE
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW) 4513 Group
1
32
P13
D1
2
31
P12
D2
3
30
P11
D3
4
29
P10
D4
5
28
P03
D5
6
27
P02
D6/CNTR0
7
26
P01
D7/CNTR1
8
25
P00
P20/SCK
9
24
AIN3/CMP1+
23
AIN2/CMP1-
22
AIN1/CMP0+
21
AIN0/CMP0-
20
P31/INT1
10
P22/SIN
11
M34513E4SP
P21/SOUT
M34513Mx-XXXSP
D0
RESET
12
CNVSS
13
XOUT
14
19
P30/INT0
XIN
15
18
VDCE
VSS
16
17
VDD
25 P03
26 P10
27 P11
28 P12
30 D0
29 P13
31 D1
32 D2
Outline 32P4B
D3 1
24 P02
D4 2
D5 3
23 P01
D6/CNTR0 4
M34513Mx-XXXFP
D7/CNTR1 5
P20/SCK 6
M34513ExFP
P21/SOUT 7
P22/SIN 8
21
20
AIN3/CMP1+
AIN2/CMP1-
19
AIN1/CMP0+
18
VDCE 15
P30/INT0 16
VSS 13
VDD 14
XIN 12
11
XOUT
CNVSS 10
RESET 9
AIN0/CMP017 P31/INT1
Outline 32P6B-A
1-4
22 P00
4513/4514 Group User’s Manual
HARDWARE
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW) 4514 Group
42 P12
D0 2
41 P11
D1 3
40 P10
D2 4
39 P03
D3 5
38 P02
D4 6
D6/CNTR0 8
D7/CNTR1 9
P50 10
P51 11
P52 12
P53 13
P20/SCK
14
P21/SOUT
15
P22/SIN 16
M34514E8FP
D5 7
M34514Mx-XXXFP
P13 1
RESET 17
CNVSS 18
XOUT
37 P01
36 P00
35 P43/AIN7
34 P42/AIN6
33 P41/AIN5
32 P40/AIN4
31 AIN3/CMP1+
30 AIN2/CMP129 AIN1/CMP0+
28 AIN0/CMP027 P33
26 P32
25 P31/INT1
24 P30/INT0
19
XIN 20
23 VDCE
22 VDD
VSS 21
Outline 42P2R-A
4513/4514 Group User’s Manual
1-5
1-6
Port P0
| [ Port
g o P1
1
4
4513/4514 Group User’s Manual
Serial I/O
(8 bits ✕ 1)
A-D converter
(10 bits ✕ 4 ch)
Watchdog timer
(16 bits)
Timer 4 (8 bits)
Timer 3 (8 bits)
Timer 2 (8 bits)
Timer 1 (8 bits)
Timer
Port P2
3
Register A (4 bits) Register B (4 bits)
Register D (3 bits) Register E (8 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1 level)
ALU (4 bits)
4500 Series
CPU core
Voltage comparator
(2 circuits)
Internal peripheral functions
I/O port
4
Port D
8
128, 256, 384 words × 4 bits
RAM
words × 10 bits
2048, 4096,6144, 8192
ROM
Memory
Voltage drop detection circuit
XIN–XOUT
System clock generating circuit
Port P3
2
HARDWARE
BLOCK DIAGRAM
BLOCK DIAGRAM (4513 Group)
Port P0
Port P1
4
Port P2
3
4
Port P4
Port D
8
4513/4514 Group User’s Manual
Serial I/O
(8 bits ✕ 1)
A-D converter
(10 bits ✕ 8 ch)
Register A (4 bits) Register B (4 bits)
Register D (3 bits) Register E (8 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1 level)
ALU (4 bits)
384 words × 4 bits
RAM
6144, 8192 words × 10 bits
ROM
Memory
Watchdog timer
(16 bits)
XIN—XOUT
System clock generating circuit
Port P5
4
Voltage drop detection circuit
4500 Series
CPU core
Voltage comparator
(2 circuits)
Port P3
4
Timer 4 (8 bits)
Timer 3 (8 bits)
Timer 2 (8 bits)
Timer 1 (8 bits)
Timer
Internal peripheral functions
I/O port
4
HARDWARE
BLOCK DIAGRAM
BLOCK DIAGRAM (4514 Group)
1-7
HARDWARE
PERFORMANCE OVERVIEW
PERFORMANCE OVERVIEW
Parameter
4513 Group
Number of
4514 Group
basic instructions
Minimum instruction execution time
M34513M2
Memory sizes ROM
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
RAM
M34513M2
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
I/O (Input is
Input/Output D0 –D7
examined by
ports
skip decision)
P00–P03 I/O
P10–P13 I/O
P20–P22 Input
P30–P33 I/O
Timers
P40–P43
P50–P53
CNTR0
CNTR1
INT0
INT1
Timer 1
Timer 2
Timer 3
Timer 4
I/O
I/O
I/O
I/O
Input
Input
A-D converter
Voltage comparator
Serial I/O
Sources
Interrupt
Nesting
Subroutine nesting
Device structure
4513 Group
Package
4514 Group
Operating temperature range
Supply voltage
Active mode
Power
dissipation
(typical value)
RAM back-up mode
1-8
Function
123
128
0.75 µs (at 4.0 MHz oscillation frequency, in high-speed mode)
2048 words ✕ 10 bits
4096 words ✕ 10 bits
6144 words ✕ 10 bits
8192 words ✕ 10 bits
6144 words ✕ 10 bits
8192 words ✕ 10 bits
128 words ✕ 4 bits
256 words ✕ 4 bits
384 words ✕ 4 bits
384 words ✕ 4 bits
384 words ✕ 4 bits
384 words ✕ 4 bits
Eight independent I/O ports;
ports D 6 and D7 are also used as CNTR0 and CNTR1, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
3-bit input port; ports P2 0, P21 and P2 2 are also used as SCK, SOUT and S IN, respectively.
4-bit I/O port (2-bit I/O port for the 4513 Group); ports P30 and P3 1 are also used as INT0 and
INT1, respectively. The 4513 Group does not have ports P32 , P33.
4-bit I/O port; The 4513 Group does not have this port.
4-bit I/O port with a direction register; The 4513 Group does not have this port.
1-bit I/O; CNTR0 pin is also used as port D6 .
1-bit I/O; CNTR1 pin is also used as port D7 .
1-bit input; INT0 pin is also used as port P3 0 and equipped with a key-on wakeup function.
1-bit input; INT1 pin is also used as port P3 1 and equipped with a key-on wakeup function.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register is also used as an event counter.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register is also used as an event counter.
10-bit wide, This is equipped with an 8-bit comparator function.
2 circuits (CMP0, CMP1)
8-bit ✕ 1
8 (two for external, four for timer, one for A-D, and one for serial I/O)
1 level
8 levels
CMOS silicon gate
32-pin plastic molded SDIP (32P4B)/LQFP(32P6B-A)
42-pin plastic molded SSOP (42P2R-A)
–20 °C to 85 °C
2.0 V to 5.5 V for Mask ROM version, 2.5 V to 5.5 V for One Time PROM version (Refer to the
electrical characteristics because the supply voltage depends on the oscillation frequency.)
1.8 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in middle- speed mode, output transistors in the cut-off state)
3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors
in the cut-off state)
0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)
4513/4514 Group User’s Manual
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Pin
VDD
VSS
VDCE
Name
Input/Output
Power supply
—
Ground
—
Voltage drop detecInput
tion circuit enable
CNVSS
RESET
CNVSS
Reset input
XIN
XOUT
D0 –D7
System clock input
System clock output
I/O port D
(Input is examined
by skip decision.)
P00 –P03
I/O port P0
I/O
P10 –P13
I/O port P1
I/O
P20 –P22
Input port P2
P30 –P33
I/O port P3
I/O
P40 –P43
I/O port P4
I/O
P50 –P53
I/O port P5
I/O
AIN0 –AIN7
Analog input
CNTR0
Timer input/output
I/O
CNTR1
Timer input/output
I/O
INT0, INT1
Interrupt input
Input
SIN
Serial data input
Input
SOUT
Serial data output
SCK
Serial I/O clock
input/output
CMP0CMP0+
Voltage comparator
input
Input
CMP1CMP1+
Voltage comparator
input
Input
—
I/O
Input
Output
I/O
Input
Input
Output
I/O
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
VDCE pin is used to control the operation/stop of the voltage drop detection circuit.
When “H” level is input to this pin, the circuit is operating. When “L” level is inpu to
this pin, the circuit is stopped.
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. When the watchdog timer
causes the system to be reset or system reset is performed by the voltage drop detection circuit, the RESET pin outputs “L” level.
I/O pins of the system clock generating circuit. X IN and XOUT can be connected to
ceramic resonator. A feedback resistor is built-in between them.
Each pin of port D has an independent 1-bit wide I/O function. Each pin has an output latch. For input use, set the latch of the specified bit to “1.” The output structure
is N-channel open-drain.
Ports D 6 and D7 are also used as CNTR0 and CNTR1, respectively.
Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs
when the output latch is set to “1.” The output structure is N-channel open-drain.
Every pin of the ports has a key-on wakeup function and a pull-up function. Both
functions can be switched by software.
3-bit input port. Ports P20 , P21 and P22 are also used as SCK, SOUT and SIN , respectively.
4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the
specified bit to “1.” The output structure is N-channel open-drain. Ports P30 and
P31 are also used as INT0 and INT1, respectively.
The 4513 Group does not have ports P3 2, P33 .
4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output
structure is N-channel open-drain. Ports P4 0–P43 are also used as analog input
pins A IN4–AIN7, respectively.
The 4513 Group does not have port P4.
4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O
function. For input use, set the direction register to “0.” For output use, set the direction regiser to “1.” The output structure is CMOS.
The 4513 Group does not have port P5.
Analog input pins for A-D converter. A IN0 –AIN3 are also used as voltage comparator input pins and A IN4–AIN7 are also used as port P4.
The 4513 Group does not have A IN4–AIN7.
CNTR0 pin has the function to input the clock for the timer 2 event counter, and to
output the timer 1 underflow signal divided by 2.
CNTR0 pin is also used as port D 6.
CNTR1 pin has the function to input the clock for the timer 4 event counter, and to
output the timer 3 underflow signal divided by 2.
CNTR1 pin is also used as port D 7.
INT0, INT1 pins accept external interrupts. They also accept the input signal to return the system from the RAM back-up state.
INT0, INT1 pins are also used as ports P3 0 and P31, respectively.
SIN pin is used to input serial data signals by software.
SIN pin is also used as port P22.
SOUT pin is used to output serial data signals by software.
SOUT pin is also used as port P2 1.
SCK pin is used to input and output synchronous clock signals for serial data transfer by software.
SCK pin is also used as port P20.
CMP0-, CMP0+ pins are used as the voltage comparator input pin when the voltage comparator function is selected by software.
CMP0-, CMP0+ pins are also used as AIN0 and AIN1.
CMP1-, CMP1+ pins are used as the voltage comparator input pin when the voltage comparator function is selected by software.
CMP1-, CMP1+ pins are also used as AIN2 and AIN3.
4513/4514 Group User’s Manual
1-9
HARDWARE
PIN DESCRIPTION
MULTIFUNCTION
Pin
D6
D7
P20
P21
P22
P30
P31
Multifunction
CNTR0
CNTR1
SCK
SOUT
SIN
INT0
INT1
Pin
CNTR0
CNTR1
SCK
SOUT
SIN
INT0
INT1
Multifunction
D6
D7
P20
P21
P22
P30
P31
Pin
AIN0
AIN1
AIN2
AIN3
P40
P41
P42
P43
Multifunction
CMP0CMP0+
CMP1CMP1+
AIN4
AIN5
AIN6
AIN7
Pin
CMP0CMP0+
CMP1CMP1+
AIN4
AIN5
AIN6
AIN7
Multifunction
AIN0
AIN1
AIN2
AIN3
P40
P41
P42
P43
Notes 1: Pins except above have just single function.
2: The input of D 6, D 7, P2 0–P22 , CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P3 1, P4 0–P4 3 can be used even when CNTR0, CNTR1,
SCK, S OUT, S IN, INT0, INT1, and AIN0–AIN7 are selected.
3: The 4513 Group does not have P4 0/A IN4–P43 /AIN7.
CONNECTIONS OF UNUSED PINS
Pin
XOUT
VDCE
D0–D5
D6/CNTR0
D7/CNTR1
P20/S CK
P21/S OUT
P22/S IN
P30/INT0
P31/INT1
P32, P3 3
P40/A IN4–P43/A IN7
P50–P53 (Note 1)
AIN0 /CMP0AIN1/CMP0+
AIN2 /CMP1AIN3/CMP1+
P00–P03
P10–P13
1-10
Connect to VSS , or set the output latch to
“0” and open.
Notes 1: After system is released from reset, port P5 is in an input mode (direction register FR0 = 00002)
2: When the P00–P03 and P10 –P13 are connected to V SS , turn off
their pull-up transistors (register PU0i=“0”) and also invalidate the
key-on wakeup functions (register K0i=“0”) by software. When
these pins are connected to V SS while the key-on wakeup functions are left valid, the system fails to return from RAM back-up
state. When these pins are open, turn on their pull-up transistors
(register PU0i=“1”) by software, or set the output latch to “0.”
Be sure to select the key-on wakeup functions and the pull-up
functions with every two pins. If only one of the two pins for the
key-on wakeup function is used, turn on their pull-up transistors by
software and also disconnect the other pin. (i = 0, 1, 2, or 3.)
Connect to VSS , or set the output latch to
“0” and open.
When the input mode is selected by software, pull-up to V DD through a resistor or
pull-down to V DD.
When selecting the output mode, open.
Connect to V SS.
(Note when the output latch is set to “0” and pins are open)
● After system is released from reset, port is in a high-impedance state until it is set the output latch to “0” by software. Accordingly, the voltage
level of pins is undefined and the excess of the supply current may occur
while the port is in a high-impedance state.
● To set the output latch periodically by software is recommended because
value of output latch may change by noise or a program run away
(caused by noise).
Connection
Open (when using an external clock).
Connect to V SS.
Connect to VSS , or set the output latch to
“0” and open.
Connect to V SS.
Open or connect to V SS (Note 2)
Open or connect to V SS (Note 2)
(Note when connecting to V SS and V DD)
● Connect the unused pins to V SS and V DD using the thickest wire at the
shortest distance against noise.
4513/4514 Group User’s Manual
HARDWARE
PIN DESCRIPTION
PORT FUNCTION
Port
Port D
Pin
Port P0
D0–D5
D6/CNTR0
D7/CNTR1
P00 –P03
Port P1
Port P2
Port P3
(Note 1)
Port P4
(Note 2)
Port P5
(Note 2)
Input
Output
I/O
(8)
Output structure
N-channel open-drain
I/O
unit
1
Control
instructions
SD, RD
SZD
CLD
OP0A
IAP0
Control
registers
Remark
W6
I/O
(4)
N-channel open-drain
4
PU0, K0
P10 –P13
I/O
(4)
N-channel open-drain
4
OP1A
IAP1
PU0, K0
P20 /SCK
P21 /SOUT
P22 /SIN
P30 /INT0
P31 /INT1
P32 , P33
P40 /AIN4
–P43 /AIN7
P50 –P53
Input
(3)
3
IAP2
J1
I/O
(4)
N-channel open-drain
4
OP3A
IAP3
I1, I2
I/O
(4)
I/O
(4)
N-channel open-drain
4
Q2
CMOS
4
OP4A
IAP4
OP5A
IAP5
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in key-on wakeup
function
(P30/INT0, P31 /INT1)
FR0
Notes 1: The 4513 Group does not have P32 and P3 3.
2: The 4513 Group does not have these ports.
DEFINITION OF CLOCK AND CYCLE
● System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bit 3 of the clock control register MR.
Table Selection of system clock
Register MR
MR 3
0
1
System clock
f(XIN)
f(XIN )/2
Note: f(XIN)/2 is selected after system is released from reset.
● Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
4513/4514 Group User’s Manual
1-11
HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS
K00
Pull-up
transistor
Key-on wakeup input
PU00
IAP0 instruction
Register A
P00,P01
Ai
D
OP0A instruction
T
Q
K01
Pull-up
transistor
Key-on wakeup input
PU01
IAP0 instruction
Register A
P02,P03
Ai
D
OP0A instruction
T
Q
K02
Pull-up
transistor
Key-on wakeup input
PU02
IAP1 instruction
P10,P11
Register A
Ai
D
OP1A instruction
T
Q
K0 3
Pull-up
transistor
Key-on wakeup input
PU03
IAP1 instruction
Register A
Ai
OP1A instruction
P12,P13
D
T
Q
•
•i
1-12
This symbol represents a parasitic diode on the port.
represents 0, 1, 2, or 3.
4513/4514 Group User’s Manual
HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
IAP2 instruction
Register A
Synchronous clock input for serial transfer
J11
P20/SCK
0
Synchronous clock output for serial transfer
1
J10
IAP2 instruction
Register A
J11
P21/SOUT
0
Serial data output
1
Serial data input
IAP2 instruction
Register A
P22/SIN
Key-on wakeup input
External interrupt circuit
IAP3 instruction
Register A
P30/INT0,P31/INT1
D
Ai
OP3A instruction
T
Q
IAP3 instruction
Register A
Ai
OP3A instruction
P32,P33
D
T
Q
This symbol represents a parasitic diode on the port.
•
• Applied potential to ports P20—P22 must be VDD.
• i represents 0, 1, 2, or 3.
• The 4513 Group does not have ports P32, P33.
4513/4514 Group User’s Manual
1-13
HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
Q1
Decoder
Analog input
Q30
CMP0
AIN0/CMP0-
+
Q32
Q1
Decoder
AIN1/CMP0+
Analog input
Q1
Decoder
Analog input
Q31
CMP1
AIN2/CMP1-
+
Q33
Q1
Decoder
AIN3/CMP1+
Analog input
IAP4 instruction
P40/AIN4–P43/AIN7
Register A
Ai
OP4A instruction
D
T Q
Q1
Decoder
Analog input
This symbol represents a parasitic diode on the port.
•
• i represents 0, 1, 2, or 3.
• The 4513 Group does not have port P4.
1-14
4513/4514 Group User’s Manual
HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
Direction register FR0i
Ai
D
OP5A instruction
T
P50–P53
Q
Register A
IAP5 instruction
Register Y
Decoder
Skip decision
(SZD instruction)
CLD instruction
D0–D5
S
SD instruction
RD instruction
R
Q
Skip decision (SZD instruction)
Clock input for timer 2 event count
Register Y
Decoder
CLD instruction
S
SD instruction
R
RD instruction
Q
W60
0
Timer 1 underflow signal divided by 2 or
signal of AND operation between
timer 1 underflow signal divided by 2 and
timer 2 underflow signal divided by 2
D6/CNTR0
1
Skip decision (SZD instruction)
Clock input for timer 4 event count
Register Y
Decoder
CLD instruction
S
SD instruction
R
RD instruction
Timer 3 underflow signal divided by 2 or
signal of AND operation between
timer 3 underflow signal divided by 2 and
timer 4 underflow signal divided by 2
Q
W62
0
D7/CNTR1
1
This symbol represents a parasitic diode on the port.
•
• Applied potential to ports D0–D7 must be 12 V.
• i represents 0, 1, 2, or 3.
• The 4513 Group does not have port P5.
4513/4514 Group User’s Manual
1-15
HARDWARE
PIN DESCRIPTION
I12
Falling
One-sided edge
detection circuit
0
I11
0
P30/INT0
1
EXF0
External 0
interrupt
EXF1
External 1
interrupt
1
Both edges
detection circuit
Rising
Wakeup
Skip
SNZI0
I22
Falling
One-sided edge
detection circuit
0
I21
0
P31/INT1
1
1
Both edges
detection circuit
Rising
Wakeup
Skip
SNZI1
This symbol represents a parasitic diode on the port.
External interrupt circuit structure
1-16
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
(M(DP))
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
Addition
ALU
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A3 A2 A1 A0
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
(4) Register D
Register B
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).
B3 B2 B1 B0
TAB instruction
Register A
A3 A 2 A1 A0
TEAB instruction
Register E E 7 E6 E5 E4 E3 E2 E 1 E0
TABE instruction
A3 A2 A1 A0
B3 B2 B1 B0
TBA instruction
Register B
Register A
Fig. 3 Registers A, B and register E
TABP p instruction
ROM
Specifying address
p6 p5
PCH
p4 p3 p2 p1 p0
PCL
DR2 DR1DR0 A3 A2 A1 A0
8
4
0
Low-order 4bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents of The contents of
register D
register A
Fig. 4 TABP p instruction execution example
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1-17
HARDWARE
FUNCTION BLOCK OPERATIONS
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations
together. The contents of registers SKs are destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
SK6
(SP) = 5
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the
contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table reference instruction.
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
Subroutine
Address
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC) ← (SK0)
(SP) ← 7
Note : Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
(8) Program counter (PC)
Program counter
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PC H does not specify after the last page of the
built-in ROM.
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure
8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
Specifying
RAM digit
Register Y (4)
Register X (4)
Register Z (2)
Specifying RAM file
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D7
0
1
0
D6
1
Register Y (4)
D5
D4
D0
1
Port D output latch
Fig. 9 SD instruction execution example
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1-19
HARDWARE
FUNCTION BLOCK OPERATIONS
PROGRAM MEMOY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed
of 10 bits. ROM is separated every 128 words by the unit of page
(addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34514M8/E8.
Table 1 ROM size and pages
Product
M34513M2
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
ROM size
(✕ 10 bits)
2048 words
4096 words
6144 words
8192 words
6144 words
8192 words
9 8
000016
007F16
008016
00FF16
010016
017F16
018016
7
6
5
4
3
2
1 0
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
Pages
16 (0 to 15)
32 (0 to 31)
48 (0 to 47)
64 (0 to 63)
48 (0 to 47)
64 (0 to 63)
A part of page 1 (addresses 0080 16 to 00FF 16 ) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt address
is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt
address.
Page 2 (addresses 0100 16 to 017F 16) is the special page for subroutine calls. Subroutines written in this page can be called from
any page with the 1-word instruction (BM). Subroutines extending
from page 2 to another page can also be called with the BM instruction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
0FFF16
Page 31
1FFF16
Page 63
Fig. 10 ROM map of M34514M8/E8
008016
9 8 7 6 5 4 3 2 1 0
External 0 interrupt address
008216
External 1 interrupt address
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
008816
Timer 3 interrupt address
008A16
Timer 4 interrupt address
008C16
A-D interrupt address
008E16
Serial I/O interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16 ) structure
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4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
DATA MEMORY (RAM)
Table 2 RAM size
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Product
M34513M2
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
128 words
256 words
384 words
384 words
384 words
384 words
RAM size
✕ 4 bits (512 bits)
✕ 4 bits (1024 bits)
✕ 4 bits (1536 bits)
✕ 4 bits (1536 bits)
✕ 4 bits (1536 bits)
✕ 4 bits (1536 bits)
RAM 384 words ✕ 4 bits (1536 bits)
Register Z
0
Register X 0 1 2 3 4 5 6 7
1
15 0 1 2 3 4 5 6 7
Register Y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M34513M6
M34513M8/E8
15
M34514M6
Z=0, X=0 to 15
M34514M8/E8 Z=1, X=0 to 7
384 words
256 words
M34513M4/E4 Z=0, X=0 to 15
M34513M2
Z=0, X=0 to 7
128 words
Fig. 12 RAM map
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1-21
HARDWARE
FUNCTION BLOCK OPERATIONS
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
Table 3 Interrupt sources
Priority
Interrupt name
level
1
External 0 interrupt
Activated condition
2
External 1 interrupt
3
Timer 1 interrupt
Level change of
INT0 pin
Level change of
INT1 pin
Timer 1 underflow
4
Timer 2 interrupt
Timer 2 underflow
5
Timer 3 interrupt
Timer 3 underflow
6
Timer 4 interrupt
Timer 4 underflow
7
A-D interrupt
8
Serial I/O interrupt
Completion of
A-D conversion
Completion of
serial I/O transfer
Interrupt
address
Address 0
in page 1
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
Address A
in page 1
Address C
in page 1
Address E
in page 1
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows
shown in Table 3.
1-22
Table 4 Interrupt request flag, interrupt enable bit and skip instruction
Interrupt name
Request flag
External 0 interrupt
EXF0
EXF1
External 1 interrupt
T1F
Timer 1 interrupt
T2F
Timer 2 interrupt
T3F
Timer 3 interrupt
T4F
Timer 4 interrupt
ADF
A-D interrupt
SIOF
Serial I/O interrupt
Skip instruction
SNZ0
SNZ1
SNZT1
SNZT2
SNZT3
SNZT4
SNZAD
SNZSI
Table 5 Interrupt enable bit function
Interrupt enable bit Occurrence of interrupt
Enabled
1
Disabled
0
4513/4514 Group User’s Manual
Enable bit
V10
V11
V12
V13
V20
V21
V22
V23
Skip instruction
Invalid
Valid
HARDWARE
FUNCTION BLOCK OPERATIONS
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as
follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an interrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Main
routine
• Stack register (SK)
The address of main routine to be
....................................................................................................
executed when returning
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
INT0 pin
(L→H or
H→L input)
(L→H or
H→L input)
Timer 1
underflow
Timer 3
underflow
Timer 4
underflow
•
•
•
•
Completion of
A-D conversion
EI
RTI
Interrupt is
enabled
EXF0
Address 0
in page 1
V10
INT1 pin
Timer 2
underflow
Interrupt
service routine
Interrupt
occurs
• Program counter (PC)
.............................................................. Each interrupt address
Completion of
serial I/O transfer
Activated
condition
EXF1
Address 2
in page 1
V11
T1F
V12
T2F
V13
T3F
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
V20
T4F
V21
ADF
V22
Address A
in page 1
Address C
in page 1
SIOF
V23
INTE
Request flag
(state retained)
Enable
bit
Enable
flag
Address E
in page 1
Fig. 15 Interrupt system diagram
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
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1-23
HARDWARE
FUNCTION BLOCK OPERATIONS
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, external 1, timer 1 and timer 2
are assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
• Interrupt control register V2
Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are assigned to register V2. Set the contents of this register through
register A with the TV2A instruction. The TAV2 instruction can be
used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
External 1 interrupt enable bit
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Serial I/O interrupt enable bit
V22
A-D interrupt enable bit
V21
Timer 4 interrupt enable bit
V20
Timer 3 interrupt enable bit
at RAM back-up : 00002
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
Note: “R” represents read enabled, and “W” represents write enabled.
1-24
R/W
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
0
1
0
1
0
1
0
1
at RAM back-up : 00002
4513/4514 Group User’s Manual
R/W
HARDWARE
FUNCTION BLOCK OPERATIONS
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10–V1 3 and V20 –V23 ), and interrupt request flag are
“1.” The interrupt actually occurs 2 to 3 machine cycles after the
cycle in which all three conditions are satisfied. The interrupt oc-
curs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions
(Refer to Figure 16).
When an interrupt request flag is set after its interrupt is enabled (Note 1)
f (XIN) (middle-speed mode)
f (XIN) (high-speed mode)
1 machine cycle
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
System clock
Interrupt enable
flag (INTE)
EI instruction
execution cycle
Interrupt disabled state
Interrupt enabled state
Retaining level of system
clock for 4 periods or more
is necessary.
INT0, INT1
External
interrupt
EXF0, EXF1
Timer 1,
Timer 2,
Timer 3,
Timer 4,
A-D, and
Serial I/O
interrupts
Interrupt activated
condition is satisfied.
T1F, T2F, T3F,
T4F, ADF,SIOF
Flag cleared
The program starts from
the interrupt address.
2 to 3 machine cycles
(Notes 2, 3)
Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset.
2: The address is stacked to the last cycle.
3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
4513/4514 Group User’s Manual
1-25
HARDWARE
FUNCTION BLOCK OPERATIONS
EXTERNAL INTERRUPTS
The 4513/4514 Group has two external interrupts (external 0 and
external 1). An external interrupt request occurs when a valid
waveform is input to an interrupt input pin (edge detection).
The external interrupts can be controlled with the interrupt control
registers I1 and I2.
Table 7 External interrupt activated conditions
Name
Input pin
Valid waveform
selection bit
I11
I12
Activated condition
External 0 interrupt
P30 /INT0
When the next waveform is input to P30/INT0 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
External 1 interrupt
P31 /INT1
When the next waveform is input to P31/INT1 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
I12
Falling
One-sided edge
detection circuit
0
I21
I22
I11
0
P30/INT0
1
EXF0
External 0
interrupt
EXF1
External 1
interrupt
1
Both edges
detection circuit
Rising
Wakeup
Skip
SNZI0
I22
Falling
0
One-sided edge
detection circuit
I21
0
P31/INT1
1
1
Rising
Both edges
detection circuit
Wakeup
Skip
SNZI1
This symbol represents a parasitic diode on the port.
Fig. 17 External interrupt circuit structure
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4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
(1) External 0 interrupt request flag (EXF0)
(2) External 1 interrupt request flag (EXF1)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to P30/INT0 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip
instruction.
The P30/INT0 pin need not be selected the external interrupt input
INT0 function or the normal I/O port P30 function. However, the
EXF0 flag is set to “1” when a valid waveform is input even if it is
used as an I/O port P30.
External 1 interrupt request flag (EXF1) is set to “1” when a valid
waveform is input to P31/INT1 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF1 flag can be examined with the skip instruction
(SNZ1). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip
instruction.
The P31/INT1 pin need not be selected the external interrupt input
INT1 function or the normal I/O port P31 function. However, the
EXF1 flag is set to “1” when a valid waveform is input even if it is
used as an I/O port P31 .
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to P30/INT0 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
• External 1 interrupt activated condition
External 1 interrupt activated condition is satisfied when a valid
waveform is input to P31/INT1 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 1 interrupt is as follows.
➀ Select the valid waveform with the bits 1 and 2 of register I1.
➁ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➂ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➃ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
➀ Select the valid waveform with the bits 1 and 2 of register I2.
➁ Clear the EXF1 flag to “0” with the SNZ1 instruction.
➂ Set the NOP instruction for the case when a skip is performed
with the SNZ1 instruction.
➃ Set both the external 1 interrupt enable bit (V11) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid waveform is input to the P30/INT0 pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
The external 1 interrupt is now enabled. Now when a valid waveform is input to the P31 /INT1 pin, the EXF1 flag is set to “1” and the
external 1 interrupt occurs.
4513/4514 Group User’s Manual
1-27
HARDWARE
FUNCTION BLOCK OPERATIONS
(3) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
• Interrupt control register I2
Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the
TI2A instruction. The TAI2 instruction can be used to transfer the
contents of register I2 to register A.
Table 8 External interrupt control registers
Interrupt control register I1
I1 3
Not used
I1 2
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
at reset : 00002
0
1
0
1
I11
INT0 pin edge detection circuit control bit
I1 0
INT0 pin
timer 1 control enable bit
0
1
0
1
Interrupt control register I2
I2 3
Not used
I2 2
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
I2 1
I2 0
0
1
INT1 pin edge detection circuit control bit
INT1 pin
timer 3 control enable bit
0
1
0
1
R/W
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
at reset : 00002
0
1
at RAM back-up : state retained
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
instruction)/“L” level
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I1 2 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I2 2 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
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4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
TIMERS
The 4513/4514 Group has the programmable timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a setting
value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
“1”
Timer interrupt
“0”
request flag
An interrupt occurs or
a skip instruction is executed.
Fig. 18 Auto-reload function
4513/4514 Group User’s Manual
1-29
HARDWARE
FUNCTION BLOCK OPERATIONS
The 4513/4514 Group timer consists of the following circuits.
• Prescaler : frequency divider
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 8-bit programmable timer
• Timer 4 : 8-bit programmable timer
(Timers 1 to 4 have the interrupt function, respectively)
• 16-bit timer
Prescaler and timers 1 to 4 can be controlled with the timer control
registers W1 to W6. The 16-bit timer is a free counter which is not
controlled with the control register.
Each function is described below.
Table 9 Function related timers
Circuit
Prescaler
Timer 1
Timer 2
Timer 3
Timer 4
16-bit timer
1-30
Structure
Frequency divider
8-bit programmable
binary down counter
Count source
• Instruction clock
• Prescaler output (ORCLK)
(link to P30/INT0 input)
• Timer 1 underflow
8-bit programmable
binary down counter
• Prescaler output (ORCLK)
• CNTR0 input
• 16-bit timer underflow
• Timer 2 underflow
8-bit programmable
• Prescaler output (ORCLK)
binary down counter
(link to P31/INT1 input)
8-bit programmable
• Timer 3 underflow
• Prescaler output (ORCLK)
binary down counter
• CNTR1 input
16-bit fixed dividing
frequency
• Instruction clock
Frequency
dividing ratio
4, 16
1 to 256
Use of output signal
• Timer 1, 2, 3 and 4 count sources
• Timer 2 count source
• CNTR0 output
• Timer 1 interrupt
Control
register
W1
W1
W6
1 to 256
• Timer 3 count source
• Timer 2 interrupt
• CNTR0 output
W2
W6
1 to 256
• Timer 4 count source
W3
W6
1 to 256
65536
• Timer 3 interrupt
• CNTR1 output
• Timer 4 interrupt
• CNTR1 output
• Watchdog timer
(The 15th bit is counted twice)
• Timer 2 count source
(16-bit timer underflow)
4513/4514 Group User’s Manual
W4
W6
HARDWARE
FUNCTION BLOCK OPERATIONS
Instruction clock
Prescaler
W13
Divistion circuit
(divided by 2)
MR3
XIN
1
0
Internal clock
generating circuit
(divided by 3)
I12
0
P30/INT0
1/4
0
1
1/16
1
1
0
Both edges
detection circuit
Rising
ORCLK
I11
One-sided edge
detection circuit
Falling
W12
0
(Note 1)
SQ
1
I10
W10
1
0
R
W11 (Note 3)
0
Timer 1 (8)
T1F
Timer 1
interrupt
T2F
Timer 2
interrupt
1
Reload register R1 (8)
T1AB
(TAB1)
(TR1AB)
T1AB
Register B Register A
Timer 1 underflow signal
W21,W20
W23(Note 3)
00
0
01
Timer 2 (8)
1
10 Not available
11
Reload register R2 (8)
(T2AB)
(TAB2)
I22
Falling
P31/INT1
0
One-sided edge
detection circuit
1
Rising
Both edges
detection circuit
Register B Register A
I21
0
1
I20
W31,W30
Timer 2 underflow signal
(Note 2)
W32
SQ
1
0
R
W33(Note 3)
00
0
01
10Not available
11Not available
Timer 3 (8)
1
T3F
Timer 3
interrupt
Reload register R3 (8)
T3AB
(TAB3)
(TR3AB)
T3AB
Register B Register A
Timer 3 underflow signal
W41,W40
W43(Note 3)
00
0
01
10Not available
1
11Not available
Timer 4 (8)
T4F
Timer 4
interrupt
Reload register R4 (8)
(T4AB)
(TAB4)
Register B Register A
Data is set automatically from each reload
16-bit timer (WDT)
register when timer 1, 2, 3, or 4 underflows
Instruction clock
1 - - - - - - - - - - - 15 16
(auto-reload function)
Notes 1: Timer 1 count start synchronous circuit is set
by the valid edge of P30/INT0 pin selected by
S
WRST instruction
bits 1 (I11) and 2 (I12) of register I1.
WEF Q
Reset signal
R
2: Timer 3 count start synchronous circuit is set
by the valid edge of P31/INT1 pin selected by
bits 1 (I21) and 2 (I22) of register I2.
3: Count source is stopped by clearing to “0.”
System reset
WDF1 WDF2
Fig. 19 Timers structure
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1-31
HARDWARE
FUNCTION BLOCK OPERATIONS
Table 10 Timer control registers
Timer control register W1
at reset : 00002
W13
Prescaler control bit
W12
Prescaler dividing ratio selection bit
W11
Timer 1 control bit
W10
Timer 1 count start synchronous circuit
control bit
0
1
0
1
0
1
0
1
Timer control register W2
W23
Timer 2 control bit
W22
Not used
0
1
0
1
W21 W20
0
0
0
1
1
0
1
1
Timer 2 count source selection bits
W20
Timer control register W3
Timer 3 control bit
W32
Timer 3 count start synchronous circuit
control bit
W31
Timer 3 count source selection bits
W30
0
1
0
1
W31 W30
0
0
0
1
1
0
1
1
Timer control register W4
W43
Timer 4 control bit
W42
Not used
W41
Timer 4 count source selection bits
W40
Timer control register W6
W63
CNTR1 output control bit
W62
D7/CNTR1 function selection bit
W61
CNTR0 output control bit
W60
D6/CNTR0 output control bit
Count source
Timer 1 underflow signal
Prescaler output
CNTR0 input
16 bit timer (WDT) underflow signal
R/W
at RAM back-up : state retained
R/W
Stop (state retained)
Operating
This bit has no function, but read/write is enabled.
Count source
Timer 3 underflow signal
Prescaler output
CNTR1 input
Not available
at RAM back-up : state retained
R/W
Timer 3 underflow signal output divided by 2
CNTR1 output control by timer 4 underflow signal divided by 2
D7 (I/O)/CNTR1 input
CNTR1 (I/O)/D7 (input)
Timer 1 underflow signal output divided by 2
CNTR0 output control by timer 2 underflow signal divided by 2
D6 (I/O)/CNTR0 input
CNTR0 (I/O)/D6 (input)
Note: “R” represents read enabled, and “W” represents write enabled.
1-32
at RAM back-up : state retained
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
Count source
Timer 2 underflow signal
Prescaler output
Not available
Not available
at reset : 00002
0
1
0
1
0
1
0
1
R/W
This bit has no function, but read/write is enabled.
at reset : 00002
0
1
0
1
W41 W40
0
0
0
1
1
0
1
1
at RAM back-up : state retained
Stop (state retained)
Operating
at reset : 00002
W33
R/W
Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
at reset : 00002
W21
at RAM back-up : 00002
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
(1) Timer control registers
(4) Timer 1 (interrupt function)
• Timer control register W1
Register W1 controls the count operation of timer 1, the selection
of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this
register through register A with the TW1A instruction. The TAW1
instruction can be used to transfer the contents of register W1 to
register A.
• Timer control register W2
Register W2 controls the count operation and count source of
timer 2. Set the contents of this register through register A with
the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.
• Timer control register W3
Register W3 controls the count operation and count source of
timer 3 and the selection of count start synchronous circuit. Set
the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the
contents of register W3 to register A.
• Timer control register W4
Register W4 controls the count operation and count source of
timer 4. Set the contents of this register through register A with
the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A.
• Timer control register W6
Register W6 controls the D 6/CNTR0 pin and D7 /CNTR1 functions, the selection and operation of the CNTR0 and CNTR1
output. Set the contents of this register through register A with
the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload
register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction.
When writing data to reload register R1 with the TR1AB instruction,
the downcount after the underflow is started from the setting value
of reload register R1.
Timer 1 starts counting after the following process;
➀ set data in timer 1, and
➁ set the bit 1 of register W1 to “1.”
However, P3 0/INT0 pin input can be used as the start trigger for
timer 1 count operation by setting the bit 0 of register W1 to “1.”
When a value set in timer 1 is n, timer 1 divides the count source
signal by n + 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the timer
1 interrupt request flag (T1F) is set to “1,” new data is loaded from
reload register R1, and count continues (auto-reload function).
Data can be read from timer 1 with the TAB1 instruction. When
reading the data, stop the counter and then execute the TAB1 instruction. Timer 1 underflow signal divided by 2 can be output from
D6/CNTR0 pin.
(2) Precautions
Note the following for the use of timers.
• Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
• Count source
Stop timer 1, 2, 3, or 4 counting to change its count source.
• Reading the count value
Stop timer 1, 2, 3, or 4 counting and then execute the TAB1,
TAB2, TAB3, or TAB4 instruction to read its data.
• Writing to reload registers R1 and R3
When writing data to reload registers R1 or R3 while timer 1 or
timer 3 is operating, avoid a timing when timer 1 or timer 3
underflows.
(5) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload
register (R2) with the T2AB instruction.
Timer 2 starts counting after the following process;
➀ set data in timer 2,
➁ select the count source with the bits 0 and 1 of register W2, and
➂ set the bit 3 of register W2 to “1.”
When a value set in timer 2 is n, timer 2 divides the count source
signal by n + 1 (n = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2, and count continues (auto-reload function).
Data can be read from timer 2 with the TAB2 instruction. When
reading the data, stop the counter and then execute the TAB2 instruction. The output from D 6/CNTR0 pin by timer 2 underflow
signal divided by 2 can be controlled.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio can be
selected. The count source of prescaler is the instruction clock.
Use the bit 2 of register W1 to select the prescaler dividing ratio
and the bit 3 to start and stop its operation. Prescaler is initialized,
and the output signal (ORCLK) stops when the bit 3 of register W1
is cleared to “0.”
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1-33
HARDWARE
FUNCTION BLOCK OPERATIONS
(6) Timer 3 (interrupt function)
(9) Timer I/O pin (D 6/CNTR0, D7/CNTR1)
Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload
register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction.
When writing data to reload register R3 with the TR3AB instruction,
the downcount after the underflow is started from the setting value
of reload register R3.
Timer 3 starts counting after the following process;
➀ set data in timer 3,
➁ select the count source with the bits 0 and 1 of register W3, and
➂ set the bit 3 of register W3 to “1.”
However, P3 1/INT1 pin input can be used as the star t trigger for
timer 3 count operation by setting the bit 2 of register W3 to “1.”
When a value set in timer 3 is n, timer 3 divides the count source
signal by n + 1 (n = 0 to 255).
Once count is started, when timer 3 underflows (the next count
pulse is input after the contents of timer 3 becomes “0”), the timer
3 interrupt request flag (T3F) is set to “1,” new data is loaded from
reload register R3, and count continues (auto-reload function).
Data can be read from timer 3 with the TAB3 instruction. When
reading the data, stop the counter and then execute the TAB3 instruction. Timer 3 underflow signal divided by 2 can be output from
D7/CNTR1 pin.
D6/CNTR0 pin has functions to input the timer 2 count source, and
to output the timer 1 and timer 2 underflow signals divided by 2. D7 /
CNTR1 pin has functions to input the timer 4 count source, and to
output the timer 3 and timer 4 underflow signals divided by 2.
The selection of D6/CNTR0 pin function can be controlled with the
bit 0 of register W6. The selection of D7/CNTR1 pin function can be
controlled with the bit 2 of register W6.
The following signals can be selected for the CNTR0 output signal
with the bit 1 of register W6.
• timer 1 underflow signal divided by 2
• the signal of AND operation between timer 1 underflow signal divided by 2 and timer 2 underflow signal divide by 2
The following signals can be selected for the CNTR1 output signal
with the bit 3 of register W6.
• timer 3 underflow signal divided by 2
• the signal of AND operation between timer 3 underflow signal divided by 2 and timer 4 underflow signal divide by 2
Timer 2 counts the rising waveform of CNTR0 input when the
CNTR0 input is selected as the count source.
Timer 4 counts the rising waveform of CNTR1 input when the
CNTR1 input is selected as the count source.
(7) Timer 4 (interrupt function)
Each of timer 1 and timer 3 has the count start synchronous circuit
which synchronizes P30/INT0 pin and P3 1/INT1 pin, respectively,
and can start the timer count operation.
Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register W1 to “1.” The control by P3 0/INT0 pin input
can be performed by setting the bit 0 of register I1 to “1.”
The count start synchronous circuit is set by level change (“H”→“L”
or “L”→“H”) of P30 /INT0 pin input. This valid waveform is selected
by bits 1 (I11) and 2 (I12) of register I1 as follows;
• I11 = “0”: Synchronized with one-sided edge (falling or rising)
• I11 = “1”: Synchronized with both edges (both falling and rising)
When register I11=“0” (synchronized with the one-sided edge), the rising or falling waveform can be selected by bit 2 of register I1;
• I12 = “0”: Falling waveform
• I12 = “1”: Rising waveform
Timer 3 count start synchronous circuit function is selected by setting the bit 2 of register W3 to “1.” The control by P3 1/INT1 pin input
can be performed by setting the bit 0 of register I2 to “1.”
The count start synchronous circuit is set by level change (“H”→“L”
or “L”→“H”) of P31 /INT1 pin input. This valid waveform is selected
by bits 1 (I21) and 2 (I22) of register I2 as follows;
• I21 = “0”: Synchronized with one-sided edge (falling or rising)
• I21 = “1”: Synchronized with both edges (both falling and rising)
When register I21=“0” (synchronized with the one-sided edge), the rising or falling waveform can be selected by bit 2 of register I2;
• I22 = “0”: Falling waveform
• I22 = “1”: Rising waveform
When timer 1 and timer 3 count start synchronous circuits are
used, the count start synchronous circuits are set, the count source
is input to each timer by inputting valid waveform to P30/INT0 pin
and P3 1/INT1 pin. Once set, the count start synchronous circuit is
cleared by clearing the bit I10 or I2 0 to “0” or reset.
Timer 4 is an 8-bit binary down counter with the timer 4 reload register (R4). Data can be set simultaneously in timer 4 and the reload
register (R4) with the T4AB instruction.
Timer 4 starts counting after the following process;
➀ set data in timer 4,
➁ select the count source with the bits 0 and 1 of register W4, and
➂ set the bit 3 of register W4 to “1.”
When a value set in timer 4 is n, timer 4 divides the count source
signal by n + 1 (n = 0 to 255).
Once count is started, when timer 4 underflows (the next count
pulse is input after the contents of timer 4 becomes “0”), the timer
4 interrupt request flag (T4F) is set to “1,” new data is loaded from
reload register R4, and count continues (auto-reload function).
Data can be read from timer 4 with the TAB4 instruction. When
reading the data, stop the counter and then execute the TAB4 instruction. The output from D7 /CNTR1 pin by timer 4 underflow
signal divided by 2 can be controlled.
(8) Timer interrupt request flags (T1F, T2F,
T3F, and T4F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2, SNZT3, and SNZT4).
Use the interrupt control registers V1, V2 to select an interrupt or a
skip instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.
1-34
(10) Count start synchronous circuit (timer 1
and 3)
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of a 16-bit timer (WDT),
watchdog timer enable flag (WEF), and watchdog timer flags
(WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source. The underflow signal is generated when the count value
reaches “000016 .” This underflow signal can be used as the timer 2
count source.
When the WRST instruction is executed after system is released
from reset, the WEF flag is set to “1”. At this time, the watchdog
timer starts operating.
When the count value of timer WDT reaches “BFFF16” or “3FFF 16,”
the WDF1 flag is set to “1.” If the WRST instruction is never executed while timer WDT counts 32767, WDF2 flag is set to “1,” and
the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 32766 machine cycle
or less by software when using watchdog timer to keep the microcomputer operating normally.
To prevent the WDT stopping in the event of misoperation, WEF
flag is designed not to initialize once the WRST instruction has
been executed. Note also that, if the WRST instruction is never executed, the watchdog timer does not start.
FFFF16
BFFF16
3FFF16
The value of timer (WDT)
0000 16
WEF flag
WDF1 flag
WDF2 flag
RESET pin output
WRST
instruction
executed
WRST
instruction
executed
System reset
Fig. 20 Watchdog timer function
The contents of WEF, WDF1 and WDF2 flags and timer WDT are
initialized at the RAM back-up mode.
If WDF2 flag is set to “1” at the same time that the microcomputer
enters the RAM back-up state, system reset may be performed.
When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state (refer to Figure 21)
••
•
•
•
•
WRST
EPOF
; WDF1 flag reset
; POF instruction enabled
POF
Oscillation
stop
(RAM back-up state)
Fig. 21 Program example to enter the RAM back-up mode
when using the watchdog timer
4513/4514 Group User’s Manual
1-35
HARDWARE
FUNCTION BLOCK OPERATIONS
SERIAL I/O
Table 11 Serial I/O pins
The 4513/4514 Group has a built-in clock synchronous serial I/O
which can serially transmit or receive 8-bit data.
Serial I/O consists of;
• serial I/O register SI
• serial I/O mode register J1
• serial I/O transmission/reception completion flag (SIOF)
• serial I/O counter
Registers A and B are used to perform data transfer with internal
CPU, and the serial I/O pins are used for external data transfer.
The pin functions of the serial I/O pins can be set with the register
J1.
Division circuit
(divided by 2)
Pin
P20 /SCK
P21 /SOUT
P22 /SIN
Note: Input ports P20 –P22 can be used regardless of register J1.
MR3
Internal clock
generation circuit
(divided by 3)
1
XIN
0
Instruction clock
J12
1/4
1/8
P20/SCK
P21/SOUT
P22/SIN
Pin function when selecting serial I/O
Clock I/O (SCK)
Serial data output (SOUT)
Serial data input (SIN)
Serial I/O mode register J1
1
J13
J12
J11
J10
0
Synchronous
circuit
SCK
Serial I/O counter (3)
SIOF
Serial I/O interrupt
SOUT
SIN
MSB
Serial I/O register SI (8)
TSIAB
J11
J10
Register B (4)
LSB
TABSI
Register A (4)
Note: The output structure of SCK and SOUT pins is N-channel open-drain.
Fig. 22 Serial I/O structure
Table 12 Serial I/O mode register
Serial I/O mode register J1
at reset : 00002
J13
Not used
J12
Serial I/O internal clock dividing ratio
selection bit
J11
Serial I/O port selection bit
J10
Serial I/O synchronous clock selection bit
0
1
0
1
0
1
0
1
R/W
This bit has no function, but read/write is enabled.
Instruction clock signal divided by 8
Instruction clock signal divided by 4
Input ports P20, P2 1, P22 selected
Serial I/O ports SCK, SOUT, SIN/input ports P20 , P21 , P22 selected
External clock
Internal clock (instruction clock divided by 4 or 8)
Note: “R” represents read enabled, and “W” represents write enabled.
1-36
at RAM back-up : state retained
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
When transmitting (D7–D0 : transfer data)
Serial I/O register (SI)
When receiving
SIN pin
SOUT pin
SOUT pin
SIN pin
Serial I/O register (SI)
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
∗
D7 D6 D5 D4 D3 D2 D1
∗ ∗
Transfer started
D7 D6 D5 D4 D3 D2
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
Transfer data to be set
D0
∗ ∗ ∗ ∗ ∗ ∗ ∗
D1 D0
Transfer completed
∗ ∗ ∗ ∗ ∗ ∗
D7 D6 D5 D4 D3 D2 D1 D0
Fig. 23 Serial I/O register state when transferring
(1) Serial I/O register SI
(3) Serial I/O start instruction (SST)
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and
B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of
register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When register SI is used as a work register without using serial I/O,
pull up the SCK pin or set the pin function to an input port P20 .
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial I/O transmission/reception is started.
(4) Serial I/O mode register J1
Register J1 controls the synchronous clock, P20/SCK , P21/SOUT
and P2 2/S IN pin function. Set the contents of this register through
register A with the TJ1A instruction. The TAJ1 instruction can be
used to transfer the contents of register J1 to register A.
(2) Serial I/O transmission/reception
completion flag (SIOF)
Serial I/O transmission/reception completion flag (SIOF) is set to
“1” when serial data transmission or reception completes. The
state of SIOF flag can be examined with the skip instruction
(SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
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1-37
HARDWARE
FUNCTION BLOCK OPERATIONS
(5) How to use serial I/O
Figure 24 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the
Slave (external clock)
Master (clock control)
SRDY signal
D5
✕
✕
(Bit 3)
0
✕
1
✕
1
D5
SCK
SCK
SOUT
SIN
SIN
SOUT
(Bit 0)
(Bit 3)
wiring between each pin with a resistor. Figure 25 shows the data
transfer timing and Table 13 shows the data transfer sequence.
Serial I/O mode register J1
(Bit 3)
✕
✕
1
(Bit 0)
0 Serial I/O mode register J1
Internal clock selected as
a synchronous clock
External clock selected as
a synchronous clock
Serial I/O port
SCK,SOUT,SIN
Serial I/O port
SCK,SOUT,SIN
Instruction clock divided by
8 or 4 selected as a transfer
clock
This bit is not valid
when J1 0=“0”
(Bit 0)
Interrupt control register V2
✕
(Bit 3)
0
✕
✕
Serial I/O interrupt enable bit
(SNZSI instruction is valid)
(Bit 0)
✕ Interrupt control register V2
Serial I/O interrupt enable bit
(SNZSI instruction is valid)
✕ : Set an arbitrary value.
Fig. 24 Serial I/O connection example
1-38
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
Master
SOUT
M7’
SIN
S7’
S0
M3
M2
M1
M0
S1
M4
S2
S3
M5
S4
M6
S5
M7
S6
S7
SST instruction
SCK
Slave
SST instruction
SRDY signal
SOUT
SIN
S1
S0
S7’
M7’
M0
S2
M1
S3
M2
S4
M3
S5
M4
S6
M5
S7
M6
M7
M0–M7 : the contents of master serial I/O S0–S7 : the contents of slave serial I/O register
Rising of SCK : serial input Falling of SCK : serial output
Fig. 25 Timing of serial I/O data transfer
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HARDWARE
FUNCTION BLOCK OPERATIONS
Table 13 Processing sequence of data transfer from master to slave
Master (transmission)
[Initial setting]
• Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 24.
TJ1A and TV2A instructions
• Setting the port received the reception enable
signal (SRDY ) to the input mode.
(Port D5 is used in this example)
SD instruction
* [Transmission enable state]
• Storing transmission data to serial I/O register SI.
TSIAB instruction
[Transmission]
•Check port D5 is “L” level.
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
SNZSI instruction
•Wait (timing when continuously transferring)
Slave (reception)
[Initial setting]
• Setting serial I/O mode register J1, and interrupt control register V2 shown in
Figure 24.
TJ1A and TV2A instructions
• Setting the port transmitted the reception enable signal (SRDY) and outputting
“H” level (reception impossible).
(Port D5 is used in this example)
SD instruction
*[Reception enable state]
• The SIOF flag is cleared to “0.”
SST instruction
• “L” level (reception possible) is output from port D5 .
RD instruction
[Reception]
• Check reception completes.
SNZSI instruction
• “H” level is output from port D 5.
SD instruction
[Data processing]
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally because serial transfer is performed as long as clock is externally
input. (Unlike an internal clock, an external clock is not stopped
when serial transfer is completed.) However, the SIOF flag is set to
“1” when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to “H.”
1-40
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
A-D CONVERTER
Table 14 A-D converter characteristics
Parameter
Characteristics
Conversion format
Successive comparison method
Resolution
10 bits
Relative accuracy
Linearity error: ±2LSB
Non-linearity error: ±0.9LSB
Conversion speed
46.5 µs (High-speed mode at 4.0 MHz
oscillation frequency)
Analog input pin
4 for 4513 Group
8 for 4514 Group
The 4513/4514 Group has a built-in A-D conversion circuit that
performs conversion by 10-bit successive comparison method.
Table 14 shows the characteristics of this A-D converter. This AD converter can also be used as an 8-bit comparator to compare
analog voltages input from the analog input pin with preset values.
Register B (4)
Register A (4)
4
TAQ2
TQ2A
IAP4
(P40—P43)
Q23 Q22 Q21 Q20
4
TAQ1
TQ1A
Q13 Q12 Q11 Q10
4
4
2
8
TALA
TABAD
8
TADAB
Instruction clock
OP4A
(P40—P43)
1/6
3
Q23
AIN1/CMP0+
AIN2/CMP1AIN3/CMP1+
P40/AIN4
P41/AIN5
P42/AIN6
P43/AIN7
8-channel multi-plexed analog switch
0
(Note 3)
AIN0/CMP0-
ADF
(1)
A-D control circuit
1
A-D interrupt
1
Successive comparison
register (AD) (10)
Comparator
0
Q23
Q23
DAC
operation
signal
0
8
10
10
0
1
1
1
Q23
8
8
DA converter
(Note 1)
8
VDD
VSS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q23=1).
The value of the comparator register is retained even when the mode is switched to the A-D conversion
mode (Q23=0) because it is separated from the successive comparison register (AD). Also, the resolution in
the comparator mode is 8 bits because the comparator register consists of 8 bits.
3: The 4513 Group does not have ports P40/AIN4–P43/AIN7 and the IAP4 and OP4A instructions.
Fig. 26 A-D conversion circuit structure
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1-41
HARDWARE
FUNCTION BLOCK OPERATIONS
Table 15 A-D control registers
A-D control register Q1
Q13
at reset : 00002
Not used
Q12
Q11
Analog input pin selection bits (Note 2)
Q10
0
1
Q12Q11 Q10
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A-D control register Q2
Q23
Q22
Q21
Q20
P4 3/A IN7 and P42/A IN6 pin function selection bit (Not used for the 4513 Group)
P41/A IN5 pin function selection bit
(Not used for the 4513 Group)
P40/A IN4 pin function selection bit
(Not used for the 4513 Group)
0
1
0
1
0
1
0
1
R/W
This bit has no function, but read/write is enabled.
Selected pins
AIN0
AIN1
AIN2
AIN3
AIN4 (Not available for the 4513 Group)
AIN5 (Not available for the 4513 Group)
AIN6 (Not available for the 4513 Group)
AIN7 (Not available for the 4513 Group)
at reset : 00002
A-D operation mode selection bit
at RAM back-up : state retained
at RAM back-up : state retained
R/W
A-D conversion mode
Comparator mode
P43, P4 2
(read/write enabled for the 4513 Group)
AIN7, AIN6/P4 3, P42 (read/write enabled for the 4513 Group)
P41
(read/write enabled for the 4513 Group)
AIN5 /P41
P40
AIN4 /P40
(read/write enabled for the 4513 Group)
(read/write enabled for the 4513 Group)
(read/write enabled for the 4513 Group)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select A IN4–A IN7 with register Q1 after setting register Q2.
(1) Operating at A-D conversion mode
(4) A-D conversion start instruction (ADST)
The A-D conversion mode is set by setting the bit 3 of register Q2 to “0.”
A-D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(2) Successive comparison register AD
Register AD stores the A-D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute this instruction during AD conversion.
When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can
be obtained with the reference voltage VDD by the following formula:
Logic value of comparison voltage Vref
Vref =
V DD
✕n
1024
n: The value of register AD (n = 0 to 1023)
(5) A-D control register Q1
Register Q1 is used to select one of analog input pins. The 4513
Group does not have AIN4 –AIN7 . Accordingly, do not select these
pins with register Q1.
(6) A-D control register Q2
Register Q2 is used to select the pin function of P4 0/AIN4 , P41/
AIN5 , P42 /AIN6 , and P43 /AIN7. The A-D conversion mode is selected when the bit 3 of register Q2 is “0,” and the comparator
mode is selected when the bit 3 of register Q2 is “1.” After set this
register, select the analog input with register Q1.
Even when register Q2 is used to set the pins for analog input,
P40 /A IN4–P43 /A IN7 continue to function as P4 0–P4 3 I/O. Accordingly, when any of them are used as I/O port P4 and others are
used as analog input pins, make sure to set the outputs of pins that
are set for analog input to “1.” Also, for the port input, the port input
function of the pin functions as analog input is undefined.
(3) A-D conversion completion flag (ADF)
A-D conversion completion flag (ADF) is set to “1” when A-D conversion completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
1-42
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
(7) Operation description
A-D conversion is started with the A-D conversion start instruction
(ADST). The internal operation during A-D conversion is as follows:
➀ When A-D conversion starts, the register AD is cleared to
“000 16.”
➁ Next, the topmost bit of the register AD is set to “1,” and the
comparison voltage Vref is compared with the analog input voltage VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is
Vref > VIN, it is cleared to “0.”
The 4513/4514 Group repeats this operation to the lowermost bit of
the register AD to convert an analog value to a digital value. A-D
conversion stops after 62 machine cycles (46.5 µ s when f(XIN ) =
4.0 MHz in high-speed mode) from the start, and the conversion result is stored in the register AD. An A-D interrupt activated condition
is satisfied and the ADF flag is set to “1” as soon as A-D conversion
completes (Figure 27).
Table 16 Change of successive comparison register AD during A-D conversion
At starting conversion
-------------
1st comparison
1
0
0
-----
0
0
0
0
0
0
-------------------------
2nd comparison
✼1
1
0
-----
-------------
After 10th comparison
completes
✼1: 1st comparison result
✼3: 3rd comparison result
✼9: 9th comparison result
✼1
✼2
1
-----------------
0
0
0
✼3
-----
-------------
VDD
✼8
✼9
✼A
VDD
±
4
VDD
VDD
-------------
✼2
2
2
A-D conversion result
✼1
VDD
2
-------------
3rd comparison
Comparison voltage (V ref) value
Change of successive comparison register AD
2
VDD
±
±
VDD
±
4
○
○
○
○
±
8
VDD
1024
✼2: 2nd comparison result
✼8: 8th comparison result
✼A: 10th comparison result
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1-43
HARDWARE
FUNCTION BLOCK OPERATIONS
(8) A-D conversion timing chart
Figure 27 shows the A-D conversion timing chart.
ADST instruction
62 machine cycles
A-D conversion
completion flag (ADF)
DAC operation signal
Fig. 27 A-D conversion timing chart
(9) How to use A-D conversion
How to use A-D conversion is explained using as example in which
the analog input from P40/A IN4 pin is A-D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y)
= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),
and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.
The A-D interrupt is not used in this example.
➀ After selecting the AIN4 pin function with the bit 0 of the register
Q2, select AIN4 pin and A-D conversion mode with the register
Q1 (refer to Figure 28).
➁ Execute the ADST instruction and start A-D conversion.
➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A-D conversion.
➃ Transfer the low-order 2 bits of converted data to the high-order
2 bits of register A (TALA instruction).
➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➅ Transfer the high-order 8 bits of converted data to registers A
and B (TABAD instruction).
➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➇ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
(Bit 3)
(Bit 0)
✕
0
✕
1
A IN4 function selected
A-D conversion mode
(Bit 3)
✕
(Bit 0)
1
0
0
A-D control register Q1
A IN4 pin selected
✕ : Set an arbitrary value
Fig. 28 Setting registers
1-44
A-D control register Q2
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
(10) Operation at comparator mode
(12) Comparison result store flag (ADF)
The A-D converter is set to comparator mode by setting bit 3 of the
register Q2 to “1.”
Below, the operation at comparator mode is described.
In comparator mode, the ADF flag, which shows completion of A-D
conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is
lower than the comparison voltage, the ADF flag is set to “1.” The
state of ADF flag can be examined with the skip instruction
(SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(11) Comparator register
In comparator mode, the built-in DA comparator is connected to the
comparator register as a register for setting comparison voltages.
The contents of register B is stored in the high-order 4 bits of the
comparator register and the contents of register A is stored in the
low-order 4 bits of the comparator register with the TADAB instruction.
When changing from A-D conversion mode to comparator mode,
the result of A-D conversion (register AD) is undefined.
However, because the comparator register is separated from register AD, the value is retained even when changing from comparator
mode to A-D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
n: The value of register AD (n = 0 to 255)
(13) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator operating.
The comparator stops 8 machine cycles after it has started (6 µ s at
f(XIN) = 4.0 MHz in high-speed mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.”
(14) Notes for the use of A-D conversion 1
Note the following when using the analog input pins also for I/O
port P4 functions:
• Even when P40 /AIN4–P4 3/A IN7 are set to pins for analog input,
they continue to function as P40 –P43 I/O. Accordingly, when any
of them are used as I/O port P4 and others are used as analog
input pins, make sure to set the outputs of pins that are set for
analog input to “1.” Also, the port input function of the pin functions as an analog input is undefined.
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
ADST instruction
8 machine cycles
Comparison result
store flag(ADF)
DAC operation signal
→
Comparator operation completed.
(The value of ADF is determined)
Fig. 29 Comparator operation timing chart
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1-45
HARDWARE
FUNCTION BLOCK OPERATIONS
(15) Notes for the use of A-D conversion 2
(16) Definition of A-D converter accuracy
Do not change the operating mode (both A-D conversion mode and
comparator mode) of A-D converter with bit 3 of register Q2 while
A-D converter is operating.
When the operating mode of A-D converter is changed from the
comparator mode to A-D conversion mode with the bit 3 of register
Q2, note the following;
• Clear bit 2 of register V2 to “0” to change the operating mode of
the A-D converter from the comparator mode to A-D conversion
mode with the bit 3 of register Q2.
• The A-D conversion completion flag (ADF) may be set when the
operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a
value to register Q2, and execute the SNZAD instruction to clear
the ADF flag.
The A-D conversion accuracy is defined below (refer to Figure 30).
• Relative accuracy
➀ Zero transition voltage (V 0T)
This means an analog input voltage when the actual A-D conversion output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST )
This means an analog input voltage when the actual A-D conversion output data changes from “1023” to ”1022.”
➂ Linearity error
This means a deviation from the line between V 0T and VFST of
a converted value between V0T and VFST .
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converter value between V0T and V FST by 1
LSB at the relative accuracy.
• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A-D conversion characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error = b–a [LSB]
a
Linearity error = c [LSB]
a
b
a
n+1
n
Actual A-D conversion
characteristics
c
a: 1LSB by relative accuracy
b: Vn+1–Vn
c: Difference between ideal Vn
and actual Vn
Ideal line of A-D conversion
between V0–V1022
1
0
V0
V1
Zero transition voltage (V0T)
Vn
Vn+1
Vn: Analog input voltage when the output data changes from “n” to “n+1” (n = 0 to 1022)
VFST –V0T
(V)
1022
• 1LSB at absolute accuracy →
1-46
VDD
1024
VDD
Analog voltage
Fig. 30 Definition of A-D conversion accuracy
• 1LSB at relative accuracy →
V1022
(V)
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
VOLTAGE COMPARATOR
The 4513/4514 Group has 2 voltage comparator circuits that
perform comparison of voltage between 2 pins. Table 17 shows
the characteristics of this voltage comparison.
Table 17 Voltage comparator characteristics
Parameter
Characteristics
Voltage comparator function 2 circuits (CMP0, CMP1)
Input pin
CMP0-, CMP0+
(also used as A IN0, AIN1)
CMP1-, CMP1+
Supply voltage
Input voltage
Comparison check error
Response time
CMP0–/AIN0
CMP0+/AIN1
CMP1–/AIN2
CMP1+/AIN3
(also used as A IN2, AIN3)
3.0 V to 5.5 V
0.3 V DD to 0.7 VDD
Typ. 20 mV, Max.100 mV
Max. 20 µs
–
CMP0
+
–
CMP1
+
Q33 Q32 Q31 Q30 Voltage comparator control register Q3 (4)
TQ3A
TAQ3
Register A (4)
Note: Bits 0 and 1 of register Q3 can be only read.
Fig. 31 Voltage comparator structure
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1-47
HARDWARE
FUNCTION BLOCK OPERATIONS
Table 18 Voltage comparator control register Q3
Voltage comparator control register Q3 (Note 2)
Q33
Voltage comparator (CMP1) control bit
Q32
Voltage comparator (CMP0) control bit
Q31
CMP1 comparison result store bit
Q30
CMP0 comparison result store bit
at reset : 00002
0
1
0
1
0
1
0
1
Voltage comparator
Voltage comparator
Voltage comparator
Voltage comparator
CMP1- > CMP1+
at RAM back-up : state retained
(CMP1)
(CMP1)
(CMP0)
(CMP0)
R/W
invalid
valid
invalid
valid
CMP1- < CMP1+
CMP0- > CMP0+
CMP0- < CMP0+
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Bits 0 and 1 of register Q3 can be only read.
(1) Voltage comparator control register Q3
(3) Precautions
Register Q3 controls the function of the voltage comparator.
The function of the voltage comparator CMP0 becomes valid by
setting bit 2 of register Q3 to “1,” and becomes invalid by setting bit
2 of register Q3 to ”0.” The comparison result of the voltage comparator CMP0 is stored into bit 0 of register Q3.
The function of the voltage comparator CMP1 becomes valid by
setting bit 3 of register Q3 to “1,” and becomes invalid by setting bit
3 of register Q3 to ”0.” The comparison result of the voltage comparator CMP1 is stored into bit 1 of register Q3.
When the voltage comparator is used, note the following;
• Voltage comparator function
When the voltage comparator function is valid with the voltage
comparator control register Q3, it is operating even in the RAM
back-up mode. Accordingly, be careful about such state because
it causes the increase of the operation current in the RAM backup mode.
In order to reduce the operation current in the RAM back-up
mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage
comparator function by software before the POF instruction is
executed.
Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required
for the low-power dissipation, invalidate the voltage comparator
by software when it is unused.
(2) Operation description of voltage
comparator
The voltage comparator function becomes valid by setting each
control bit of register Q3 to “1” and compares the voltage of the input pin. The comparison result is stored into each comparison
result store bit of register Q3.
The comparison result is as follows;
• When CMP0- > CMP0+, Q30 = “0”
When CMP0- < CMP0+, Q30 = “1”
• When CMP1- > CMP1+, Q31 = “0”
When CMP1- < CMP1+, Q31 = “1”
1-48
• Register Q3
Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written.
• Reading the comparison result of voltage comparator
Read the voltage comparator comparison result from register Q3
after the voltage comparator response time (max. 20 µs) is
passed from the voltage comparator function becomes valid.
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
RESET FUNCTION
System reset is performed by applying “L” level to RESET pin for
1 machine cycle or more when the following condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.
f(XIN)
(Note)
f(XIN) is counted 16892 to
RESET
Software starts
(address 0 in page 0)
16895 times.
Note: It depends on the internal state of the microcomputer
when reset is performed.
Fig. 32 Reset release timing
=
Reset input
f(XIN) is counted 16892 to
1 machine cycle or more
16895 times.
0.85VDD
Software starts
(address 0 in page 0)
RESET
0.3VDD
(Note)
Note: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 33 RESET pin input waveform and reset operation
4513/4514 Group User’s Manual
1-49
HARDWARE
FUNCTION BLOCK OPERATIONS
(1) Power-on reset
Reset can be performed automatically at power on (power-on reset) by connecting resistors, a diode, and a capacitor to RESET
pin. Connect RESET pin and the external circuit at the shortest distance.
VDD
VD D
RESET pin voltage
Internal reset signal
RESET pin
(Note)
Reset state
Voltage drop detection circuit
Watchdog timer output
Internal reset signal
WEF
Reset released
Power-on
Note:
This symbol represents a parasitic diode.
Applied potential to RESET pin must be VDD or less.
Fig. 34 Power-on reset circuit example
(2) Internal state at reset
Table 19 shows port state at reset, and Figure 35 shows internal
state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except
shown in Figure 35 are undefined, so set the initial value to them.
Table 19 Port state at reset
Name
D0 –D5
D6 /CNTR0, D7 /CNTR1
D0–D5
D6, D7
P00–P03
P10–P13
P20 /SCK, P21/SOUT, P22/S IN
P30/INT0, P3 1/INT1
P32, P33 (Note 4)
P00–P03
P10–P13
P20–P22
P30, P31
P32, P33
P40/AIN4–P43 /AIN7 (Note 4)
P50–P53 (Note 4)
P40–P43
P50–P53
State
Function
High impedance (Note)
High impedance (Notes 1, 2)
High impedance
High impedance (Note 1)
High impedance (Note 1)
High impedance (Note 3)
Notes 1: Output latch is set to “1.”
2: Pull-up transistor is turned OFF.
3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 00002 )
4: The 4513 Group does not have these ports.
1-50
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
• Program counter (PC) ..........................................................................................................
0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) .................................................................................................. 0
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• External 1 interrupt request flag (EXF1) .............................................................................. 0
• Interrupt control register V1 ..................................................................................................
0 0 0 0
• Interrupt control register V2 ..................................................................................................
0 0 0 0
• Interrupt control register I1 ...................................................................................................
0 0 0 0
• Interrupt control register I2 ...................................................................................................
0 0 0
• Timer 1 interrupt request flag (T1F) .....................................................................................
• Timer 2 interrupt request flag (T2F) .....................................................................................
• Timer 3 interrupt request flag (T3F) .....................................................................................
• Timer 4 interrupt request flag (T4F) .....................................................................................
• Watchdog timer flags (WDF1, WDF2) ..................................................................................
• Watchdog timer enable flag (WEF) ......................................................................................
• Timer control register W1 .....................................................................................................
0 0 0
• Timer control register W2 .....................................................................................................
0 0 0
• Timer control register W3 .....................................................................................................
0 0 0
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled)
(Interrupt disabled)
0
0
0
0
0
0
0
0
0
(Prescaler and timer 1 stopped)
(Timer 2 stopped)
• Timer control register W4 .....................................................................................................
0 0 0
• Timer control register W6 .....................................................................................................
0 0 0
• Clock control register MR .....................................................................................................
1 0 0
• Serial I/O transmission/reception completion flag (SIOF) ...................................................
0
0
0
0
0
(Timer 3 stopped)
(Timer 4 stopped)
• Serial I/O mode register J1 ..................................................................................................
0 0 0
✕ ✕ ✕ ✕ ✕ ✕ ✕
• Serial I/O register SI .............................................................................................................
• A-D conversion completion flag (ADF) .................................................................................
• A-D control register Q1 ......................................................................................................
0 0 0...
• A-D control register Q2 .........................................................................................................
0 0 0
0
✕
0
0
0
(External clock selected and serial
I/O port not selected)
• Voltage comparator control register Q3 ...............................................................................
0 0 0
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Successive comparison register AD ....................................................................................
• Comparator register..........................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ .✕
...
• Key-on wakeup control register K0 ......................................................................................
0 0 0
• Pull-up control register PU0 .................................................................................................
0 0 0
0
✕
✕
0
0
• Direction register FR0 ..........................................................................................................
0 0 0
• Carry flag (CY) ......................................................................................................................
• Register A .............................................................................................................................
0 0 0
• Register B .............................................................................................................................
0 0 0
• Register D .............................................................................................................................
✕ ✕
✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register E .............................................................................................................................
0 (Port P5: input mode)
0
0
0
✕
• Register X .............................................................................................................................
0 0 0
• Register Y .............................................................................................................................
0 0 0
• Register Z .............................................................................................................................
✕
• Stack pointer (SP) ................................................................................................................
1 1
✕
0
0
✕
1
“✕” represents undefined.
Fig. 35 Internal state at reset
4513/4514 Group User’s Manual
1-51
HARDWARE
FUNCTION BLOCK OPERATIONS
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
RESET pin
Internal reset signal
Voltage drop detection circuit
Watchdog timer output
WEF
Note: The output structure of RESET pin is N-channel open-drain.
Fig. 36 Voltage drop detection reset circuit
VDD
VRST (detection voltage)
Voltage drop detection
circuit output
The microcomputer starts
operation after f(XIN) is counted
16892 to 16895 times.
RESET pin
Notes 1: Pull-up RESET pin externally.
2: Refer to the voltage drop detection circuit in the electrical characteristics
for the rating value of VRST (detection voltage).
Fig. 37 Voltage drop detection circuit operation waveform
1-52
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
RAM BACK-UP MODE
Table 20 Functions and states retained at RAM back-up
The 4513/4514 Group has the RAM back-up mode.
When the EPOF and POF instructions are executed continuously,
system enters the RAM back-up state. The POF instruction is
equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM. Table 20 shows the function
and states retained at RAM back-up. Figure 38 shows the state
transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the
state of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF and POF instructions continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
• voltage drop detection circuit detects the voltage drop.
In this case, the P flag is “0.”
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Timer control register W1
Timer control registers W2 to W4, W6
Clock control register MR
Interrupt control registers V1, V2
Interrupt control registers I1, I2
Timer 1 function
Timer 2 function
Timer 3 function
Timer 4 function
A-D conversion function
A-D control registers Q1, Q2
Voltage comparator function
Voltage comparator control register Q3
Serial I/O function
Serial I/O mode register J1
Pull-up control register PU0
Key-on wakeup control register K0
Direction register FR0
External 0 interrupt request flag (EXF0)
External 1 interrupt request flag (EXF1)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Timer 3 interrupt request flag (T3F)
Timer 4 interrupt request flag (T4F)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
A-D conversion completion flag (ADF)
Serial I/O transmission/reception completion flag
(SIOF)
Interrupt enable flag (INTE)
RAM back-up
✕
O
O
✕
O
✕
✕
O
✕
(Note 3)
(Note 3)
(Note 3)
✕
O
O (Note 5)
O
✕
O
O
O
O
✕
✕
✕
(Note 3)
(Note 3)
(Note 3)
✕ (Note 4)
✕ (Note 4)
✕ (Note 4)
✕
✕
✕
Notes 1:“O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
execute the POF instruction.
5: The state is retained when the voltage comparator function is selected with the voltage comparator control register Q3.
4513/4514 Group User’s Manual
1-53
HARDWARE
FUNCTION BLOCK OPERATIONS
(4) Return signal
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped. Table 21 shows the return
condition for each return source.
(5) Ports P0 and P1 control registers
• Key-on wakeup control register K0
Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the
TK0A instruction. In addition, the TAK0 instruction can be used to
transfer the contents of register K0 to register A.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the ports P0 and P1 pull-up
transistor. Set the contents of this register through register A with
the TPU0A instruction. In addition, the TAPU0 instruction can be
used to transfer the contents of register PU0 to register A.
External wakeup
signal
Table 21 Return source and return condition
Return source
Return condition
Ports P0, P1
Return by an external falling
edge input (“H”→“L”).
1-54
Port P3 0/INT0
Port P3 1/INT1
Return by an external “H” level or
“L” level input.
The EXF0 flag is not set.
Return by an external “H” level or
“L” level input.
The EXF1 flag is not set.
Remarks
Set the port using the key-on wakeup function selected with register K0 to
“H” level before going into the RAM back-up state because the port P0
shares the falling edge detection circuit with port P1.
Select the return level (“L” level or “H” level) with the bit 2 of register I1 according to the external state before going into the RAM back-up state.
Select the return level (“L” level or “H” level) with the bit 2 of register I2 according to the external state before going into the RAM back-up state.
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
A
(Stabilizing time a )
Reset
B
POF instruction
is executed
f(XIN) stop
f(XIN) oscillation
Return input
(Stabilizing time a )
(RAM back-up
mode)
Stabilizing time a : Time required to stabilize the f(XIN) oscillation is automatically generated by hardware.
Fig. 38 State transition
Power down flag P
POF instruction
Reset input or
voltage drop detection
circuit output
S
Q
Software start
R
P = “1”
?
No
● Set source • • • • • • • POF instruction is executed
● Clear source • • • • • • Reset input
Cold start
Fig. 39 Set source and clear source of the P flag
Yes
Warm start
Fig. 40 Start condition identified example using the SNZP instruction
4513/4514 Group User’s Manual
1-55
HARDWARE
FUNCTION BLOCK OPERATIONS
Table 22 Key-on wakeup control register, pull-up control register, and interrupt control register
Key-on wakeup control register K0
K03
K02
K01
K00
at reset : 00002
Pins P12 and P13 key-on wakeup
control bit
Pins P10 and P11 key-on wakeup
control bit
Pins P02 and P03 key-on wakeup
0
1
0
1
0
control bit
Pins P00 and P01 key-on wakeup
control bit
1
0
1
Pull-up control register PU0
PU0 3
PU0 2
PU0 1
PU0 0
0
1
0
1
0
1
0
1
control bit
Pins P00 and P01 pull-up transistor
control bit
Interrupt control register I1
I13
Not used
I12
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
I11
I10
0
1
INT0 pin edge detection circuit control bit
INT0 pin
timer 1 control enable bit
0
1
0
1
Interrupt control register I2
I23
I22
I21
I20
0
1
0
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
1
INT1 pin edge detection circuit control bit
timer 3 control enable bit
0
1
0
1
at RAM back-up : state retained
R/W
at RAM back-up : state retained
R/W
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
at reset : 00002
Not used
INT1 pin
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
at reset : 00002
0
1
R/W
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
at reset : 00002
Pins P12 and P13 pull-up transistor
control bit
Pins P10 and P11 pull-up transistor
control bit
Pins P02 and P03 pull-up transistor
at RAM back-up : state retained
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
instruction)/“L” level
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I1 2 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I2 2 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
1-56
4513/4514 Group User’s Manual
HARDWARE
FUNCTION BLOCK OPERATIONS
CLOCK CONTROL
• Control circuit to switch the middle-speed mode and high-speed
mode
• Control circuit to return from the RAM back-up state
The clock control circuit consists of the following circuits.
• System clock generating circuit
• Control circuit to stop the clock oscillation
Division circuit
(divided by 2)
XIN
XOUT
Oscillation
circuit
System clock
MR3
Internal clock
generation circuit
(divided by 3)
1
0
Instruction clock
Counter
Wait time (Note)
control circuit
POF instruction
R
S
Software
start signal
RESET
Key-on wake up control register
K00,K01,K02,K03
Ports P00, P01
MultiPorts P02, P03
Falling detected
Ports P10, P11
plexer
Ports P12, P13
I12
Q
“L” level
0
P30/INT0
1
“H” level
I22
“L” level
0
P31/INT1
1
“H” level
Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
Fig. 41 Clock control circuit structure
Table 23 Clock control register MR
Clock control register MR
MR3
System clock selection bit
MR2
Not used
MR1
Not used
MR0
Not used
at reset : 10002
0
1
0
1
0
1
0
1
at RAM back-up : 10002
R/W
f(XIN) (high-speed mode)
f(XIN)/2 (middle-speed mode)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Note : “R” represents read enabled, and “W” represents write enabled.
4513/4514 Group User’s Manual
1-57
HARDWARE
FUNCTION BLOCK OPERATIONS/ROM ORDERING METHOD
Clock signal f(X IN) is obtained by externally connecting a ceramic
resonator.
Connect this external circuit to pins XIN and X OUT at the shortest
distance. A feedback resistor is built in between pins XIN and XOUT .
When an external clock signal is input, connect the clock source to
XIN and leave XOUT open. When using an external clock, the maximum value of external clock oscillating frequency is shown in Table
24.
4513/4514
Note: Externally connect a
damping resistor Rd depending on the oscillation
XOUT
frequency.
(A feedback resistor is
built-in.)
Rd
Use the resonator manufacturer’s recommended
value because constants
COUT
such as capacitance depend on the resonator.
XIN
CIN
Fig. 42 Ceramic resonator external circuit
4513/4514
XIN
XOUT
VDD
VSS
External oscillation circuit
Fig. 43 External clock input circuit
Table 24 Maximum value of external clock oscillation frequency
Middle-speed mode
Mask ROM version
High-speed mode
Middle-speed mode
One Time PROM version
High-speed mode
Supply voltage
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
ROM ORDERING METHOD
Please submit the information described below when ordering
Mask ROM.
(1) Mask ROM Order Confirmation Form ..................................... 1
(2) Data to be written into mask ROM ............................... EPROM
(three sets containing the identical data)
(3) Mark Specification Form .......................................................... 1
1-58
4513/4514 Group User’s Manual
Oscillation frequency (duty ratio)
3.0 MHz (40 % to 60 %)
3.0 MHz (40 % to 60 %)
1.0 MHz (40 % to 60 %)
0.8 MHz (40 % to 60 %)
3.0 MHz (40 % to 60 %)
3.0 MHz (40 % to 60 %)
1.0 MHz (40 % to 60 %)
HARDWARE
LIST OF PRECAUTIONS
LIST OF PRECAUTIONS
➀Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µ F) between pins VDD
and V SS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ in series at the shortest distance.
➁Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
➂Timer count source
Stop timer 1, 2, 3, or 4 counting to change its count source.
➃Reading the count value
Stop timer 1, 2, 3, or 4 counting and then execute the TAB1,
TAB2, TAB3, or TAB4 instruction to read its data.
➆P31/INT1 pin
When the interrupt valid waveform of P31 /INT1 pin is changed
with the bit 2 of register I2 in software, be careful about the following notes.
• Clear the bit 1 of register V1 to “0” before the interrupt valid waveform of P3 1/INT1 pin is changed with the bit 2 of register I2 (refer
to Figure 45➂).
• Depending on the input state of the P31 /INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I2 and
execute the SNZ1 instruction to clear the EXF1 flag after executing at least one instruction (refer to Figure 45➃).
...
LA 8
TV1A
LA 8
TI2A
NOP
SNZ1
NOP
; (✕✕0✕ 2)
; The SNZ1 instruction is valid ........... ➂
; Change of the interrupt valid waveform
........................................................... ➃
; The SNZ1 instruction is executed
...
✕ : this bit is not related to the setting of INT1.
➄Writing to reload registers R1 and R3
When writing data to reload registers R1 or R3 while timer 1 or
timer 3 is operating, avoid a timing when timer 1 or timer 3
underflows.
➅P30/INT0 pin
When the interrupt valid waveform of the P3 0 /INT0 pin is
changed with the bit 2 of register I1 in software, be careful about
the following notes.
• Clear the bit 0 of register V1 to “0” before the interrupt valid waveform of P3 0/INT0 pin is changed with the bit 2 of register I1 (refer
to Figure 44➀).
• Depending on the input state of the P30 /INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I1, and
execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 44➁)
Fig. 45 External 1 interrupt program example
➇One Time PROM version
The operating power voltage of the One Time PROM version is
2.5 V to 5.5 V.
➈Multifunction
The input of D6, D7, P20–P22, I/O of P3 0 and P31, input of CMP0-,
CMP0+, CMP1-, CMP1+, and I/O of P40 –P43 can be used even
when CNTR0, CNTR1, SCK , SOUT, S IN, INT0, INT1, AIN0–AIN3
and A IN4–AIN7 are selected.
...
LA
4
TV1A
LA
4
TI1A
NOP
SNZ0
NOP
; (✕✕✕02 )
; The SNZ0 instruction is valid ........... ➀
;
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
...
✕ : this bit is not related to the setting of INT0 pin.
Fig. 44 External 0 interrupt program example
4513/4514 Group User’s Manual
1-59
HARDWARE
LIST OF PRECAUTIONS
➉ A-D converter-1
When the operating mode of the A-D converter is changed from
the comparator mode to the A-D conversion mode with the bit 3
of register Q2 in a program, be careful about the following notes.
• Clear the bit 2 of register V2 to “0” to change the operating mode
of the A-D converter from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 (refer to Figure 46➄).
• The A-D conversion completion flag (ADF) may be set when the
operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a
value to register Q2, and execute the SNZAD instruction to clear
the ADF flag.
Do not change the operating mode (both A-D conversion mode
and comparator mode) of A-D converter with the bit 3 of register
Q2 during operating the A-D converter.
Sensor
AIN
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 47 Analog input external circuit example-1
...
LA
8
TV2A
LA
0
TQ2A
; (✕0✕✕2 )
; The SNZAD instruction is valid ........➄
; (0✕✕✕2 )
; Change of the operating mode of the A-D
converter from the comparator mode to the
A-D conversion mode
SNZAD
NOP
...
About 1kΩ
Sensor
Fig. 48 Analog input external circuit example-2
12
✕: this bit is not related to the change of the
operating mode of the A-D conversion.
Fig. 46 A-D converter operating mode program example
11
A-D converter-2
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog
voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A-D accuracy
may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure
47).
When the overvoltage applied to the A-D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 48. In addition, test
the application products sufficiently.
1-60
AIN
POF instruction
Execute the POF instruction immediately after executing the
EPOF instruction to enter the RAM back-up.
Note that system cannot enter the RAM back-up state when executing only the POF instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Analog input pins
Note the following when using the analog input pins also for I/O
port P4 functions:
• Even when P40/A IN4 –P43 /AIN7 are set to pins for analog input,
they continue to function as P40–P43 I/O. Accordingly, when any
of them are used as I/O port P4 and others are used as analog
input pins, make sure to set the outputs of pins that are set for
analog input to “1.” Also, the port input function of the pin functions as an analog input is undefined.
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
13
14
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
15
Port P3
In the 4513 Group, when the IAP3 instruction is executed, note
that the high-order 2 bits of register A is undefined.
4513/4514 Group User’s Manual
HARDWARE
LIST OF PRECAUTIONS
16
Voltage comparator function
When the voltage comparator function is valid with the voltage
comparator control register Q3, it is operating even in the RAM
back-up mode. Accordingly, be careful about such state because
it causes the increase of the operation current in the RAM backup mode.
In order to reduce the operation current in the RAM back-up
mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage
comparator function by software before the POF instruction is executed.
Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required
for the low-power dissipation, invalidate the voltage comparator
when it is unused by software.
17
Register Q3
Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written.
18
Reading the comparison result of voltage comparator
Read the voltage comparator comparison result from register Q3
after the voltage comparator response time (max. 20 µ s) is
passed from the voltage comparator function become valid.
4513/4514 Group User’s Manual
1-61
HARDWARE
SYMBOL
SYMBOL
The symbols shown below are used in the following instruction function table and instruction list.
Symbol
A
B
DR
E
Q1
Q2
Q3
AD
J1
SI
V1
V2
I1
I2
W1
W2
W3
W4
W6
MR
K0
PU0
FR0
X
Y
Z
DP
PC
PC H
PC L
SK
SP
CY
R1
R2
R3
R4
T1
T2
T3
T4
Contents
Symbol
T1F
T2F
Register A (4 bits)
Register B (4 bits)
Register D (3 bits)
Register E (8 bits)
A-D control register Q1 (4 bits)
A-D control register Q2 (4 bits)
Voltage comparator control register Q3 (4 bits)
Successive comparison register AD (10 bits)
Serial I/O mode register J1 (4 bits)
Serial I/O register SI (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Interrupt control register I2 (4 bits)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
Timer 1
Timer 2
Timer 3
Timer 4
EXF0
EXF1
P
ADF
SIOF
D
P0
P1
P2
Timer control register W6 (4 bits)
Clock control register MR (4 bits)
Key-on wakeup control register K0 (4 bits)
Pull-up control register PU0 (4 bits)
Direction register FR0 (4 bits)
Carry flag
Timer 1 reload register
Timer 2 reload register
Timer 3 reload register
Timer 4 reload register
T3F
T4F
WDF1
WEF
INTE
P3
P4
P5
Contents
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Timer 4 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
External 1 interrupt request flag
Power down flag
A-D conversion completion flag
Serial I/O transmission/reception completion flag
Port D (8 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (3 bits)
Port P3 (4 bits)
Port P4 (4 bits)
Port P5 (4 bits)
x
Hexadecimal variable
y
z
p
n
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
i
j
A3A2A1A0
←
↔
?
( )
—
M(DP)
a
p, a
C
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
Direction of data movement
Data exchange between a register and memory
Decision of state shown before “?”
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a 1 a 0
Label indicating address a6 a5 a4 a3 a2 a 1 a 0
in page p5 p 4 p 3 p 2 p1 p0
Hex. C + Hex. number x (also same for others)
+
x
Note : The 4513/4514 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction
is skipped.
1-62
4513/4514 Group User’s Manual
HARDWARE
LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION
TBA
(B) ← (A)
TAY
(A) ← (Y)
TYA
(Y) ← (A)
TEAB
(E7 –E4 ) ← (B)
(E3 –E0 ) ← (A)
XAMI j
TMA j
LA n
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
(A) ← n
n = 0 to 15
TABE
TDA
(B) ← (E7 –E4 )
(A) ← (E3 –E0 )
TABP p
(DR2–DR 0) ← (A2–A0 )
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
TAD
(A2 –A0 ) ← (DR2 –DR0 )
(A3 ) ← 0
TAZ
(A1, A0 ) ← (Z1 , Z0)
(PCL) ← (DR2–DR 0,
A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(A3, A2) ← 0
(SP) ← (SP) – 1
GroupMnemonic
ing
Bit operation
(A) ← (B)
Function
Comparison
operation
TAB
GroupMnemonic
ing
RAM to register transfer
Function
Branch operation
Register to register transfer
GroupMnemonic
ing
SB j
(Mj(DP)) ← 1
j = 0 to 3
RB j
(Mj(DP)) ← 0
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
(A) = (M(DP)) ?
SEA n
(A) = n ?
n = 0 to 15
Ba
(PCL) ← a6–a0
BL p, a
(PCH) ← p
(PCL) ← a6–a0
BLA p
(PCH) ← p
(PCL) ← (DR2–DR0 ,
A3 –A0)
TAX
(A) ← (X)
AM
(A) ← (A) + (M(DP))
TASP
(A2 –A0 ) ← (SP2–SP0)
AMC
(A) ← (A) + (M(DP)) +
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(CY)
(CY) ← Carry
(PCH) ← 2
(PCL) ← a6–a0
LZ z
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
(Z) ← z, z = 0 to 3
INY
(Y) ← (Y) + 1
DEY
(Y) ← (Y) – 1
TAM j
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
XAMD j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
An
(A) ← (A) + n
n = 0 to 15
AND
(A) ← (A) AND (M(DP))
OR
(A) ← (A) OR (M(DP))
SC
(CY) ← 1
RC
(CY) ← 0
SZC
(CY) = 0 ?
CMA
(A) ← (A)
RAR
→ CY → A3A2A1A0
BML p, a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
BMLA p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0 ,
A3 –A0)
RTI
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
4513/4514 Group User’s Manual
Return operation
RAM addresses
LXY x, y
Arithmetic operation
(A3 ) ← 0
Subroutine operation
BM a
RAM to register transfer
Function
RT
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
1-63
HARDWARE
LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic
ing
Function
DI
(INTE) ← 0
TAW4
(A) ← (W4)
EI
(INTE) ← 1
TW4A
(W4) ← (A)
SNZ0
(EXF0) = 1 ?
TAW6
(A) ← (W6)
After skipping
(EXF0) ← 0
TW6A
(W6) ← (A)
TAB1
(B) ← (T1 7–T14)
(A) ← (T1 3–T10)
T1AB
(R17 –R14 ) ← (B)
(T1 7–T14) ← (B)
(R13 –R10 ) ← (A)
(T1 3–T10) ← (A)
SNZ1
(EXF1) = 1 ?
After skipping
SNZI0
I1 2 = 1 : (INT0) = “H” ?
I1 2 = 0 : (INT0) = “L” ?
SNZI1
I2 2 = 1 : (INT1) = “H” ?
I2 2 = 0 : (INT1) = “L” ?
TAV1
TV1A
(V1) ← (A)
TAV2
(A) ← (V2)
TV2A
(V2) ← (A)
(A) ← (P1)
OP1A
(P1) ← (A)
(B) ← (T3 7–T34)
IAP2
(A2 –A0 ) ← (P22–P20)
(A) ← (I2)
(T3 3–T30) ← (A)
TI2A
(I2) ← (A)
TAW1
(A) ← (W1)
TW1A
(W1) ← (A)
TAW2
(A) ← (W2)
T4AB
Timer operation
(T3F) ← 0
IAP1
TAI2
TAB4
TR1AB
TR3AB
(T3F) = 1 ?
After skipping
(T2 7–T24) ← (B)
(R23 –R20 ) ← (A)
(T2 3–T20) ← (A)
(R37 –R34 ) ← (B)
(T3 7–T34) ← (B)
(R33 –R30 ) ← (A)
(W3) ← (A)
SNZT3
(A) ← (T3 3–T30)
T3AB
TW3A
After skipping
(T2F) ← 0
(P0) ← (A)
(R27 –R24 ) ← (B)
(I1) ← (A)
(A) ← (W3)
(T2F) = 1 ?
OP0A
T2AB
TI1A
TAW3
SNZT2
(A) ← (P0)
(A) ← (I1)
(W2) ← (A)
(T1F) = 1 ?
After skipping
(T1F) ← 0
IAP0
(B) ← (T2 7–T24)
(A) ← (T2 3–T20)
TAI1
TW2A
SNZT1
(T4F) = 1 ?
After skipping
(T4F) ← 0
TAB2
TAB3
Function
SNZT4
(A) ← (V1)
Timer operation
Interrupt operation
(EXF1) ← 0
GroupMnemonic
ing
Timer operation
Function
(A3 ) ← 0
IAP3
(A) ← (P3)
OP3A
(P3) ← (A)
IAP4*
(A) ← (P4)
OP4A*
(P4) ← (A)
IAP5*
(A) ← (P5)
OP5A*
(P5) ← (A)
CLD
(D) ← 1
(R17 –R14 ) ← (B)
(R13 –R10 ) ← (A)
RD
(D(Y)) ← 0
(Y) = 0 to 7
(R37 –R34 ) ← (B)
(R33 –R30 ) ← (A)
SD
(D(Y)) ← 1
(B) ← (T4 7–T44)
(A) ← (T4 3–T40)
(R47 –R44 ) ← (B)
(T4 7–T44) ← (B)
(R43 –R40 ) ← (A)
(T4 3–T40) ← (A)
Input/Output operation
GroupMnemonic
ing
(Y) = 0 to 7
SZD
*: The 4513 Group does not have these instructions.
1-64
4513/4514 Group User’s Manual
(D(Y)) = 0 ?
(Y) = 0 to 7
HARDWARE
LIST OF INSTRUCTION FUNCTION
LIST OF INSTRUCTION FUNCTION (continued)
TK0A
(K0) ← (A)
TAK0
(A) ← (K0)
TPU0A
(PU0) ← (A)
TAPU0
(A) ← (PU0)
TFR0A*
TABSI
TSIAB
Grouping Mnemonic
(A) ← (SI 3–SI0 )
(B) ← (SI 7–SI4 )
(SI3–SI0 ) ← (A)
(SI7–SI4 ) ← (B)
TAJ1
(A) ← (J1)
TJ1A
(J1) ← (A)
Function
TABAD
(A) ← (AD 5–AD 2)
(B) ← (AD 9–AD 6)
However, in the comparator mode,
(A) ← (AD 3–AD 0)
(B) ← (AD 7–AD 4)
TALA
(A) ← (AD1 , AD0, 0, 0)
TADAB
(AD3–AD 0) ← (A)
(AD7–AD 4) ← (B)
TAQ1
(A) ← (Q1)
TQ1A
(Q1) ← (A)
ADST
(ADF) ← 0
A-D conversion starting
SNZAD
(ADF) = 1 ?
After skipping
(ADF) ← 0
(FR0) ← (A)
SST
(SIOF) ← 0
Serial I/O starting
SNZSI
(SIOF) = 1 ?
After skipping
TAQ2
(A) ← (Q2)
(SIOF) ← 0
TQ2A
(Q2) ← (A)
NOP
(PC) ← (PC) + 1
POF
RAM back-up
EPOF
POF instruction valid
SNZP
(P) = 1 ?
WRST
(WDF1) ← 0, (WEF) ← 1
TAMR
(A) ← (MR)
TMRA
(MR) ← (A)
TAQ3
(A) ← (Q3)
TQ3A
(Q33, Q32) ← (A3, A2)
Other operation
Serial I/O control operation
Function
A-D conversion operation
Input/Output operation
Grouping Mnemonic
(Q3 1 ) ← (CMP1 comparison result)
(Q3 0 ) ← (CMP0 comparison result)
*: The 4513 Group does not have these instructions.
4513/4514 Group User’s Manual
1-65
HARDWARE
INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (for 4513 Group)
D9–D4 000000 000001000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111
010000 011000
010111 011111
Hex.
D3–D0 notation
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10–17 18–1F
0000
0
NOP
BLA
SZB
BMLA
0
–
TASP
A
0
LA
0
TABP TABP TABP TABP
BML BML*** BL
0
16*** 32** 48*
BL***
BM
B
0001
1
–
CLD
SZB
1
–
–
TAD
A
1
LA
1
TABP TABP TABP TABP
BML BML*** BL
1
17*** 33** 49*
BL***
BM
B
0010
2
POF
–
SZB
2
–
–
TAX
A
2
LA
2
TABP TABP TABP TABP
BML BML*** BL
2
18*** 34** 50*
BL***
BM
B
0011
3
SZB
3
–
–
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML BML*** BL
3
19*** 35** 51*
BL***
BM
B
0100
4
DI
RD
SZD
–
RT
TAV1
A
4
LA
4
BL***
BM
B
0101
5
EI
SD
SEAn
–
RTS TAV2
A
5
LA
5
TABP TABP TABP TABP
BML BML*** BL
4
20*** 36** 52*
TABP TABP TABP TABP
BML BML*** BL
5
21*** 37** 53*
BL***
BM
B
0110
6
RC
–
SEAM
–
RTI
–
A
6
LA
6
TABP TABP TABP TABP
BML BML*** BL
6
22*** 38** 54*
BL***
BM
B
0111
7
SC
DEY
–
–
–
–
A
7
LA
7
TABP TABP TABP TABP
BML BML*** BL
7
23*** 39** 55*
BL***
BM
B
1000
8
–
AND
–
SNZ0
LZ
0
–
A
8
LA
8
TABP TABP TABP TABP
BML BML*** BL
8
24*** 40** 56*
BL***
BM
B
1001
9
–
OR
TDA SNZ1
LZ
1
–
A
9
LA
9
BL***
BM
B
1010
A
AM TEAB TABE SNZI0
LZ
2
–
A
10
LA
10
TABP TABP TABP TABP
BML BML*** BL
9
25*** 41** 57*
TABP TABP TABP TABP
BML BML*** BL
10 26*** 42** 58*
BL***
BM
B
1011
B
AMC
–
–
SNZI1
LZ
3
EPOF
A
11
LA
11
TABP TABP TABP TABP
BML BML*** BL
11 27*** 43** 59*
BL***
BM
B
1100
C
TYA
CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
BML BML*** BL
12 28*** 44** 60*
BL***
BM
B
1101
D
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
BML BML*** BL
13 29*** 45** 61*
BL***
BM
B
1110
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
BML BML*** BL
14 30*** 46** 62*
BL***
BM
B
1111
F
–
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
BML BML*** BL
15 31*** 47** 63*
BL***
BM
B
SNZP INY
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9 –D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
1-66
The second word
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
•
•
•
•
*, **, and *** cannot be used in the M34513M2-XXXSP/FP.
* and ** cannot be used in the M34513M4-XXXSP/FP.
* and ** cannot be used in the M34513E4FP.
* cannot be used in the M34513M6-XXXFP.
4513/4514 Group User’s Manual
HARDWARE
INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (continued) (for 4513 Group)
D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111
110000
111111
Hex.
D3–D0 notation
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30–3F
TAW6 IAP0 TAB1 SNZT1
–
WRST
TMA TAM XAM XAMI XAMD LXY
0
0
0
0
0
IAP1 TAB2 SNZT2
–
–
TMA TAM XAM XAMI XAMD LXY
1
1
1
1
1
T3AB TAJ1 TAMR IAP2 TAB3 SNZT3
–
–
TMA TAM XAM XAMI XAMD LXY
2
2
2
2
2
IAP3 TAB4 SNZT4
–
–
TMA TAM XAM XAMI XAMD LXY
3
3
3
3
3
0000
0
–
TW3A OP0A T1AB
–
0001
1
–
TW4A OP1A T2AB
–
0010
2
TJ1A
0011
3
–
0100
4
TQ1A
–
–
–
TAQ1 TAI2
–
–
–
–
–
TMA TAM XAM XAMI XAMD LXY
4
4
4
4
4
0101
5
TQ2A
–
–
–
TAQ2
–
–
–
–
–
TMA TAM XAM XAMI XAMD LXY
5
5
5
5
5
0110
6
TQ3A TMRA
–
–
TAQ3 TAK0
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
6
6
6
6
6
0111
7
–
TI1A
–
–
–
TAPU0
–
–
SNZAD
–
–
TMA TAM XAM XAMI XAMD LXY
7
7
7
7
7
1000
8
–
TI2A
–
TSIAB
–
–
–
TABSI SNZSI
–
–
TMA TAM XAM XAMI XAMD
LXY
8
8
8
8
8
1001
9
–
–
–
TADAB TALA
–
–
TABAD
–
–
–
TMA TAM XAM XAMI XAMD LXY
9
9
9
9
9
1010
A
–
–
–
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
10
10
10
10
10
1011
B
–
TK0A
–
TR3AB TAW1
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
11
11
11
11
11
1100
C
–
–
–
–
TAW2
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
12
12
12
12
12
1101
D
–
–
TPU0A
–
TAW3
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
13
13
13
13
13
1110
E
TW1A
–
–
–
TAW4
–
–
–
–
SST
–
TMA TAM XAM XAMI XAMD
LXY
14
14
14
14
14
1111
F
TW2A
–
–
TR1AB
–
–
–
–
–
ADST
–
TMA TAM XAM XAMI XAMD
LXY
15
15
15
15
15
–
–
TW6A OP3A T4AB
–
–
–
–
TAI1
–
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
4513/4514 Group User’s Manual
1-67
HARDWARE
INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (for 4514 Group)
D9 –D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111
010000 011000
010111 011111
Hex.
D3–D0 notation
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10–17 18–1F
0000
0
NOP
BLA
SZB
BMLA
0
–
TASP
A
0
LA
0
TABP TABP TABP TABP
BML
48*
0
16
32
BML
BL
BL
BM
B
0001
1
–
CLD
SZB
1
–
–
TAD
A
1
LA
1
TABP TABP TABP TABP
BML
49*
1
17
33
BML
BL
BL
BM
B
0010
2
POF
–
SZB
2
–
–
TAX
A
2
LA
2
TABP TABP TABP TABP
BML
50*
2
18
34
BML
BL
BL
BM
B
0011
3
SNZP INY
SZB
3
–
–
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML
51*
3
19
35
BML
BL
BL
BM
B
0100
4
DI
RD
SZD
–
RT
TAV1
A
4
LA
4
TABP TABP TABP TABP
BML
52*
4
20
36
BML
BL
BL
BM
B
0101
5
EI
SD
SEAn
–
RTS TAV2
A
5
LA
5
TABP TABP TABP TABP
BML
53*
5
21
37
BML
BL
BL
BM
B
0110
6
RC
–
SEAM
–
RTI
–
A
6
LA
6
TABP TABP TABP TABP
BML
54*
6
22
38
BML
BL
BL
BM
B
0111
7
SC
DEY
–
–
–
–
A
7
LA
7
TABP TABP TABP TABP
BML
55*
7
23
39
BML
BL
BL
BM
B
1000
8
–
AND
–
SNZ0
LZ
0
–
A
8
LA
8
TABP TABP TABP TABP
BML
56*
8
24
40
BML
BL
BL
BM
B
1001
9
–
OR
TDA SNZ1
LZ
1
–
A
9
LA
9
TABP TABP TABP TABP
57* BML
9
25
41
BML
BL
BL
BM
B
1010
A
AM
TEAB TABE SNZI0
LZ
2
–
A
10
LA
10
TABP TABP TABP TABP
BML
58*
10
26
42
BML
BL
BL
BM
B
1011
B
AMC
–
–
SNZI1
LZ
3
EPOF
A
11
LA
11
TABP TABP TABP TABP
59* BML
11
27
43
BML
BL
BL
BM
B
1100
C
TYA
CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
BML
60*
12
28
44
BML
BL
BL
BM
B
1101
D
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
61* BML
13
29
45
BML
BL
BL
BM
B
1110
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
62* BML
14
30
46
BML
BL
BL
BM
B
1111
F
–
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
63* BML
15
31
47
BML
BL
BL
BM
B
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9 –D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
1-68
The second word
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
• * cannot be used in the M34514M6-XXXFP.
4513/4514 Group User’s Manual
HARDWARE
INSTRUCTION CODE TABLE
INSTRUCTION CODE TABLE (continued) (for 4514 Group)
D9–D4 100000 100001100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111
Hex.
D3–D0 notation
20
21
22
23
24
25
26
27
28
2B
2C
2D
2E
2F
110000
111111
29
2A
30–3F
TAW6 IAP0 TAB1 SNZT1
–
WRST
TMA TAM XAM XAMI XAMD LXY
0
0
0
0
0
IAP1 TAB2 SNZT2
–
–
TMA TAM XAM XAMI XAMD LXY
1
1
1
1
1
T3AB TAJ1 TAMR IAP2 TAB3 SNZT3
–
–
TMA TAM XAM XAMI XAMD LXY
2
2
2
2
2
TAI1 IAP3 TAB4 SNZT4
–
–
TMA TAM XAM XAMI XAMD LXY
3
3
3
3
3
0000
0
–
TW3A OP0A T1AB
–
0001
1
–
TW4A OP1A T2AB
–
0010
2
TJ1A
0011
3
–
0100
4
TQ1A
–
OP4A
–
TAQ1 TAI2 IAP4
–
–
–
–
TMA TAM XAM XAMI XAMD LXY
4
4
4
4
4
0101
5
TQ2A
–
OP5A
–
TAQ2
IAP5
–
–
–
–
TMA TAM XAM XAMI XAMD LXY
5
5
5
5
5
0110
6
TQ3A TMRA
–
–
TAQ3 TAK0
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
6
6
6
6
6
0111
7
–
TI1A
–
–
–
SNZAD
–
–
TMA TAM XAM XAMI XAMD LXY
7
7
7
7
7
1000
8
–
TI2A TFR0ATSIAB
–
–
TMA TAM XAM XAMI XAMD
LXY
8
8
8
8
8
1001
9
–
–
–
1010
A
–
–
–
1011
B
–
TK0A
–
1100
C
–
–
–
1101
D
–
–
1110
E
TW1A
1111
F
TW2A
–
–
TW6A OP3A T4AB
–
–
–
–
TAPU0
–
–
–
–
TABSI SNZSI
–
–
TABAD
–
–
–
TMA TAM XAM XAMI XAMD LXY
9
9
9
9
9
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
10
10
10
10
10
TR3AB TAW1
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
11
11
11
11
11
–
TAW2
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
12
12
12
12
12
TPU0A
–
TAW3
–
–
–
–
–
–
TMA TAM XAM XAMI XAMD
LXY
13
13
13
13
13
–
–
–
TAW4
–
–
–
–
SST
–
TMA TAM XAM XAMI XAMD LXY
14
14
14
14
14
–
–
TR1AB
–
–
–
–
–
ADST
–
TMA TAM XAM XAMI XAMD
LXY
15
15
15
15
15
TADAB TALA
–
–
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D 9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
4513/4514 Group User’s Manual
1-69
HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS
Number of
words
Number of
cycles
Instruction code
TAB
0
0
0
0
0
1
1
1
1
0
0 1 E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0 0 E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0 1 F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0 0 C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0 1 A
1
1
(E 7–E4) ← (B)
(E 3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0 2 A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0 2 9
1
1
(DR2–DR 0) ← (A2 –A0)
TAD
0
0
0
1
0
1
0
0
0
1
0 5 1
1
1
(A 2–A0) ← (DR 2–DR 0)
(A 3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0 5 3
1
1
(A 1, A0) ← (Z1, Z0)
(A3 , A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0 5 2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0 5 0
1
1
(A 2–A0) ← (SP2–SP0)
(A 3) ← 0
LXY x, y
1
1
x3 x 2 x1 x0 y3 y2 y 1 y0
3 x y
1
1
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
LZ z
0
0
0
1
0
0
1
0
z 1 z0
0 4 8
+z
1
1
(Z) ← z, z = 0 to 3
INY
0
0
0
0
0
1
0
0
1
1
0 1 3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0 1 7
1
1
(Y) ← (Y) – 1
TAM j
1
0
1
1
0
0
j
j
j
j
2 C j
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2 F j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2 E j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2 B j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Parameter
Mnemonic
RAM to register transfer
RAM addresses
Register to register transfer
Type of
instructions
1-70
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
4513/4514 Group User’s Manual
Function
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of registers A and B to register E.
–
–
Transfers the contents of register E to registers A and B.
–
–
Transfers the contents of register A to register D.
–
–
Transfers the contents of register D to register A.
–
–
Transfers the contents of register Z to register A.
–
–
Transfers the contents of register X to register A.
–
–
Transfers the contents of stack pointer (SP) to register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped.
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1
to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction
is skipped.
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Datailed description
4513/4514 Group User’s Manual
1-71
HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Arithmetic operation
Bit operation
Comparison
operation
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1
n
n
n
n
notation
Number of
cycles
Mnemonic
Type of
instructions
Number of
words
Instruction code
Parameter
0 7 n
1
1
(A) ← n
n = 0 to 15
Hexadecimal
Function
LA n
0
0
0
1
1
TABP p
0
0
1
0
p5 p 4 p 3 p 2 p 1 p 0
0 8 p
+p
1
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR 0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1 (Note)
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
n = 0 to 15
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A) AND (M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
SB j
0
0
0
1
0
1
1
1
j
j
0 5 C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0 4 C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0 2 j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
0
0
0
0
1
0
0
1
1
0
0 2 6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0 2 5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0 7 n
Note : p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and
M34514M8/E8.
1-72
4513/4514 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
Datailed description
Continuous
description
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
–
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) 2 specified by registers A and D in page p.
When this instruction is executed, 1 stage of stack register is used.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
–
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
–
–
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
–
–
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one’s complement for register A’s contents in register A.
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
4513/4514 Group User’s Manual
1-73
HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of
words
Number of
cycles
Instruction code
Ba
0
1
1
a6 a5 a4 a 3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
BL p, a
0
0
1
1
p4 p 3 p 2 p 1 p 0
0 E p
+p
2
2
(PCH) ← p
(PCL) ← a6–a0
(Note)
1
0
p5 a6 a5 a4 a 3 a2 a1 a0
2 p a
+a
0
0
0
0
1
0
0 1 0
2
2
1
0
p5 p4 0
0
p 3 p2 p1 p0
2 p p
(PCH) ← p
(PCL) ← (DR2–DR 0, A3–A0)
(Note)
BM a
0
1
0
a6 a5 a4 a 3 a2 a1 a0
1 a a
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
p4 p 3 p 2 p 1 p 0
0 C p
+p
2
2
1
0
p5 a6 a5 a4 a 3 a2 a1 a0
2 p a
+a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
(Note)
0
0
0
1
1
0
0 3 0
2
2
1
0
p5 p4 0
0
p 3 p2 p1 p0
2 p p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR 2–DR0 ,A3–A0 )
(Note)
RTI
0
0
0
1
0
0
0
1
1
0
0 4 6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
1
0
0
0
1
0
0
0 4 4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4 5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
DI
0
0
0
0
0
0
0
1
0
0
0 0 4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0 0 5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3 8
1
1
(EXF0) = 1 ?
After skipping
(EXF0) ← 0
SNZ1
0
0
0
0
1
1
1
0
0
1
0 3 9
1
1
(EXF1) = 1 ?
After skipping
(EXF1) ← 0
Parameter
Mnemonic
Interrupt operation
Return operation
Subroutine operation
Branch operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BLA p
BMLA p
0
0
1
0
0
0
0
0
0
0
Hexadecimal
notation
Function
Note : p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and
M34514M8/E8.
1-74
4513/4514 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch out of a page : Branches to address (DR2 DR 1 DR0 A3 A2 A1 A0) 2 specified by registers D and A in
page p.
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR 1 DR 0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
–
–
Clears (0) to the interrupt enable flag INTE, and disables the interrupt.
–
–
Sets (1) to the interrupt enable flag INTE, and enables the interrupt.
(EXF0) = 1
–
Skips the next instruction when the contents of EXF0 flag is “1.”
After skipping, clears (0) to the EXF0 flag.
(EXF1) = 1
–
Skips the next instruction when the contents of EXF1 flag is “1.”
After skipping, clears (0) to the EXF1 flag.
Datailed description
4513/4514 Group User’s Manual
1-75
HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SNZI0
0
0
0
0
1
1
1
0
1
0
notation
Number of
cycles
Mnemonic
Type of
instructions
Number of
words
Instruction code
Parameter
0 3 A
1
1
Hexadecimal
Function
I12 = 1 : (INT0) = “H” ?
I12 = 0 : (INT0) = “L” ?
SNZI1
0
0
0
0
1
1
1
0
1
1
0 3 B
1
1
I22 = 1 : (INT1) = “H” ?
Timer operation
Interrupt operation
I22 = 0 : (INT1) = “L” ?
1-76
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
TAI2
1
0
0
1
0
1
0
1
0
0
2 5 4
1
1
(A) ← (I2)
TI2A
1
0
0
0
0
1
1
0
0
0
2 1 8
1
1
(I2) ← (A)
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
TAW3
1
0
0
1
0
0
1
1
0
1
2 4 D
1
1
(A) ← (W3)
TW3A
1
0
0
0
0
1
0
0
0
0
2 1 0
1
1
(W3) ← (A)
TAW4
1
0
0
1
0
0
1
1
1
0
2 4 E
1
1
(A) ← (W4)
TW4A
1
0
0
0
0
1
0
0
0
1
2 1 1
1
1
(W4) ← (A)
TAW6
1
0
0
1
0
1
0
0
0
0
2 5 0
1
1
(A) ← (W6)
TW6A
1
0
0
0
0
1
0
0
1
1
2 1 3
1
1
(W6) ← (A)
4513/4514 Group User’s Manual
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
Datailed description
(INT0) = “H”
However, I12 = 1
–
When bit 2 (I12) of register I1 is “1” : Skips the next instruction when the level of INT0 pin is “H.”
(INT0) = “L”
However, I12 = 0
–
When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT0 pin is “L.”
(INT1) = “H”
However, I22 = 1
–
When bit 2 (I22) of register I2 is “1” : Skips the next instruction when the level of INT1 pin is “H.”
(INT1) = “L”
However, I22 = 0
–
When bit 2 (I22) of register I2 is “0” : Skips the next instruction when the level of INT1 pin is “L.”
–
–
Transfers the contents of interrupt control register V1 to register A.
–
–
Transfers the contents of register A to interrupt control register V1.
–
–
Transfers the contents of interrupt control register V2 to register A.
–
–
Transfers the contents of register A to interrupt control register V2.
–
–
Transfers the contents of interrupt control register I1 to register A.
–
–
Transfers the contents of register A to interrupt control register I1.
–
–
Transfers the contents of interrupt control register I2 to register A.
–
–
Transfers the contents of register A to interrupt control register I2.
–
–
Transfers the contents of timer control register W1 to register A.
–
–
Transfers the contents of register A to timer control register W1.
–
–
Transfers the contents of timer control register W2 to register A.
–
–
Transfers the contents of register A to timer control register W2.
–
–
Transfers the contents of timer control register W3 to register A.
–
–
Transfers the contents of register A to timer control register W3.
–
–
Transfers the contents of timer control register W4 to register A.
–
–
Transfers the contents of register A to timer control register W4.
–
–
Transfers the contents of timer control register W6 to register A.
–
–
Transfers the contents of register A to timer control register W6.
4513/4514 Group User’s Manual
1-77
HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of
words
Number of
cycles
Instruction code
TAB1
1
0
0
1
1
1
0
0
0
0
2 7 0
1
1
(B) ← (T17–T14 )
(A) ← (T13–T10 )
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
(R17–R14) ← (B)
(T17–T14 ) ← (B)
(R13–R10) ← (A)
(T13–T10 ) ← (A)
TAB2
1
0
0
1
1
1
0
0
0
1
2 7 1
1
1
(B) ← (T27–T24 )
(A) ← (T23–T20 )
T2AB
1
0
0
0
1
1
0
0
0
1
2 3 1
1
1
(R27–R24) ← (B)
(T27–T24 ) ← (B)
(R23–R20) ← (A)
(T23–T20 ) ← (A)
TAB3
1
0
0
1
1
1
0
0
1
0
2 7 2
1
1
(B) ← (T37–T34 )
(A) ← (T33–T30 )
T3AB
1
0
0
0
1
1
0
0
1
0
2 3 2
1
1
(R37–R34) ← (B)
(T37–T34 ) ← (B)
(R33–R30) ← (A)
(T33–T30 ) ← (A)
TAB4
1
0
0
1
1
1
0
0
1
1
2 7 3
1
1
(B) ← (T47–T44 )
(A) ← (T43–T40 )
T4AB
1
0
0
0
1
1
0
0
1
1
2 3 3
1
1
(R47–R44) ← (B)
(T47–T44 ) ← (B)
(R43–R40) ← (A)
(T43–T40 ) ← (A)
TR1AB
1
0
0
0
1
1
1
1
1
1
2 3 F
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
TR3AB
1
0
0
0
1
1
1
0
1
1
2 3 B
1
1
(R37–R34) ← (B)
(R33–R30) ← (A)
SNZT1
1
0
1
0
0
0
0
0
0
0
2 8 0
1
1
(T1F) = 1 ?
After skipping
(T1F) ← 0
SNZT2
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
(T2F) = 1 ?
After skipping
(T2F) ← 0
SNZT3
1
0
1
0
0
0
0
0
1
0
2 8 2
1
1
(T3F) = 1 ?
After skipping
(T3F) ← 0
SNZT4
1
0
1
0
0
0
0
0
1
1
2 8 3
1
1
(T4F) = 1 ?
After skipping
(T4F) ← 0
Parameter
Mnemonic
Timer operation
Type of
instructions
1-78
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
4513/4514 Group User’s Manual
Function
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Transfers the contents of timer 1 to registers A and B.
–
–
Transfers the contents of registers A and B to timer 1 and timer 1 reload register.
–
–
Transfers the contents of timer 2 to registers A and B.
–
–
Transfers the contents of registers A and B to timer 2 and timer 2 reload register.
–
–
Transfers the contents of timer 3 to registers A and B.
–
–
Transfers the contents of registers A and B to timer 3 and timer 3 reload register.
–
–
Transfers the contents of timer 4 to registers A and B.
–
–
Transfers the contents of registers A and B to timer 4 and timer 4 reload register.
–
–
Transfers the contents of registers A and B to timer 1 reload register.
–
–
Transfers the contents of registers A and B to timer 3 reload register.
(T1F) = 1
–
Skips the next instruction when the contents of T1F flag is “1.”
After skipping, clears (0) to T1F flag.
(T2F) =1
–
Skips the next instruction when the contents of T2F flag is “1.”
After skipping, clears (0) to T2F flag.
(T3F) = 1
–
Skips the next instruction when the contents of T3F flag is “1.”
After skipping, clears (0) to T3F flag.
(T4F) = 1
–
Skips the next instruction when the contents of T4F flag is “1.”
After skipping, clears (0) to T4F flag.
Datailed description
4513/4514 Group User’s Manual
1-79
HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of
words
Number of
cycles
Instruction code
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A2–A0) ← (P22–P20)
(A3) ← 0
IAP3
1
0
0
1
1
0
0
0
1
1
2 6 3
1
1
(A) ← (P3)
OP3A
1
0
0
0
1
0
0
0
1
1
2 2 3
1
1
(P3) ← (A)
IAP4*
1
0
0
1
1
0
0
1
0
0
2 6 4
1
1
(A) ← (P4)
OP4A*
1
0
0
0
1
0
0
1
0
0
2 2 4
1
1
(P4) ← (A)
IAP5*
1
0
0
1
1
0
0
1
0
1
2 6 5
1
1
(A) ← (P5)
OP5A*
1
0
0
0
1
0
0
1
0
1
2 2 5
1
1
(P5) ← (A)
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 7
SZD
0
0
0
0
1
0
0
1
0
0
0 2 4
2
2
(D(Y)) = 0 ?
(Y) = 0 to 7
0
0
0
0
1
0
1
0
1
1
0 2 B
TK0A
1
0
0
0
0
1
1
0
1
1
2 1 B
1
1
(K0) ← (A)
TAK0
1
0
0
1
0
1
0
1
1
0
2 5 6
1
1
(A) ← (K0)
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
TAPU0
1
0
0
1
0
1
0
1
1
1
2 5 7
1
1
(A) ← (PU0)
TFR0A*
1
0
0
0
1
0
1
0
0
0
2 2 8
1
1
(FR0) ← (A)
Parameter
Mnemonic
Input/Output operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
*: The 4513 Group does not have these instructions.
1-80
4513/4514 Group User’s Manual
Function
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Transfers the input of port P0 to register A.
–
–
Outputs the contents of register A to port P0.
–
–
Transfers the input of port P1 to register A.
–
–
Outputs the contents of register A to port P1.
–
–
Transfers the input of port P2 to register A.
–
–
Transfers the input of port P3 to register A.
–
–
Outputs the contents of register A to port P3.
–
–
Transfers the input of port P4 to register A.
–
–
Outputs the contents of register A to port P4.
–
–
Transfers the input of port P5 to register A.
–
–
Outputs the contents of register A to port P5.
–
–
Sets (1) to port D.
–
–
Clears (0) to a bit of port D specified by register Y.
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
(Y) = 0 to 7
–
Skips the next instruction when a bit of port D specified by register Y is “0.”
–
–
Transfers the contents of register A to key-on wakeup control register K0.
–
–
Transfers the contents of key-on wakeup control register K0 to register A.
–
–
Transfers the contents of register A to pull-up control register PU0.
–
–
Transfers the contents of pull-up control register PU0 to register A.
–
–
Transfers the contents of register A to direction register FR0.
Datailed description
4513/4514 Group User’s Manual
1-81
HARDWARE
MACHINE INSTRUCTIONS
MACHINE INSTRUCTIONS (continued)
Number of
words
Number of
cycles
Instruction code
TABSI
1
0
0
1
1
1
1
0
0
0
2 7 8
1
1
(A) ← (SI 3–SI0 )
(B) ← (SI 7–SI4 )
TSIAB
1
0
0
0
1
1
1
0
0
0
2 3 8
1
1
(SI3–SI0 ) ← (A)
(SI7–SI4 ) ← (B)
TAJ1
1
0
0
1
0
0
0
0
1
0
2 4 2
1
1
(A) ← (J1)
TJ1A
1
0
0
0
0
0
0
0
1
0
2 0 2
1
1
(J1) ← (A)
SST
1
0
1
0
0
1
1
1
1
0
2 9 E
1
1
(SIOF) ← 0
Serial I/O starting
SNZSI
1
0
1
0
0
0
1
0
0
0
2 8 8
1
1
(SIOF) = 1 ?
After skipping
(SIOF) ← 0
TABAD
1
0
0
1
1
1
1
0
0
1
2 7 9
1
1
(A) ← (AD 5–AD 2)
(B) ← (AD 9–AD 6)
However, in the comparator mode,
(A) ← (AD 3–AD 0)
(B) ← (AD 7–AD 4)
TALA
1
0
0
1
0
0
1
0
0
1
2 4 9
1
1
(A) ← (AD1, AD 0, 0, 0)
TADAB
1
0
0
0
1
1
1
0
0
1
2 3 9
1
1
(AD3–AD 0) ← (A)
(AD7–AD 4) ← (B)
TAQ1
1
0
0
1
0
0
0
1
0
0
2 4 4
1
1
(A) ← (Q1)
TQ1A
1
0
0
0
0
0
0
1
0
0
2 0 4
1
1
(Q1) ← (A)
ADST
1
0
1
0
0
1
1
1
1
1
2 9 F
1
1
(ADF) ← 0
A-D conversion starting
SNZAD
1
0
1
0
0
0
0
1
1
1
2 8 7
1
1
(ADF) = 1 ?
After skipping
(ADF) ← 0
TAQ2
1
0
0
1
0
0
0
1
0
1
2 4 5
1
1
(A) ← (Q2)
TQ2A
1
0
0
0
0
0
0
1
0
1
2 0 5
1
1
(Q2) ← (A)
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
0
0
0
1
0
0 0 2
1
1
RAM back-up
EPOF
0
0
0
1
0
1
1
0
1
1
0 5 B
1
1
POF instruction valid
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF1) ← 0
(WEF) ← 1
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR) ← (A)
TAQ3
1
0
0
1
0
0
0
1
1
0
2 4 6
1
1
(A) ← (Q3)
TQ3A
1
0
0
0
0
0
0
1
1
0
2 0 6
1
1
(Q33, Q32) ← (A3, A2)
(Q31) ← (CMP1 comparison result)
(Q30) ← (CMP0 comparison result)
Parameter
Mnemonic
Other operation
A-D conversion operation
Serial I/O control operation
Type of
instructions
1-82
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
4513/4514 Group User’s Manual
Function
HARDWARE
Skip condition
Carry flag CY
MACHINE INSTRUCTIONS
–
–
Transfers the contents of serial I/O register SI to registers A and B.
–
–
Transfers the contents of registers A and B to serial I/O register SI.
–
–
Transfers the contents of serial I/O mode register J1 to register A.
–
–
Transfers the contents of register A to serial I/O mode register J1.
–
–
Clears (0) to SIOF flag and starts serial I/O.
(SIOF) = 1
–
Skips the next instruction when the contents of SIOF flag is “1.”
After skipping, clears (0) to SIOF flag.
–
–
Transfers the high-order 8 bits of the contents of register AD to registers A and B.
–
–
Transfers the low-order 2 bits of the contents of register AD to the high-order 2 bits of the contents of register A. Simultaneously, the low-order 2 bits of the contents of the register A is “0.”
–
–
Transfers the contents of registers A and B to the comparator register at the comparator mode.
–
–
Transfers the contents of the A-D control register Q1 to register A.
–
–
Transfers the contents of register A to the A-D control register Q1.
–
–
Clears the ADF flag, and the A-D conversion at the A-D conversion mode or the comparator operation at the
comparator mode is started.
(ADF) = 1
–
Skips the next instruction when the contents of ADF flag is “1”.
After skipping, clears (0) the contents of ADF flag.
–
–
Transfers the contents of the A-D control register Q2 to register A.
–
–
Transfers the contents of register A to the A-D control register Q2.
–
–
No operation
–
–
Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
–
–
Makes the immediate POF instruction valid by executing the EPOF instruction.
(P) = 1
–
Skips the next instruction when P flag is “1”. After skipping, P flag remains unchanged.
–
–
Operates the watchdog timer and initializes the watchdog timer flag WDF1.
–
–
Transfers the contents of the clock control register MR to register A.
–
–
Transfers the contents of register A to the clock control register MR.
–
–
Transfers the contents of the voltage comparator control register Q3 to register A.
–
–
Transfers the contents of the high-order 2 bits of register A to the high-order 2 bits of voltage comparator
control register Q3, and the comparison result of the voltage comparator is transferred to the low-order 2 bits
of the register Q3.
Datailed description
4513/4514 Group User’s Manual
1-83
HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
External 1 interrupt enable bit
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Serial I/O interrupt enable bit
V22
A-D interrupt enable bit
V21
Timer 4 interrupt enable bit
V20
Timer 3 interrupt enable bit
Interrupt control register I1
I13
Not used
I12
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
0
1
I11
INT0 pin edge detection circuit control bit
I10
INT0 pin
timer 1 control enable bit
0
1
0
1
Interrupt control register I2
I23
Not used
I22
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
0
1
I21
INT1 pin edge detection circuit control bit
I20
INT1 pin
timer 3 control enable bit
0
1
0
1
R/W
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
at reset : 00002
0
1
at RAM back-up : 00002
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
at reset : 00002
0
1
R/W
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
0
1
0
1
0
1
0
1
at RAM back-up : 00002
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
instruction)/“L” level
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I1 2 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I2 2 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
1-84
4513/4514 Group User’s Manual
HARDWARE
CONTROL REGISTERS
Timer control register W1
W1 3
Prescaler control bit
W1 2
Prescaler dividing ratio selection bit
W11
Timer 1 control bit
W1 0
Timer 1 count start synchronous circuit
control bit
Timer 2 control bit
W2 2
Not used
at reset : 00002
0
1
0
1
W21 W20
0
0
0
1
1
0
1
1
W2 1
Timer 2 count source selection bits
W2 0
Timer control register W3
Timer 3 control bit
W3 2
Timer 3 count start synchronous circuit
control bit
W3 1
Timer 3 count source selection bits
W3 0
Timer 4 control bit
W4 2
Not used
W4 1
Timer 4 count source selection bits
W4 0
CNTR1 output control bit
W6 2
D7/CNTR1 function selection bit
W6 1
CNTR0 output control bit
W6 0
D6/CNTR0 output control bit
This bit has no function, but read/write is enabled.
Count source
Timer 1 underflow signal
Prescaler output
CNTR0 input
16 bit timer (WDT) underflow signal
at RAM back-up : state retained
R/W
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
W31 W30
Count source
0
Timer 2 underflow signal
0
0
Prescaler output
1
1
Not available
0
1
Not available
1
at reset : 00002
0
1
0
1
R/W
This bit has no function, but read/write is enabled.
Count source
Timer 3 underflow signal
Prescaler output
CNTR1 input
Not available
at reset : 00002
0
1
0
1
0
1
0
1
at RAM back-up : state retained
Stop (state retained)
Operating
W41 W40
0
0
0
1
1
0
1
1
Timer control register W6
W6 3
R/W
0
1
0
1
Timer control register W4
W4 3
at RAM back-up : state retained
Stop (state retained)
Operating
at reset : 00002
W3 3
R/W
Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
0
1
0
1
0
1
0
1
Timer control register W2
W2 3
at RAM back-up : 00002
at reset : 00002
at RAM back-up : state retained
R/W
Timer 3 underflow signal output divided by 2
CNTR1 output control by timer 4 underflow signal divided by 2
D7(I/O)/CNTR1 input
CNTR1 (I/O)/D7 (input)
Timer 1 underflow signal output divided by 2
CNTR0 output control by timer 2 underflow signal divided by 2
D6(I/O)/CNTR0 input
CNTR0 (I/O)/D6 (input)
Note: “R” represents read enabled, and “W” represents write enabled.
4513/4514 Group User’s Manual
1-85
HARDWARE
CONTROL REGISTERS
Serial I/O mode register J1
at reset : 00002
J13
Not used
J12
Serial I/O internal clock dividing ratio
selection bit
J11
Serial I/O port selection bit
J10
Serial I/O synchronous clock selection bit
0
1
0
1
0
1
0
1
A-D control register Q1
Q13
Q12
Q11
Analog input pin selection bits (Note 2)
Q10
Q23
Q22
Q21
Q20
P43 /A IN7 and P42/A IN6 pin function selection bit (Not used for the 4513 Group)
P41/A IN5 pin function selection bit
(Not used for the 4513 Group)
P40/A IN4 pin function selection bit
(Not used for the 4513 Group)
0
1
0
1
0
1
0
1
Comparator control register Q3 (Note 3)
Voltage comparator (CMP1) control bit
Q32
Voltage comparator (CMP0) control bit
Q31
CMP1 comparison result store bit
Q30
CMP0 comparison reslut store bit
0
1
0
1
0
1
0
1
System clock selection bit
MR2
Not used
MR1
Not used
MR0
Not used
1
0
1
Selected pins
AIN2
AIN3
AIN4 (Not available for the 4513 Group)
AIN5 (Not available for the 4513 Group)
AIN6 (Not available for the 4513 Group)
AIN7 (Not available for the 4513 Group)
at RAM back-up : state retained
R/W
A-D conversion mode
Comparator mode
P43, P4 2
(read/write enabled for the 4513 Group)
AIN7, AIN6/P4 3, P42 (read/write enabled for the 4513 Group)
P41
(read/write enabled for the 4513 Group)
AIN5/P4 1
(read/write enabled for the 4513 Group)
P40
(read/write enabled for the 4513 Group)
AIN4/P4 0
(read/write enabled for the 4513 Group)
Voltage
Voltage
Voltage
Voltage
at RAM back-up : state retained
R/W
comparator (CMP1) invalid
comparator (CMP1) valid
comparator (CMP0) invalid
comparator (CMP0) valid
CMP1- > CMP1+
CMP1- < CMP1+
CMP0- > CMP0+
CMP0- < CMP0+
at RAM back-up : 10002
f(XIN) (high-speed mode)
f(XIN)/2 (middle-speed mode)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Notes 1: “R” represents read enabled, “W” represents write enabled.
2: Select A IN4–AIN7 with register Q1 after setting register Q2.
3: Bits 0 and 1 of register Q3 can be only read.
1-86
R/W
AIN0
AIN1
at reset : 10002
0
1
0
1
0
at RAM back-up : state retained
This bit has no function, but read/write is enabled.
at reset : 00002
Clock control register MR
MR3
Input ports P20, P2 1, P22 selected
Serial I/O ports SCK, SOUT, SIN/input ports P20 , P21 , P22 selected
External clock
Internal clock (instruction clock divided by 4 or 8)
at reset : 00002
A-D operation mode selection bit
Q33
Instruction clock signal divided by 8
Instruction clock signal divided by 4
0
1
Q12Q11 Q10
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A-D control register Q2
R/W
This bit has no function, but read/write is enabled.
at reset : 00002
Note used
at RAM back-up : state retained
4513/4514 Group User’s Manual
R/W
HARDWARE
CONTROL REGISTERS
Key-on wakeup control register K0
K03
K02
K01
K00
Pins P12 and P13 key-on wakeup
control bit
Pins P10 and P1 1 key-on wakeup
control bit
Pins P02 and P03 key-on wakeup
control bit
Pins P00 and P01 key-on wakeup
control bit
at reset : 00002
0
1
0
1
0
1
0
1
Pull-up control register PU0
PU0 3
PU0 2
PU0 1
PU0 0
Pins P1 2 and P13 pull-up transistor
control bit
Pins P10 and P11 pull-up transistor
control bit
Pins P0 2 and P03 pull-up transistor
control bit
Pins P0 0 and P01 pull-up transistor
control bit
0
1
0
1
Direction register FR0 (Note 2)
FR03
Port P5 3 input/output control bit
FR02
Port P5 2 input/output control bit
FR01
Port P5 1 input/output control bit
FR00
Port P5 0 input/output control bit
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
1
0
1
0
1
at RAM back-up : state retained
R/W
at RAM back-up : state retained
W
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
at reset : 00002
0
1
0
R/W
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
at reset : 00002
0
1
0
1
at RAM back-up : state retained
Port P53 input
Port P53 output
Port P52
Port P52
Port P51
Port P51
input
output
input
output
Port P50 input
Port P50 output
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: The 4513 Group does not have the direction register FR0.
4513/4514 Group User’s Manual
1-87
HARDWARE
BUILT-IN PROM VERSION
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4513/4514 Group has
programmable ROM version software compatible with mask ROM.
The built-in PROM of One Time PROM version can be written to
and not be erased.
The built-in PROM versions have functions similar to those of the
mask ROM versions, but they have PROM mode that enables writing to built-in PROM.
Table 25 shows the product of built-in PROM version. Figure 49
and 50 show the pin configurations of built-in PROM versions.
Table 25 Product of built-in PROM version
Product
M34513E4SP/FP
M34513E8FP
M34514E8FP
PROM size
RAM size
(✕ 10 bits)
4096 words
8192 words
8192 words
(✕ 4 bits)
256 words
384 words
384 words
Package
ROM type
SP: 32P4B FP: 32P6B-A
32P6B-A
42P2R-A
One Time PROM version
[shipped in blank]
32
P13
2
31
P12
P13 1
42 P12
D2
3
30
P11
D0 2
41 P11
D3
4
29
P10
D1 3
40 P10
D4
5
28
P03
D2 4
39 P03
D5
6
27
P02
D3 5
38 P02
D6/CNTR0
7
26
P01
D4 6
37 P01
D7/CNTR1
8
25
P00
D5 7
36 P00
P20/SCK
9
24
AIN3/CMP1+
23
AIN2/CMP1-
P21/SOUT
10
P22/SIN
11
22
AIN1/CMP0+
AIN0/CMP0-
RESET
12
CNVSS
13
XOUT
14
19
P30/INT0
XIN
15
18
VDCE
VSS
16
17
VDD
21
20
P31/INT1
Outline 32P4B
D6/CNTR0 8
D7/CNTR1 9
P50 10
P51 11
P52 12
P53 13
P20/SCK
14
P21/SOUT
15
M34514E8FP
1
D1
M34513E4SP
D0
25 P03
27 P11
26 P10
28 P12
30 D0
29 P13
32 D2
31 D1
23 P01
31 AIN3/CMP1+
30 AIN2/CMP129 AIN1/CMP0+
28 AIN0/CMP0-
26 P32
25 P31/INT1
24 P30/INT0
19
23 VDCE
22 VDD
Outline 42P2R-A
22 P00
D6/CNTR0 4
21
D7/CNTR1 5
P20/SCK 6
20
AIN3/CMP1+
AIN2/CMP1-
19
AIN1/CMP0+
P21/SOUT 7
P22/SIN 8
18
AIN0/CMP0-
M34513ExFP
Fig. 50 Pin configuration of built-in PROM version of 4514 Group
P30/INT0 16
VDCE 15
VSS 13
VDD 14
11
XIN 12
XOUT
RESET 9
CNVSS 10
17 P31/INT1
Outline 32P6B-A
Fig. 49 Pin configuration of built-in PROM version of 4513 Group
1-88
32 P40/AIN4
27 P33
VSS 21
24 P02
33 P41/AIN5
RESET 17
CNVSS 18
XIN 20
D4 2
D5 3
34 P42/AIN6
P22/SIN 16
XOUT
D3 1
35 P43/AIN7
4513/4514 Group User’s Manual
HARDWARE
BUILT-IN PROM VERSIONS
(1) PROM mode
Table 26 Programming adapters
The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read
from the built-in PROM.
In the PROM mode, the programming adapter can be used with a
general-purpose PROM programmer to write to or read from the
built-in PROM as if it were M5M27C256K. Programming adapters
are listed in Table 26.Contact addresses at the end of this sheet for
the appropriate PROM programmer.
• Writing and reading of built-in PROM
Programming voltage is 12.5 V. Write the program in the PROM
of the built-in PROM version as shown in Figure 51.
(2) Notes on handling
➀A high-voltage is used for writing. Take care that overvoltage is
not applied. Take care especially at turning on the power.
➁For the One Time PROM version shipped in blank, Mitsubishi
Electric corp. does not perform PROM writing test and screening
in the assembly process and following processes. In order to improve reliability after writing, performing writing and test
according to the flow shown in Figure 52 before using is recommended (Products shipped in blank: PROM contents is not
written in factory when shipped).
Microcomputer
Programming adapter
PCA7442SP
M34513E4SP
M34513E4FP, M34513E8FP
M34514E8FP
Address
000016
PCA7442FP
PCA7441
AAAAAAAAA
AAAAAAAAA
AAAAAAAAA
AAAAAAAAA
AAAAAAAAA
AAAAAAAAA
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
1FFF16
400016
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
5FFF16
7FFF16
Set “FF16” to the shaded area.
Fig. 51 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 52 Flow of writing and test of the product shipped in blank
4513/4514 Group User’s Manual
1-89
HARDWARE
BUILT-IN PROM VERSION
1-90
4513/4514 Group User’s Manual
CHAPTER 2
APPLICATION
2.1 I/O pins
2.2 Interrupts
2.3 Timers
2.4 Serial I/O
2.5 A-D converter
2.6 Voltage comparator
2.7 Reset
2.8 Voltage drop detection circuit
2.9 RAM back-up
2.10 Oscillation circuit
APPLICATION
2.1 I/O pins
2.1 I/O pins
The 4513/4514 Group has the twenty-eight I/O pins (eighteen I/O pins for 4513 Group), three input pins.
(Ports P2 0–P2 2 , P3 0, P3 1 , D 6 and D 7 are also used as serial I/O pins S CK, S OUT , S IN, and INT0, INT1,
CNTR0 and CNTR1 pins, respectively).
This section describes each port I/O function, related registers, application example using each port function
and notes.
2.1.1 I/O ports
(1)
Port P0
Port P0 is a 4-bit I/O port.
Port P0 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor
which turns ON/OFF with register PU0.
■ Input/output of port P0
● Data input to port P0
Set the output latch of specified port P0i (i=0 to 3) to “1” with the OP0A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P0 is transferred to register A when the IAP0 instruction is executed.
● Data output from port P0
The contents of register A is output to port P0 with the OP0A instruction.
The output structure is an N-channel open-drain.
(2)
Port P1
Port P1 is a 4-bit I/O port.
Port P1 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor
which turns ON/OFF with register PU0.
■ Input/output of port P1
● Data input to port P1
Set the output latch of specified port P1i (i=0 to 3) to “1” with the OP1A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P1 is transferred to register A when the IAP1 instruction is executed.
● Data output from port P1
The contents of register A is output to port P1 with the OP1A instruction.
The output structure is an N-channel open-drain.
(3)
Port P2
Port P2 is a 3-bit input port.
■ Input of port P2
● Data input to port P2
The state of port P2 is transferred to register A when the IAP2 instruction is executed. However,
port P2 is 3 bits and A3 is fixed to “0.”
2-2
4513/4514 Group User’s Manual
APPLICATION
2.1 I/O pins
(4)
Port P3
Port P3 is a 4-bit I/O port for the 4514 Group, and a 2-bit I/O port for the 4513 Group.
■ Input/output of port P3
● Data input to port P3
Set the output latch of specified port P3i (i=0 to 3) to “1” with the OP3A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P3 is transferred to register A when the IAP3 instruction is executed.
However, A2 and A 3 are undefined in the 4513 Group.
● Data output from port P3
The contents of register A is output to port P3 with the OP3A instruction.
The output structure is an N-channel open-drain.
(5)
Port P4 (The 4513 Group does not have this port.)
Port P4 is a 4-bit I/O port.
■ Input/output of port P4
Ports P40–P4 3 are also used as A IN4–A IN7. Therefore, when P40 /AIN4–P43 /AIN7 are used as port
P4, set corresponding bits of A-D control register Q2 to “0”.
● Data input to port P4
Set the output latch of specified port P4i (i=0 to 3) to “1” with the OP4A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P4 is transferred to register A when the IAP4 instruction is executed.
● Data output from port P4
The contents of register A is output to port P4 with the OP4A instruction.
The output structure is an N-channel open-drain.
(6)
Port P5 (The 4513 Group does not have this port.)
Port P5 is a 4-bit I/O port.
■ Input/output of port P5
Port P5 has direction register FR0 to input/output by the bit.
● Data input to port P5
Set the bit of register FR0i(i=0 to 3) corresponding to specified port P5i (i=0 to 3) to “0.” When
the register FR0 is set to “1,” the value of output latch is input.
The state of port P5 is transferred to register A when the IAP5 instruction is executed.
● Data output from port P5
Set the bit of register FR0i(i=0 to 3) corresponding to specified port P5i (i=0 to 3) to “1.” When
the register FR0 is set to “0,” specified port P5i is in the high-impedance state.
The contents of register A is output to port P5 with the OP5A instruction.
The output structure is CMOS.
4513/4514 Group User’s Manual
2-3
APPLICATION
2.1 I/O pins
(7)
Port D
D0–D 7 are eight independent I/O ports.
■ Input/output of port D
Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D0–D 7, select one
of port D with the register Y of the data pointer first.
● Data input to port D
Set the output latch of specified port Di (i = 0 to 7) to “1” with the SD instruction.
When the output latch is set to “0,” “L” level is input.
When the SZD instruction is executed, if the port specified by register Y is “0,” the next
instruction is skipped. If it is “1,” the next instruction is executed.
● Data output from port D
Set the output level to the output latch with the SD and RD instructions.
The state of pin enters the high-impedance state when the SD instruction is executed.
The states of all port D enter the high-impedance state when the CLD instruction is executed.
The state of pin becomes “L” level when the RD instruction is executed.
The output structure is an N-channel open-drain.
Notes 1: When the SD and RD instructions are used, do not set “10002 ” or more to register Y.
2: Port D 6 is also used as CNTR0, and port D7 is also used as CNTR1. Accordingly, when
using ports D 6 and D 7 functions, set bit 0 (W6 0) and bit 2 (W6 2 ) of timer control register
W6 to “0.”
2.1.2 Related registers
(1)
Pull-up control register PU0
Register PU0 controls the ON/OFF of the ports P0 0–P0 3 and P1 0–P1 3 pull-up transistor.
Set the contents of this register through register A with the TPU0A instruction.
The contents of register PU0 is transferred to register A with the TAPU0 instruction.
Table 2.1.1 shows the pull-up control register PU0.
Table 2.1.1 Pull-up control register PU0
Pull-up control register PU0
PU03
PU02
PU01
at reset : 0000 2
at RAM back-up : state retained
Ports P1 2, P13
0
Pull-up transistor OFF
pull-up transistor control bit
Ports P1 0, P11
pull-up transistor control bit
Ports P0 2, P03
pull-up transistor control bit
1
0
1
0
1
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
transistor
transistor
transistor
transistor
transistor
ON
OFF
ON
OFF
ON
Ports P0 0, P01
Pull-up transistor OFF
0
pull-up transistor control bit
Pull-up transistor ON
1
Note: “R” represents read enabled, and “W” represents write enabled.
PU00
2-4
4513/4514 Group User’s Manual
R/W
APPLICATION
2.1 I/O pins
(2)
Key-on wakeup control register K0
Register K0 controls the ON/OFF of the key-on wakeup function of ports P00–P0 3 and P1 0–P1 3.
Set the contents of this register through register A with the TK0A instruction.
The contents of register K0 is transferred to register A with the TAK0 instruction.
Table 2.1.2 shows the key-on wakeup control register K0.
Table 2.1.2 Key-on wakeup control register K0
Key-on wakeup control register K0
K0 3
K0 2
K0 1
at reset : 0000 2
Ports P1 2, P13
key-on wakeup control bit
Ports P1 0, P11
key-on wakeup control bit
Ports P0 2, P03
0
1
0
1
0
key-on wakeup control bit
Ports P0 0, P01
K0 0
key-on wakeup control bit
Note: “R” represents read enabled, and “W”
Key-on
Key-on
Key-on
Key-on
Key-on
at RAM back-up : state retained
wakeup
wakeup
wakeup
wakeup
wakeup
R/W
not used
used
not used
used
not used
Key-on wakeup used
1
Key-on wakeup not used
0
Key-on wakeup used
1
represents write enabled.
(3) A-D control register Q2
Bits 0 to 2 of register Q2 controls the pin function selection bits.
Set the contents of this register through register A with the TQ2A instruction.
The contents of register Q2 is transferred to register A with the TAQ2 instruction.
Table 2.1.3 shows the A-D control register Q2.
Table 2.1.3 A-D control register Q2
A-D control register Q2
Q2 3
Q2 2
Q2 1
at reset : 0000 2
A-D operation mode control bit
P4 3 /AIN7 , P4 2/A IN6 pin function
selection bit (Note 3)
P41/AIN5 pin function selection bit
(Note 3)
at RAM back-up : state retained
0
1
A-D conversion mode
Comparator mode
0
1
0
1
0
P4 3, P4 2 (I/O) (Note 4)
A IN7, A IN6/P4 3 , P42 (Output) (Note 4)
P4 1 (I/O) (Note 4)
A IN5 /P41 (Output) (Note 4)
P4 0 (I/O) (Note 4)
R/W
P40/AIN4 pin function selection bit
(Note 3)
A IN4 /P40 (Output) (Note 4)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select AIN4 –A IN7 with register Q1 after setting register Q2.
3: For the 4513 Group, these bits are not used.
4: For the 4513 Group, only read/write of these bits is enabled.
5: When setting ports, Q2 3 is not used.
Q2 0
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APPLICATION
2.1 I/O pins
(4)
Direction register FR0 (The 4513 Group does not have this register.)
Register FR0 is used to switch to input/output of P50–P5 3.
Set the contents of this register through register A with the TFR0A instruction.
Table 2.1.4 shows the direction register FR0.
Table 2.1.4 Direction register FR0
Direction register FR0 (Note 2)
at reset : 00002
FR03
Port P53 input/output control bit
FR02
Port P52 input/output control bit
0
1
0
Port
Port
Port
Port
1
0 Port
FR01 Port P51 input/output control bit
1 Port
0 Port
FR00 Port P50 input/output control bit
1 Port
Notes 1: “W” represents write enabled.
2: The 4513 Group does not have register
(5)
P53
P53
P52
P52
input
output
input
output
P51
P51
P50
P50
input
output
input
output
at RAM back-up : state retained
W
FR0.
Timer control register W6
D6/CNTR0 function selection bit is assigned to bit 0, D7 /CNTR1 function selection bit is assigned to
bit 2.
Set the contents of this register through register A with the TW6A instruction.
The contents of register W6 is transferred to register A with the TAW6 instruction.
Table 2.1.5 shows the timer control register W6.
Table 2.1.5 Timer control register W6
Timer control register W6
W63
W62
W61
at reset : 00002
0
CNTR1 output control bit
1
0
D7/CNTR1 function selection bit
1
0
CNTR0 output control bit
1
at RAM back-up : state retained
Timer 3 underflow signal output divided by 2
CNTR1 output control by timer 4 underflow signal divided by 2
D7(I/O)/CNTR1 input
CNTR1 I/O/D 7 (input)
Timer 1 underflow signal output divided by 2
CNTR0 output control by timer 2 underflow signal divided by 2
D6 (I/O)/CNTR0 input
0
1 CNTR0 I/O/D 6 (input)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When setting ports, W6 3 and W61 are not used.
W60
2-6
D6/CNTR0 function selection bit
R/W
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APPLICATION
2.1 I/O pins
2.1.3 Port application examples
(1)
Key input by key scan
Key matrix can be set up by connecting keys externally because port D output structure is an Nchannel open-drain and port P0 has the pull-up resistor.
Outline: The connecting required external part is just keys.
Specifications: Port D is used to output “L” level and port P0 is used to input 16 keys. Multiple key
inputs are not detected.
Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing.
M34513/M34514
SW4
SW3
SW2
SW1
SW8
SW7
SW6
SW5
SW12
SW11
SW10
SW9
SW16
SW15
SW14
SW13
D0
D1
D2
D3
P00
P01
P02
P03
Fig. 2.1.1 Key input by key scan
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APPLICATION
2.1 I/O pins
Switching key input selection port (D 0 →D 1)
Stabilizing wait time for input
Reading port (key input)
Key input period
D0
D1
D2
“H”
“L”
“H”
“L”
“H”
“L”
D3
“H”
“L”
IAP0
IAP0
IAP0
IAP0
Input to
SW1–SW4
Input to
SW5–SW8
Input to
SW9–SW12
Input to
SW13–SW16
Note: “H” output of port D becomes high-impedance state.
Fig. 2.1.2 Key scan input timing
2-8
4513/4514 Group User’s Manual
IAP0
Input to
SW1–SW4
APPLICATION
2.1 I/O pins
2.1.4 Notes on use
(1)
Note when an I/O port except port P5 is used as an input port
Set the output latch to “1” and input the port value before input. If the output latch is set to “0,” “L”
level can be input.
(2)
Noise and latch-up prevention
Connect an approximate 0.1 µF bypass capacitor directly to the VSS line and the V DD line with the
thickest possible wire at the shortest distance, and equalize its wiring in width and length.
The CNVSS pin is also used as the V PP pin (programming voltage = 12.5 V) at the built-in PROM
version.
Connect the CNV SS/VPP pin to VSS through an approximate 5 kΩ resistor which is connected to the
CNVSS/VPP pin at the shortest distance.
(3)
Note on multifunction
The input of D6 , D 7, P2 0–P2 2 , CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P3 1 ,
P40–P43 can be used even when CNTR0, CNTR1, S CK, SOUT, SIN , AIN0–AIN3, INT0, INT1, and AIN4–
A IN7 are selected.
(4)
Connection of unused pins
Table 2.1.6 shows the connections of unused pins.
(5)
SD, RD instructions
When the SD and RD instructions are used, do not set “10002 ” or more to register Y.
(6)
Analog input pins
When both analog input AIN4 –A IN7 and I/O port P4 function are used, note the following;
• Notes when selecting analog input pins
Even when register Q2 is used to set the pins for analog input, P4 0/A IN4–P4 3 /AIN7 continue to
function as P4 0 –P43 I/O. Accordingly, when any of them are used as I/O port P4 and others are
used as analog input pins, make sure to set the outputs of pins that are set for analog input to
“1.” Also, for the port input, the port input function of the pin functions as analog input is undefined.
(7)
Notes on port P3
In the 4513 Group, when the IAP3 instruction is executed, the contents of high-order 2 bits of register
A are undefined.
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APPLICATION
2.1 I/O pins
Table 2.1.6 connections of unused pins
Connection
Pin
Open (when using an external clock).
X OUT
VDCE
D0 –D 5
D6 /CNTR0
D7 /CNTR1
P2 0/SCK
P2 1/SOUT
P2 2/SIN
P3 0/INT0
P3 1/INT1
P3 2 , P33
P4 0/AIN4 –P43/AIN7
P5 0 –P53 (Note 1)
A IN0 /CMP0A IN1 /CMP0+
A IN2 /CMP1A IN3 /CMP1+
P0 0–P0 3
P1 0–P1 3
Connect to V SS.
Connect to V SS, or set the output latch to “0” and open.
Connect to V SS.
Connect to V SS, or set the output latch to “0” and open.
Connect to V SS, or set the output latch to “0” and open.
When the input mode is selected by software, pull-up to V DD through a resistor or
pull-down to VSS . When selecting the output mode, open.
Connect to V SS.
Open or connect to V SS (Note 2).
Open or connect to V SS (Note 2).
Notes 1: After system is released from reset, port P5 is in an input mode (direction register FR0 = 00002 )
2: When the P00 –P03 and P1 0–P1 3 are connected to V SS, turn off their pull-up transistors (register
PU0i=“0”) and also invalidate the key-on wakeup functions (register K0i=“0”) by software. When
these pins are connected to V SS while the key-on wakeup functions are left valid, the system fails
to return from RAM back-up state. When these pins are open, turn on their pull-up transistors
(register PU0i=“1”) by software, or set the output latch to “0.”
Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If
only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors
by software and also disconnect the other pin. (i = 0, 1, 2, or 3.)
(Note in order to set the output latch to “0” and make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port
is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply
current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by
noise or a program run away (caused by noise).
(Note in order to connect unused pins to V SS or V DD)
• To avoid noise, connect the unused pins to V SS or VDD at the shortest distance using a thick wire.
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APPLICATION
2.2 Interrupts
2.2 Interrupts
The 4513/4514 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4,
A-D, and serial I/O.
This section describes individual types of interrupts, related registers, application examples using interrupts
and notes.
2.2.1 Interrupt functions
(1)
External 0 interrupt (INT0)
The interrupt request occurs by the change of input level of INT0 pin.
The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register I1.
■ External 0 interrupt INT0 processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the external 0 interrupt occurs, the interrupt
processing is executed from address 0 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZ0 instruction is valid when the bit 0 of register V1 is set
to “0.”
(2)
External 1 interrupt (INT1)
The interrupt request occurs by the change of input level of INT1 pin.
The interrupt valid waveform can be selected by the bits 1 and 2 of the interrupt control register I2.
■ External 1 interrupt INT1 processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 1 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the external 1 interrupt occurs, the interrupt
processing is executed from address 2 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZ1 instruction is valid when the bit 1 of register V1 is set
to “0.”
(3)
Timer 1 interrupt
The interrupt request occurs by the timer 1 underflow.
■ Timer 1 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 1 interrupt occurs, the interrupt processing
is executed from address 4 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set
to “0.”
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APPLICATION
2.2 Interrupts
(4)
Timer 2 interrupt
The interrupt request occurs by the timer 2 underflow.
■ Timer 2 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 2 interrupt occurs, the interrupt processing
is executed from address 6 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set
to “0.”
(5)
Timer 3 interrupt
The interrupt request occurs by the timer 3 underflow.
■ Timer 3 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 0 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the timer 3 interrupt occurs, the interrupt processing
is executed from address 8 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT3 instruction is valid when the bit 0 of register V2 is set
to “0.”
(6)
Timer 4 interrupt
The interrupt request occurs by the timer 4 underflow.
■ Timer 4 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 1 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the timer 4 interrupt occurs, the interrupt processing
is executed from address A in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT4 instruction is valid when the bit 1 of register V2 is set
to “0.”
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APPLICATION
2.2 Interrupts
(7)
A-D interrupt
The interrupt request occurs by the end of the A-D conversion.
■ A-D interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the A-D interrupt occurs, the interrupt processing
is executed from address C in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set
to “0.”
(8)
Serial I/O interrupt
The interrupt request occurs by the end of the serial I/O transmit/receive.
■ Serial I/O interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the serial I/O interrupt occurs, the interrupt
processing is executed from address E in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZSI instruction is valid when the bit 3 of register V2 is set
to “0.”
2.2.2 Related registers
(1)
Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable.
Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE
flag is cleared to “0” with the DI instruction.
When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are
disabled until the EI instruction is executed.
Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more
instruction.
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APPLICATION
2.2 Interrupts
(2)
Interrupt control register V1
Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1.
Set the contents of this register through register A with the TV1A instruction.
In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A.
Table 2.2.1 shows the interrupt control register V1.
Table 2.2.1 Interrupt control register V1
Interrupt control register V1
V1 3
Timer 2 interrupt enable bit
V1 2
Timer 1 interrupt enable bit
V1 1
External 1 interrupt enable bit
at reset : 0000 2
0
1
0
1
0
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
at RAM back-up : 0000 2
R/W
disabled (SNZT2 instruction is valid)
enabled (SNZT2 instruction is invalid)
disabled (SNZT1 instruction is valid)
enabled (SNZT1 instruction is invalid)
disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
1
Interrupt disabled (SNZ0 instruction is valid)
0
V1 0
External 0 interrupt enable bit
Interrupt enabled (SNZ0 instruction is invalid)
1
Note: “R” represents read enabled, and “W” represents write enabled.
(3)
Interrupt control register V2
Interrupt enable bits of timer 3, timer 4, A-D, and serial I/O are assigned to register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.2.2 shows the interrupt control register V2.
Table 2.2.2 Interrupt control register V2
Interrupt control register V2
V2 3
Serial I/O interrupt enable bit
V2 2
A-D interrupt enable bit
V2 1
Timer 4 interrupt enable bit
V2 0
Timer 3 interrupt enable bit
at reset : 0000 2
at RAM back-up : 0000 2
0
1
0
1
Interrupt
Interrupt
Interrupt
Interrupt
disabled (SNZSI instruction is valid)
enabled (SNZSI instruction is invalid)
disabled (SNZAD instruction is valid)
enabled (SNZAD instruction is invalid)
0
1
0
1
Interrupt
Interrupt
Interrupt
Interrupt
disabled (SNZT4 instruction is valid)
enabled (SNZT4 instruction is invalid)
disabled (SNZT3 instruction is valid)
enabled (SNZT3 instruction is invalid)
R/W
Note: “R” represents read enabled, and “W” represents write enabled.
(4)
2-14
Interrupt request flag
The activated condition for each interrupt is examined. Each interrupt request flag is set to “1” when
the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt
enable bit.
Each interrupt request flag is cleared to “0” when either;
•an interrupt occurs, or
•the next instruction is skipped with a skip instruction.
4513/4514 Group User’s Manual
APPLICATION
2.2 Interrupts
(5)
Interrupt control register I1
The INT0 pin timer 1 control enable bit is assigned to bit 0, INT0 pin edge detection circuit control
bit is assigned to bit 1, and interrupt valid waveform for INT0 pin/return level selection bit is assigned
to bit 2.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.2.3 shows the interrupt control register I1.
Table 2.2.3 Interrupt control register I1
Interrupt control register I1
at reset : 0000 2
0
1
I1 3
Not used
I1 2
Interrupt valid waveform for INT0
pin/return level selection bit
(Note 2)
0
1
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized
with the SNZI0 instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized
with the SNZI0 instruction)/“H” level
INT0 pin edge detection circuit
One-sided edge detected
0
control bit
Both edges detected
1
INT0 pin
Disabled
0
I1 0
timer 1 control enable bit
Enabled
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set.
Accordingly, clear EXF0 flag with the SNZ0 instruction.
I1 1
(6)
Interrupt control register I2
The INT1 pin timer 3 control enable bit is assigned to bit 0, the INT1 pin edge detection circuit control
bit is assigned to bit 1 and the interrupt valid waveform for INT1 pin/return level selection bit is
assigned to bit 2.
Set the contents of this register through register A with the TI2A instruction.
In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 2.2.4 shows the interrupt control register I2.
Table 2.2.4 Interrupt control register I2
Interrupt control register I2
at reset : 0000 2
0
1
I2 3
Not used
I2 2
Interrupt valid waveform for INT1
pin/return level selection bit
(Note 2)
INT1 pin edge detection circuit
control bit
0
1
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT1 pin is recognized
with the SNZI1 instruction)/“L” level
Rising waveform (“H” level of INT1 pin is recognized
with the SNZI1 instruction)/“H” level
One-sided edge detected
Both edges detected
0
1
INT1 pin
Disabled
0
I2 0
timer 3 control enable bit
Enabled
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set.
Accordingly, clear EXF1 flag with the SNZ1 instruction.
I2 1
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APPLICATION
2.2 Interrupts
2.2.3 Interrupt application examples
(1)
External 0 interrupt
The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can
recognize the change of both edges (“H”→“L” or “L”→“H”).
Outline: An external 0 interrupt can be used by dealing with the change of edge (“H”→“L” or
“L”→“H”) in both directions as a trigger.
Specifications: An interrupt occurs by the change of an external signals edge (“H”→“L” or “L”→“H”).
Figure 2.2.1 shows an operation example of an external 0 interrupt, and Figure 2.2.2 shows a setting
example of an external 0 interrupt.
(2)
External 1 interrupt
The INT1 pin is used for external 1 interrupt, of which valid waveforms can be chosen, which can
recognize the change of both edges (“H”→“L” or “L”→“H”).
Outline: An external 1 interrupt can be used by dealing with the change of edge (“H”→“L” or
“L”→“H”) in both directions as a trigger.
Specifications: An interrupt occurs by the change of an external signals edge (“H”→“L” or “L”→“H”).
Figure 2.2.3 shows an operation example of an external 1 interrupt, and Figure 2.2.4 shows a setting
example of an external 1 interrupt.
(3)
Timer 1 interrupt
Constant period interrupts by a setting value to timer 1 can be used.
Outline: The constant period interrupts by the timer 1 underflow signal can be used.
Specifications: Prescaler and timer 1 divide the system clock frequency f(XIN) = 4.0 MHz, and the
timer 1 interrupt occurs every 1 ms.
Figure 2.2.5 shows a setting example of the timer 1 constant period interrupt.
(4)
Timer 2 interrupt
Constant period interrupts by a setting value to timer 2 can be used.
Outline: The constant period interrupts by the timer 2 underflow signal can be used.
Specifications: Timer 2 divides the 16-bit fixed dividing frequency timer, and the timer 2 interrupt
occurs every about 2 sec.
Figure 2.2.6 shows a setting example of the timer 2 constant period interrupt.
(5)
Timer 3 interrupt
Constant period interrupts by a setting value to timer 3 can be used.
Outline: The constant period interrupts by the timer 3 underflow signal can be used.
Specifications: Prescaler and timer 3 divide the system clock frequency f(XIN) = 4.0 MHz, and the
timer 3 interrupt occurs every 1 ms.
Figure 2.2.7 shows a setting example of the timer 3 constant period interrupt.
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APPLICATION
2.2 Interrupts
(6)
Timer 4 interrupt
Constant period interrupts by a setting value to timer 4 can be used.
Outline: The constant period interrupts by the timer 4 underflow signal can be used.
Specifications: Prescaler, timer 3 and timer 4 divide the system clock frequency f(XIN) = 4.0 MHz,
and the timer 4 interrupt occurs every 250 ms.
Figure 2.2.8 shows a setting example of the timer 4 constant period interrupt.
P30/INT0
“H”
“L”
P30/INT0
“H”
An interrupt occurs after the valid waveform “falling” is detected.
An interrupt occurs after the valid waveform “rising” is detected.
“L”
Fig. 2.2.1 INT0 interrupt operation example
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APPLICATION
2.2 Interrupts
➀ Disable Interrupts
INT0 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
INT0 interrupt occurrence disabled
✕ ✕ ✕ 0 (TV1A instruction)
b3
Interrupt control register V1
b0
➁ Set Port
Port used for INT0 interrupt is set to input port.
b3
Port P30 output latch
b0
✕ ✕ ✕ 1 Set to input (OP3A instruction)
➂ Set Valid Waveform
Valid waveform of INT pin is selected.
Both edges detection selected
b3
b0
Interrupt control register I1 ✕ ✕ 1 ✕ Both edges detection selected (TI1A instruction)
➃ Clear Interrupt Request
External interrupt activated condition is cleared.
INT0 interrupt request flag EXF0 “0”
INT0 interrupt activated condition cleared
(SNZ0 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
AAAAAAA
AAAAAAA
➄ Enable Interrupts
The INT0 interrupt which is temporarily disabled is enabled.
b3
b0
INT0 interrupt occurrence enabled
Interrupt control register V1 ✕ ✕ ✕ 1 (TV1A instruction)
All interrupts enabled (EI instruction)
Interrupt enable flag INTE “1”
INT0 interrupt execution started
“✕”: it can be “0” or “1.”
Fig. 2.2.2 INT0 interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
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APPLICATION
2.2 Interrupts
P31/INT1
P31/INT1
“H”
“L”
“H”
An interrupt occurs after the valid waveform “falling” is detected.
An interrupt occurs after the valid waveform “rising” is detected.
“L”
Fig. 2.2.3 INT1 interrupt operation example
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APPLICATION
2.2 Interrupts
➀ Disable Interrupts
INT1 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
INT1 interrupt occurrence disabled
✕ ✕ 0 ✕ (TV1A instruction)
b3
Interrupt control register V1
b0
➁ Set Port
Port used for INT1 interrupt is set to input port.
b3
Port P31 output latch
b0
✕ ✕ 1 ✕ Set to input (OP3A instruction)
➂ Set Valid Waveform
Valid waveform of INT pin is selected.
Both edges detection selected
b3
b0
Interrupt control register I2 ✕ ✕ 1 ✕ Both edges detection selected (TI2A instruction)
➃ Clear Interrupt Request
External interrupt activated condition is cleared.
INT1 interrupt request flag EXF1 “0”
INT1 interrupt activated condition cleared
(SNZ1 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag EXF1, insert the NOP instruction after the SNZ1 instruction.
AAAAAAA
AAAAAAA
➄ Enable Interrupts
The INT1 interrupt which is temporarily disabled is enabled.
b3
b0
INT1 interrupt occurrence enabled
Interrupt control register V1 ✕ ✕ 1 ✕ (TV1A instruction)
All interrupts enabled (EI instruction)
Interrupt enable flag INTE “1”
“✕”: it can be “0” or “1.”
INT1 interrupt execution started
Fig. 2.2.4 INT1 interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
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APPLICATION
2.2 Interrupts
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Timer 1 interrupt occurrence disabled
✕0 ✕✕
(TV1A instruction)
b3
Interrupt control register V1
b0
➁ Stop Timer Operation
Timer 1 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
b3
Timer control register W1
b0
Timer 1 stop (TW1A instruction)
0 1 0 ✕ Prescaler stop
Prescaler divided by 16 selected
➂ Set Timer Value
Timer 1 count time is set. (The formula is shown ❈A below.)
Timer 1 reload register R1 “5216”
Timer count value 82 set (T1AB instruction)
➃ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F “0” g0 h Timer 1 interrupt activated condition cleared
(SNZT1 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
➄ Start Timer Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3
b0
Timer control register W1 1 1 1 ✕ Timer 1 operation start (TW1A instruction)
Prescaler operation stop
AAAAAA
AAAAAA
➅ Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled.
b3
b0
Timer 1 interrupt occurrence enabled
Interrupt control register V1 ✕ 1 ✕ ✕
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
Constant period interrupt execution start
❈A The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 1 ms are set as follows.
–1
1 ms ≅ (4.0 MHz) ✕ 3
✕ 16
✕ (82+1)
System clock Instruction Prescaler Timer 1
clock
dividing
count
ratio
value
“✕”: it can be “0” or “1.”
Fig. 2.2.5 Timer 1 constant period interrupt setting example
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APPLICATION
2.2 Interrupts
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Interrupt control register V1 0 ✕ ✕ ✕ Timer 2 interrupt occurrence disabled
(TV1A instruction)
b3
b0
➁ Stop Timer Operation
Timer is temporarily stopped.
Timer 2 count source is selected.
b3
b0
Timer control register W2 0 ✕ 1 1
Timer 2 stop (TW2A instruction)
16-bit timer (WDT) underflow signal selected
for count source
➂ Set Timer Value
Timer 2 count time is set. (The formula is shown ❈A below.)
Timer 2 reload register R2 “2716”
Timer count value 39 set (T2AB instruction)
➃ Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F “0”
Timer 2 interrupt activated condition cleared
(SNZT2 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
➄ Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
b3
b0
Timer control register W2 1 ✕ 1 1 Timer 2 operation start (TW2A instruction)
➅ Enable Interrupts
AAAAAAA
AAAAAAA
The timer 2 interrupt which is temporarily disabled is enabled.
b3
b0
Timer 2 interrupt occurrence enabled
Interrupt control register V1 1 ✕ ✕ ✕ (TV1A instruction)
All interrupts enabled (EI instruction)
Interrupt enable flag INTE “1”
Constant period interrupt execution start
❈A The timer 2 count value to make the interrupt occur every about 2 s is set as follows.
2 s ≅ (4.0 MHz) –1 ✕ 3
✕ 216
✕
System clock Instruction 16-bit
clock
fixed
dividing
frequency
(39+1)
Timer 2
count
value
“✕”: it can be “0” or “1.”
Fig. 2.2.6 Timer 2 constant period interrupt setting example
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2.2 Interrupts
➀ Disable Interrupts
Timer 3 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Timer 3 interrupt occurrence disabled
✕✕✕ 0
(TV2A instruction)
b3
Interrupt control register V2
b0
➁ Stop Timer 3 Operation
Timer 3 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
b3
b0
0 1 ✕✕
Timer control register W1
b3
Timer control register W3
b0
Prescaler stop (TW1A instruction)
Prescaler divided by 16 selected
Timer 3 stop (TW3A instruction)
0✕ 0 1
Prescaler selected for count source
➂ Set Timer Value
Timer 3 count time is set. (The formula is shown ❈A below.)
Timer 3 reload register R3 “5216”
Timer count value 82 set (T3AB instruction)
➃ Clear Interrupt Request
Timer 3 interrupt activated condition is cleared.
Timer 3 interrupt request flag T3F “0”
g0 h
Timer 3 interrupt activated condition cleared
(SNZT3 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T3F, insert the NOP instruction after the SNZT3 instruction.
➄ Start Timer 3 Operation
Timer 3 and prescaler temporarily stopped are restarted.
b3
b0
Timer control register W3 1 ✕ 0 1 Timer 3 operation start (TW3A instruction)
b3
b0
Timer control register W1 1 1 ✕ ✕ Prescaler operation start (TW1A instruction)
➅ Enable Interrupts
AAAAAA
AAAAAA
The timer 3 interrupt which is temporarily disabled is enabled.
b3
b0
Timer 3 interrupt occurrence enabled
Interrupt control register V2 ✕ ✕ ✕ 1 (TV2A instruction)
All interrupts enabled (EI instruction)
Interrupt enable flag INTE “1”
Constant period interrupt execution start
❈A The prescaler dividing ratio and time 3 count value to make the interrupt occur every 1 ms are set as follows.
–1
1 ms ≅ (4.0 MHz) ✕ 3
✕ 16
✕ (82+1)
System clock Instruction Prescaler Timer 3
clock
dividing
count
ratio
value
“✕”: it can be “0” or “1.”
Fig. 2.2.7 Timer 3 constant period interrupt setting example
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APPLICATION
2.2 Interrupts
➀ Disable Interrupts
Timer 4 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Timer 4 interrupt occurrence disabled
✕ ✕ 0 ✕ (TV2A instruction)
b3
Interrupt control register V2
b0
➁ Stop Timer Operation
Timer 4, timer 3 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
b3
Timer control register W1
b0
0 1 ✕ ✕
b3
Timer control register W3
b0
0✕ 0 1
b3
Timer control register W4
Prescaler stop (TW1A instruction)
Prescaler divided by 16 selected
Timer 3 stop (TW3A instruction)
Prescaler selected for count source
b0
0 ✕ 0 0 Timer 4 stop (TW4A instruction)
Timer 3 underflow signal selected for count source
➂ Set Timer Value
Timer 3 and timer 4 count times are set. (The formula is shown ❈A below.)
Timer 3 reload register R3
Timer 4 reload register R4
“5216”
“F916”
Timer count value 82 set (T3AB instruction)
Timer count value 249 set (T4AB instruction)
➃ Clear Interrupt Request
Timer 4 interrupt activated condition is cleared.
Timer 4 interrupt request flag T4F “0”
Timer 4 interrupt activated condition cleared
(SNZT4 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T4F, insert the NOP instruction after the SNZT4 instruction.
➄ Start Timer 4 Operation
Timer 4, timer 3 and prescaler temporarily stopped are restarted.
b3
b0
Timer control register W4 1 ✕ 0 0 Timer 4 operation start (TW4A instruction)
b3
b0
Timer control register W3 1 ✕ 0 1
b3
Timer 3 operation start (TW3A instruction)
b0
Timer control register W1 1 1 ✕ ✕ Prescaler operation start (TW1A instruction)
➅ Enable Interrupts
AAAAAA
AAAAAA
The timer 4 interrupt which is temporarily disabled is enabled.
b3
b0
Timer 4 interrupt occurrence enabled
Interrupt control register V2 ✕ ✕ 1 ✕
(TV2A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
Constant period interrupt execution start
❈A The prescaler dividing ratio, time 3 count value and timer 4 count value to make the interrupt occur
every 250 ms are set as follows.
–1
250 ms ≅ (4.0 MHz) ✕
3 ✕
16 ✕ (82+1) ✕ (249+1)
System clock Instruction Prescaler Timer 3 Timer 4
clock
dividing
count
count
ratio
value
value
“✕”: it can be “0” or “1.”
Fig. 2.2.8 Timer 4 constant period interrupt setting example
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2.2 Interrupts
2.2.4 Notes on use
(1)
Setting of INT0 interrupt valid waveform
Depending on the input state of P30 /INT0 pin, the external interrupt request flag (EXF0) may be set
to “1” when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register
I1, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one
instruction.
(2)
Setting of INT1 interrupt valid waveform
Depending on the input state of P31 /INT1 pin, the external interrupt request flag (EXF1) may be set
to “1” when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register
I2, and execute the SNZ1 instruction to clear the EXF1 flag to “0” after executing at least one
instruction.
(3)
Multiple interrupts
Multiple interrupts cannot be used in the 4513/4514 Group.
(4)
Notes on interrupt processing
When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt
disable state). In order to enable the interrupt at the same time when system returns from the
interrupt, write EI and RTI instructions continuously.
(5)
P30 /INT0 pin
The P3 0/INT0 pin need not be selected the external interrupt input INT function or the normal output
port P30 function. However, the EXF0 flag is set to “1” when a valid waveform is input to INT0 pin
even if it is used as an I/O port P3 0.
(6)
P31 /INT1 pin
The P3 1/INT1 pin need not be selected the external interrupt input INT function or the normal output
port P31 function. However, the EXF1 flag is set to “1” when a valid waveform is input to INT1 pin
even if it is used as an I/O port P3 1.
(7)
EPOF instruction
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
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2.3 Timers
2.3 Timers
The 4513/4514 Group has four 8-bit timers (each has a reload register) and a 16-bit fixed dividing frequency
timer which has the watchdog timer function.
This section describes individual types of timers, related registers, application examples using timers and
notes.
2.3.1 Timer functions
(1)
Timer 1
■ Timer operation
(Timer 1 has the timer 1 count start trigger function from P30/INT0 pin input)
(2)
Timer 2
■ Timer operation
(3)
Timer 3
■ Timer operation
(Timer 3 has the timer 3 count start trigger function from P31 /INT1 pin input)
(4)
Timer 4
■ Timer operation
(5)
16-bit timer
■ Timer 2 count source
(16-bit fixed dividing frequency)
■ Watchdog function
Watchdog timer provides a method to reset the system when a program runs incorrectly.
When the count value of timer WDT reaches “BFFF16 ” or “3FFF16 ,” the WDF1 flag is set to “1.”
If the WRST instruction is never executed while timer WDT counts 32767, WDF2 flag is set to “1”
to reset the microcomputer.
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2.3 Timers
2.3.2 Related registers
(1)
Interrupt control register V1
The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned
to bit 3.
Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 2.3.1 shows the interrupt control register V1.
Table 2.3.1 Interrupt control register V1
Interrupt control register V1
V1 3
Timer 2 interrupt enable bit
V1 2
Timer 1 interrupt enable bit
at reset : 0000 2
0
1
0
1
Interrupt
Interrupt
Interrupt
Interrupt
at RAM back-up : 0000 2
R/W
disabled (SNZT2 instruction is valid)
enabled (SNZT2 instruction is invalid)
disabled (SNZT1 instruction is valid)
enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
0
Interrupt enabled (SNZ1 instruction is invalid)
1
Interrupt disabled (SNZ0 instruction is valid)
0
V1 0
External 0 interrupt enable bit
Interrupt enabled (SNZ0 instruction is invalid)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When timer is used, V1 1 and V1 0 are not used.
V1 1
(2)
External 1 interrupt enable bit
Interrupt control register V2
The timer 3 interrupt enable bit is assigned to bit 0, and the timer 4 interrupt enable bit is assigned
to bit 1.
Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 2.3.2 shows the interrupt control register V2.
Table 2.3.2 Interrupt control register V2
Interrupt control register V2
V2 3
Serial I/O interrupt enable bit
V2 2
A-D interrupt enable bit
at reset : 0000 2
0
1
0
at RAM back-up : 0000 2
R/W
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
1
Interrupt disabled (SNZT4 instruction is valid)
0
V2 1
Timer 4 interrupt enable bit
Interrupt enabled (SNZT4 instruction is invalid)
1
Interrupt disabled (SNZT3 instruction is valid)
0
V2 0
Timer 3 interrupt enable bit
Interrupt enabled (SNZT3 instruction is invalid)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When timer is used, V2 2 and V2 3 are not used.
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2.3 Timers
(3) Timer control register W1
The timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is
assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler
control bit is assigned to bit 3.
Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction
can be used to transfer the contents of register W1 to register A.
Table 2.3.3 shows the timer control register W1.
Table 2.3.3 Timer control register W1
Timer control register W1
at reset : 0000 2
W13
Prescaler control bit
W12
Prescaler dividing ratio selection
bit
W11
Timer 1 control bit
W10
Timer 1 count synchronous circuit
control bit
at RAM back-up : 0000 2
0
1
0
1
Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
0
1
0
1
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
R/W
Note: “R” represents read enabled, and “W” represents write enabled.
(4)
Timer control register W2
The timer 2 count source selection bits are assigned to bits 0 and 1, and the timer 2 control bit is
assigned to bit 3.
Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction
can be used to transfer the contents of register W2 to register A.
Table 2.3.4 shows the timer control register W2.
Table 2.3.4 Timer control register W2
Timer control register W2
W23
Timer 2 control bit
at reset : 0000 2
0
at RAM back-up : state retained
R/W
Stop (state retained)
Operating
1
0
This bit has no function, but read/write is enabled.
W22 Not used
1
W21 W20
Count source
W21
0
0 Timer 1 underflow signal
Timer 2 count source selection
0
1 Prescaler output
bits
1
0 CNTR0 input
W20
1
1 16-bit timer (WDT) underflow signal
Note: “R” represents read enabled, and “W” represents write enabled.
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2.3 Timers
(5) Timer control register W3
The timer 3 count source selection bits are assigned to bits 0 and 1, the timer 3 count start synchronous
circuit control bit is assigned to bit 2 and the timer 3 control bit is assigned to bit 3.
Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction
can be used to transfer the contents of register W3 to register A.
Table 2.3.5 shows the timer control register W3.
Table 2.3.5 Timer control register W3
Timer control register W3
W33
at reset : 0000 2
0
1
Timer 3 control bit
at RAM back-up : state retained
R/W
Stop (state retained)
Operating
Count start synchronous circuit not selected
0
Count start synchronous circuit selected
1
W31 W30
Count source
W31
0
0 Timer 2 underflow signal
Timer 3 count source selection
0
1 Prescaler output
bits
1
0 Not available
W30
1
1 Not available
Note: “R” represents read enabled, and “W” represents write enabled.
W32
(6)
Timer 3 count start synchronous
circuit control bit
Timer control register W4
The timer 4 count source selection bits are assigned to bits 0 and 1, and the timer 4 control bit is
assigned to bit 3.
Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction
can be used to transfer the contents of register W4 to register A.
Table 2.3.6 shows the timer control register W4.
Table 2.3.6 Timer control register W4
Timer control register W4
W43
Timer 4 control bit
W42
Not used
W41
W40
at reset : 0000 2
0
1
0
1
W41 W40
0
0
Timer 4 count source selection
0
1
bits
1
0
1
1
at RAM back-up : state retained
R/W
Stop (state retained)
Operating
This bit has no function, but read/write is enabled.
Count source
Timer 3 underflow signal
Prescaler output
CNTR1 input
Not available
Note: “R” represents read enabled, and “W” represents write enabled.
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2.3 Timers
2.3.3 Timer application examples
(1)
Timer operation: measurement of constant period
The constant period by the setting timer count value can be measured.
Outline: The constant period by the timer 1 underflow signal can be measured.
Specifications: Timer 1 and prescaler divides the system clock frequency f(X IN) = 4.0 MHz, and the
timer 1 interrupt request occurs every 3 ms.
Figure 2.3.3 shows the setting example of the constant period measurement.
(2)
CNTR0 output operation: piezoelectric buzzer output
Outline: Square wave output from timer 1 can be used for piezoelectric buzzer output.
Specifications: 4 kHz square wave is output from the CNTR0 pin at system clock frequency f(XIN)
= 4.0 MHz. Also, timer 1 interrupt occurs simultaneously.
Figure 2.3.1 shows the peripheral circuit example, and Figure 2.3.4 shows the setting example of
CNTR0 output.
In order to reduce the current dissipation,
output is high-impedance state during buzzer
output stop.
4513/4514
125 µs125 µs
CNTR0
Set dividing ratio for timer 1 underflow cycle to 125 µs.
Fig. 2.3.1 Peripheral circuit example
(3)
CNTR0 input operation: event count
Outline: Count operation can be performed by using the signal (rising waveform) input from CNTR0
pin as the event.
Specifications: The low-frequency pulse from external as the timer 2 count source is input to CNTR0
pin, and the timer 2 interrupt request occurs every 100 counts.
Figure 2.3.5 shows the setting example of CNTR0 input.
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2.3 Timers
(4)
CNTR1 output control: square wave output control
Outline: The output/stop of square wave from timer 3 every timer 4 underflow can be controlled.
Specifications: 4 kHz square wave is output from timer 3 at system clock frequency f(XIN) = 4.0
MHz. Also, timer 4 controls ON/OFF of square wave every constant period.
Figure 2.3.6 shows the setting example of CNTR1 output.
(5)
Timer operation: timer start by external input
Outline: The constant period can be measured by external input.
Specifications: Timer 1 operates by INT0 input as a trigger and an interrupt occurs after 1 ms.
Figure 2.3.7 and Figure 2.3.8 show the setting example of timer start.
(6)
Watchdog timer
Watchdog timer provides a method to reset the system when a program run-away occurs.
In the 4513/4514 Group, bit 15 of 16-bit timer is counted twice for the watchdog timer.
Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at
a certain period which consists of timer 16-bit timers’ 32767 counts or less (execute WRST instruction
at a cycle of 32766 machine cycles or less).
Outline: Execute the WRST instruction in 16-bit timer’s 32767 counts at the normal operation. If a
program runs incorrectly, the WRST instruction is not executed and system reset occurs.
Specifications: System clock frequency f(XIN ) = 4.0 MHz is used, and program run-away is detected
by executing the WRST instruction in 24 ms.
Figure 2.3.2 shows the watchdog timer function, and Figure 2.3.9 shows the example of watchdog
timer.
FFFF16
BFFF16
3FFF16
Value of timer WDT
0000 16
WEF flag
WDF1 flag
WDF2 flag
RESET pin output
WRST
instruction
execution
WRST
instruction
execution
System reset
Fig. 2.3.2 Watchdog timer function
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2.3 Timers
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Timer 1 interrupt occurrence disabled
✕ 0 ✕ ✕ (TV1A instruction)
b3
Interrupt control register V1
b0
➁ Stop Timer Operation
Timer 1 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
b3
Timer control register W1
b0
Timer 1 stop (TW1A instruction)
0 1 0 ✕ Prescaler stop
Prescaler divided by 16 selected
➂ Set Timer Value
Timer 1 count time is set. (The formula is shown ❈A below.)
Timer 1 reload register R1 “F916”
Timer count value 249 set (T1AB instruction)
➃ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F “0” g0 h
Timer 1 interrupt activated condition cleared
(SNZT1 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
➄ Start Timer 1 Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3
b0
Timer control register W1 1 1 1 ✕ Timer 1 operation start (TW1A instruction)
Prescaler operation start
➅ Enable Interrupts
AAAAAA
AAAAAA
The timer 1 interrupt which is temporarily disabled is enabled.
b3
b0
Timer 1 interrupt occurrence enabled
Interrupt control register V1 ✕ 1 ✕ ✕
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
Constant period interrupt execution start
❈A The prescaler dividing ratio and timer 1 count value to make the interrupt occur
every 4 ms are set as follows.
–1
4 ms ≅ (4.0 MHz) ✕
3
✕
16 ✕
System clock Instruction Prescaler
clock
dividing
ratio
(249+1)
Timer 1
count
value
“✕”: it can be “0” or “1.”
Fig. 2.3.3 Constant period measurement setting example
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2.3 Timers
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
b3
Interrupt control register V1
b0
✕ 0 ✕✕
Timer 1 interrupt occurrence disabled
(TV1A instruction)
➁ Stop Timer Operation
Timer 1 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
b3
Timer control register W1
b0
Timer 1 stop (TW1A instruction)
0 0 0 ✕ Prescaler stop
Prescaler divided by 4 selected
➂ Set Timer Value, Select CNTR0 Output
CNTR0 output is selected.
Timer 1 count time is set.
b3
b0
Timer control register W6 ✕ ✕ 0 1 CNTR0 output selected (TW6A instruction)
Timer 1 reload register R1 “2916”
Timer count value 41 set (T1AB instruction)
➃ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F “0”g0 h
Timer 1 interrupt activated condition cleared
(SNZT1 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
➄ Start Timer 1 Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3
b0
Timer control register W1 1 0 1 ✕ Timer 1 operation start (TW1A instruction)
Prescaler operation start
➅ Enable Interrupts
AAAAAA
AAAAAA
AAAAAAA
AAAAAAA
The timer 1 interrupt which is temporarily disabled is enabled.
b3
b0
Timer 1 interrupt occurrence enabled
Interrupt control register V1 ✕ 1 ✕ ✕ (TV1A instruction)
All interrupts enabled (EI instruction)
Interrupt enable flag INTE “1”
➆ Stop CNTR0 Output
D6/CNTR0 pin is set to CNTR0 input pin, and it is set to the high-impedance state.
Timer control register W6
b3
b0
✕ ✕ 0 0 CNTR0 input pin set (TW6A instruction)
Output latch of port D6 is set to “1.”
(SD instruction)
“✕”: it can be “0” or “1.”
Fig. 2.3.4 CNTR0 output setting example
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2.3 Timers
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
b3
Interrupt control register V1
b0
0 ✕ ✕ ✕ Timer 2 interrupt occurrence disabled
(TV1A instruction)
➁ Stop Timer Operation
Timer 1 operation is temporarily stopped.
Timer 2 count source is selected.
b3
Timer control register W2
b0
0✕ 1 0
Timer 2 stop (TW2A instruction)
CNTR0 input selected for count source
➂ Set Timer Value
Timer 2 count time is set.
Timer 2 reload register R2 “6316”
Timer count value 99 set (T2AB instruction)
➃ Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F “0”g0 h
Timer 2 interrupt activated condition cleared
(SNZT2 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
➄ Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
b3
b0
Timer control register W2 1 ✕ 1 0 Timer 2 operation start (TW2A instruction)
AAAAAAA
AAAAAAA
➅ Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
b3
b0
Timer 2 interrupt occurrence enabled
Interrupt control register V1 1 ✕ ✕ ✕
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
“✕”: it can be “0” or “1.”
Fig. 2.3.5 CNTR1 input setting example
However, specify the pulse width input to CNTR0 pin/CNTR1 pin. Refer to section “2.3.4 Notes on use” for
the timer external input period condition.
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APPLICATION
2.3 Timers
➀ Disable Interrupts
Timer 3 and timer 4 interrupt are temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Timer 3 and timer 4 interrupt occurrence disabled
✕ ✕ 0 0 (TV2A instruction)
b3
Interrupt control register V2
b0
➁ Stop Timer Operation
Timer is temporarily stopped.
Dividing ratio of prescaler is selected.
Timer 3 count source is selected.
Timer 4 count source is selected.
b3
b0
Timer 3 stop (TW3A instruction)
Timer control register W3 0 ✕ 0 1 Prescaler selected for count source
b3
Timer control register W4
b0
Timer 4 stop (TW4A instruction)
0 ✕ 0 0
Timer 3 underflow selected for count source
b3
b0
Instruction clock divided by 4 selected
Timer control register W1 1 0 ✕ ✕
(TW1A instruction)
➂ Set Timer Value, Select CNTR1 Output
CNTR1 output is selected.
Timer 3 and timer 4 count time are set.b3
b0
Timer control register W6 1 1 ✕ ✕ CNTR1 output selected (TW6A instruction)
Timer 3 reload register R3 “2916”
Timer 3 reload register R4 “FF16”
Timer count value 41 set (T3AB instruction)
Timer count value 255 set (T4AB instruction)
➃ Start Timer Operation
Timer 3 and timer 4 temporarily stopped are restarted.
b3
b0
Timer control register W3 1 ✕ 0 1 Timer 3 operation start (TW3A instruction)
b3
b0
Timer control register W4 1 ✕ 0 0
AAAAAA
Timer 4 operation start (TW4A instruction)
➄ Enable Interrupts
Interrupt enable flag INTE
“1”
All interrupts enabled (EI instruction)
“✕”: it can be “0” or “1.”
Fig. 2.3.6 CNTR0 output control setting example
4513/4514 Group User’s Manual
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APPLICATION
2.3 Timers
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
b3
Interrupt control register V1
All interrupts disabled (DI instruction)
b0
✕ 0 ✕ 0 Timer 1 interrupt occurrence disabled
(TV1A instruction)
INT0 interrupt occurrence disabled
➁ Stop Timer Operation
Timer 1 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
b3
Timer control register W1
b0
Timer 1 stop (TW1A instruction)
0 0 0 ✕
Prescaler stop
Prescaler divided by 4 selected
➂ Set Timer Value
Timer 1 count time is set.
Timer count value 82 set (T1AB instruction)
Timer 1 reload register R1 “5216”
➃ Set Port
P30/INT0 pin is set to INT0 input.
b3
b0
Port P30 output latch ✕ ✕ ✕ 1
INT0 input set (OP3A instruction)
➄ Set Valid Waveform
Valid waveform of INT0 pin is selected. Timer 1 control is enabled.
b3
b0
Interrupt control register I1 ✕ 1 0 1
Rising edge detected (TI1A instruction)
➅ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
INT0 interrupt activated condition is cleared.g0 h
Timer 1 interrupt request flag T1F “0”
INT0 interrupt request flag EXF0 “0”
Timer 1 interrupt activated condition cleared
(SNZT1 instruction)
INT0 interrupt activated condition cleared
(SNZ0 instruction)
Note when the interrupt request is cleared
When ➅ is executed, considering the skip of the next instruction according to the
interrupt request flags T1F and EXF0, insert the NOP instruction after the SNZT1
and SNZ0 instructions.
AAAAAA
AAAAAA
➆ Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled.
b3
b0
Timer 1 interrupt occurrence enabled
Interrupt control register V1 ✕ 1 ✕ ✕
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
Timer start by external input
“✕”: it can be “0” or “1.”
Fig. 2.3.7 Timer start by external input setting example (1)
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APPLICATION
2.3 Timers
Processing in interrupt service routine
➇ Stop Timer
Timer 1 control disabled
b3
Interrupt control register I1
➈ Reset Timer
(TI1A instruction)
(TI1A instruction)
Timer count value 82 set (T1AB instruction)
Timer 1 reload register R1 “5216”
b3
Timer 1 control enabled
b0
✕ 1 0 0
Interrupt control register I1
b0
✕ 1 0 1
“✕”: it can be “0” or “1.”
Fig. 2.3.8 Timer start by external input setting example (2)
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APPLICATION
2.3 Timers
➀ Activate Watchdog Timer
Watchdog timer is activated.
Watchdog timer enable flag WEF “1”
Watchdog timer enable flag WEF set
(WRST instruction)
Main routine (every 20 ms)
Reset Flag WDF
Watchdog timer flag WDF1 is reset.
“0”
g0 h
Watchdog timer flag WDF1 cleared
(WRST instruction)
Main routine execution
Repeat
Do not clear watchdog timer WDF flag in interrupt service routine.
Interrupt may be executed even if program run-away occurs.
When going to RAM back-up mode
•
•
••
•
•
WRST
; WDF flag cleared
EPOF
; POF instruction enabled
POF
↓
Oscillation stop (RAM back-up mode)
In the RAM back-up mode, WEF, WDF1 and WDF2 flags are initialized. However, when WDF2 flag is set to “1”, at the
same time, system enters RAM back-up mode, microcomputer may be reset. When watchdog timer and RAM back-up
mode are used, execute the WRST instruction before system enters the RAM back-up mode to initialize WDF flag.
“✕”: it can be “0” or “1.”
Fig. 2.3.9 Watchdog timer setting example
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APPLICATION
2.3 Timers
2.3.4 Notes on use
(1)
Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
(2)
Count source
Stop timer 1, 2, 3, or 4 counting to change its count source.
(3)
Reading the count values
Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to
read its data.
(4)
Writing to reload registers R1, R3
When writing data to reload registers R1, R3 while timer 1 and 3 are operating, avoid a timing when
timers 1 and 3 underflow.
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APPLICATION
2.4 Serial I/O
2.4 Serial I/O
The 4513/4514 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit
data.
This section describes serial I/O functions, related registers, application examples using serial I/O and
notes.
2.4.1 Carrier functions
Serial I/O consists of the serial I/O register SI, serial I/O mode register J1, serial I/O transmit/receive
completion flag SIOF and serial I/O counter.
A clock-synchronous serial I/O uses the shift clock generated by the clock control circuit as a synchronous
clock. Accordingly, the data transmit and receive operations are synchronized with this shift clock.
In transmit operation, data is transmitted bit by bit from the S OUT pin synchronously with the falling edges
of the shift clock.
In receive operation, data is received bit by bit from the S IN pin synchronously with the rising edges of the
shift clock.
Note: 4513/4514 Group only supports LSB-first transmission and reception.
■
Shift clock
When using the internal clock of 4513/4514 Group as a synchronous clock, eight shift clock pulses
are output from the SCK pin when a transfer operation is started. Also, when using some external
clock as a synchronous clock, the clock that is input from the SCK pin is used as the shift clock.
■
Data transfer rate (baudrate)
When using the internal clock, the data transfer rate can be determined by selecting the instruction
clock divided by 4 or 8.
When using an external clock, the clock frequency input to the SCK pin determines the data transfer
rate.
Figure 2.4.1 shows the serial I/O block diagram.
Division circuit
(divided by 2)
MR3
Internal clock
generation circuit
(divided by 3)
1
XIN
0
Instruction clock
J12
1/4
1/8
P20/SCK
Serial I/O mode register J1
1
J13
SOUT
P22/SIN
SIN
J11
J10
0
Synchronous
circuit
SCK
P21/SOUT
J12
MSB
Serial I/O counter (3)
Serial I/O register SI (8)
TSIAB
J11
J10
Register B (4)
LSB
TABSI
Register A (4)
Note: The output structure of SCK and SOUT pins is N-channel open-drain.
Fig. 2.4.1 Serial I/O block diagram
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SIOF
Serial I/O interrupt
APPLICATION
2.4 Serial I/O
2.4.2 Related registers
(1)
Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to
register SI through registers A and B with the TSIAB instruction.
(2)
Serial I/O mode register J1
Serial I/O synchronous clock selection bit is assigned to bit 0, serial I/O port selection bit is assigned
to bit 1 and serial I/O internal clock dividing ratio selection bit is assigned to bit 2.
Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction
can be used to transfer the contents of register J1 to register A.
Table 2.4.1 shows the serial I/O mode register J1.
Table 2.4.1 Serial I/O mode register J1
Serial I/O mode register J1
at reset : 0000 2
0
1
J13
Not used
J12
Serial I/O internal clock dividing
ratio selection bit
J11
Serial I/O port selection bit
0
1
0
1
0
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
Instruction clock signal divided by 8
Instruction clock signal divided by 4
Input ports P20, P2 1, P2 2 selected
Serial I/O ports SCK, S OUT, SIN/input ports P20 , P21, P22 selected
External clock
Serial I/O synchronous clock
Internal clock (instruction clock divided by 4 or 8)
selection bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
J10
(3)
Serial I/O transmission/reception completion flag (SIOF)
Serial I/O transmission/reception completion flag (SIOF) is set to “1” when serial data transmission
or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI).
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APPLICATION
2.4 Serial I/O
2.4.3 Operation description
Figure 2.4.2 shows the serial I/O connection example, Figure 2.4.3 shows the serial I/O register state, and
Figure 2.4.4 shows the serial I/O transfer timing.
Master (internal clock selected)
Slave (external clock selected)
4513/4514
4513/4514
Control signal
D5
D5
SCK
SCK
SOUT
SIN
SIN
SOUT
Note: The control signal is used to inform the master by the pin level
that the slave is in a ready state to receive.
The 4513/4514 Group does not have a control pin exclusively
used for serial I/O.
Accordingly, if a control signal is required, use the normal input/output ports.
Fig. 2.4.2 Serial I/O connection example
Slave (S7–S0: Transfer data)
Master (M7–M0: Transfer data)
Serial I/O register (SI)
M7 M6 M5 M4 M3 M2 M1 M0
M7 M6 M5 M4 M3 M2 M1 M0
SIN pin
SOUT pin
SOUT pin
SIN pin
Transfer data setting
Serial I/O register (SI)
S7 S6 S5 S4 S3 S2 S1 S0
S7 S6 S5 S4 S3 S2 S1 S0
Transfer starts
∗
M7 M6 M5 M4 M3 M2 M1
Falling of clock
∗
S0 M7 M6 M5 M4 M3 M2 M1
Rising of clock
M0 S7 S6 S5 S4 S3 S2 S1
∗
Falling of clock
∗
S0 M7 M6 M5 M4 M3 M2
S7 S6 S5 S4 S3 S2 S1 S0
Transfer completes
M0 S7 S6 S5 S4 S3 S2
M7 M6 M5 M4 M3 M2 M1 M0
Fig. 2.4.3 Serial I/O register state when transmitting/receiving
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S7 S6 S5 S4 S3 S2 S1
4513/4514 Group User’s Manual
APPLICATION
2.4 Serial I/O
Master
SOUT
M7’
S7 ’
SIN
M2
M1
M0
S0
S1
M3
S2
M4
S3
M5
S4
M6
S5
M7
S6
S7
SST instruction
SCK
Slave
SST instruction
Control signal
SOUT
SIN
S0
S7’
M7’
S2
S1
M0
M1
S3
M2
S4
M3
S5
M4
S6
M5
S7
M6
M7
M0–M7: the contents of master serial I/O register
S0–S7: the contents of slave serial I/O register
Rising of SCK: serial input
Falling of SCK: serial output
M0’–M7’: previous MSB contents of master and slave
Fig. 2.4.4 Serial I/O transfer timing
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APPLICATION
2.4 Serial I/O
The full duplex communication of master and slave is described using the connection example shown in
Figure 2.4.2.
(1)
Transmit/receive operation of master
➀ The transmit data is written into the serial I/O register SI with the TSIAB instruction. When the
TSIAB instruction is executed, the contents of register A are transferred to the low-order 4 bits of
register SI and the contents of register B are transferred to the high-order 4 bits of register SI.
➁ Whether the microcomputer on the receiving side is ready to receive or not is checked. In the
connection example in Figure 2.4.2, check that the input level of control signal is “L” level.
➂ Serial transfer is started with the SST instruction.
When the SST instruction is executed, the serial I/O transmit/receive completion flag (SIOF) is
cleared to “0.”
➃ The transmit data is output from the SOUT pin synchronously with the falling edges of the shift
clock.
➄ The transmit data is output bit by bit beginning with the LSB bit of register SI. Each time one bit
is output, the contents of register SI is shifted one bit position toward the LSB.
➅ Also, the receive data is input from the S IN pin synchronously with the rising edges of the shift
clock.
➆ The receive data is input bit by bit to the MSB bit of register SI.
➇ A serial I/O interrupt request occurs when the transfer of transmit data and receive data is
completed, and the SIOF flag is set to “1.”
➈ The receive data is taken in within the serial I/O interrupt service routine; or the data is taken in
after examining the completion of the transmit/receive operation with the SNZSI instruction without
using an interrupt.
Also, the SIOF flag is cleared to “0” when an interrupt occurs or the SNZSI instruction is executed.
Notes 1: Repeat steps ➀ through ➈ to transmit or receive multiple data in succession.
2: For the program on the master side, make sure that transmission is not started before the
control signal is released back “H” after a transmit operation is started first.
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APPLICATION
2.4 Serial I/O
(2)
Transmit/receive operation of slave
➀ The transmit data is written into the serial I/O register SI with the TSIAB instruction. When the
TSIAB instruction is executed, the contents of register A are transferred to the low-order bits of
register SI and the contents of register B are transferred to the high-order bits of register SI. At
this time, the SCK pin must be at the “H” level.
➁ Serial transfer is started with the SST instruction. However, in Figure 2.4.2 where an external
clock is selected, transfer is not started until the clock is input. When the SST instruction is
executed, the serial I/O transmit/receive completion flag (SIOF) is cleared to “0.”
➂ The microcomputer on the transmitting side is informed that the receiving side is ready to receive.
In the connection example in Figure 2.4.2, this notification is done by pulling the control signal “L”
level.
➃ The transmit data is output from the S OUT pin synchronously with the falling edges of the shift
clock.
➄ The transmit data is output bit by bit beginning with the LSB bit of register SI. Each time one bit
is output, the contents of register SI are shifted to one bit position toward the LSB.
➅ Also, the receive data is input from the SIN pin synchronously with the rising edges of the shift
clock.
➆ The receive data is input bit by bit to the MSB bit of register SI.
➇ A serial I/O interrupt request occurs when the transmit/receive of data is completed, and the SIOF
flag is set to “1.”
➈ The receive data is taken in within the serial I/O interrupt service routine; or the data is taken in
after examining the completion of the transmit/receive operation with the SNZSI instruction without
using an interrupt.
Also, the SIOF flag is cleared to “0” when an interrupt occurs or the SNZSI instruction is executed.
Make sure that the control signal pin level is “H” after the receive operation is completed.
Note: Repeat steps ➀ through ➈ to transmit or receive multiple data in succession.
2.4.4 Serial I/O application example
(1)
Serial I/O
Outline: The 4513/4514 Group can communicate with peripheral ICs.
Specifications: Figure 2.4.2 Serial I/O connection example.
Figure 2.4.5 shows the master serial I/O setting example, and Figure 2.4.6 shows the slave serial
I/O setting example.
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APPLICATION
2.4 Serial I/O
➀ Disable Interrupts
Serial I/O interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
b3
Interrupt control register V2
All interrupts disabled (DI instruction)
b0
0✕ ✕✕
Serial I/O interrupt occurrence disabled
(TV2A instruction)
➁ Set Serial I/O
b3
b0 Internal clock selected (TJ1A instruction)
Serial I/O mode register J1 ✕ 1 1 1 Serial I/O port selected
Dividing ratio = 4 selected
➂ Clear Interrupt Request
Serial I/O interrupt activated condition is cleared.
Serial I/O transmit/receive “0”g0 h
completion flag SIOF
Serial I/O interrupt activated condition cleared
(SNZSI instruction)
Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction according to the
SIOF flag, insert the NOP instruction after the SNZSI instruction.
When interrupt is
not used
When interrupt is used
➃ Set Interrupt
➃ Set Interrupt
Interrupts except serial I/O is enabled
(EI instruction)
Serial I/O interrupt temporarily disabled is enabled.
b3
b0
Serial I/O interrupt occurrence
Interrupt control register V2 1 ✕ ✕ ✕
enabled (TV2A instruction)
Interrupt enable flag INTE
“1”
All interrupts enabled
(EI instruction)
➄ Start Condition of Serial I/O operation
Slave side is enabled to receive is checked.
Pin level of control signal = “L”
➅ Start Serial I/O Operation
Serial transfer is started (SST instruction) after checking
slave side is enabled to receive.
g0 h
➆ Check Serial I/O Interrupt Request
➆ Serial I/O Interrupt Occur
SIOF flag is checked (SNZSI instruction).
➇ Execute Receive Data
Data received by serial transfer is executed.
Register SI → register A, register B (TABSI instruction)
When serial communication is executed, ➄ to ➇ are repeated.
“✕”: it can be “0” or “1.”
Fig. 2.4.5 Master serial I/O setting example
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APPLICATION
2.4 Serial I/O
➀ Disable Interrupts
Serial I/O interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Serial I/O interrupt occurrence disabled
0✕ ✕✕
(TV2A instruction)
b3
Interrupt control register V2
b0
➁ Set Serial I/O
b3
b0
Exernal clock selected (TJ1A instruction)
Serial I/O mode register J1 ✕ ✕ 1 0
Serial I/O port selected
➂ Clear Interrupt Request
Serial I/O interrupt activated condition is cleared.
Serial I/O transmit/receive “0”g0 h
completion flag SIOF
Serial I/O interrupt activated condition cleared
(SNZSI instruction)
Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction according to the
SIOF flag, insert the NOP instruction after the SNZSI instruction.
When interrupt is
not used
When interrupt is used
➃ Set Interrupt
➃ Set Interrupt
Interrupts except serial I/O is enabled
(EI instruction)
Serial I/O interrupt temporarily disabled is enabled.
b3
b0
Serial I/O interrupt occurrence
Interrupt control register V2 1 ✕ ✕ ✕
enabled (TV2A instruction)
Interrupt enable flag INTE
“1”
All interrupts enabled
(EI instruction)
➄ Set When Transmit/Receive Operation Start Enabled
Serial transfer start state (SST instruction)
System enters to control signal transmission enabled state (“L” level)
However, SCK pin initial level = “H” level
➅ Start Serial I/O Operation
Serial transfer starts by clock of master side
➆ Check Serial I/O Interrupt Request
➆ Serial I/O Interrupt Occur
SIOF flag is checked (SNZSI instruction).
➇ Receive Data Processing
System enters to control signal transmission disabled state (“H” level)
Data processing received by serial transfer is executed.
Register SI → register A, register B (TABSI instruction)
When serial communication is executed, ➄ to ➇ are repeated.
“✕”: it can be “0” or “1.”
Fig. 2.4.6 Slave serial I/O example
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APPLICATION
2.4 Serial I/O
2.4.5 Notes on use
(1) Note when an external clock is used as a synchronous clock:
• An external clock is selected as the synchronous clock, the clock is not controlled internally.
• Serial transfer is continued as long as an external clock is input. If an external clock is input 9 times
or more and serial transfer is continued, the receive data is transferred directly as transmit data,
so that be sure to control the clock externally.
Note also that the SIOF flag is set when a clock is counted 8 times.
• Make sure that the initial input level on the external clock pin is always “H” level.
• Table 2.4.2 shows the recommended operating conditions when using serial I/O with an external
clock. Figure 2.4.7 shows an input waveform of external clock.
Table 2.4.2 Recommended operating conditions (serial I/O)
Condition
Parameter
V DD = 4.0 V to 5.5 V
Middle-speed mode V DD = 2.5 V to 5.5 V
Limits
Unit
Min. Typ. Max.
1.5
3.0
µs
Serial I/O external clock period
VDD = 2.0 V to 5.5 V (Note 2)
4.0
(Note 1)
V DD = 4.0 V to 5.5 V
750
ns
V DD = 2.5 V to 5.5 V
1.5
µs
High-speed mode
VDD = 2.0 V to 5.5 V (Note 2)
Notes 1: Limits shown in Table 2.4.2 represent the pulse widths of “H” and “L.”
2: It is effective only for mask version.
2.0
External clock
input waveform
“L” pulse width “H” pulse width
Note: Set “H” and “L” pulse width for external waveform according to using
supply voltage and recommended operating conditions.
Fig. 2.4.7 Input waveform of external clock
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APPLICATION
2.5 A-D converter
2.5 A-D converter
The 4513/4514 Group has an A-D converter with the 10-bit successive comparison method: 4 channels for
the 4513 Group, 8 channels for the 4514 Group.
This A-D converter can also be used as a comparator to compare analog voltages input from the analog
input pin with preset values.
This section describes the related registers, application examples using the A-D converter and notes.
Figure 2.5.1 shows the A-D converter block diagram.
Register B (4)
Register A (4)
4
TAQ2
TQ2A
IAP4
(P40—P43)
Q23 Q22 Q21 Q20
4
4
TAQ1
TQ1A
Q13 Q12 Q11 Q10
4
2
8
TALA
TABAD
8
TADAB
Instruction clock
OP4A
(P40—P43)
1/6
3
Q23
AIN1/CMP0+
AIN2/CMP1AIN3/CMP1+
P40/AIN4
P41/AIN5
P42/AIN6
P43/AIN7
8-channel multi-plexed analog switch
0
(Note 3)
AIN0/CMP0-
ADF
(1)
A-D control circuit
1
A-D interrupt
1
Successive comparison
register (AD) (10)
Comparator
0
Q23
Q23
10
DAC
operation
signal
0
8
10
0
1
1
1
Q23
8
8
DA converter
(Note 1)
8
VDD
VSS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q23=1).
The value of the comparator register is retained even when the mode is switched to the A-D conversion
mode (Q23=0) because it is separated from the successive comparison register (AD). Also, the resolution in
the comparator mode is 8 bits because the comparator register consists of 8 bits.
3: The 4513 Group does not have ports P40/AIN4–P43/AIN7 and the IAP4 and OP4A instructions.
Fig. 2.5.1 A-D converter structure
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APPLICATION
2.5 A-D converter
2.5.1 Related registers
(1)
A-D control register Q1
Analog input pin selection bits are assigned to register Q1.
Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction
can be used to transfer the contents of register Q1 to register A.
Table 2.5.1 shows the A-D control register Q1.
Table 2.5.1 A-D control register Q1
A-D control register Q1
Q1 3
Q1 2
Q1 1
Q1 0
Notes
(2)
at reset : 0000 2
0
1
Not used
at power down : state retained
R/W
This bit has no function, but read/write is enabled.
Q12 Q11 Q10
Selected pin
0
0
0 A IN0
0
0
1 A IN1
0
1
0 A IN2
Analog input pin selection bits
0
1
1 A IN3
(Note 2)
1
0
0 A IN4 (Not available for 4513 Group)
1
0
1 A IN5 (Not available for 4513 Group)
1
1
0 A IN6 (Not available for 4513 Group)
1
1
1 A IN7 (Not available for 4513 Group)
1: “R” represents read enabled, and “W” represents write enabled.
2: Select AIN4–A IN7 with register Q1 after setting register Q2.
A-D control register Q2
Analog input pin selection bits and A-D operation mode control bit are assigned to register Q2.
Set the contents of this register through register A with the TQ2A instruction. The TAQ2 instruction
can be used to transfer the contents of register Q2 to register A.
Table 2.5.2 shows the A-D control register Q2.
Table 2.5.2 A-D control register Q2
A-D control register Q2
at reset : 0000 2
Q23
A-D operation mode control bit
Q22
P4 3 /AIN7 , P42 /AIN6 pin function
selection bit (Note 3)
0
1
0
1
at power down : state retained
A-D conversion mode
Comparator mode
P4 3, P4 2 (I/O) (Note 4)
A IN7, A IN6/P4 3 , P42 (Output) (Note 4)
P41/AIN5 pin function selection bit
P4 1 (I/O) (Note 4)
0
(Note 3)
A IN5 /P41 (Output) (Note 4)
1
P40/AIN4 pin function selection bit
P4 0 (I/O) (Note 4)
0
Q20
(Note 3)
A IN4 /P40 (Output) (Note 4)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select AIN4–A IN7 with register Q1 after setting register Q2.
3: In the 4513 Group, these bits are not used.
4: In the 4513 Group, only read/write of these bits is enabled.
Q21
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APPLICATION
2.5 A-D converter
2.5.2 A-D converter application examples
(1)
A-D conversion mode
Outline: Analog input signal from a sensor can be converted into digital values.
Specifications: Analog voltage values from a sensor is converted into digital values by using a 10bit successive comparison method. Use the AIN0 pin for this analog input.
Figure 2.5.2 shows the A-D conversion mode setting example.
➀ Disable Interrupts
A-D interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
A-D interrupt occurrence disabled
✕ 0 ✕✕
(TV2A instruction)
b3
Interrupt control register V2
b0
➁ Set A-D Converter
A-D conversion mode is selected to A-D operation mode.
Analog input pin AIN0 is selected.
b3
b0
A-D control register Q2 0 ✕ ✕ ✕ A-D conversion mode selected (TQ2A instruction)
b3
b0
A-D control register Q1 ✕ 0 0 0 AIN0 selected (TQ1A instruction)
➂ Clear Interrupt Request
A-D interrupt activated condition is cleared.
A-D conversion completion flag ADF “0”
A-D conversion interrupt activated condition cleared
(SNZAD instruction)
Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction according to the
flag ADF, insert the NOP instruction after the SNZAD instruction.
When interrupt is
not used
When interrupt is used
➃ Set Interrupt
➃ Set Interrupt
Interrupts except A-D conversion is
enabled (EI instruction)
A-D conversion interrupt temporarily disabled is enabled.
b3
b0
Interrupt control register V2 ✕ 1 ✕ ✕ A-D interrupt occurrence enabled
(TV2A instruction)
Interrupt enable flag INTE
“1”
All interrupts enabled
(EI instruction)
➄ Start A-D Conversion
A-D conversion operation is started (ADST instruction).
When interrupt is not used
When interrupt is used
➅ Check A-D Interrupt Request
➅ A-D Conversion Interrupt Occur
A-D conversion completion flag is
checked (SNZAD instruciton)
➆ Execute A-D Conversion
High-order 8 bits of register AD → register A and register B (TABAD instruction)
Low-order 2 bits of register AD → high-order 2 bits of register A (TALA instruction)
“0” is set to low-order 2 bits of register A
When A-D conversion is executed by the same channel, ➄ to ➆ is repeated.
When A-D conversion is executed by the another channel, ➀ to ➆ is repeated.
“✕”: it can be “0” or “1.”
Fig. 2.5.2 A-D conversion mode setting example
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APPLICATION
2.5 A-D converter
2.5.3 Notes on use
(1)
Note when the A-D conversion starts again
When the A-D conversion starts again with the ADST instruction during A-D conversion, the previous
input data is invalidated and the A-D conversion starts again.
(2)
A-D control register Q2
Select A IN4–A IN7 with register Q1 after setting register Q2.
(3)
A-D converter-1
Each analog input pin is equipped with a capacitor which is used to compare the analog voltage.
Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A-D accuracy may not be obtained. Therefore, reduce
the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins.
Figure 2.5.3 shows the analog input external circuit example-1.
When the overvoltage applied to the A-D conversion circuit may occur, connect an external circuit
in order to keep the voltage within the rated range as shown the Figure 2.5.4. In addition, test the
application products sufficiently.
Sensor
AINi
(Note)
About 1 kΩ
Sensor
AINi
(Note)
Note: i = 0 to 7
Note: Apply the voltage within the specifications
to an analog input pin. (i = 0 to 7)
Fig. 2.5.4 Analog input external circuit example-2
Fig. 2.5.3 Analog input external circuit example-1
(4)
Notes for the use of A-D conversion 2
When the operating mode of the A-D converter is changed from the comparator mode to the A-D
conversion mode with bit 3 of register Q2 in a program, be careful about the following notes.
• Clear bit 2 of register V2 to “0” to change the operating mode of the A-D converter from the
comparator mode to the A-D conversion mode with bit 3 of register Q2 (refer to Figure 2.5.5➀).
• The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D
converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a
value to register Q2, and execute the SNZAD instruction to clear the ADF flag.
Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D
converter with bit 3 of register Q2 during operating the A-D converter.
••
•
Clear bit 2 of register V2 to “0”.......➀
↓
Change of the operating mode of the A-D converter
from the comparator mode to the A-D conversion mode
↓
Clear the ADF flag to “0” with the SNZAD instruction
↓
Execute the NOP instruction for the case when a skip is
performed with the SNZAD instruction
••
•
Fig. 2.5.5 A-D converter operating mode program example
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2.5 A-D converter
(5)
A-D converter is used at the comparator mode
The analog input voltage is higher than the comparison voltage as a result of comparison, the
contents of ADF flag retains “0,” not set to “1.”
In this case, the A-D interrupt does not occur even when the usage of the A-D interrupt is enabled.
Accordingly, consider the time until the comparator operation is completed, and examine the state
of ADF flag by software. The comparator operation is completed after 8 machine cycles.
(6)
Analog input pins
Even when P40/A IN4–P43/A IN7 are set to pins for analog input, they continue to function as P40–P43
I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins,
make sure to set the outputs of pins that are set for analog input to “1.” Also, the port input function
of the pin functions as an analog input is undefined.
(7)
TALA instruction
When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is “0.”
(8)
Recommended operating conditions when using A-D converter
The recommended operating conditions of supply voltage and system clock frequency when using AD converter are different from those when not using A-D converter.
Table 2.5.3 shows the recommended operating conditions when using A-D converter.
Table 2.5.3 Recommended operating conditions (when using A-D converter)
Parameter
V DD
System clock frequency
V DD
(at ceramic resonance)
V DD
V DD
System clock frequency
V DD
(at external clock input)
V DD
Condition
= 4.5 V to 5.5 V (high-speed mode)
= 4.0 V to 5.5 V (high-speed mode)
=
=
=
=
2.7
4.5
4.0
2.7
V
V
V
V
to
to
to
to
5.5
5.5
5.5
5.5
V
V
V
V
Limits
Min. Typ.
0.4
0.4
0.4
(middle-speed mode)
0.4
(high-speed mode)
Duty
0.4
(high-speed mode)
40 % to 60 %
0.4
(middle-speed mode)
4513/4514 Group User’s Manual
Max.
4.2
2.0
4.2
3.0
1.0
3.0
Unit
MHz
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APPLICATION
2.6 Voltage comparator
2.6 Voltage comparator
The 4513/4514 Group has two voltage comparators; CMP0-, CMP0+, CMP1-, CMP1+.
This section describes the voltage comparator function, related registers, and notes.
2.6.1 Voltage comparator function
(1)
CMP0
■ Voltage comparison
The voltage of CMP0- is compared with that of CMP0+, and the result is stored into bit 0 of the
voltage comparator control register Q3.
(2)
CMP1
■ Voltage comparison
The voltage of CMP1- is compared with that of CMP1+, and the result is stored into bit 1 of the
voltage comparator control register Q3.
2.6.2 Related registers
(1)
Voltage comparator control register Q3
The voltage comparator (CMP1) control bit is assigned to bit 3, the voltage comparator (CMP0)
control bit is assigned to bit 2, the CMP1 comparison result store bit is assigned to bit 1 and the
CMP0 comparison result store bit is assigned to bit 0.
Set the contents of this register through register A with the TQ3A instruction. The TAQ3 instruction
can be used to transfer the contents of register Q3 to register A.
Table 2.6.1 shows the voltage comparator control register Q3.
Table 2.6.1 Voltage comparator control register Q3
Voltage comparator control register Q3
at reset : 0000 2
at RAM back-up : state retained
(Note 2)
Voltage comparator (CMP1) invalid
0
Voltage comparator (CMP1)
Q3 3
Voltage comparator (CMP1) valid
1
control bit
Voltage comparator (CMP0) invalid
0
Voltage comparator (CMP0)
Q3 2
Voltage comparator (CMP0) valid
control bit
1
CMP1- > CMP1+
0
Q3 1
CMP1 comparison result store bit
CMP1- < CMP1+
1
CMP0- > CMP0+
0
Q3 0
CMP0 comparison reslut store bit
CMP0- < CMP0+
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Bits 0 and 1 of register Q3 can be only read.
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2.6 Voltage comparator
2.6.3 Notes on use
●
Voltage comparator function
When the voltage comparator function is valid with the voltage comparator control register Q3, it is
operating even in the RAM back-up mode. Accordingly, be careful about such state because it
causes the increase of the operation current in the RAM back-up mode.
In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register
Q3 = “0”) the voltage comparator function by software before the POF instruction is executed.
Also, while the voltage comparator function is valid, current is always consumed by voltage comparator.
On the system required for the low-power dissipation, invalidate the voltage comparator when it is
unused by software.
●
Register Q3
Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written.
●
Reading the comparison result of voltage comparator
Read the voltage comparator comparison result from register Q3 after the voltage comparator response
time (max. 20 µs) is passed from the voltage comparator function become valid.
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APPLICATION
2.7 Reset
2.7 Reset
System reset is performed by applying “L” level to the RESET pin for 1 machine cycle or more when the
following conditions are satisfied:
● the value of supply voltage is the minimum value or more of the recommended operating conditions
● oscillation is stabilized.
Then when “H” level is applied to RESET pin, the software starts from address 0 in page 0 after elapsing
of the internal oscillation stabilizing time (f(XIN ) is counted for 16892 to 16895 machine cycles). Figure 2.7.2
shows the oscillation stabilizing time.
2.7.1 Reset circuit
The 4513/4514 Group has the power-on reset circuit and voltage drop detection circuit.
(1)
Power-on reset
Reset can be performed automatically at power on (power-on reset) by connecting resistors, a diode,
and a capacitor to RESET pin. Connect a capacitor between the RESET pin and VSS at the shortest
distance.
VDD
VD D
RESET pin voltage
Internal reset signal
RESET pin
Reset state
Voltage drop detection circuit
(Note)
Watchdog timer output
Internal reset signal
WEF
Reset released
Power-on
Note:
This symbol represents a parasitic diode.
Applied potential to RESET pin must be VDD or less.
Fig. 2.7.1 Power-on reset circuit example
=
Reset input
1 machine cycle or more
f(XIN) is counted 16892 to
16895 times.
0.85VDD
Software starts
(address 0 in page 0)
RESET
0.3VDD
(Note)
Note: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 2.7.2 Oscillation stabilizing time after system is released from reset
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APPLICATION
2.7 Reset
2.7.2 Internal state at reset
Figure 2.7.3 shows the internal state at reset. The contents of timers, registers, flags and RAM other than
shown in Figure 2.7.3 are undefined, so that set them to initial values.
• Program counter (PC) ............................................................................................
0 0 0 0 0 0
0
0
0
0
0
0
0
0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) ...................................................................................
0 (Interrupt disabled)
• Power down flag (P) ...............................................................................................
0
• External 0 interrupt request flag (EXF0) ................................................................
0
• External 1 interrupt request flag (EXF1) ................................................................
0
• Interrupt control register V1 ...................................................................................
0 0 0 0
(Interrupt disabled)
• Interrupt control register V2 ...................................................................................
0 0 0 0
• Interrupt control register I1 ....................................................................................
0 0 0 0
(Interrupt disabled)
• Interrupt control register I2 ....................................................................................
0 0 0 0
• Timer 1 interrupt request flag (T1F) ......................................................................0
• Timer 2 interrupt request flag (T2F) ......................................................................0
• Timer 3 interrupt request flag (T3F) ......................................................................0
• Timer 4 interrupt request flag (T4F) ......................................................................0
• Watchdog timer flags (WDF1, WDF2) ...................................................................0
• Watchdog timer enable flag (WEF) .......................................................................0
• Timer control register W1 ......................................................................................
0 0 0 0
(Prescaler, timer 1 stopped)
• Timer control register W2 ......................................................................................
0 0 0 0
• Timer control register W3 ......................................................................................
0 0 0 0
(Timer 2 stopped)
(Timer 3 stopped)
• Timer control register W4 ......................................................................................
0 0 0 0
• Timer control register W6 ......................................................................................
0 0 0 0
• Clock control register MR ......................................................................................
1 0 0 0
(Timer 4 stopped)
• Serial I/O transmit/receive completion flag ............................................................
0
• Serial I/O mode register J1 ....................................................................................
0 0 0 0
(External clock selected,
serial I/O port not selected))
• Serial I/O register SI ..............................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• A-D conversion completion flag ADF ....................................................................0
• A-D control register Q1 ..........................................................................................
0 0 0 0
• A-D control register Q2 ..........................................................................................
0 0 0 0
• Voltage comparator control register Q3 ................................................................
0 0 0 0
• Successive comparison register AD ......................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Comparator register ...............................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Key-on wakeup control register K0 .......................................................................
0 0 0 0
• Pull-up control register PU0 ...................................................................................
0 0 0 0
• Direction register FR0 ............................................................................................
0 0 0 0
(Port P5 input mode)
• Carry flag (CY) .......................................................................................................
0
• Register A ..............................................................................................................
0 0 0 0
• Register B ..............................................................................................................
0 0 0 0
• Register D ..............................................................................................................
✕ ✕ ✕
✕
✕
✕
✕
✕
✕
✕ ✕
• Register E ..............................................................................................................
• Register X ..............................................................................................................
0 0 0 0
• Register Y ..............................................................................................................
0 0 0 0
• Register Z ...............................................................................................................
✕ ✕
• Stack pointer (SP) ..................................................................................................
1 1 1
“✕” represents undefined.
Fig. 2.7.3 Internal state at reset
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APPLICATION
2.8 Voltage drop detection circuit
2.8 Voltage drop detection circuit
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer
if the supply voltage drops below a set value.
Figure 2.8.1 shows the voltage drop detection reset circuit, and Figure 2.8.2 shows the operation waveform
example of the voltage drop detection circuit.
RESET pin
Internal reset signal
Voltage drop detection circuit
Watchdog timer output
WEF
Note: The output structure of RESET pin is N-channel open-drain.
Fig. 2.8.1 Voltage drop detection reset circuit
VDD
VRST (detection voltage)
Voltage drop detection
circuit output
The microcomputer starts
operation after f(XIN) is counted
16892 to 16895 times.
RESET pin
Notes 1: Pull-up RESET pin externally.
2: Refer to the voltage drop detection circuit in the electrical characteristics
for the rating value of VRST (detection voltage).
Fig. 2.8.2 Voltage drop detection circuit operation waveform
Note: Refer to section “3.1 Electrical characteristics” for the reset voltage of the voltage drop detection
circuit.
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APPLICATION
2.9 RAM back-up
2.9 RAM back-up
2.9.1 RAM back-up mode
The system enters RAM back-up mode when the POF instruction is executed after the EPOF instruction
is executed. Table 2.9.1 shows the function and state retained at RAM back-up mode. Also, Table 2.9.2
shows the return source from this state.
(1)
RAM back-up mode
As oscillation stops with RAM, the state of reset circuit retained, current dissipation can be reduced
without losing the contents of RAM.
Table 2.9.1 Functions and states retained at RAM
RAM back-up
Function
Program counter (PC), registers A, B,
✕
carry flag (CY), stack pointer (SP) (Note 2)
O
Contents of RAM
O
Port level
back-up mode
Function
RAM back-up
O
Pull-up control register PU0
O
Key-on wakeup control register K0
O
Direction register FR0
✕
External 0 interrupt request flag (EXF0)
✕
Timer control register W1
External 1 interrupt request flag (EXF1)
✕
O
Timer control registers W2 to W4. W6
Timer 1 interrupt request flag (T1F)
✕
✕
Clock control register MR
Timer 2 interrupt request flag (T2F)
(Note 3)
✕
Interrupt control registers V1, V2
Timer 3 interrupt request flag (T3F)
(Note 3)
O
Interrupt control registers I1, I2
Timer 4 interrupt request flag (T4F)
(Note 3)
Timer 1 function
✕
Watchdog timer flags (WDF1, WDF2) ✕ (Note 4)
Timer 2 function
(Note 3)
Watchdog timer enable flag (WEF)
✕ (Note 4)
Timer 3 function
(Note 3)
16-bit timer (WDT)
✕ (Note 4)
Timer 4 function
(Note 3)
A-D conversion completion flag (ADF)
✕
A-D function
✕
Serial I/O transmit/receive completion flag
✕
A-D control registers Q1, Q2
O
(SIOF)
Voltage comparator function
O (Note 5)
Interrupt enable flag (INTE)
✕
Voltage comparator control register Q3
O
Serial I/O function
✕
Serial I/O mode register J1
O
Notes 1: “O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at RAM back-up, and set an initial value
after returning.
2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM backup.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction.
5: The state is retained when the voltage comparator function is selected with the voltage comparator
control register Q3.
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APPLICATION
2.9 RAM back-up
Table 2.9.2 Return source and return condition
Return source
External wakeup
signal
Ports P0, P1
Port P3 0/INT0
Port P3 1/INT1
Return condition
Remarks
Return by an external falling Set the port using the key-on wakeup function selected
edge input (“H”→“L”).
with register K0 to “H” level before going into the RAM
back-up state because the port P0 shares the falling
edge detection circuit with port P1.
Return by an external “H” level
or “L” level input.
The EXF0 flag is not set.
Return by an external “H” level
or “L” level input.
The EXF1 flag is not set.
(2)
Select the return level (“L” level or “H” level) with the bit
2 of register I1 according to the external state before
going into the RAM back-up state.
Select the return level (“L” level or “H” level) with the bit
2 of register I2 according to the external state before
going into the RAM back-up state.
Start condition identification
When system returns from both RAM back-up mode and reset, software is started from address 0
in page 0.
The start condition (warm start or cold start) can be identified by examining the state of the power
down flag (P) with the SNZP instruction.
Table 2.9.3 Start condition identification
Return condition
P flag
External wakeup signal input
1
Reset
0
Software start
P = “1”
?
No
Cold start
Yes
Warm start
Fig. 2.9.1 Start condition identified example
2.9.2 Related register
(1) Key-on wakeup control register K0
Key-on wakeup control register K0 controls key-on wakeup functions of ports P0 0–P03 , P10 –P13.
Set the contents of this register through register A with the TK0A instruction. The TAK0 instruction
can be used to transfer the contents of register K0 to register A.
Table 2.9.4 shows the key-on wakeup control register K0.
Table 2.9.4 Key-on wakeup control register K0
Key-on wakeup control register K0
K0 3
K0 2
at reset : 0000 2
Pins P12 and P13 key-on wakeup
control bit
Pins P10 and P11 key-on wakeup
control bit
Pins P02 and P03 key-on wakeup
control bit
0
1
0
1
Key-on
Key-on
Key-on
Key-on
at RAM back-up : state retained
wakeup
wakeup
wakeup
wakeup
not used
used
not used
used
0
Key-on wakeup not used
1
Key-on wakeup used
0
Pins P00 and P01 key-on wakeup
Key-on wakeup not used
K0 0
1
control bit
Key-on wakeup used
Note: “R” represents read enabled, and “W” represents write enabled.
K0 1
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2.9 RAM back-up
(2) Pull-up control register PU0
Pull-up control register PU0 controls the pull-up functions of ports P0 0–P03 , P10 –P13.
Set the contents of this register through register A with the TPU0A instruction. The TAPU0 instruction
can be used to transfer the contents of register PU0 to register A.
Table 2.9.5 shows the pull-up control register PU0.
Table 2.9.5 Pull-up control register PU0
Pull-up control register PU0
PU0 3
PU0 2
PU0 1
Pins P12 and
transistor control
Pins P10 and
transistor control
Pins P02 and
transistor control
Pins P00 and
transistor control
P13
bit
P11
bit
P03
bit
P01
bit
at reset : 0000 2
pull-up
pull-up
pull-up
at RAM back-up : state retained
0
Pull-up transistor OFF
1
0
1
0
1
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
transistor
transistor
transistor
transistor
transistor
R/W
ON
OFF
ON
OFF
ON
pull-up
Pull-up transistor OFF
0
Pull-up transistor ON
1
Note: “R” represents read enabled, and “W” represents write enabled.
PU0 0
(3)
Interrupt control register I1
The interrupt valid waveform for INT0 pin/return level selection bit is assigned to bit 2, INT0 pin edge
detection circuit control bit is assigned to bit 1, and INT0 pin timer 1 control enable bit is assigned
to bit 0.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.9.6 shows the interrupt control register I1.
Table 2.9.6 Interrupt control register I1
Interrupt control register I1
at reset : 0000 2
0
I1 3
Not used
I1 2
Interrupt valid waveform for INT0
pin/return level selection bit
(Note 2)
1
0
1
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized
with the SNZI0 instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized
with the SNZI0 instruction)/“H” level
One-sided edge detected
INT0 pin edge detection circuit
0
control bit
Both edges detected
1
INT0 pin
Disabled
0
I1 0
timer 1 control enable bit
Enabled
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set.
Accordingly, clear EXF0 flag with the SNZ0 instruction.
I1 1
4513/4514 Group User’s Manual
2-61
APPLICATION
2.9 RAM back-up
(4)
Interrupt control register I2
The interrupt valid waveform for INT1 pin/return level selection bit is assigned to bit 2, the INT1 pin
edge detection circuit control bit is assigned to bit 1, and the INT1 pin timer 1 control enable bit is
assigned to bit 1.
Set the contents of this register through register A with the TI2A instruction.
In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 2.9.7 shows the interrupt control register I2.
Table 2.9.7 Interrupt control register I2
Interrupt control register I2
at reset : 0000 2
at RAM back-up : state retained
R/W
0
1
This bit has no function, but read/write is enabled.
Interrupt valid waveform for INT1
pin/return level selection bit
0
Falling waveform (“L” level of INT1 pin is recognized
with the SNZI1 instruction)/“L” level
(Note 2)
1
I2 3
Not used
I2 2
Rising waveform (“H” level of INT1 pin is recognized
with the SNZI1 instruction)/“H” level
INT1 pin edge detection circuit
One-sided edge detected
0
I2 1
control bit
Both edges detected
1
INT1 pin
Disabled
0
I2 0
timer 3 control enable bit
Enabled
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set.
Accordingly, clear EXF1 flag with the SNZ1 instruction.
2.9.3 Notes on use
(1)
Key-on wakeup function
After setting ports (P1 specified with register PU0 and P0) which key-on wakeup function is valid to
“H,” execute the POF instruction.
“L” level is input to the falling edge detection circuit even if one of ports which key-on wakeup
function is valid is in the “L” level state, and the edge is not detected.
(2)
POF instruction
Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM
back-up state.
Note that system cannot enter the RAM back-up state when executing only the POF instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
(3)
Return from RAM back-up
After system returns from RAM back-up, set the undefined registers and flags.
Especially, be sure to set data pointer (registers Z, X, Y).
2-62
4513/4514 Group User’s Manual
APPLICATION
2.10 Oscillation circuit
2.10 Oscillation circuit
The 4513/4514 Group has an internal oscillation circuit to produce the clock required for microcomputer
operation.
The clock signal f(XIN) is obtained by connecting a ceramic resonator to X IN pin and X OUT pin.
2.10.1 Oscillation circuit
(1)
f(XIN) clock generating circuit
The clock signal f(X IN) is obtained by connecting a ceramic resonator externally.
Connect this external circuit to pins XIN and XOUT at the shortest distance. A feed-back resistor is
built-in between XIN pin and X OUT pin.
Figure 2.10.1 shows an example of an oscillation circuit connecting a ceramic resonator externally.
Keep the maximum value of oscillation frequency within the range listed Table 2.10.1.
Table 2.10.1 Maximum value of
Supply voltage
2.5 V to 5.5 V
(f(X IN)/2)
4.0 V to 5.5 V
(f(X IN))
2.5 V to 5.5 V
(f(X IN))
oscillation frequency and supply voltage
(System clock)
Oscillation frequency
Middle-speed mode
4.2 MHz
High-speed mode
4.2 MHz
High-speed mode
2.0 V to 5.5 V (Note) (f(X IN)/2) Middle-speed mode
2.0 V to 5.5 V (Note) (f(X IN))
High-speed mode
Note: 2.5 V to 5.5 V for the One Timer PROM version.
2.0 MHz
3.0 MHz
1.5 MHz
Note: Externally connect a
damping resistor Rd depending on the oscillaXOUT
tion frequency. (A feedback resistor is built-in.)
Rd
Use the resonator
manufacturer’s recommended value because
COUT
constants such as capacitance depend on the
resonator.
4513/4514
XIN
CIN
Fig. 2.10.1 Oscillation circuit example connecting
ceramic resonator externally
4513/4514 Group User’s Manual
2-63
APPLICATION
2.10 Oscillation circuit
2.10.2 Oscillation operation
System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer
operation. For the 4513/4514 Group, the clock (f(XIN)), (f(X IN)/2) which is supplied from the oscillation
circuit is selected with the register MR.
Figure 2.10.2 shows the structure of the clock control circuit.
Division circuit
(divided by 2)
XIN
XOUT
Oscillation
circuit
System clock
MR3
1
0
Internal clock
generation circuit
(divided by 3)
Instruction clock
Counter
Wait time (Note)
control circuit
POF instruction
R
S
Software
start signal
RESET
Key-on wake up control register
K00,K01,K02,K03
Ports P00, P01
MultiPorts P02, P03
Falling detected
Ports P10, P11
plexer
Ports P12, P13
I12
Q
0
P30/INT0
1
“H” level
I22
“L” level
0
P31/INT1
1
“H” level
Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
Fig. 2.10.2 Structure of clock control circuit
2.10.3 Notes on use
(1)
2-64
Value of a part connected to an oscillator
Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and
the board. Accordingly, consult the oscillator manufacturer for values of each part connected the
oscillator.
4513/4514 Group User’s Manual
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Typical characteristics
3.3 List of precautions
3.4 Notes on noise
3.5 Mask ROM confirmation form
3.6 Mark specification form
3.7 Package outline
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
VDD
VI
VI
VI
VO
VO
VO
Pd
Parameter
Conditions
Supply voltage
Input voltage P0, P1, P2, P3, P4, P5, RESET ,
XIN, VDCE
Input voltage D0–D7
Input voltage AIN0–AIN7
Output voltage P0, P1, P3, P4, P5, RESET
Output voltage D0 –D7
Output voltage XOUT
Power dissipation
Output transistors in cut-off state
Ta = 25 °C
Package: 42P2R
Package: 32P6B
Package: 32P4B
Topr
Tstg
3-2
Operating temperature range
Storage temperature range
4513/4514 Group User’s Manual
Ratings
–0.3 to 7.0
Unit
V
–0.3 to VDD+0.3
V
–0.3 to 13
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to 13
V
V
V
V
–0.3 to VDD+0.3
300
300
1100
–20 to 85
V
mW
–40 to 125
°C
°C
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions 1
(Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Mask ROM version
Middle-speed mode
VDD
Supply voltage
Limits
Conditions
Mask ROM version
High-speed mode
f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 3.0 MHz
f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 2.0 MHz
f(XIN) ≤ 1.5 MHz
One Time PROM version
VRAM
VSS
VIH
VIH
VIH
VIH
VIL
VIL
VIL
RAM back-up voltage
(at RAM back-up mode)
Supply voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
f(XIN) ≤ 4.2 MHz
Middle-speed mode
One Time PROM version f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 2.0 MHz
High-speed mode
Mask ROM version
One Time PROM version
Min.
2.5
2.0
4.0
2.5
Typ.
Max.
5.5
5.5
5.5
2.0
5.5
5.5
2.5
5.5
4.0
2.5
1.8
2.0
5.5
5.5
RESET
CNTR0, CNTR1, S IN, SCK, INT0, INT1
P0, P1, P2, P3, P4, P5, D 0–D7 , XIN, VDCE
RESET
CNTR0, CNTR1, S IN, SCK, INT0, INT1
VDD = 5.0 V
P5
VDD = 3.0 V
IOH(peak)
“H” level peak output current
I OH(avg)
“H” level average output current
P5 (Note)
I OL(peak)
“L” level peak output current
P3, RESET
I OL(peak)
“L” level peak output current
D6, D7
I OL(peak)
“L” level peak output current
D0–D5
I OL(peak)
“L” level peak output current
P0, P1, P4, P5, SCK ,
SOUT
I OL(avg)
“L” level average output current
P3, RESET (Note)
I OL(avg)
“L” level average output current
D6, D7 (Note)
I OL(avg)
“L” level average output current
D0–D5 (Note)
I OL(avg)
“L” level average output current
ΣI OH(avg)
“H” level total average current
ΣIOL(avg)
“L” level total average current
P0, P1, P4, P5, SCK ,
SOUT (Note)
P5
P5, D, RESET, SCK, SOUT
P0, P1, P3, P4
0.8V DD
0.8V DD
0.85V DD
0.85V DD
0
0
0
–20
–10
–10
V
V
0
P0, P1, P2, P3, P4, P5, X IN, VDCE
D0–D7
Unit
VDD
12
VDD
VDD
V
V
V
V
V
0.2V DD
0.3V DD
0.15VDD
V
V
V
mA
VDD
VDD
VDD
VDD
VDD
= 5.0 V
= 3.0 V
= 5.0 V
= 3.0 V
= 5.0 V
VDD
VDD
VDD
VDD
VDD
= 3.0 V
= 5.0 V
= 3.0 V
= 5.0 V
= 3.0 V
30
24
12
24
12
VDD
VDD
VDD
VDD
VDD
= 5.0 V
= 3.0 V
= 5.0 V
= 3.0 V
= 5.0 V
5
2
30
15
15
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
7
12
6
mA
–5
10
4
40
mA
mA
mA
mA
mA
mA
mA
mA
–30
80
mA
80
Note: The average output current (IOH, IOL) is the average value during 100 ms.
4513/4514 Group User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions 2
(Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
f(XIN)
Parameter
Oscillation frequency
(with a ceramic resonator)
Conditions
Mask ROM version
VDD = 2.5 V to 5.5 V
Middle-speed mode
One Time PROM version
Middle-speed mode
VDD = 2.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
4.2
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 4.0 V to 5.5 V
VDD = 2.5 V to 5.5 V
4.2
2.0
1.5
VDD = 2.0 V to 5.5 V
3.0
VDD = 2.5 V to 5.5 V
3.0
VDD =
VDD =
VDD =
VDD =
3.0
1.0
Mask ROM version
High-speed mode
One Time PROM version
High-speed mode
f(XIN)
Oscillation frequency
(with external clock input)
Mask ROM version
Middle-speed mode
One Time PROM version
Middle-speed mode
Mask ROM version
High-speed mode
One Time PROM version
High-speed mode
Mask ROM version
Middle-speed mode
tw(SCK)
Serial I/O external clock period
(“H” and “L” pulse width)
One Time PROM version
Middle-speed mode
Mask ROM version
High-speed mode
One Time PROM version
High-speed mode
Mask ROM version
Middle-speed mode
tw(CNTR)
Timer external input period
(“H” and “L” pulse width)
One Time PROM version
Middle-speed mode
Mask ROM version
High-speed mode
One Time PROM version
High-speed mode
3-4
Limits
Typ.
Max.
4.2
3.0
Min.
MHz
4.2
2.0
4.0 V to 5.5 V
2.5 V to 5.5 V
2.0 V to 5.5 V
4.0 V to 5.5 V
MHz
0.8
3.0
1.0
VDD
VDD
VDD
VDD
VDD
= 2.5 V to 5.5 V
= 4.0 V to 5.5 V
= 2.5 V to 5.5 V
= 2.0 V to 5.5 V
= 4.0 V to 5.5 V
1.5
3.0
4.0
1.5
VDD
VDD
VDD
VDD
VDD
= 2.5 V to 5.5 V
= 4.0 V to 5.5 V
= 2.5 V to 5.5 V
= 2.0 V to 5.5 V
= 4.0 V to 5.5 V
3.0
750
1.5
2.0
750
VDD
VDD
VDD
VDD
VDD
= 2.5 V to 5.5 V
= 4.0 V to 5.5 V
= 2.5 V to 5.5 V
= 2.0 V to 5.5 V
= 4.0 V to 5.5 V
1.5
1.5
3.0
4.0
1.5
VDD
VDD
VDD
VDD
VDD
= 2.5 V to 5.5 V
= 4.0 V to 5.5 V
= 2.5 V to 5.5 V
= 2.0 V to 5.5 V
= 4.0 V to 5.5 V
3.0
750
1.5
2.0
750
VDD = 2.5 V to 5.5 V
1.5
4513/4514 Group User’s Manual
Unit
µs
ns
µs
ns
µs
µs
ns
µs
ns
µs
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics
(Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
VOH
“H” level output voltage P5
VOL
“L” level output voltage P0, P1, P4, P5
VOL
“L” level output voltage P3, RESET
VOL
“L” level output voltage D6, D7
Test conditions
VDD
VDD
VDD
VDD
=5V
=3V
=5V
=3V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VOL
I IH
I IH
I IL
I IL
Typ.
“H” level input current
P0, P1, P2, P3, P4, P5, RESET , VDCE
“H” level input current D0–D7
2
0.9
2
0.9
2
0.9
I OL = 2 mA
I OL = 30 mA
I OL = 10 mA
I OL = 15 mA
I OL = 5 mA
port P5: input state
VI = 12 V
VI = 0 V No pull-up of ports P0 and P1,
port P4 selected, port P5: input state
VI = 0 V
“L” level input current
P0, P1, P2, P3, P4, P5, RESET , VDCE
“L” level input current D0–D7
VDD = 5 V
Middle-speed mode
VDD = 3 V
Middle-speed mode
VDD = 5 V
Supply current
at RAM back-up mode
RPU
Pull-up resistor value
VT+ – VT–
Hysteresis INT0, INT1, CNTR0, CNTR1,
SIN, S CK
VT+ – VT–
Hysteresis RESET
High-speed mode
VDD = 3 V
High-speed mode
Ta = 25 °C
VDD = 5 V
VDD
VDD
VDD
VDD
VDD
=3V
=5V
=3V
=5V
=3V
2
0.9
2
0.9
VDD = 5 V
VDD = 3 V
4513/4514 Group User’s Manual
V
V
V
1
µA
µA
0.6
0.9
0.3
0.1
40
V
µA
1.8
0.5
0.9
0.2
3.0
20
V
µA
–1
f(XIN) = 4.0 MHz
f(XIN) = 400 kHz
f(XIN) = 2.0 MHz
f(XIN) = 400 kHz
Unit
1
–1
f(XIN) = 4.0 MHz
f(XIN) = 400 kHz
f(XIN) = 4.0 MHz
f(XIN) = 400 kHz
VI = 0 V
Max.
V
VDD = 5 V
I OL = 15 mA
VDD = 3 V
I OL = 3 mA
VI = VDD, port P4 selected,
“L” level output voltage D0–D5
at active mode
I DD
I OH = –10 mA
I OH = –5 mA
I OL = 12 mA
I OL = 6 mA
I OL = 5 mA
Limits
Min.
3
2
50
100
0.3
0.3
1.5
0.6
5.5
1.5
2.7
0.6
9.0
1.8
2.7
0.9
1
10
6
125
250
mA
µA
kΩ
V
V
3-5
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter recommended operating conditions
Table 3.1.5 A-D converter recommended operating conditions
(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
VDD
Supply voltage
VIA
Analog input voltage
f(XIN)
Oscillation frequency
Conditions
Middle-speed mode, V DD ≥ 2.7 V
High-speed mode, VDD ≥ 2.7 V
Min.
Limits
Typ.
2.7
0
0.8
0.4
Max.
5.5
VDD
Unit
V
V
MHz
MHz
Table 3.1.6 A-D converter characteristics
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
–
Parameter
Test conditions
Min.
Limits
Typ.
Resolution
–
Linearity error
–
Differential non-linearity error
V0T
Zero transition voltage
VFST
Full-scale transition voltage
IADD
A–D operating current
TCONV
A-D conversion time
–
Comparator resolution
–
Comparator error (Note)
–
Comparator comparison time
Ta
Ta
Ta
Ta
=
=
=
=
VDD
VDD
VDD
VDD
VDD
25 °C, VDD = 2.7 V to 5.5 V
–25 °C to 85 ° C, VDD = 3.0 V to 5.5 V
25 °C, VDD = 2.7 V to 5.5 V
–25 °C to 85 ° C, VDD = 3.0 V to 5.5 V
= 5.12 V
= 3.072 V
= 5.12 V
= 3.072 V
= 5.0 V
0
0
5105
3060
f(XIN) = 0.4 MHz to 4.0 MHz
f(XIN) = 0.4 MHz to 2.0 MHz
5
3
5115
3069
0.7
0.2
VDD = 3.0 V
f(XIN ) = 4.0 MHz, Middle-speed mode
f(XIN ) = 4.0 MHz, High-speed mode
Comparator mode
Unit
Max.
10
bits
±2
LSB
±0.9
LSB
20
15
5125
3075
2.0
0.4
93.0
46.5
8
±20
VDD = 5.12 V
VDD = 3.072 V
f(XIN ) = 4.0 MHz, Middle-speed mode
f(XIN ) = 4.0 MHz, High-speed mode
±15
12
6
mV
mV
mA
µs
bits
mV
µs
Note: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage V ref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
n = Value of register AD (n = 0 to 255)
3.1.5 Voltage drop detection circuit characteristics
Table 3.1.7 Voltage drop detection circuit characteristics
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
VRST
Detection voltage
I RST
Operation current of voltage
drop detection circuit
3-6
Test conditions
Parameter
Ta = 25 °C
VDD = 5.0 V
4513/4514 Group User’s Manual
Min.
2.7
3.3
Limits
Typ.
3.5
Max.
4.1
3.7
50
100
Unit
V
µA
APPENDIX
3.1 Electrical characteristics
3.1.6 Voltage comparator characteristics
Table 3.1.8 Voltage comparator recommended operating conditions
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
VDD
Conditions
Parameter
Supply voltage
Voltage comparator input voltage
Voltage comparator response time
VINCMP
t CMP
VDD = 3.0 V to 5.5 V
VDD = 3.0 V to 5.5 V
Min.
3.0
0.3VDD
Limits
Typ.
Max.
5.5
0.7VDD
20
Unit
V
V
µs
Table 3.1.9 Voltage comparator characteristics
(Ta = –20 °C to 85 °C, VDD = 3.0 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Test conditions
–
Comparison decision voltage error
I CMP
Voltage comparator operation current
Min.
Limits
Typ.
Max.
20
100
mV
15
50
µA
CMP0- > CMP0+, CMP0- < CMP0+
CMP1- > CMP1+, CMP1- < CMP1+
VDD = 5.0 V
Unit
3.1.7 Basic timing diagram
Machine cycle
Parameter
Clock
Pin name
XIN
System clock = f(XIN)
Mi
Mi+1
XIN
System clock = f(XIN)/2
Port D output
D0–D7
Port D input
D0–D7
Ports P0, P1, P3,
P4, P5 output
P00–P03
P10–P13
P30–P33
P40–P43
P50–P53
Ports P0, P1, P2, P3, P00–P03
P10–P13
P4, P5 input
P20–P22
P30–P33
P40–P43
P50–P53
Interrupt input
INT0,INT1
4513/4514 Group User’s Manual
3-7
APPENDIX
3.2 Typical characteristics
3.2 Typical characteristics
3.2.1 V DD–I DD characteristics
(1)
CPU operating, middle-speed mode
2.5
Ta = 25 °C
2.4
2.3
2.2
2.1
2
1.9
Supply current I DD (mA)
1.8
1.7
1.6
1.5
1.4
f(X IN) = 4 MHz
1.3
1.2
1.1
1
f(XIN ) = 1 MHz
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
Supply voltage V DD (V)
(2)
CPU operating, high-speed mode
2.5
Ta = 25 °C
2.4
2.3
2.2
2.1
2
f(X IN) = 4 MHz
1.9
Supply current I DD (mA)
1.8
1.7
1.6
1.5
1.4
1.3
1.2
f(X IN) = 1 MHz
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2
2.5
3
3.5
4
4.5
Supply voltage VDD (V)
3-8
4513/4514 Group User’s Manual
5
5.5
APPENDIX
3.2 Typical characteristics
(3)
A-D operating, middle-speed mode
Ta = 25 °C
2.5
2.4
2.3
2.2
2.1
2
1.9
f(X IN) = 4 MHz
Supply current IDD (mA)
1.8
1.7
1.6
1.5
1.4
f(XIN ) = 1 MHz
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2
(4)
2.5
3
3.5
4
4.5
5
5.5
Supply voltage VDD (V)
A-D operating, high-speed mode
Ta = 25 °C
2.5
2.4
f(X IN) = 4 MHz
2.3
2.2
2.1
2
1.9
1.8
Supply current I DD (mA)
1.7
1.6
1.5
f(X IN) = 1 MHz
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
Supply voltage V DD (V)
4513/4514 Group User’s Manual
3-9
APPENDIX
3.2 Typical characteristics
(5)
RAM back-up
Ta = 25 °C
5
4.5
4
3.5
Supply current I DD (nA)
3
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
Supply voltage V DD (V)
3-10
4513/4514 Group User’s Manual
4.5
5
5.5
APPENDIX
3.2 Typical characteristics
3.2.2 V OL–I OL characteristics
(1)
Ports P0, P1, P4, P5, SCK , SOUT
Ta = 25 °C
100
90
V DD = 6 V
80
V DD = 5 V
Output current IOL (mA)
70
60
V DD = 4 V
50
40
V DD = 3 V
30
20
V DD = 2 V
10
0
0
0.5
1
1.5
2
Output voltage VOL (V)
(2)
Port P3, RESET pin
Ta = 25 °C
100
90
Output current I OL (mA)
80
70
60
50
V DD = 6 V
40
V DD = 5 V
30
V DD = 4 V
V DD = 3 V
20
10
V DD = 2 V
0
0
0.5
1
1.5
2
Output voltage V OL (V)
4513/4514 Group User’s Manual
3-11
APPENDIX
3.2 Typical characteristics
(3)
Pins D0–D 5
Ta = 25 °C
100
90
Output current IOL (mA)
80
70
60
V DD = 6 V
V DD = 5 V
50
V DD = 4 V
40
V DD = 3 V
30
20
V DD = 2 V
10
0
0
0.5
1
1.5
2
Output voltage V OL (V)
(4)
Pins D6/CNTR0, D 7/CNTR1
Ta = 25 °C
100
90
80
Output current I OL (mA)
V DD = 6 V
70
V DD = 5 V
V DD = 4 V
60
50
V DD = 3 V
40
30
V DD = 2 V
20
10
0
0
0.5
1
Output voltage V OL (V)
3-12
4513/4514 Group User’s Manual
1.5
2
APPENDIX
3.2 Typical characteristics
3.2.3 V OH–I OH characteristics (Port P5)
V DD = 2 V
0
V DD = 3 V
V DD = 4 V
V DD = 5 V
V DD = 6 V
Ta = 25 °C
-10
-20
Output current IOH (mA)
-30
-40
-50
-60
-70
-80
-90
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Output voltage V OH (V)
3.2.4 V DD–R PU characteristics (Ports P0, P1)
350
Ta = 25 °C
Pull-up resistor R PU (kΩ)
300
250
200
150
100
50
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply voltage V DD (V)
4513/4514 Group User’s Manual
3-13
APPENDIX
3.2 Typical characteristics
3.2.5 A-D converter typical characteristics
30
1LSB WIDTH
+1LSB
➀
0
➂
➃
0
➄
ERROR
1LSB WIDTH [
mV]
ERROR [mV]
➁
-1LSB
-30
0
1
1022 1023
Fig. 3.2.1 A-D conversion characteristics data
Figure 3.2.1 shows the A-D accuracy measurement data.
(1) Non-linearity error ......................... This means a deviation from the ideal characteristics between V0 to
V 1022 of actual A-D conversion characteristics. In Figure 3.2.1, it is
(➃–➀)/1LSB.
(2) Differencial non-linearity error .... This means a deviation from the ideal characteristics between the
input voltages V 0 to V1022 necessary to change the output data to
“1.” In Figure 3.2.1, this is ➁/1LSB.
(3) Zero transition error ..................... This means a deviation from the ideal characteristics between the
input voltages 0 to VDD when the output data changes from “0” to “1.”
In Figure 3.2.1, this is the value of ➀.
(4) Full-scale transition error ............. This means a deviation from the ideal characteristics between the
input voltages 0 to V DD when the output data changes from “1022”
to “1023.” In Figure 3.2.1, this is the value of ➄.
(5) Absolute accuracy ........................ This menas a deviation from the ideal characteristics between 0 to
V DD of actual A-D conversion characteristics. In Figure 3.2.1, this is
the value of ERROR in each of ➀, ➂, ➃ and ➄.
For the A-D converter characteristics, refer to the section 3.1 Electrical characteristics.
3-14
4513/4514 Group User’s Manual
APPENDIX
3.2 Typical characteristics
(1)
V DD = 3.072 V, f(XIN) = 2 MHz, high-speed mode
Ta = 25 °C
ERROR / 1LSB WIDTH(mV)
4.5
1LSB WIDTH
3
1.5
ERRO R
0
-1.5
-3
-4.5
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
400
416
432
448
464
480
496
512
656
672
688
704
720
736
752
768
912
928
944
960
976
992
1008
1024
STEP No.
ERROR / 1LSB WIDTH(mV)
4.5
3
1.5
0
-1.5
-3
-4.5
256
272
288
304
320
336
352
368
384
STEP No.
ERROR / 1LSB WIDTH(mV)
4.5
3
1.5
0
-1.5
-3
-4.5
512
528
544
560
576
592
608
624
640
STEP No.
ERROR / 1LSB WIDTH(mV)
4.5
3
1.5
0
-1.5
-3
-4.5
768
784
800
816
832
848
864
880
896
STEP No.
4513/4514 Group User’s Manual
3-15
APPENDIX
3.2 Typical characteristics
(2)
V DD = 5.12 V, f(XIN ) = 4 MHz, high-speed mode
Ta = 25 °C
ERROR / 1LSB WIDTH(mV)
7.5
1LSB WIDTH
5
2.5
ERRO R
0
-2.5
-5
-7.5
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
400
416
432
448
464
480
496
512
656
672
688
704
720
736
752
768
912
928
944
960
976
992
1008
1024
STEP No.
ERROR / 1LSB WIDTH(mV)
7.5
5
2.5
0
-2.5
-5
-7.5
256
272
288
304
320
336
352
368
384
STEP No.
ERROR / 1LSB WIDTH(mV)
7.5
5
2.5
0
-2.5
-5
-7.5
512
528
544
560
576
592
608
624
640
STEP No.
ERROR / 1LSB WIDTH(mV)
7.5
5
2.5
0
-2.5
-5
-7.5
768
784
800
816
832
848
864
880
896
STEP No.
3-16
4513/4514 Group User’s Manual
APPENDIX
3.2 Typical characteristics
3.2.6 Analog input current characteristics pins A IN0–A IN7
(1)
V DD = 3.0 V, f(XIN ) = 2 MHz, middle-speed mode
Ta = 25 °C
25
Analog input current IAIN (nA)
20
15
10
5
0
-5
-10
-15
-20
-25
0
0.5
1
1.5
2
2.5
3
Analog input voltage VAIN (V)
(2)
V DD = 3.0 V, f(XIN ) = 4 MHz, middle-speed mode
Ta = 25 °C
100
80
Analog input current IAIN (nA)
60
40
20
0
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Analog input voltage VAIN (V)
4513/4514 Group User’s Manual
3-17
APPENDIX
3.2 Typical characteristics
(3)
V DD = 3.0 V, f(X IN) = 2 MHz, high-speed mode
Ta = 25 °C
50
40
Analog input current IAIN (nA)
30
20
10
0
-10
-20
-30
-40
-50
0
0.5
1
1.5
2
2.5
3
Analog input voltage VAIN (V)
(4)
V DD = 5.0 V, f(X IN) = 4 MHz, high-speed mode
Ta = 25 °C
200
160
120
Analog input current IAIN (nA)
80
40
0
-40
-80
-120
-160
-200
0
0.5
1
1.5
2
2.5
3
3.5
Analog input voltage VAIN (V)
3-18
4513/4514 Group User’s Manual
4
4.5
5
APPENDIX
3.2 Typical characteristics
3.2.7 V DD–V IH/VIL characteristics
(1)
RESET pin
Ta = 25 °C
5.5
V IH
(rating value)
5
4.5
V IH
4
3.5
V IH/VIL (V)
3
V IL
2.5
2
V IL
(rating value)
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply voltage V DD (V)
(2)
Ports P0, P1, P2, P3, P4, P5, D, X IN pin, VDCE pin
Ta = 25 °C
5.5
5
V IH (rating value)
4.5
4
V IH/VIL (V)
3.5
3
V IH, V IL
2.5
2
1.5
V IL (rating value)
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply voltage VDD (V)
4513/4514 Group User’s Manual
3-19
APPENDIX
3.2 Typical characteristics
(3)
Pins INT0, INT1, CNTR0, CNTR1, S CK, SIN
Ta = 25 °C
5.5
V IL
(rating value)
5
4.5
4
V IH/VIL (V)
3.5
V IH
V IL
3
2.5
2
1.5
1
V IH
(rating value)
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply voltage V DD (V)
3.2.8 Detection voltage temperature characteristics of voltage drop detection circuit
4.5
4.4
4.3
4.2
4.1
Detection voltage VRST (V)
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
Storage temperature range Ta (°C)
3-20
4513/4514 Group User’s Manual
60
65
70
75
80
85
APPENDIX
3.3 List of precautions
3.3 List of precautions
➀Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins V DD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNV SS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 kΩ in series at the shortest distance.
➁Prescaler
Stop the prescaler operation to change its frequency dividing ratio.
➆P31/INT1 pin
When the interrupt valid waveform of P31 /INT1 pin is changed
with the bit 2 of register I2 in software, be careful about the following notes.
• Clear the bit 1 of register V1 to “0” before the interrupt valid waveform of P3 1/INT1 pin is changed with the bit 2 of register I2 (refer
to Figure 45➂).
• Depending on the input state of the P31 /INT1 pin, the external 1
interrupt request flag (EXF1) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I2 and
execute the SNZ1 instruction to clear the EXF1 flag after executing at least one instruction (refer to Figure 45➃).
...
➂Timer count source
Stop timer 1, 2, 3, or 4 counting to change its count source.
➃Reading the count value
Stop timer 1, 2, 3, or 4 counting and then execute the TAB1,
TAB2, TAB3, or TAB4 instruction to read its data.
➄Writing to reload registers R1 and R3
When writing data to reload registers R1 or R3 while timer 1 or
timer 3 is operating, avoid a timing when timer 1 or timer 3
underflows.
➅P30 /INT0 pin
When the interrupt valid waveform of the P3 0 /INT0 pin is
changed with the bit 2 of register I1 in software, be careful about
the following notes.
• Clear the bit 0 of register V1 to “0” before the interrupt valid waveform of P30/INT0 pin is changed with the bit 2 of register I1 (refer
to Figure 44➀).
• Depending on the input state of the P30/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the interrupt valid
waveform is changed. Accordingly, clear bit 2 of register I1, and
execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction (refer to Figure 44➁)
LA 8
TV1A
LA 8
TI2A
NOP
SNZ1
NOP
; (✕✕0✕ 2)
; The SNZ1 instruction is valid ........... ➂
; Change of the interrupt valid waveform
........................................................... ➃
; The SNZ1 instruction is executed
...
✕ : this bit is not related to the setting of INT1.
Fig. 45 External 1 interrupt program example
➇One Time PROM version
The operating power voltage of the One Time PROM version is
2.5 V to 5.5 V.
➈Multifunction
The input of D6, D7, P20–P22, I/O of P3 0 and P31, input of CMP0-,
CMP0+, CMP1-, CMP1+, and I/O of P40 –P43 can be used even
when CNTR0, CNTR1, SCK , SOUT, S IN, INT0, INT1, AIN0–AIN3
and A IN4–AIN7 are selected.
...
LA
4
TV1A
LA
4
TI1A
NOP
SNZ0
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
;
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
...
✕ : this bit is not related to the setting of INT0 pin.
Fig. 44 External 0 interrupt program example
4513/4514 Group User’s Manual
3-21
APPENDIX
3.3 List of precautions
➉ A-D converter-1
When the operating mode of the A-D converter is changed from
the comparator mode to the A-D conversion mode with the bit 3
of register Q2 in a program, be careful about the following notes.
• Clear the bit 2 of register V2 to “0” to change the operating mode
of the A-D converter from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 (refer to Figure 46➄).
• The A-D conversion completion flag (ADF) may be set when the
operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode. Accordingly, set a
value to register Q2, and execute the SNZAD instruction to clear
the ADF flag.
Do not change the operating mode (both A-D conversion mode
and comparator mode) of A-D converter with the bit 3 of register
Q2 during operating the A-D converter.
Sensor
AIN
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 47 Analog input external circuit example-1
...
LA
8
TV2A
LA
0
TQ2A
; (✕0✕✕2 )
; The SNZAD instruction is valid ........➄
; (0✕✕✕2 )
; Change of the operating mode of the A-D
converter from the comparator mode to the
A-D conversion mode
SNZAD
NOP
...
About 1kΩ
Sensor
Fig. 48 Analog input external circuit example-2
12
✕: this bit is not related to the change of the
operating mode of the A-D conversion.
Fig. 46 A-D converter operating mode program example
11
A-D converter-2
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog
voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A-D accuracy
may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure
47).
When the overvoltage applied to the A-D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 48. In addition, test
the application products sufficiently.
3-22
AIN
POF instruction
Execute the POF instruction immediately after executing the
EPOF instruction to enter the RAM back-up.
Note that system cannot enter the RAM back-up state when executing only the POF instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Analog input pins
Note the following when using the analog input pins also for I/O
port P4 functions:
• Even when P40/A IN4 –P43 /AIN7 are set to pins for analog input,
they continue to function as P40–P43 I/O. Accordingly, when any
of them are used as I/O port P4 and others are used as analog
input pins, make sure to set the outputs of pins that are set for
analog input to “1.” Also, the port input function of the pin functions as an analog input is undefined.
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
13
14
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
15
Port P3
In the 4513 Group, when the IAP3 instruction is executed, note
that the high-order 2 bits of register A is undefined.
4513/4514 Group User’s Manual
APPENDIX
3.3 List of precautions
16
Voltage comparator function
When the voltage comparator function is valid with the voltage
comparator control register Q3, it is operating even in the RAM
back-up mode. Accordingly, be careful about such state because
it causes the increase of the operation current in the RAM backup mode.
In order to reduce the operation current in the RAM back-up
mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage
comparator function by software before the POF instruction is executed.
Also, while the voltage comparator function is valid, current is always consumed by voltage comparator. On the system required
for the low-power dissipation, invalidate the voltage comparator
when it is unused by software.
17
Register Q3
Bits 0 and 1 of register Q3 can be only read. Note that they cannot be written.
18
Reading the comparison result of voltage comparator
Read the voltage comparator comparison result from register Q3
after the voltage comparator response time (max. 20 µ s) is
passed from the voltage comparator function become valid.
4513/4514 Group User’s Manual
3-23
APPENDIX
3.4 Notes on noise
3.4 Notes on noise
Countermeasures against noise are described below.
The following countermeasures are effective against
noise in theory, however, it is necessary not only to
take measures as follows but to evaluate before actual
use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function
as an antenna which feeds noise into the
microcomputer.
The shorter the total wiring length (by mm unit), the
less the possibility of noise insertion into a
microcomputer.
(1)
Package
Select the smallest possible package to make
the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package,
for example QFP and not DIP, makes the
total wiring length short to reduce influence
of noise.
(2) Wiring for RESET input pin
Make the length of wiring which is connected
to the RESET input pin as short as possible.
Especially, connect a capacitor across the
RESET input pin and the VSS pin with the
shortest possible wiring.
● Reason
In order to reset a microcomputer correctly,
1 machine cycle or more of the width of a
pulse input into the RESET pin is required.
If noise having a shorter pulse width than
this is input to the RESET input pin, the
reset is released before the internal state
of the microcomputer is completely initialized.
This may cause a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
DIP
Reset
circuit
SDIP
SOP
VSS
RESET
VSS
QFP
O.K.
Fig. 3.4.2 Wiring for the RESET input pin
Fig. 3.4.1 Selection of packages
3-24
4513/4514 Group User’s Manual
APPENDIX
3.4 Notes on noise
(3)
Wiring for clock input/output pins
• Make the length of wiring which is connected
to clock I/O pins as short as possible.
• Make the length of wiring across the
grounding lead of a capacitor which is
connected to an oscillator and the VSS pin
of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation
from other V SS patterns.
Noise
(4) Wiring to CNVSS pin
Connect the CNVSS pin to the V SS pin with
the shortest possible wiring.
● Reason
The operation mode of a microcomputer is
influenced by a potential at the CNV SS pin.
If a potential difference is caused by the
noise between pins CNVSS and V SS , the
operation mode may become unstable. This
may cause a microcomputer malfunction or
a program runaway.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
CNVSS
CNVSS
VSS
VSS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
● Reason
If noise enters clock I/O pins, clock
waveforms may be deformed. This may
cause a program failure or program runaway.
Also, if a potential difference is caused by
the noise between the V SS level of a
microcomputer and the V SS level of an
oscillator, the correct clock will not be input
in the microcomputer.
O.K.
Fig. 3.4.4 Wiring for CNV SS pin
4513/4514 Group User’s Manual
3-25
APPENDIX
3.4 Notes on noise
(5) Wiring to VPP pin of One Time PROM version
In the built-in PROM version of the 4513/4514
Group, the CNV SS pin is also used as the
built-in PROM power supply input pin V PP.
● When the V PP pin is also used as the
CNVSS pin
Connect an approximately 5 kΩ resistor to
the V PP pin the shortest possible in series
and also to the VSS pin. When not
connecting the resistor, make the length of
wiring between the V PP pin and the V SS
pin the shortest possible (refer to Figure
3.4.5)
3.4.2 Connection of bypass capacitor across V SS
line and V DD line
Connect an approximately 0.1 µF bypass capacitor
across the V SS line and the VDD line as follows:
• Connect a bypass capacitor across the V SS pin
and the V DD pin at equal length.
• Connect a bypass capacitor across the V SS pin
and the VDD pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal
lines for V SS line and VDD line.
• Connect the power source wiring via a bypass
capacitor to the V SS pin and the V DD pin.
AA
AA
AA
AA
AA
VDD
Note: Even when a circuit which included an
approximately 5 kΩ resistor is used in the
Mask ROM version, the microcomputer
operates correctly.
● Reason
The V PP pin of the One Time PROM version is the power source input pin for the
built-in PROM. When programming in the
built-in PROM, the impedance of the VPP
pin is low to allow the electric current for
writing flow into the PROM. Because of
this, noise can enter easily. If noise enters
the V PP pin, abnormal instruction codes or
data are read from the built-in PROM, which
may cause a program runaway.
VSS
N.G.
VDD
VSS
O.K.
Fig. 3.4.6 Bypass capacitor across the VSS line
and the VDD line
When the VPP pin is also used as the CNVSS pin
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.5 Wiring for the VPP pin of the One Time
PROM version
3-26
AA
AA
AA
AA
AA
4513/4514 Group User’s Manual
APPENDIX
3.4 Notes on noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor
to an analog signal line which is connected to an
analog input pin in series. Besides, connect the
resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across
the V SS pin and the analog input pin. Besides,
connect the capacitor to the V SS pin as close as
possible. Also, connect the capacitor across the
analog input pin and the VSS pin at equal length.
●
Reason
Signals which is input in an analog input pin
(such as an A-D converter/comparator input
pin) are usually output signals from sensor.
The sensor which detects a change of event
is installed far from the printed circuit board
with a microcomputer, the wiring to an analog
input pin is longer necessarily. This long wiring
functions as an antenna which feeds noise
into the microcomputer, which causes noise
to an analog input pin.
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates
clocks for a microcomputer operation from being
affected by other signals.
(1) Keeping oscillator away from large current
signal lines
Install a microcomputer (and especially an
oscillator) as far as possible from signal lines
where a current larger than the tolerance of
current value flows.
● Reason
In the system using a microcomputer, there
are signal lines for controlling motors, LEDs,
and thermal heads or others. When a large
current flows through those signal lines,
strong noise occurs because of mutual
inductance.
Microcomputer
Mutual inductance
M
Noise
(Note)
Analog
input pin
Thermistor
XIN
XOUT
VSS
Large
current
Microcomputer
GND
Fig. 3.4.8 Wiring for a large current signal line
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a
capacitor
(2) Installing oscillator away from signal lines
where potential levels change frequently
Install an oscillator and a connecting pattern
of an oscillator away from signal lines where
potential levels change frequently. Also, do
not cross such signal lines over the clock lines
or the signal lines which are sensitive to noise.
● Reason
Signal lines where potential levels change
frequently (such as the CNTR pin signal
line) may affect other lines at signal rising
edge or falling edge. If such lines cross
over a clock line, clock waveforms may be
deformed, which causes a microcomputer
failure or a program runaway.
4513/4514 Group User’s Manual
3-27
APPENDIX
3.4 Notes on noise
N.G.
Do not cross
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as
follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port
in series.
CNTR
XIN
XOUT
VSS
Fig. 3.4.9 Wiring to a signal line where potential
levels change frequently
(3)
Oscillator protection using V SS pattern
As for a two-sided printed circuit board, print
a VSS pattern on the underside (soldering side)
of the position (on the component side) where
an oscillator is mounted.
Connect the VSS pattern to the microcomputer
V SS pin with the shortest possible wiring.
Besides, separate this VSS pattern from other
V SS patterns.
An example of VSS patterns on the
underside of a printed circuit board
AAAAAAA
AAA
AAAAAA
AAA
Oscillator wiring
pattern example
XIN
XOUT
VSS
<Software>
• As for an input port, read data several times by
a program for checking whether input levels are
equal or not.
• As for an output port or an I/O port, since the
output data may reverse because of noise, rewrite
data to its output latch at fixed periods.
• Rewrite data to pull-up control registers at fixed
periods.
3.4.6 Providing of watchdog timer function by
software
If a microcomputer runs away because of noise or
others, it can be detected by a software watchdog
timer and the microcomputer can be reset to normal
operation. This is equal to or more effective than
program runaway detection by a hardware watchdog
timer. The following shows an example of a watchdog
timer provided by software.
In the following example, to reset a microcomputer
to normal operation, the main routine detects errors
of the interrupt processing routine and the interrupt
processing routine detects errors of the main routine.
This example assumes that interrupt processing is
repeated multiple times in a single main routine
processing.
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 V SS pattern on the underside of an
oscillator
3-28
4513/4514 Group User’s Manual
APPENDIX
3.4 Notes on noise
<The main routine>
• Assigns a single word of RAM to a software
watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the
main routine. The initial value N should satisfy
the following condition:
N+1≥
(Counts of interrupt processing executed in
each main routine)
As the main routine execution cycle may change
because of an interrupt processing or others, the
initial value N should have a margin.
• Watches the operation of the interrupt processing
routine by comparing the SWDT contents with
counts of interrupt processing after the initial value
N has been set.
• Detects that the interrupt processing routine has
failed and determines to branch to the program
initialization routine for recovery processing in the
following case:
If the SWDT contents do not change after interrupt
processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each
interrupt processing.
• Determines that the main routine operates normally
when the SWDT contents are reset to the initial
value N at almost fixed cycles (at the fixed interrupt
processing count).
• Detects that the main routine has failed and
determines to branch to the program initialization
routine for recovery processing in the following
case:
If the SWDT contents are not initialized to the
initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
EI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
≤0
>0
RTI
Return
Main routine
errors
Fig. 3.4.11 Watchdog timer by software
4513/4514 Group User’s Manual
3-29
APPENDIX
3.5 Mask ROM order confirmation form
3.5 Mask ROM order confirmation form
GZZ-SH52-45B <81A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34513M2-XXXSP/FP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽ .
✽ Customer
TEL (
Date
issued
Issuance
signature
Company
name
)
Date:
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✽ 1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Microcomputer name:
M34513M2-XXXSP
M34513M2-XXXFP
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
Low-order
5-bit data
High-order
5-bit data
000016
2.00K
07FF16
400016 2.00K
47FF16
Low-order
5-bit data
High-order
5-bit data
7FFF16
0000 16
2.00K
07FF16
4000 16
2.00K
47FF16
FFFF16
Set “FF16” in the shaded area.
Set “111 2” in the area
of low-order and high-order 5-bit data.
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (32P4B for M34513M2-XXXSP, 32P6B-A for
M34513M2-XXXFP) and attach to the Mask ROM Order Confirmation Form.
✽ 3. Comments
3-30
4513/4514 Group User’s Manual
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-44B <81A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34513M4-XXXSP/FP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽ .
✽ Customer
TEL (
Date
issued
Issuance
signature
Company
name
)
Date:
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✽ 1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Microcomputer name:
M34513M4-XXXSP
M34513M4-XXXFP
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
4.00K
0FFF16
400016 4.00K
4FFF16
7FFF16
Low-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
High-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
000016
4.00K
0FFF16
400016
4.00K
4FFF16
FFFF16
Set “FF16 ” in the shaded area.
Set “111 2 ” in the area
of low-order and high-order 5-bit data.
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (32P4B for M34513M4-XXXSP, 32P6B-A for
M34513M4-XXXFP) and attach to the Mask ROM Order Confirmation Form.
✽ 3. Comments
4513/4514 Group User’s Manual
3-31
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH53-01B <85A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34513M6-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽ .
✽ Customer
TEL (
Date
issued
Issuance
signature
Company
name
)
Date:
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✽ 1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
6.00K
17FF16
400016 6.00K
57FF16
7FFF16
Low-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
High-order
5-bit data
1234567890123456789012345
000016
6.00K
17FF16
400016
6.00K
1234567890123456789012345 57FF16
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
FFFF16
Set “FF16 ” in the shaded area.
Set “111 2 ” in the area
of low-order and high-order 5-bit data.
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (32P6B-A for M34513M6-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✽ 3. Comments
3-32
4513/4514 Group User’s Manual
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-99B <85A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34513M8-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽ .
✽ Customer
TEL (
Date
issued
Issuance
signature
Company
name
)
Date:
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✽ 1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
8.00K
1FFF16
400016 8.00K
5FFF16
7FFF16
Low-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
High-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
000016
8.00K
1FFF16
400016
8.00K
5FFF16
FFFF16
Set “FF16 ” in the shaded area.
Set “111 2 ” in the area
of low-order and high-order 5-bit data.
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (32P6B-A for M34513M8-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✽ 3. Comments
4513/4514 Group User’s Manual
3-33
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-41B <81A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34514M6-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽ .
✽ Customer
TEL (
Date
issued
Issuance
signature
Company
name
)
Date:
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✽ 1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
6.00K
17FF16
400016 6.00K
57FF16
7FFF16
Low-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
High-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
000016
6.00K
17FF16
400016
6.00K
57FF16
FFFF16
Set “FF16 ” in the shaded area.
Set “111 2 ” in the area
of low-order and high-order 5-bit data.
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (42P2R-A for M34514M6-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✽ 3. Comments
3-34
4513/4514 Group User’s Manual
APPENDIX
3.5 Mask ROM order confirmation form
GZZ-SH52-40B <81A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34514M8-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✽ .
✽ Customer
TEL (
Date
issued
Issuance
signature
Company
name
)
Date:
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✽ 1. Confirmation
Specify the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
8.00K
1FFF16
400016 8.00K
5FFF16
7FFF16
Low-order
5-bit data
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
High-order
5-bit data
1234567890123456789012345
000016
8.00K
1FFF16
400016
8.00K
1234567890123456789012345 5FFF16
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
FFFF16
Set “FF16 ” in the shaded area.
Set “111 2 ” in the area
of low-order and high-order 5-bit data.
✽ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (42P2R-A for M34514M8-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✽ 3. Comments
4513/4514 Group User’s Manual
3-35
APPENDIX
3.6 Mark specification form
3.6 Mark specification form
32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
17
32
Mitsubishi lot number
(6-digit or 7-digit)
Mitsubishi IC catalog name
1
16
B. Customer’s Parts Number + Mitsubishi catalog name
17
32
Customer’s Parts Number
Note : The fonts and size of characters
are standard Mitsubishi type.
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
1
Note1 :
2:
3:
4:
16
The mark field should be written right aligned.
The fonts and size of characters are standard Mitsubishi type.
Customer’s Parts Number can be up to 16 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &, , (periods), and (commas) are usable.
If the Mitsubishi logo
is not required, check the box on the right.
Mitsubishi logo is not required
.
,
C. Special Mark Required
32
17
1
16
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as
close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the Special Mark, check the
Special logo required
box on the right. Please submit a clean original of the logo. For the new special
character fonts a clean font original (ideally logo drawing) must be submitted.
3 : The standard Mitsubishi font is used for all characters except for a logo.
3-36
4513/4514 Group User’s Manual
APPENDIX
3.6 Mark specification form
32P6B (32-PIN LQFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
17
24
16
25
Mitsubishi IC catalog name
Mitsubishi IC catalog name
Mitsubishi lot number
(4-digit or 5-digit)
32
9
1
8
B. Customer’s Parts Number + Mitsubishi catalog name
24
17
16
25
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 7 characters : Only 0 ~
9, A ~ Z, +, –, /, (, ), &, , (periods), (commas) are usable.
.
32
,
9
1
8
4513/4514 Group User’s Manual
3-37
APPENDIX
3.6 Mark specification form
42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
42
22
Mitsubishi IC catalog name
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
21
1
B. Customer’s Parts Number + Mitsubishi catalog name
42
22
Mitsubishi lot number
(6-digit or 7-digit)
1
21
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 11 characters : Only 0 ~
9, A ~ Z, +, –, /, (, ), &, , (periods), (commas) are usable.
4 : If the Mitsubishi logo
is not required, check the box below.
Mitsubishi logo is not required
.
,
C. Special Mark Required
42
22
1
21
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the
Special Mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
Special logo required
3-38
4513/4514 Group User’s Manual
APPENDIX
3.7 Package outline
3.7 Package outline
32P4B
Plastic 32pin 400mil SDIP
EIAJ Package Code
SDIP32-P-400-1.78
Weight(g)
2.2
Lead Material
Alloy 42/Cu Alloy
17
1
16
E
32
e1
c
JEDEC Code
–
D
Symbol
L
A1
A
A2
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
e
b1
b
b2
SEATING PLANE
32P6B-A
Dimension in Millimeters
Min
Nom
Max
–
–
5.08
0.51
–
–
–
3.8
–
0.35
0.45
0.55
0.9
1.0
1.3
0.63
0.73
1.03
0.22
0.27
0.34
27.8
28.0
28.2
8.75
8.9
9.05
–
1.778
–
–
10.16
–
3.0
–
–
0°
–
15°
Plastic 32pin 7✕7mm body LQFP
EIAJ Package Code
LQFP32-P-77-0.80
Weight(g)
Lead Material
Alloy 42
MD
e
JEDEC Code
–
b2
ME
HD
D
32
25
I2
1
24
E
HE
Recommended Mount Pad
Symbol
17
8
9
16
A
L1
e
y
b
A1
c
A2
F
L
Detail F
4513/4514 Group User’s Manual
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
1.7
–
–
0.1
0.2
0
1.4
–
–
0.3
0.35
0.45
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
0.8
–
–
8.8
9.0
9.2
8.8
9.0
9.2
0.3
0.5
0.7
1.0
–
–
0.1
–
–
0°
10°
–
0.5
–
–
1.0
–
–
–
–
7.4
–
–
7.4
3-39
APPENDIX
3.7 Package outline
42P2R-A
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
JEDEC Code
–
Weight(g)
0.63
Lead Material
Alloy 42/Cu Alloy
e
42
b2
E
HE
e1
I2
22
F
Recommended Mount Pad
Symbol
1
21
A
D
b
L
y
A1
L1
e
A2
c
Detail F
3-40
4513/4514 Group User’s Manual
A
A1
A2
b
c
D
E
e
HE
L
L1
y
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
2.4
–
–
–
–
0.05
–
2.0
–
0.5
0.4
0.35
0.2
0.15
0.13
17.7
17.5
17.3
8.6
8.4
8.2
–
0.8
–
12.23
11.93
11.63
0.7
0.5
0.3
–
1.765
–
0.15
–
–
0°
–
10°
–
0.5
–
–
11.43
–
–
1.27
–
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
4513/4514 Group
Dec. First Edition 1998
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1998 MITSUBISHI ELECTRIC CORPORATION
REVISION DESCRIPTION LIST
Rev.
No.
1.0
4513/4514 GROUP USER'S MANUAL
Revision Description
First Edition
Rev.
date
981211
(1/1)
User’s Manual
4513/4514 Group
© 1998 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Dec. 1998.
Specifications subject to change without notice.