RENESAS M34524M8

REJ09B0107-0200Z
4524 Group
4
User's Manual
RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER
720 FAMILY / 4500 SERIES
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 2.00
Revision date: Aug 06, 2004
www.renesas.com
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1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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These materials are intended as a reference to assist our customers in the selection of the
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REVISION HISTORY
Rev.
Date
Description
Page
1.00 Dec 19, 2003
4524 Group User’s Manual
–
2.00 Aug 06, 2004 All pages
1-5
1-6
1-35
1-45
1-46
1-47
1-61
1-65
1-69
1-78
2-57
2-74
2-77
3-47
Summary
First edition issued
Words standardized: On-chip oscillator, A/D converter
Power dissipation
revised.
____________
Description of RESET pin revised.
Fig.26 : Note 9 added.
Some description revised.
Fig.31: “DI” instruction added.
Table 11:Revised.
(5) LCD power supply circuit revised.
Fig.51: State of quartz-crystal oscillator added.
Fig.55:
• Note 5 added,
• “T5F” added to the transitions between from state E to states B, A, C and D
• “Key-on wakeup”→“Wakeup”
Note on Power source Voltage added.
Table 2.5.1 : Notes 4 revised.
Fig.2.7.4: State of quartz-crystal oscillator added.
Fig.2.9.1:
• Note 5 added,
• “T5F” added to the transitions between from state E to states B, A, C and D
• “Key-on wakeup”→“Wakeup”
Note on Power source Voltage added.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting
examples of related registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the list of registers.
As for the Mask ROM confirmation form, the ROM programming confirmation form, and the Mark specification
form which are to be submitted when ordering, refer to the “Renesas Technology Corp.” Hompage (http:/
/www.renesas.com/en/rom).
As for the Development tools and related documents, refer to the Product Info - 4524 Group (http://
www.renesas.com/eng/products/mpumcu/specific/lcd_mcu/expand/e4524.htm) of “Renesas Technology
Corp.” Homepage.
Table of contents
4524 Group
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................... 2
FEATURES ......................................................................................................................................... 2
APPLICATION ................................................................................................................................... 2
PIN CONFIGURATION ..................................................................................................................... 3
BLOCK DIAGRAM ............................................................................................................................ 4
PERFORMANCE OVERVIEW .......................................................................................................... 5
PIN DESCRIPTION ........................................................................................................................... 6
MULTIFUNCTION ........................................................................................................................ 7
DEFINITION OF CLOCK AND CYCLE .................................................................................... 7
PORT FUNCTION ....................................................................................................................... 8
CONNECTIONS OF UNUSED PINS ........................................................................................ 9
PORT BLOCK DIAGRAMS ...................................................................................................... 10
FUNCTION BLOCK OPERATIONS .............................................................................................. 18
CPU ............................................................................................................................................. 18
PROGRAM MEMORY (ROM) .................................................................................................. 21
DATA MEMORY (RAM) ............................................................................................................ 22
INTERRUPT FUNCTION .......................................................................................................... 23
EXTERNAL INTERRUPTS ....................................................................................................... 27
TIMERS ...................................................................................................................................... 32
WATCHDOG TIMER ................................................................................................................. 45
A/D CONVERTER (COMPARATOR) ...................................................................................... 47
SERIAL I/O ................................................................................................................................. 53
LCD FUNCTION ........................................................................................................................ 57
RESET FUNCTION ................................................................................................................... 62
VOLTAGE DROP DETECTION CIRCUIT .............................................................................. 66
POWER DOWN FUNCTION .................................................................................................... 67
CLOCK CONTROL .................................................................................................................... 72
ROM ORDERING METHOD .......................................................................................................... 74
LIST OF PRECAUTIONS ............................................................................................................... 75
CONTROL REGISTERS ................................................................................................................. 79
INSTRUCTIONS ............................................................................................................................... 86
SYMBOL ..................................................................................................................................... 86
INDEX LIST OF INSTRUCTION FUNCTION ........................................................................ 87
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) .......................................................... 92
MACHINE INSTRUCTIONS (INDEX BY TYPES) (CONTINUED) ..................................... 132
INSTRUCTION CODE TABLE ............................................................................................... 148
BUILT-IN PROM VERSION ......................................................................................................... 150
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Table of contents
4524 Group
CHAPTER 2 APPLICATION
2.1 I/O pins ....................................................................................................................................... 2
2.1.1 I/O ports ............................................................................................................................. 2
2.1.2 Related registers ............................................................................................................... 5
2.1.3 Port application examples .............................................................................................. 13
2.1.4 Notes on use ................................................................................................................... 14
2.2 Interrupts .................................................................................................................................. 16
2.2.1 Interrupt functions ........................................................................................................... 16
2.2.2 Related registers ............................................................................................................. 19
2.2.3 Interrupt application examples ....................................................................................... 22
2.2.4 Notes on use ................................................................................................................... 32
2.3 Timers ....................................................................................................................................... 33
2.3.1 Timer functions ................................................................................................................ 33
2.3.2 Related registers ............................................................................................................. 34
2.3.3 Timer application examples ........................................................................................... 39
2.3.4 Notes on use ................................................................................................................... 49
2.4 A/D converter .......................................................................................................................... 50
2.4.1 Related registers ............................................................................................................. 51
2.4.2 A/D converter application examples ............................................................................. 52
2.4.3 Notes on use ................................................................................................................... 54
2.5 Serial I/O ................................................................................................................................... 56
2.5.1 Carrier functions .............................................................................................................. 56
2.5.2 Related registers ............................................................................................................. 57
2.5.3 Operation description ...................................................................................................... 59
2.5.4 Serial I/O application example ...................................................................................... 62
2.5.5 Notes on use ................................................................................................................... 65
2.6 LCD function ............................................................................................................................ 66
2.6.1 Operation description ...................................................................................................... 66
2.6.2 Related registers ............................................................................................................. 67
2.6.3 LCD application examples ............................................................................................. 69
2.6.4 Notes on use ................................................................................................................... 71
2.7 Reset .......................................................................................................................................... 72
2.7.1 Reset circuit ..................................................................................................................... 72
2.7.2 Internal state at reset ..................................................................................................... 73
2.7.3 Notes on use ................................................................................................................... 74
2.8 Voltage drop detection circuit ............................................................................................. 75
2.8.1 Note on use ..................................................................................................................... 76
2.9 Power down ............................................................................................................................. 77
2.9.1 Power down mode .......................................................................................................... 78
2.9.2 Related registers ............................................................................................................. 81
2.9.3 Power down function application example .................................................................. 85
2.9.4 Notes on use ................................................................................................................... 86
2.10 Oscillation circuit ................................................................................................................. 87
2.10.1 Oscillation circuit ........................................................................................................... 87
2.10.2 Oscillation operation ..................................................................................................... 89
2.10.3 Related register ............................................................................................................. 90
2.10.4 Notes on use ................................................................................................................. 90
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Table of contents
4524 Group
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ........................................................................................................ 2
3.1.1 Absolute maximum ratings ............................................................................................... 2
3.1.2 Recommended operating conditions ............................................................................... 3
3.1.3 Electrical characteristics ................................................................................................... 5
3.1.4 A/D converter recommended operating conditions ....................................................... 7
3.1.5 Voltage drop detection circuit characteristics ................................................................ 8
3.1.6 Basic timing diagram ........................................................................................................ 8
3.2 Typical characteristics ............................................................................................................ 9
3.2.1 V DD–IDD characteristics ...................................................................................................... 9
3.2.2 Frequency characteristics ............................................................................................... 15
3.2.3 Port typical characteristics (V DD = 5.0 V) .................................................................... 18
3.2.4 Port typical characteristics (V DD = 3.0 V) .................................................................... 21
3.2.5 Input threshold characteristics ....................................................................................... 24
3.2.6 Pull-up resistor: VDD–RPU characteristics example .................................................... 27
3.2.7 Internal resistor for LCD power: Ta–RVLC ................................................................. 28
3.2.8 A/D converter typical characteristics ............................................................................ 29
3.2.9 Analog input current characteristics example ............................................................. 32
3.2.10 A/D converter operation current (V DD–I ADD) characteristics ...................................... 36
3.2.11 Voltage drop detection circuit characteristics ........................................................... 36
3.3 List of precautions ................................................................................................................. 38
3.3.1 Program counter .............................................................................................................. 38
3.3.2 Stack registers (SKs) ...................................................................................................... 38
3.3.3 Notes on I/O port ............................................................................................................ 38
3.3.4 Notes on interrupt ........................................................................................................... 41
3.3.5 Notes on timer ................................................................................................................. 42
3.3.6 Notes on A/D conversion ............................................................................................... 43
3.3.7 Notes on serial I/O ......................................................................................................... 44
3.3.8 Notes on LCD function ................................................................................................... 45
3.3.9 Notes on reset ................................................................................................................. 45
3.3.10 Notes on voltage drop detection circuit ..................................................................... 45
3.3.11 Notes on power down .................................................................................................. 46
3.3.12 Notes on oscillation circuit ........................................................................................... 47
3.3.13 Electric characteristic differences between Mask ROM and One Time PROM version MCU ... 47
3.3.14 Notes on Power Source Voltage ................................................................................ 47
3.4 Notes on noise ........................................................................................................................ 48
3.4.1 Shortest wiring length ..................................................................................................... 48
3.4.2 Connection of bypass capacitor across V SS line and V DD line .................................. 50
3.4.3 wiring to analog input pins ............................................................................................ 51
3.4.4 Oscillator concerns .......................................................................................................... 51
3.4.5 setup for I/O ports .......................................................................................................... 52
3.4.6 providing of watchdog timer function by software ...................................................... 52
3.5 Package outline ...................................................................................................................... 54
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List of figures
4524 Group
List of figures
CHAPTER 1 HARDWARE
Pin configuration (top view) (4524 Group) .................................................................................... 3
Block diagram (4524 Group) ........................................................................................................... 4
Port block diagram (1) .................................................................................................................... 10
Port block diagram (2) .................................................................................................................... 11
Port block diagram (3) .................................................................................................................... 12
Port block diagram (4) .................................................................................................................... 13
Port block diagram (5) .................................................................................................................... 14
Port block diagram (6) .................................................................................................................... 15
Port block diagram (7) .................................................................................................................... 16
Port block diagram (8) .................................................................................................................... 17
Fig. 1 AMC instruction execution example .................................................................................. 18
Fig. 2 RAR instruction execution example .................................................................................. 18
Fig. 3 Registers A, B and register E ........................................................................................... 18
Fig. 4 TABP p instruction execution example ............................................................................. 18
Fig. 5 Stack registers (SKs) structure .......................................................................................... 19
Fig. 6 Example of operation at subroutine call .......................................................................... 19
Fig. 7 Program counter (PC) structure ........................................................................................ 20
Fig. 8 Data pointer (DP) structure ................................................................................................ 20
Fig. 9 SD instruction execution example ..................................................................................... 20
Fig. 10 ROM map of M34524ED .................................................................................................. 21
Fig. 11 Page 1 (addresses 008016 to 00FF 16) structure ............................................................ 21
Fig. 12 RAM map ............................................................................................................................ 22
Fig. 13 Program example of interrupt processing ...................................................................... 24
Fig. 14 Internal state when interrupt occurs ............................................................................... 24
Fig. 15 Interrupt system diagram .................................................................................................. 24
Fig. 16 Interrupt sequence ............................................................................................................. 26
Fig. 17 External interrupt circuit structure ................................................................................... 27
Fig. 18 External 0 interrupt program example-1 ......................................................................... 30
Fig. 19 External 0 interrupt program example-2 ......................................................................... 30
Fig. 20 External 0 interrupt program example-3 ......................................................................... 30
Fig. 21 External 1 interrupt program example-1 ......................................................................... 31
Fig. 22 External 1 interrupt program example-2 ......................................................................... 31
Fig. 23 External 1 interrupt program example-3 ......................................................................... 31
Fig. 24 Auto-reload function .......................................................................................................... 32
Fig. 25 Timer structure (1) ............................................................................................................ 34
Fig. 26 Timer structure (2) ............................................................................................................ 35
Fig. 27 Timer 4 operation (reload register R4L: “03 16”, R4H: “0216”) ...................................... 42
Fig. 28 CNTR1 output auto-control function by timer 3 ............................................................ 43
Fig. 29 Timer 4 count start/stop timing ....................................................................................... 44
Fig. 30 Watchdog timer function ................................................................................................... 45
Fig. 31 Program example to start/stop watchdog timer ............................................................ 46
Fig. 32 Program example to enter the mode when using the watchdog timer ..................... 46
Fig. 33 A/D conversion circuit structure ...................................................................................... 47
Fig. 34 A/D conversion timing chart ............................................................................................. 50
Fig. 35 Setting registers ................................................................................................................. 50
Fig. 36 Comparator operation timing chart .................................................................................. 51
Fig. 37 Definition of A/D conversion accuracy ........................................................................... 52
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List of figures
4524 Group
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Serial I/O structure ............................................................................................................ 53
Serial I/O register state when transfer ........................................................................... 54
Serial I/O connection example ......................................................................................... 55
Timing of serial I/O data transfer .................................................................................... 55
LCD clock control circuit structure .................................................................................. 57
LCD controller/driver ......................................................................................................... 58
LCD RAM map ................................................................................................................... 59
LCD controller/driver structure ......................................................................................... 60
LCD power source circuit example (1/3 bias condition selected) .............................. 61
Reset release timing ......................................................................................................... 62
RESET pin input waveform and reset operation .......................................................... 62
Structure of reset pin and its peripherals, and power-on reset operation ................ 63
Internal state at reset ....................................................................................................... 64
Internal state at reset ....................................................................................................... 65
Voltage drop detection reset circuit ................................................................................ 66
Voltage drop detection circuit operation waveform ....................................................... 66
VDD and VRST ............................................................................................................................................................................................................... 66
State transition ................................................................................................................... 69
Set source and clear source of the P flag .................................................................... 69
Start condition identified example using the SNZP instruction ................................... 69
Clock control circuit structure .......................................................................................... 72
Switch to ceramic oscillation/RC oscillation ................................................................... 73
Handling of X IN and X OUT when operating on-chip oscillator ....................................... 73
Ceramic resonator external circuit .................................................................................. 73
External RC oscillation circuit .......................................................................................... 73
External clock input circuit ............................................................................................... 74
External quartz-crystal circuit ........................................................................................... 74
External 0 interrupt program example-1 ......................................................................... 76
External 0 interrupt program example-2 ......................................................................... 76
External 0 interrupt program example-3 ......................................................................... 76
External 1 interrupt program example-2 ......................................................................... 77
External 1 interrupt program example-3 ......................................................................... 77
A/D converter program example-3 .................................................................................. 77
Analog input external circuit example-1 ......................................................................... 78
Analog input external circuit example-2 ......................................................................... 78
VDD and VRST ............................................................................................................................................................................................................... 78
Pin configuration of built-in PROM version ................................................................. 150
PROM memory map ........................................................................................................ 151
Flow of writing and test of the product shipped in blank .......................................... 151
CHAPTER 2 APPLICATION
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2.1.1
2.1.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Key input by key scan .................................................................................................. 13
Key scan input timing ................................................................................................... 13
External 0 interrupt operation example ...................................................................... 23
External 0 interrupt setting example .......................................................................... 24
External 1 interrupt operation example ...................................................................... 25
External 1 interrupt setting example .......................................................................... 26
Timer 1 constant period interrupt setting example ................................................... 27
Timer 2 constant period interrupt setting example ................................................... 28
Timer 3 constant period interrupt setting example ................................................... 29
Timer 4 constant period interrupt setting example ................................................... 30
Timer 5 constant period interrupt setting example ................................................... 31
v
List of figures
4524 Group
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2.3.1 Peripheral circuit example ............................................................................................ 39
2.3.2 Timer 4 operation .......................................................................................................... 40
2.3.3 Watchdog timer function ............................................................................................... 41
2.3.4 Constant period measurement setting example ........................................................ 42
2.3.5 CNTR 0 output setting example .................................................................................... 43
2.3.6 CNTR 0 input setting example ...................................................................................... 44
2.3.7 Timer start by external input setting example .......................................................... 45
2.3.8 PWM output control setting example ......................................................................... 46
2.3.9 Constant period counter by timer 5 setting example ............................................... 47
2.3.10 Watchdog timer setting example ............................................................................... 48
2.4.1 A/D converter structure ................................................................................................ 50
2.4.2 A/D conversion mode setting example ....................................................................... 53
2.4.3 Analog input external circuit example-1 ..................................................................... 54
2.4.4 Analog input external circuit example-2 ..................................................................... 54
2.4.5 A/D converter operating mode program example ..................................................... 54
2.5.1 Serial I/O block diagram .............................................................................................. 56
2.5.2 Serial I/O connection example .................................................................................... 59
2.5.3 Serial I/O register state when transfer ....................................................................... 59
2.5.4 Serial I/O transfer timing .............................................................................................. 60
2.5.5 Setting example when a serial I/O of master side is not used ............................. 63
2.5.6 Setting example when a serial I/O interrupt of slave side is used ....................... 64
2.6.1 LCD clock control circuit structure .............................................................................. 66
2.6.2 LCD RAM map .............................................................................................................. 67
2.6.3 LCD display panel example ......................................................................................... 69
2.6.4 Segment assignment example ..................................................................................... 69
2.6.5 LCD RAM assignment example .................................................................................. 69
2.6.6 Initial setting example ................................................................................................... 70
2.7.1 Structure of reset pin and its peripherals,, and power-on reset operation ........... 72
2.7.2 Oscillation stabilizing time after system is released from reset ............................. 72
2.7.3 Internal state at reset ................................................................................................... 73
2.7.4 Internal state at reset ................................................................................................... 74
2.8.1 Voltage drop detection circuit ...................................................................................... 75
2.8.2 Voltage drop detection circuit operation waveform example .................................. 75
2.8.3 V DD and V RST ....................................................................................................................................................................................................... 76
2.9.1 State transition ............................................................................................................... 77
2.9.2 Start condition identified example ............................................................................... 80
2.9.3 Software setting example ............................................................................................. 85
2.10.1 Switch to ceramic oscillation/RC oscillation ............................................................ 87
2.10.2 Handling of X IN and X OUT when operating on-chip oscillator ................................. 87
2.10.3 Ceramic resonator external circuit ............................................................................ 88
2.10.4 External RC oscillation circuit ................................................................................... 88
2.10.5 External clock input circuit ......................................................................................... 88
2.10.6 External quartz-crystal circuit .................................................................................... 88
2.10.7 Structure of clock control circuit ............................................................................... 89
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List of figures
4524 Group
CHAPTER 3 APPENDIX
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3.2.1 A/D conversion characteristics data ........................................................................... 29
3.3.1 Analog input external circuit example-1 ..................................................................... 43
3.3.2 Analog input external circuit example-2 ..................................................................... 43
3.3.3 A/D converter operating mode program example ..................................................... 43
3.3.4 V DD and V RST ....................................................................................................................................................................................................... 45
3.4.1 Selection of packages .................................................................................................. 48
3.4.2 Wiring for the RESET input pin .................................................................................. 48
3.4.3 Wiring for clock I/O pins .............................................................................................. 49
3.4.4 Wiring for CNV SS pin ..................................................................................................... 49
3.4.5 Wiring for the V PP pin of the built-in PROM version ................................................ 50
3.4.6 Bypass capacitor across the V SS line and the V DD line ........................................... 50
3.4.7 Analog signal line and a resistor and a capacitor ................................................... 51
3.4.8 Wiring for a large current signal line ......................................................................... 51
3.4.9 Wiring to a signal line where potential levels change frequently .......................... 52
3.4.10 V SS pattern on the underside of an oscillator ......................................................... 52
3.4.11 Watchdog timer by software ...................................................................................... 53
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List of tables
4524 Group
List of tables
CHAPTER 1 HARDWARE
Table
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Table
Table
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Table
Table
Table
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Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Selection of system clock ..................................................................................................... 7
1 ROM size and pages ....................................................................................................... 21
2 RAM size ........................................................................................................................... 22
3 Interrupt sources ............................................................................................................... 23
4 Interrupt request flag, interrupt enable bit and skip instruction ................................. 23
5 Interrupt enable bit function ............................................................................................ 23
6 Interrupt control registers ................................................................................................ 25
7 External interrupt activated conditions ........................................................................... 27
8 External interrupt control register ................................................................................... 29
9 Function related timers .................................................................................................... 33
10 Timer related registers ................................................................................................... 36
11 A/D converter characteristics ........................................................................................ 47
12 A/D control registers ...................................................................................................... 48
13 Change of successive comparison register AD during A/D conversion ................. 49
14 Serial I/O pins ................................................................................................................. 53
15 Serial I/O control register .............................................................................................. 53
16 Processing sequence of data transfer from master to slave ................................... 56
17 Duty and maximum number of displayed pixels ........................................................ 57
18 LCD control registers ..................................................................................................... 59
19 Port state at reset .......................................................................................................... 63
20 Voltage drop detection circuit operation state ............................................................ 66
21 Functions and states retained at power down ........................................................... 67
22 Return source and return condition ............................................................................. 68
23 Key-on wakeup control register, pull-up control register and interrupt control register ...... 70
24 Clock control register MR ............................................................................................. 74
25 Product of built-in PROM version .............................................................................. 150
CHAPTER 2 APPLICATION
Table
Table
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Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2.1.1 Timer control register W3 ........................................................................................... 5
2.1.2 Timer control register W4 ........................................................................................... 5
2.1.3 Timer control register W6 ........................................................................................... 6
2.1.4 Serial I/O control register J1 ...................................................................................... 6
2.1.5 A/D control register Q2 ............................................................................................... 7
2.1.6 A/D control register Q3 ............................................................................................... 7
2.1.7 Pull-up control register PU0 ....................................................................................... 8
2.1.8 Pull-up control register PU1 ....................................................................................... 8
2.1.9 Port output structure control register FR0 ................................................................ 9
2.1.10 Port output structure control register FR1 .............................................................. 9
2.1.11 Port output structure control register FR2 ............................................................ 10
2.1.12 Port output structure control register FR3 ............................................................ 10
2.1.13 Key-on wakeup control register K0 ....................................................................... 11
2.1.14 Key-on wakeup control register K1 ....................................................................... 11
2.1.15 Key-on wakeup control register K2 ....................................................................... 12
2.1.16 Connections of unused pins ................................................................................... 15
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viii
List of tables
4524 Group
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2.2.1 Interrupt control register V1 ...................................................................................... 19
2.2.2 Interrupt control register V2 ...................................................................................... 20
2.2.3 Interrupt control register I1 ....................................................................................... 20
2.2.4 Interrupt control register I2 ....................................................................................... 21
2.2.5 Interrupt control register I3 ....................................................................................... 21
2.3.1 Interrupt control register V1 ...................................................................................... 34
2.3.2 Interrupt control register V2 ...................................................................................... 34
2.3.3 Interrupt control register I3 ....................................................................................... 35
2.3.4 Timer control register PA .......................................................................................... 35
2.3.5 Timer control register W1 ......................................................................................... 35
2.3.6 Timer control register W2 ......................................................................................... 36
2.3.7 Timer control register W3 ......................................................................................... 36
2.3.8 Timer control register W4 ......................................................................................... 37
2.3.9 Timer control register W5 ......................................................................................... 37
2.3.10 Timer control register W6 ....................................................................................... 38
2.4.1 Interrupt control register V2 ...................................................................................... 51
2.4.2 A/D control register Q1 ............................................................................................. 51
2.4.3 A/D control register Q2 ............................................................................................. 52
2.4.4 A/D control register Q3 ............................................................................................. 52
2.4.5 Recommended operating conditions (when using A/D converter) ...................... 55
2.5.1 Interrupt control register V2 ...................................................................................... 57
2.5.2 Interrupt control register I3 ....................................................................................... 57
2.5.3 Serial I/O mode register J1 ...................................................................................... 58
2.6.1 Duty and maximum number of displayed pixels .................................................... 66
2.6.2 LCD control register L1 ............................................................................................. 67
2.6.3 LCD control register L2 ............................................................................................. 68
2.6.4 Timer control register W6 ......................................................................................... 68
2.8.1 Voltage drop detection circuit operation state ....................................................... 75
2.9.1 Functions and states retained at power down mode ............................................ 79
2.9.2 Return source and return condition ......................................................................... 80
2.9.3 Start condition identification ...................................................................................... 80
2.9.4 Interrupt control register I1 ....................................................................................... 81
2.9.5 Interrupt control register I2 ....................................................................................... 81
2.9.6 Clock control register MR ......................................................................................... 82
2.9.7 Pull-up control register PU0 ..................................................................................... 82
2.9.8 Pull-up control register PU1 ..................................................................................... 83
2.9.9 Key-on wakeup control register K0 ......................................................................... 83
2.9.10 Key-on wakeup control register K1 ....................................................................... 84
2.9.11 Key-on wakeup control register K2 ....................................................................... 84
2.10.1 Clock control register MR ....................................................................................... 90
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.3.1
3.3.2
Rev.2.00 Aug, 06 2004
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Absolute maximum ratings .......................................................................................... 2
Recommended operating conditions 1 ...................................................................... 3
Recommended operating conditions 2 ...................................................................... 4
Electrical characteristics 1 .......................................................................................... 5
Electrical characteristics 2 .......................................................................................... 6
A/D converter recommended operating conditions .................................................. 7
A/D converter characteristics ...................................................................................... 7
Voltage drop detection circuit characteristics ........................................................... 8
Connections of unused pins ..................................................................................... 40
Recommended operating conditions (when using A/D converter) ...................... 44
ix
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
BLOCK DIAGRAM
PERFORMANCE OVERVIEW
PIN DESCRIPTION
FUNCTION BLOCK OPERATIONS
ROM ORDERING METHOD
LIST OF PRECAUTIONS
CONTROL REGISTERS
INSTRUCTIONS
BUILT-IN PROM VERSION
HARDWARE
DESCRIPTION/FEATURES/APPLICATION
4524 Group
DESCRIPTION
The 4524 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
main clock selection function, serial I/O, four 8-bit timers (each
timer has one or two reload registers), 10-bit A/D converter, interrupts, and LCD control circuit.
The various microcomputers in the 4524 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
●Minimum instruction execution time .................................. 0.5 µs
(at 6 MHz oscillation frequency, in high-speed through-mode)
●Supply voltage
Mask ROM version ...................................................... 2.0 to 5.5 V
One Time PROM version ............................................. 2.5 to 5.5 V
(It depends on oscillation frequency and operation mode)
●Timers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ...................................... 8-bit timer with a reload register
Timer 3 ...................................... 8-bit timer with a reload register
Timer 4 ................................. 8-bit timer with two reload registers
Timer 5 .............................. 16-bit timer (fixed dividing frequency)
Part number
M34524M8-XXXFP
M34524MC-XXXFP
M34524EDFP (Note)
ROM (PROM) size
(✕ 10 bits)
8192 words
12288 words
16384 words
● Interrupt ........................................................................ 9 sources
● Key-on wakeup function pins ................................................... 10
● LCD control circuit
Segment output ........................................................................ 20
Common output .......................................................................... 4
● Serial I/O ......................................................................... 8-bit ✕ 1
● A/D converter .............. 10-bit successive approximation method
● Voltage drop detection circuit (Reset) ......................... Typ. 3.5 V
● Watchdog timer
● Clock generating circuit
Main clock
(ceramic resonator/RC oscillation/on-chip oscillator)
Sub-clock
(quartz-crystal oscillation)
● LED drive directly enabled (port D)
APPLICATION
Household appliance, consumer electronics, office automation
equipment
RAM size
(✕ 4 bits)
512 words
512 words
512 words
Package
ROM type
64P6N-A
64P6N-A
64P6N-A
Mask ROM
Mask ROM
One Time PROM
Note: Shipped in blank.
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REJ09B0107-0200Z
1-2
HARDWARE
PIN CONFIGURATION
4524 Group
D3
D2
P13
D0
D1
P12
P11
P03
P10
P02
P01
P00
COM3
COM2
COM1
COM0
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VLC3/SEG0
VLC2/SEG1
VLC1/SEG2
SEG3
SEG4
SEG5
SEG6
49
32
D4/SIN
50
31
51
30
52
29
D5/SOUT
D6/SCK
C N VS S
VDCE
SEG7
SEG8
SEG9
56
SEG10
SEG11
SEG12
59
22
60
21
61
20
SEG13
SEG14
SEG15
62
19
63
18
64
17
53
28
54
27
55
26
25
M34524Mx-XXXFP
M34524EDFP
6
7
8
23
VDD
VSS
XOUT
XIN
RESET
D7/CNTR0
C/CNTR1
D8/INT0
D9/INT1
9 10 11 12 13 14 15 16
P20/AIN0
5
24
P21/AIN1
4
P22/AIN2
SEG17
SEG18
SEG19
P43
P42
3
P32/AIN6
P31/AIN5
P30/AIN4
P23/AIN3
2
P33/AIN7
1
SEG16
58
P41
P40
57
XCIN
XCOUT
OUTLINE 64P6N-A
Pin configuration (top view) (4524 Group)
Rev.2.00 Aug, 06 2004
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1-3
Rev.2.00 Aug, 06 2004
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Port P0
20
4
Common output
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1 level)
ALU(4 bits)
4500 series
CPU core
Port P2
4
1
Port C
2
Port D
512 words ✕ 4 bits
LCD display RAM
including 20 words ✕ 4 bits
RAM
8192, 12288, 16384 words
✕ 10 bits
ROM
Memory
Voltage drop detection circuit
Power-on reset circuit
4
Port P4
System clock generation circuit
XIN -XOUT
(Main clock)
XCIN -XCOUT
(Sub-clock)
Port P3
4
8
4524 Group
Segment output
LCD drive control circuit
(Max.20 segments ✕ 4 common)
Serial I/O
(8 bits ✕ 1)
A/D converter
(10 bits ✕ 8 ch)
Watchdog timer (16 bits)
Timer 1(8 bits)
Timer 2(8 bits)
Timer 3(8 bits)
Timer 4(8 bits)
Timer 5(16 bits)
Timer
4
Port P1
Internal peripheral functions
I/O port
4
HARDWARE
BLOCK DIAGRAM
Block diagram (4524 Group)
1-4
HARDWARE
PERFORMANCE OVERVIEW
4524 Group
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes ROM
M34524M8
M34524MC
M34524ED
RAM
Input/Output D0–D7
I/O
ports
D 8 , D9
Output
P00–P03 I/O
P10–P13 I/O
Timers
P20–P23
P30–P33
P40–P43
C
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
I/O
I/O
I/O
Output
A/D converter
Serial I/O
LCD control Selective bias value
circuit
Selective duty value
Common output
Segment output
Internal resistor for
power supply
Interrupt
Sources
Nesting
Subroutine nesting
Device structure
Package
Operating temperature range
Supply
Mask ROM version
voltage
One Time PROM version
Power
Active mode
dissipation
Clock operating mode
At RAM back-up
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Function
159
0.5 µs (at 6 MHz oscillation frequency, in high-speed through mode)
8192 words ✕ 10 bits
12288 words ✕ 10 bits
16384 words ✕ 10 bits
512 words ✕ 4 bits (including LCD display RAM 20 words ✕ 4 bits)
Eight independent I/O ports.
Input is examined by skip decision.
The output structure can be switched by software.
Ports D4, D5, D6 and D7 are also used as SIN, SOUT, SCK and CNTR0 pin.
Two independent output ports.
Ports D8 and D9 are also used as INT0 and INT1, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
by software.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
by software.
4-bit I/O port; Ports P20–P23 are also used as AIN0–AIN3, respectively.
4-bit I/O port; Ports P30–P33 are also used as AIN4–AIN7, respectively.
4-bit I/O port; The output structure can be switched by software.
1-bit output; Port C is also used as CNTR1 pin.
8-bit programmable timer with a reload register and has an event counter.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register and has an event counter.
8-bit programmable timer with two reload registers.
16-bit timer, fixed dividing frequency
10-bit ✕ 1, 8-bit comparator is equipped.
8-bit ✕ 1
1/2, 1/3 bias
2, 3, 4 duty
4
20
2r ✕ 3, 2r ✕ 2, r ✕ 3, r ✕ 2 (they can be switched by software.)
9 (two for external, five for timer, A/D, serial I/O)
1 level
8 levels
CMOS silicon gate
64-pin plastic molded QFP (64P6N)
–20 °C to 85 °C
2 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.)
2.5 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.)
2.8 mA (Ta=25°C, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN) = 32 kHz, f(STCK) = f(XIN))
20 µA (Ta=25°C, VDD = 5 V, f(XCIN) = 32 kHz)
0.1 µA (Ta=25°C, VDD = 5 V)
1-5
HARDWARE
PIN DESCRIPTION
4524 Group
PIN DESCRIPTION
Pin
VDD
RESET
Name
Power supply
Ground
CNVSS
Voltage drop
detection circuit
enable
Reset input/output
XIN
Main clock input
XOUT
Main clock output
XCIN
XCOUT
D0–D7
Sub-clock input
Sub-clock output
I/O port D
Input is examined by
skip decision.
Input
Output
I/O
D 8 , D9
Output port D
Output
P00–P03
I/O port P0
I/O
P10–P13
I/O port P1
I/O
P20–P23
I/O port P2
I/O
P30–P33
I/O port P3
I/O
P40–P43
I/O port P4
I/O
VSS
CNVSS
VDCE
Output port C
Port C
Common output
COM0–
COM3
SEG0–SEG19 Segment output
VLC3–VLC1 LCD power supply
Input/Output
—
—
—
Input
I/O
Input
Output
Output
Output
Output
–
I/O
CNTR0,
CNTR1
Timer input/output
INT0, INT1
Interrupt input
Input
AIN0–AIN7
Analog input
Input
SCK
SOUT
SIN
Serial I/O data I/O
Serial I/O data output
Serial I/O clock input
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
I/O
Output
Input
Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
This pin is used to operate/stop the voltage drop detection circuit. When “H“ level is
input to this pin, the circuit starts operating. When “L“ level is input to this pin, the
circuit stops operating.
An N-channel open-drain I/O pin for a system reset. When the watchdog timer, the
built-in power-on reset, or the voltage drop detection circuit causes the system to be
reset, the RESET pin outputs “L” level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins X IN and XOUT. A feedback resistor is built-in between them.
When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave
XOUT pin open.
I/O pins of the sub-clock generating circuit. Connect a 32 kHz quartz-crystal oscillator
between pins XCIN and XCOUT. A feedback resistor is built-in between them.
Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to “1” and select the N-channel open-drain. Ports D4–D7
is also used as SIN, SOUT, SCK and CNTR0 pin.
Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. Ports D8 and D9 are also used as INT0 pin and INT1
pin, respectively.
Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P0 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain. Port P1 has a key-on wakeup function and
a pull-up function. Both functions can be switched by software.
Port P2 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to “1”.
Ports P20–P23 are also used as AIN0–AIN3, respectively.
Port P3 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For
input use, set the latch of the specified bit to “1”.
Ports P30–P33 are also used as AIN4–AIN7, respectively.
Port P4 serves as a 4-bit I/O port. The output structure can be switched to N-channel
open-drain or CMOS by software. For input use, set the latch of the specified bit to
“1” and select the N-channel open-drain.
1-bit output port. The output structure is CMOS. Port C is also used as CNTR1 pin.
LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0–
COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty.
LCD segment output pins. SEG0–SEG2 pins are used as VLC3–VLC1 pins, respectively.
LCD power supply pins.
When the internal resistor is used, VDD pin is connected to VLC3 pin (if luminance adjustment is required, VDD pin is connected to VLC3 pin through a resistor).
When the external power supply is used, apply the voltage 0 ≤ VLC1 ≤ VLC2 ≤ VLC3 ≤ VDD.
VLC3–VLC1 pins are used as SEG0–SEG2 pins, respectively.
CNTR0 pin has the function to input the clock for the timer 1 event counter, and to
output the timer 1 or timer 2 underflow signal divided by 2.
CNTR1 pin has the function to input the clock for the timer 3 event counter, and to
output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also
used as Ports D7 and C, respectively.
INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as
Ports D8 and D9, respectively.
A/D converter analog input pins. AIN0–AIN7 are also used as ports P20–P23 and P30–
P33, respectively.
Serial I/O data transfer synchronous clock I/O pin. SCK pin is also used as port D6.
Serial I/O data output pin. SOUT pin is also used as port D5.
Serial I/O data input pin. SIN pin is also used as port D4.
1-6
HARDWARE
MULTIFUNCTION/DEFINITION OF CLOCK AND CYCLE
4524 Group
MULTIFUNCTION
Pin
D4
D5
D6
D7
D8
D9
VLC3
VLC2
VLC1
Multifunction
SIN
SOUT
SCK
CNTR0
INT0
INT1
SEG0
SEG1
SEG2
Pin
SIN
SOUT
SCK
CNTR0
INT0
INT1
SEG0
SEG1
SEG2
Multifunction
D4
D5
D6
D7
D8
D9
VLC3
VLC2
VLC1
Pin
C
P20
P21
P22
P23
P30
P31
P32
P33
Multifunction
CNTR1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Pin
CNTR1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Multifunction
C
P20
P21
P22
P23
P30
P31
P32
P33
Notes 1: Pins except above have just single function.
2: The output of D8 and D9 can be used even when INT0 and INT1 are selected.
3: The input of ports D4–D6 can be used even when SIN, SOUT and SCK are selected.
4: The input/output of D7 can be used even when CNTR0 (input) is selected.
5: The input of D7 can be used even when CNTR0 (output) is selected.
6: The port C “H” output function can be used even when CNTR1 (output) is selected.
DEFINITION OF CLOCK AND CYCLE
● Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation
Table Selection of system clock
Register MR
System clock
MR3
MR2
MR1
MR0
0
0
0
0
f(STCK) = f(XIN) or f(RING)
✕
1
f(STCK) = f(XCIN)
0
1
0
0
f(STCK) = f(XIN)/2 or f(RING)/2
✕
1
f(STCK) = f(XCIN)/2
1
0
0
0
f(STCK) = f(XIN)/4 or f(RING)/4
✕
1
f(STCK) = f(XCIN)/4
1
1
0
0
f(STCK) = f(XIN)/8 or f(RING)/8
✕
1
f(STCK) = f(XCIN)/8
● System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
● Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Operation mode
High-speed through mode
Low-speed through mode
High-speed frequency divided by 2 mode
Low-speed frequency divided by 2 mode
High-speed frequency divided by 4 mode
Low-speed frequency divided by 4 mode
High-speed frequency divided by 8 mode
Low-speed frequency divided by 8 mode
✕: 0 or 1
Note: The f(RING)/8 is selected after system is released from reset.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-7
HARDWARE
PORT FUNCTION
4524 Group
PORT FUNCTION
Port
Port D
Pin
D0–D3, D4/SIN,
D5/SOUT, D6/SCK,
D7/CNTR0
D8/INT0, D9/INT1
Port P0 P00–P03
Port P1 P10–P13
Port P2 P20/AIN0–P23/AIN3
Port P3 P30/AIN4–P33/AIN7
Port P4 P40–P43
Port C
C/CNTR1
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Input
Output
I/O
(8)
Output structure
N-channel open-drain/
CMOS
I/O
unit
1
Control
instructions
SD, RD
SZD
CLD
Output
(2)
I/O
(4)
N-channel open-drain
N-channel open-drain/
CMOS
4
OP0A
IAP0
I/O
(4)
N-channel open-drain/
CMOS
4
OP1A
IAP1
I/O
(4)
I/O
(4)
I/O
(4)
Output
(1)
N-channel open-drain
4
N-channel open-drain
4
N-channel open-drain/
CMOS
CMOS
4
OP2A
IAP2
OP3A
IAP3
OP4A
IAP4
RCP
SCP
1
Control
registers
FR1, FR2
J1
W6
I1, I2
K2
FR0
PU0
K0
FR0
PU1
K1
Q2
Remark
Output structure selection
function (programmable)
Key-on wakeup function
(programmable)
Built-in programmable pull-up
functions and key-on wakeup
functions (programmable)
Built-in programmable pull-up
functions and key-on wakeup
functions (programmable)
Q3
FR3
Output structure selection
function (programmable)
W4
1-8
HARDWARE
CONNECTION OF UNUSED PINS
4524 Group
CONNECTIONS OF UNUSED PINS
XIN
Connection
Connect to VSS.
XOUT
Open.
XCIN
XCOUT
D0–D3
Connect to VSS.
Open.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Connect to VSS.
Open.
Open.
Connect to Vss.
Pin
D4/SIN
D5/SOUT
D6/SCK
D7/CNTR0
D8/INT0
D9/INT1
C/CNTR1
P00–P03
P10–P13
Open.
Connect to Vss.
P20/AIN0–
P23/AIN3
P30/AIN4–
P33/AIN7
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Connect to Vss.
Open.
Open.
Open.
Open.
Open.
P40–P43
COM0–COM3
VLC3/SEG0
VLC2/SEG1
VLC1/SEG2
SEG3–SEG19
Usage condition
Internal oscillator is selected (CMCK and CRCK instructions are not executed.)
(Note 1)
Sub-clock input is selected for system clock (MR0=1). (Note 2)
Internal oscillator is selected (CMCK and CRCK instructions are not executed.)
(Note 1)
RC oscillator is selected (CRCK instruction is executed)
External clock input is selected for main clock (CMCK instruction is executed).
(Note 3)
Sub-clock input is selected for system clock (MR0=1). (Note 2)
Sub-clock is not used.
Sub-clock is not used.
N-channel open-drain is selected for the output structure. (Note 4)
SIN pin is not selected.
N-channel open-drain is selected for the output structure.
N-channel open-drain is selected for the output structure.
SCK pin is not selected.
N-channel open-drain is selected for the output structure.
CNTR0 input is not selected for timer 1 count source.
N-channel open-drain is selected for the output structure.
“0” is set to output latch.
“0” is set to output latch.
CNTR1 input is not selected for timer 3 count source.
The key-on wakeup function is not selected. (Note 4)
N-channel open-drain is selected for the output structure. (Note 5)
The pull-up function is not selected. (Note 4)
The key-on wakeup function is not selected. (Note 4)
The key-on wakeup function is not selected. (Note 4)
N-channel open-drain is selected for the output structure. (Note 5)
The pull-up function is not selected. (Note 4)
The key-on wakeup function is not selected. (Note 4)
N-channel open-drain is selected for the output structure. (Note 5)
SEG0 pin is selected.
SEG1 pin is selected.
SEG2 pin is selected.
Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator) is selected for main clock.
2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting “1” to bit 1 (MR1) of clock control register MR, main clock is stopped.
3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input for the main clock.
4: Be sure to select the output structure of ports D0–D3 and P40–P43 and the pull-up function and key-on wakeup function of P00–P03 and P10–P13
with every one port. Set the corresponding bits of registers for each port.
5: Be sure to select the output structure of ports P00–P03 and P10–P13 with every two ports. If only one of the two pins is used, leave another one open.
(Note when connecting to VSS and VDD)
● Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
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HARDWARE
PORT BLOCK DIAGRAM
4524 Group
PORT BLOCK DIAGRAMS
Clock (input) for timer 3 event count
W 31
W 30
PWMOD
SCP instruction
S Q
RCP instruction
R
(Note 1)
C/CNTR1 (Note 2,
Note 3)
D
Q
R
W32
Register Y
Decoder
W61
Skip decision
(SZD instruction)
FR 10
CLD
instruction
(Note 1)
S
SD instruction
Decoder
CLD
instruction
Skip decision
(SZD instruction)
FR11
(Note 1)
S
SD instruction
Decoder
CLD
instruction
Decoder
CLD
instruction
RD instruction
FR12
(Note 1)
D2 (Note 2)
R Q
RD instruction
SD instruction
Skip decision
(SZD instruction)
S
SD instruction
Register Y
D1 (Note 2)
R Q
RD instruction
Register Y
D0 (Note 2)
R Q
RD instruction
Register Y
Timer 3 underflow signal
T
Skip decision
(SZD instruction)
FR13
(Note 1)
S
D3 (Note 2)
R Q
This symbol represents a parasitic diode on the port.
Notes 1:
2: Applied potential to these ports must be VDD or less.
3: When CNTR1 input is selected, output transistor is turned OFF.
Port block diagram (1)
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1-10
HARDWARE
PORT BLOCK DIAGRAM
4524 Group
Register Y
Skip decision
(SZD instruction)
Decoder
F R 20
CLD
instruction
(Note 1)
S Q
SD instruction
D4/SIN
(Note 2)
R
RD instruction
J11
Serial data input
Skip decision
(SZD instruction)
Decoder
Register Y
CLD
instruction
FR21
D5/SOUT (Note 2)
J10
R Q
RD instruction
Serial data output
Register Y
(Note 1)
S
SD instruction
0
1
Skip decision
(SZD instruction)
Decoder
FR22
CLD
instruction
(Note 1)
S Q
D6/SCK (Note 2)
SD instruction
R
RD instruction
J11
J10
Synchronous clock (output)
for serial data transfer
J13
J12
Synchronous clock (input)
for serial data transfer
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (2)
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1-11
HARDWARE
PORT BLOCK DIAGRAM
4524 Group
Register Y
Skip decision
(SZD instruction)
Decoder
CLD
instruction
F R 23
(Note 1)
S
SD instruction
D7/CNTR0
(Note 2)
W60
R Q
RD instruction
0
1
Underflow signal divided by 2
of timer 1 or timer 2
W11
W10
Clock (input) for timer 1 event count
Timer 1 count start synchronous circuit input
Register Y
Key-on wakeup
(Note 3)
External 0 interrupt
External 0 interrupt
circuit
Decoder
CLD
instruction
(Note 1)
S
SD instruction
D8/INT0
(Note 2)
R Q
RD instruction
Timer 3 count start synchronous circuit input
Key-on wakeup
(Note 3)
External 1 interrupt
circuit
External 1 interrupt
Register Y
Decoder
CLD
instruction
SD instruction
RD instruction
(Note 1)
S
R Q
D9/INT1
(Note 2)
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: As for details, refer to the description of external interrupt circuit.
Port block diagram (3)
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HARDWARE
PORT BLOCK DIAGRAM
4524 Group
IAP0 instruction
PU00
Pull-up transistor
Register A
A0
FR00
(Note 1)
P00 (Note 2)
D
A0
OP0A instruction
T Q
K00
Key-on wakeup
“L” level
detection circuit
IAP0 instruction
PU01
Pull-up transistor
Register A
A1
FR00
(Note 1)
P01 (Note 2)
D
A1
OP0A instruction
T Q
K01
Key-on wakeup
Register A
“L” level
detection circuit
IAP0 instruction
PU02
Pull-up transistor
A2
FR01
(Note 1)
P02 (Note 2)
D
A2
OP0A instruction
T Q
K02
Key-on wakeup
Register A
“L” level
detection circuit
IAP0 instruction
PU03
Pull-up transistor
A3
FR01
A3
OP0A instruction
(Note 1)
P03 (Note 2)
D
T Q
K03
Key-on wakeup
“L” level
detection circuit
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (4)
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HARDWARE
PORT BLOCK DIAGRAM
4524 Group
Pull-up transistor
IAP1 instruction
Register A
A0
PU10
F R 02
(Note 1)
P10 (Note 2)
D
A0
OP1A instuction
T Q
K10
“L” level
detection circuit
Key-on wakeup
Pull-up transistor
IAP1 instruction
Register A
PU11
A1
F R 02
(Note 1)
P11 (Note 2)
D
A1
OP1A instuction
T Q
K11
“L” level
detection circuit
Key-on wakeup
Pull-up transistor
IAP1 instruction
Register A
PU12
A2
F R 03
(Note 1)
P12 (Note 2)
D
A2
OP1A instuction
T Q
K12
Key-on wakeup
“L” level
detection circuit
Pull-up transistor
IAP1 instruction
PU13
Register A
A3
F R 03
(Note 1)
A3
OP1A instuction
P13 (Note 2)
D
T Q
K13
Key-on wakeup
“L” level
detection circuit
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (5)
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HARDWARE
PORT BLOCK DIAGRAM
4524 Group
Ai
IAP2 instruction
Register A
(Note 3)
Ai
OP2A instruction
Q2i
(Note 3)
(Note 1)
(Note 3)
Q2i
D
P20/AIN0–P23/AIN3
(Note 2)
0
T Q
1
Q1
Decoder
Analog input
Ai
IAP3 instruction
Register A
(Note 3)
Ai
OP3A instruction
Q3i
(Note 1)
(Note 3)
Q3i
D
P30/AIN4–P33/AIN7
(Note 2)
0
T Q
(Note 3)
1
Q1
Decoder
Analog input
IAP4 instruction
Ai
Register A
(Note 3)
(Note 3) FR3i
Ai
OP4A instruction
(Note 1)
D
P40–P43
(Note 2)
T Q
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: i represents bits 0 to 3.
Port block diagram (6)
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HARDWARE
PORT BLOCK DIAGRAM
4524 Group
LCD power supply
Connecting to •
when SEG is selected.
LCD control
signal
(Note 1)
VLC3/SEG0
(Notes 2 and 3)
VDD
L23
LCD power
supply
LCD power supply
(VLC3/VDD)
LCD power supply
LCD control
signal
Connecting to •
when SEG is selected.
(Note 1)
VLC2/SEG1
(Note 2)
L22
LCD power
supply
LCD power supply
(VLC2)
LCD power
supply
LCD control
signal
L11
Connecting to •
when SEG is selected.
(Note 1)
VLC1/SEG2
(Note 2)
L21
LCD power
supply
LCD power supply
(VLC1)
L13
L20
Reset signal
L12
EPOF+POF2 instruction
(Continuous execution)
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential when VLC is selected must be as follows;
• VDD ≥ VLC3 ≥ VLC2 ≥ VLC1
3: VLC3 = VDD when SEG is selected.
Port block diagram (7)
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1-16
HARDWARE
PORT BLOCK DIAGRAM
4524 Group
LCD power supply
LCD control signal
Pch
SEG3–SEG19
LCD control signal
Nch
LCD power supply
LCD power supply
LCD control signal
Pch
COM0–COM3
Pch
LCD control signal
LCD power supply
LCD power supply
LCD control signal
Nch
Nch
LCD control signal
Port block diagram (8)
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1-17
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
(M(DP))
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
ALU
Addition
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B
TAB instruction
B3 B2 B1 B0
(4) Register D
Register A
A3 A2 A1 A0
TEAB instruction
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).
Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
A3 A2 A1 A0
B3 B2 B1 B0
Register B
TBA instruction
Register A
Fig. 3 Registers A, B and register E
TABP p instruction
ROM
Specifying address
p6 p5
PCH
p4 p3 p2 p1 p0
PCL
DR2 DR1DR0 A3 A2 A1 A0
8
4
0
Low-order 4bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents of The contents of
register D
register A
Fig. 4 TABP p instruction execution example
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations
together. The contents of registers SKs are destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the
contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table reference instruction.
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
Subroutine
Address
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC) ← (SK0)
(SP) ← 7
Note : Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed.
Program counter consists of PC H (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PCH does not specify after the last page of the
built-in ROM.
Program counter
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure
8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Specifying
RAM digit
Register Y (4)
Register X (4)
Specifying RAM file
Specifying RAM file group
Register Z (2)
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D3
0
0
0
D2
1
Register Y (4)
D1
D0
1
Port D output latch
Fig. 9 SD instruction execution example
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed
of 10 bits. ROM is separated every 128 words by the unit of page
(addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34524ED.
Table 1 ROM size and pages
Part number
M34524M8
M34524MC
M34524ED
ROM (PROM) size
(✕ 10 bits)
8192 words
12288 words
16384 words
Pages
9 8 7 6 5 4 3 2 1 0
000016
007F16
008016
00FF16
010016
017F16
018016
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
64 (0 to 63)
96 (0 to 95)
128 (0 to 127)
Note: Data in pages 64 to 127 can be referred with the TABP p instruction after the SBK instruction is executed.
Data in pages 0 to 63 can be referred with the TABP p instruction after the RBK instruction is executed.
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt address
is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt
address.
Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from
any page with the 1-word instruction (BM). Subroutines extending
from page 2 to another page can also be called with the BM instruction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
3FFF16
Page 127
Fig. 10 ROM map of M34524ED
008016
9 8 7 6 5 4 3 2 1 0
External 0 interrupt address
008216
External 1 interrupt address
008416
Timer 1 interrupt address
008616
Timer 2 interrupt address
008816
Timer 3 interrupt address
008A16
Timer 5 interrupt address
008C16
008E16
A/D interrupt address
T imer 4, Serial I/O interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM (also, set a value after system returns from RAM back-up).
RAM includes the area for LCD.
When writing “1” to a bit corresponding to displayed segment, the
segment is turned on.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Table 2 RAM size
Part number
M34524M8
M34524MC
M34524ED
RAM size
512 words ✕ 4 bits (2048 bits)
512 words ✕ 4 bits (2048 bits)
512 words ✕ 4 bits (2048 bits)
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Register Y
RAM 512 words ✕ 4 bits (2048 bits)
Register Z
1
0
Register X 0 1 2 3 ... 12 13 14 15 0 1 2 ... 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
12 13 14 15
0
1
2
3
4
5
6
8 16
9 17
10 18
11 19
12
13
14
7 15
Note: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig. 12 RAM map
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
Table 3 Interrupt sources
Priority
Interrupt name
level
1
External 0 interrupt
2
External 1 interrupt
3
Timer 1 interrupt
Level change of
INT0 pin
Level change of
INT1 pin
Timer 1 underflow
4
Timer 2 interrupt
Timer 2 underflow
5
Timer 3 interrupt
Timer 3 underflow
6
Timer 5 interrupt
Timer 5 underflow
7
A/D interrupt
8
Timer 4 interrupt or
Serial I/O interrupt
(Note)
Completion of
A/D conversion
Timer 4 underflow
or completion of
serial I/O transmit/
receive
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set to “1” when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or
its interrupt enable bit. Once set, the interrupt request flag retains
set until it is cleared to “0” by the interrupt occurrence or the skip
instruction.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set to “1” when the interrupt disable state is released, the interrupt priority level is as
follows shown in Table 3.
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Activated condition
Interrupt
address
Address 0
in page 1
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
Address A
in page 1
Address C
in page 1
Address E
in page 1
Note: Timer 4 interrupt or serial I/O interrupt can be selected by the timer 4,
serial I/O interrupt source selection bit (I30).
Table 4 Interrupt request flag, interrupt enable bit and skip instruction
Interrupt name
External 0 interrupt
External 1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 5 interrupt
A/D interrupt
Timer 4 interrupt
Serial I/O interrupt
Interrupt
request flag
EXF0
EXF1
T1F
T2F
T3F
T5F
ADF
T4F
SIOF
Skip instruction
SNZ0
SNZ1
SNZT1
SNZT2
SNZT3
SNZT5
SNZAD
SNZT4
SNZSI
Table 5 Interrupt enable bit function
Interrupt enable bit Occurrence of interrupt
Enabled
1
Disabled
0
Interrupt
nable bit
V10
V11
V12
V13
V20
V21
V22
V23
V23
Skip instruction
Invalid
Valid
1-23
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an interrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
• Program counter (PC)
............................................................... Each interrupt address
• Stack register (SK)
The address of main routine to be
....................................................................................................
executed when returning
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
Activated
condition
INT0 pin interrupt
waveform input
INT1 pin interrupt
waveform input
Timer 1
underflow
Main
routine
Timer 2
underflow
Interrupt
service routine
Interrupt
occurs
•
•
•
•
EI
R TI
Interrupt is
enabled
Timer 3
underflow
Timer 5
underflow
A/D conversion
completed
Timer 4
underflow
Request flag Enable bit
(state retained)
Enable flag
Address 0
in page 1
EXF0
V10
EXF1
V11
T1F
V12
T2F
V13
T3F
V20
Address 8
in page 1
T5F
V21
Address A
in page 1
ADF
V 22
Address C
in page 1
T4F
V23
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
Address E
in page 1
INTE
0
: Interrupt enabled state
Serial I/O
transmit/receive
completed
1
SIOF
I30
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
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Fig. 15 Interrupt system diagram
1-24
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
• Interrupt control register I3
The timer 4, serial I/O interrupt source selection bit is assigned to
register I3. Set the contents of this register through register A
with the TI3A instruction. The TAI3 instruction can be used to
transfer the contents of register I3 to register A.
• Interrupt control register V2
The timer 3, timer 5, A/D, Timer 4 and serial I/O interrupt enable
bit is assigned to register V2. Set the contents of this register
through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
External 1 interrupt enable bit
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Timer 4, serial I/O interrupt enable bit (Note 3)
V22
A/D interrupt enable bit
V21
Timer 5 interrupt enable bit
V20
Timer 3 interrupt enable bit
I30
Timer 4, serial I/O interrupt source selection
bit
R/W
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register I3
at power down : 00002
at power down : 00002
R/W
TAV2/TV2A
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 2)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid) (Note 2)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid) (Note 2)
at reset : 02
0
1
at power down : state retained
R/W
TAI3/TI3A
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source selection bit (I30).
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10–V1 3, V20–V23), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the machine cycle in which all three conditions are satisfied. The interrupt
occurs after 3 machine cycles when the interrupt conditions are
satisfied on execution of two-cycle instructions or three-cycle instructions. (Refer to Figure 16).
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Timer 1,
Timer 2,
Timer 3,
Timer 4,
Timer 5,
A/D and
Serial I/O
interrupts
External
interrupt
T1F,T2F,T3F,T4F
T5F,ADF,SIOF
EXF0,EXF1
INT0,INT1
Interrupt enable
flag (INTE)
System clock
(STCK)
T2
T3
T1
T2
T3
T2
T3
Interrupt enabled state
T1
T2
T1
T2
The program starts
from the interrupt
address.
Retaining level of system
clock for 4 periods or more
is necessary.
Interrupt disabled state
Flag cleared
T3
2 to 3 machine cycles
(Notes 1, 2)
Interrupt activated
condition is satisfied.
T1
4524 Group
Notes 1: The address to be executed when returning to the main routine is stacked to the last machine cycle.
2: The cycles are as follows according to the executed instruction at the time when each interrupt activated condition is satisfied.
On execution of one-cycle instruction: Interrupt occurs after 2 machine cycles.
On execution of two-cycle instruction: Interrupt occurs after 3 machine cycles.
On execution of three-cycle instruction: Interrupt occurs after 3 machine cycles.
EI instruction execution cycle
T1
1 machine cycle
● When an interrupt request flag is set after its interrupt is enabled (Note 1)
HARDWARE
FUNCTION BLOCK OPERATIONS
Fig. 16 Interrupt sequence
1-26
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
EXTERNAL INTERRUPTS
The 4524 Group has the external 0 interrupt and external 1 interrupt.
An external interrupt request occurs when a valid waveform is input
to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
registers I1 and I2.
Table 7 External interrupt activated conditions
Name
External 0 interrupt
Input pin
Valid waveform
selection bit
I11
I12
Activated condition
D8/INT0
When the next waveform is input to D8/INT0 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
External 1 interrupt
D9/INT1
I21
I22
When the next waveform is input to D9/INT1 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
I12
Falling
(Note 1)
0
One-sided edge
detection circuit
I11
0
D8/INT0
External 0
interrupt
EXF0
1
Rising
I13
Both edges
detection circuit
1
Timer 1 count start
synchronous circuit
(Note 2)
Level detection circuit
K21
0
Key-on wakeup
(Note 3)
Edge detection circuit
K20
1
Skip decision
(SNZI0 instruction)
I22
Falling
(Note 1)
0
One-sided edge
detection circuit
I21
0
D9/INT1
External 1
interrupt
EXF1
1
Rising
I23
Both edges
detection circuit
1
(Note 2)
Level detection circuit
K22
(Note 3)
Edge detection circuit
Timer 3 count start
synchronous circuit
K23
0
Key-on wakeup
1
Skip decision
(SNZI1 instruction)
Notes 1:
This symbol represents a parasitic diode on the port.
2: I12 (I22) = 0: “L” level detected
I12 (I22) = 1: “H” level detected
3: I12 (I22) = 0: Falling edge detected
I12 (I22) = 1: Rising edge detected
Fig. 17 External interrupt circuit structure
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HARDWARE
4524 Group
FUNCTION BLOCK OPERATIONS
(1) External 0 interrupt request flag (EXF0)
(2) External 1 interrupt request flag (EXF1)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to D8/INT0 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip
instruction.
External 1 interrupt request flag (EXF1) is set to “1” when a valid
waveform is input to D9/INT1 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF1 flag can be examined with the skip instruction
(SNZ1). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip
instruction.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to D8/INT0 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
• External 1 interrupt activated condition
External 1 interrupt activated condition is satisfied when a valid
waveform is input to D9/INT1 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 1 interrupt is as follows.
➀ Set the bit 3 of register I1 to “1” for the INT0 pin to be in the input enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➄ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
➀ Set the bit 3 of register I2 to “1” for the INT1 pin to be in the input enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I2.
➂ Clear the EXF1 flag to “0” with the SNZ1 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ1 instruction.
➄ Set both the external 1 interrupt enable bit (V1 1) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid waveform is input to the D8/INT0 pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
The external 1 interrupt is now enabled. Now when a valid waveform is input to the D9/INT1 pin, the EXF1 flag is set to “1” and the
external 1 interrupt occurs.
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(3) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
• Interrupt control register I2
Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the
TI2A instruction. The TAI2 instruction can be used to transfer the
contents of register I2 to register A.
Table 8 External interrupt control register
Interrupt control register I1
I13
INT0 pin input control bit (Note 2)
I12
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
I11
I10
INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
circuit selection bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register I2
I23
I22
I21
I20
INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 2)
INT1 pin edge detection circuit control bit
INT1 pin Timer 3 count start synchronous
circuit selection bit
0
1
0
1
0
1
R/W
TAI1/TI1A
INT0 pin input disabled
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
at reset : 00002
0
1
at power down : state retained
at power down : state retained
R/W
TAI2/TI2A
INT1 pin input disabled
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
instruction)
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
Timer 3 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of these bits (I12 , I13, I22 and I23) are changed, the external interrupt request flag (EXF0, EXF1) may be set.
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(4) Notes on External 0 interrupts
➂ Note on bit 2 of register I1
When the interrupt valid waveform of the D8/INT0 pin is changed
with the bit 2 of register I1 in software, be careful about the following notes.
• Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
18➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18➂).
• Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
20➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂).
•••
•••
➀ Note [1] on bit 3 of register I1
When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT0 pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
Fig. 20 External 0 interrupt program example-3
➁ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared, the power down function
is selected and the input of INT0 pin is disabled, be careful about
the following notes.
•••
• When the input of INT0 pin is disabled, invalidate the key-on
wakeup function of INT0 pin (register K2 0 = “0”) before system
goes into the power down mode. (refer to Figure 19➀).
; (✕✕✕02)
; INT0 key-on wakeup invalid ........... ➀
; RAM back-up
•••
LA
0
TK2A
DI
EPOF
POF2
✕ : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(5) Notes on External 1 interrupts
➂ Note on bit 2 of register I2
When the interrupt valid waveform of the D9/INT1 pin is changed
with the bit 2 of register I2 in software, be careful about the following notes.
• Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 21➀)
and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
21➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 21➂).
• Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 23➀)
and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
23➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 23➂).
•••
•••
➀ Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes.
LA
4
TV1A
LA
8
TI2A
NOP
SNZ1
LA
4
TV1A
LA
12
TI2A
NOP
SNZ1
•••
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT1 pin input is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 21 External 1 interrupt program example-1
Fig. 23 External 1 interrupt program example-3
➁ Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared, the power down function
is selected and the input of INT1 pin is disabled, be careful about
the following notes.
•••
• When the input of INT1 pin is disabled, invalidate the key-on
wakeup function of INT1 pin (register K2 2 = “0”) before system
goes into the power down mode. (refer to Figure 22➀).
; (✕0✕✕2)
; INT1 key-on wakeup invalid ........... ➀
; RAM back-up
•••
LA
0
TK2A
DI
EPOF
POF2
✕ : these bits are not used here.
Fig. 22 External 1 interrupt program example-2
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
TIMERS
The 4524 Group has the following timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
F F1 6
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
“1”
Timer interrupt
“0”
request flag
An interrupt occurs or
a skip instruction is executed.
Fig. 24 Auto-reload function
The 4524 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 8-bit programmable timer
• Timer 4 : 8-bit programmable timer
• Timer 5 : 16-bit fixed dividing frequency timer
• Timer LC : 4-bit programmable timer
• Watchdog timer : 16-bit fixed dividing frequency timer
(Timers 1, 2, 3, 4 and 5 have the interrupt function, respectively)
Prescaler and timers 1, 2, 3, 4, 5 and LC can be controlled with the
timer control registers PA, W1 to W6. The watchdog timer is a free
counter which is not controlled with the control register.
Each function is described below.
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
Table 9 Function related timers
Prescaler
8-bit programmable
• Instruction clock (INSTCK)
Frequency
dividing ratio
1 to 256
Timer 1
binary down counter
8-bit programmable
• Instruction clock (INSTCK)
1 to 256
Circuit
Structure
binary down counter
(link to INT0 input)
Count source
• Prescaler output (ORCLK)
• Timer 5 underflow
Use of output signal
Control
register
PA
• Timer 1, 2, 3, 4 and LC count sources
• Timer 2 count source
W1
• CNTR0 output
W2
• Timer 1 interrupt
(T5UDF)
• CNTR0 input
Timer 2
8-bit programmable
binary down counter
• System clock (STCK)
1 to 256
• Timer 3 count source
• Prescaler output (ORCLK)
• CNTR0 output
• Timer 1 underflow
(T1UDF)
• Timer 2 interrupt
W2
• PWM output (PWMOUT)
Timer 3
8-bit programmable
• PWM output (PWMOUT)
binary down counter
(link to INT1 input)
• Prescaler output (ORCLK)
1 to 256
• CNTR1 output control
• Timer 3 interrupt
W3
1 to 256
• Timer 2, 3 count source
W4
• Timer 2 underflow
(T2UDF)
• CNTR1 input
Timer 4
Timer 5
8-bit programmable
• XIN input
binary down counter
• Prescaler output (ORCLK)
• CNTR1 output
• Timer 4 interrupt
(PWM output function)
• XCIN input
16-bit fixed dividing
8192
• Timer 1, LC count source
frequency
16384
• Timer 5 interrupt
W5
32768
65536
Timer LC
4-bit programmable
• Bit 4 of timer 5
Watchdog
binary down counter
16-bit fixed dividing
• Prescaler output (ORCLK)
timer
frequency
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REJ09B0107-0200Z
• Instruction clock (INSTCK)
1 to 16
• LCD clock
65534
• System reset (count twice)
W6
• WDF flag decision
1-33
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
Division circuit
On-chip oscillator
Divided by 8
(CMCK)
Multiplexer
Ceramic resonance
XI N
Divided by4
MR0
0
RC oscillation
Divided by 2
10
Internal clock
generating circuit
(divided by 3)
01
00
Instruction clock
(INSTCK)
PA0 (Note 4)
0
Quartz-crystal
oscillation
W60
0
System clock (STCK)
1
(CMCK/CRCK)
(Note 1)
(CRCK)
XCIN
MR3, MR2
11
Prescaler (8)
ORCLK
1
Port D7 output
D7/CNTR0
W23
0
1 /2
1 /2
1
I1 2
Falling
0
D8/INT0
Reload register RPS (8)
T1UDF
(TPSAB)
1
T2UDF
I11
0
One-sided edge
detection circuit
(TABPS)
(Note 2)
1
Rising
1
Both edges
detection circuit
(TPSAB)
Register A
(TABPS)
I10
1
S Q
I1 3
(TPSAB)
Register B
0
R
I10
W13
T1UDF
W11, W10
00
INSTCK
01
ORCLK
10
T5UDF
Timer 1 (8)
(Note 4)
W12
0
(TAB1)
D7/CNTR0
W21, W20
00
01
ORCLK
10
T1UDF
(TR1AB)
(T1AB)
(TAB1)
Timer 2 (8)
Timer 1 underflow signal (T1UDF)
T2F
Timer 2
interrupt
Reload register R2 (8)
1
(T2AB)
(TAB2)
PWMOUT
I2 2
Falling
0
I23
(T1AB)
Register B Register A
(Note 4)
W22
0
11
D9/INT1
Timer 1
interrupt
Reload register R1 (8)
(T1AB)
1
11
STCK
T1F
1
Rising
(T2AB)
(T2AB)
(TAB2)
Register B Register A
One-sided edge
detection circuit
I2 1
(Note 3)
0
S Q
I20
1
1
Both edges
detection circuit
Timer 2 underflow signal (T2UDF)
0
R
I20
W33
T3UDF
W31, W30
00
PWMOUT
ORCLK
T2UDF
01
10
11
Timer 3 (8)
(Note 4)
W32
0
T3F
Timer 3
interrupt
Reload register R3 (8)
(T3AB)
1
(TAB3)
C/CNTR1
T5UDF: Timer 5 underflow signal (from timer 5)
PWMOUT: PWM output signal (from timer 4 output unit)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
(TR3AB)
(T3AB)
(T3AB)
Register B Register A
(TAB3)
Timer 3 underflow signal (T3UDF)
Notes 1: When CMCK instruction is executed, ceramic resonance is selected.
When CRCK instruction is executed, RC oscillation is selected.
When any instructions are not executed, on-chip oscillator clock
(internal oscillation) is selected.
2: Timer 1 count start synchronous circuit is set
by the valid edge of D8/INT0 pin selected by bits 1 (I11) and 2 (I12)
of register I1.
3: Timer 3 count start synchronous circuit is set
by the valid edge of D9/INT1 pin selected by bits 1 (I21) and 2 (I22)
of register I2.
4: Count source is stopped by clearing to “0.”
Fig. 25 Timer structure (1)
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
Register B
Register A
(T4HAB)
Reload register R4H (8)
(Note 5)
W40
0
XIN
ORCLK
(Note 4)
W41
0
Reload control circuit
W 42
“H” interval
expansion
Timer 4 (8)
1
1 /2
1
1
T
0
(T4R4L)
(T4AB)
(T4AB)
Register B
PWMOD
W43
Reload register R4L (8)
(TAB4)
Q
R
(TAB4)
Register A
T4F
SIOF
I30
0
1
Timer 4,
Serial I/O
interrupt
(From Serial I/O)
PWMOUT
(To timer 2 and timer 3)
Port C output
PWMOD
C/CNTR1
W31
W30
W32
(Note 4)
W52
0
XCIN
1
Q
D
R
T
T3UDF
W61
Timer 5 (16) (Note 6)
1 - - 4 - - - - - - - -13 14 15 16
W51, W50
11
10
01
T5F
00
W 62
0
Timer 5
interrupt
Timer 5 underflow signal (T5UDF)
(Note 4)
W63
0
Timer LC (4)
1/2
LCD clock
1
ORCLK
1
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
Watchdog timer (16)
INSTCK
1 - - - - - - - - - - - - - - - - - - - 16
(Note 7)
WRST
instruction
S
Q
WDF1
R
Reset signal
S
Q
(Note 9)
WEF
DWDT instruction
R
+
WRST instruction(Note 8)
D
Q
WDF2
T R
Watchdog
reset signal
Reset signal
INSTCK : Instruction clock (system clock divided by 3)
ORCLK : Prescaler output (instruction clock divided by 1 to 256)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 4: Count source is stopped by clearing to “0.”
5: XIN cannot be used as count source when bit 1 (MR1) of register MR
is set to “1” and f(XIN) oscillation is stopped.
6: This timer is initialized (initial value = FFFF16) by stop of count
source (W52 = “0”).
7: Flag WDF1 is cleared to “0” and the next instruction is skipped when
the WRST instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST instruction
is executed while flag WDF1 = “0”.
8: Flag WEF is cleared to “0” and watchdog timer reset does not occur
when the DWDT instruction and WRST instruction are executed
continuously.
9: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig. 26 Timer structure (2)
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
Table 10 Timer related registers
Timer control register PA
PA0
Prescaler control bit
0
1
Timer control register W1
W13
Timer 1 count auto-stop circuit selection
bit (Note 2)
W12
Timer 1 control bit
W11
Timer 1 count source selection bits
W10
CNTR0 output control bit
W22
Timer 2 control bit
W21
Timer 2 count source selection bits
W20
Timer 3 count auto-stop circuit selection
bit (Note 3)
W32
Timer 3 control bit
W31
W30
Timer 3 count source selection bits
(Note 4)
at power down : state retained
R/W
TAW1/TW1A
0
1
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
W11 W10
Count source
0
Instruction clock (INSTCK)
0
0
Prescaler output (ORCLK)
1
1
Timer 5 underflow signal (T5UDF)
0
1
CNTR0 input
1
at reset : 00002
at power down : state retained
R/W
TAW2/TW2A
0
1
0
1
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating
W21 W20
Count source
0
System clock (STCK)
0
0
Prescaler output (ORCLK)
1
1
Timer 1 underflow signal (T1UDF)
0
1
PWM signal (PWMOUT)
1
Timer control register W3
W33
W
TPAA
Stop (state initialized)
Operating
at reset : 00002
Timer control register W2
W23
at power down : 02
at reset : 02
at reset : 00002
at power down : state retained
R/W
TAW3/TW3A
0
1
0
1
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating
W31 W30
Count source
0
PWM signal (PWMOUT)
0
0
Prescaler output (ORCLK)
1
1
Timer 2 underflow signal (T2UDF)
0
1
CNTR1 input
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
Timer control register W4
W43
CNTR1 output control bit
W42
PWM signal
“H” interval expansion function control bit
W41
Timer 4 control bit
W40
Timer 4 count source selection bit
0
1
0
1
0
1
0
1
Timer control register W5
W53
Not used
W52
Timer 5 control bit
W51
Timer 5 count value selection bits
W50
Timer LC control bit
0
1
0
1
W62
Timer LC count source selection bit
W61
CNTR1 output auto-control circuit
selection bit
D7/CNTR0 pin function selection bit
(Note 2)
W60
at power down : state retained
R/W
TAW5/TW5A
This bit has no function, but read/write is enabled.
Stop (state initialized)
Operating
W51 W50
0
0
0
1
1
0
1
1
Count value
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAW4/TW4A
CNTR1 output invalid
CNTR1 output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK) divided by 2
at reset : 00002
Timer control register W6
W63
at power down : 00002
at reset : 00002
at power down : state retained
R/W
TAW6/TW6A
Stop (state retained)
Operating
Bit 4 (T54) of timer 5
Prescaler output (ORCLK)
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
D7(I/O)/CNTR0 input
CNTR0 input/output/D7 (input)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
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HARDWARE
4524 Group
FUNCTION BLOCK OPERATIONS
(1) Timer control registers
(2) Prescaler (interrupt function)
• Timer control register PA
Register PA controls the count operation of prescaler. Set the
contents of this register through register A with the TPAA instruction.
• Timer control register W1
Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the
contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents
of register W1 to register A.
• Timer control register W2
Register W2 controls the selection of CNTR0 output, and the
count operation and count source of timer 2. Set the contents of
this register through register A with the TW2A instruction. The
TAW2 instruction can be used to transfer the contents of register
W2 to register A.
• Timer control register W3
Register W3 controls the selection of timer 3 count auto-stop circuit, and the count operation and count source of timer 3. Set the
contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents
of register W3 to register A.
• Timer control register W4
Register W4 controls the CNTR1 output, the expansion of “H” interval of PWM output, and the count operation and count source
of timer 4. Set the contents of this register through register A with
the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A.
• Timer control register W5
Register W5 controls the count operation and count source of
timer 5. Set the contents of this register through register A with
the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A.
• Timer control register W6
Register W6 controls the operation and count source of timer LC,
the selection of CNTR1 output auto-control circuit and the D7/
CNTR0 pin function. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be
used to transfer the contents of register W6 to register A..
Prescaler is an 8-bit binary down counter with the prescaler reload
register PRS. Data can be set simultaneously in prescaler and the
reload register RPS with the TPSAB instruction. Data can be read
from reload register RPS with the TABPS instruction.
Stop counting and then execute the TPSAB or TABPS instruction
to read or set prescaler data.
Prescaler starts counting after the following process;
➀ set data in prescaler, and
➁ set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
Count source for prescaler is the instruction clock (INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new
data is loaded from reload register RPS, and count continues
(auto-reload function).
The output signal (ORCLK) of prescaler can be used for timer 1, 2,
3, 4 and LC count sources.
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(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload
register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read
from timer 1 with the TAB1 instruction.
Stop counting and then execute the T1AB or TAB1 instruction to
read or set timer 1 data.
When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1
underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1
➁ set count source by bits 0 and 1 of register W1, and
➂ set the bit 2 of register W1 to “1.”
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the timer
1 interrupt request flag (T1F) is set to “1,” new data is loaded from
reload register R1, and count continues (auto-reload function).
INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to “1.”
Also, in this time, the auto-stop function by timer 1 underflow can
be performed by setting the bit 3 of register W1 to “1.”
Timer 1 underflow signal divided by 2 can be output from CNTR0
pin by clearing bit 3 of register W2 to “0” and setting bit 0 of register W6 to “1”.
1-38
HARDWARE
4524 Group
FUNCTION BLOCK OPERATIONS
(4) Timer 2 (interrupt function)
(6) Timer 4 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload
register (R2) with the T2AB instruction. Data can be read from
timer 2 with the TAB2 instruction. Stop counting and then execute
the T2AB or TAB2 instruction to read or set timer 2 data.
Timer 2 starts counting after the following process;
➀ set data in timer 2,
➁ select the count source with the bits 0 and 1 of register W2, and
➂ set the bit 2 of register W2 to “1.”
Timer 4 is an 8-bit binary down counter with two timer 4 reload registers (R4L, R4H). Data can be set simultaneously in timer 4 and
the reload register R4L with the T4AB instruction. Data can be set
in the reload register R4H with the T4HAB instruction. The contents
of reload register R4L set with the T4AB instruction can be set to
timer 4 again with the T4R4L instruction. Data can be read from
timer 4 with the TAB4 instruction.
Stop counting and then execute the T4AB or TAB4 instruction to
read or set timer 4 data.
When executing the T4HAB instruction to set data to reload register R4H while timer 4 is operating, avoid a timing when timer 4
underflows.
Timer 4 starts counting after the following process;
➀ set data in timer 4
➁ set count source by bit 0 of register W4, and
➂ set the bit 1 of register W4 to “1.”
When a value set in reload register R2 is n, timer 2 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2, and count continues (auto-reload function).
Timer 2 underflow signal divided by 2 can be output from CNTR0
pin by setting bit 3 of register W2 to “1” and setting bit 0 of register
W6 to “1”.
(5) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload
register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. Data can be read
from timer 3 with the TAB3 instruction.
Stop counting and then execute the T3AB or TAB3 instruction to
read or set timer 3 data.
When executing the TR3AB instruction to set data to reload register R3 while timer 3 is operating, avoid a timing when timer 3
underflows.
Timer 3 starts counting after the following process;
➀ set data in timer 3
➁ set count source by bits 0 and 1 of register W3, and
➂ set the bit 2 of register W3 to “1.”
When a value set in reload register R3 is n, timer 3 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 3 underflows (the next count
pulse is input after the contents of timer 3 becomes “0”), the timer
3 interrupt request flag (T3F) is set to “1,” new data is loaded from
reload register R3, and count continues (auto-reload function).
INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 0 of register I2 to “1.”
Also, in this time, the auto-stop function by timer 3 underflow can
be performed by setting the bit 3 of register W3 to “1.”
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When a value set in reload register R4L is n, timer 4 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 4 underflows (the next count
pulse is input after the contents of timer 4 becomes “0”), the timer
4 interrupt request flag (T4F) is set to “1,” new data is loaded from
reload register R4L, and count continues (auto-reload function).
When bit 3 of register W4 is set to “1”, timer 4 reloads data from reload register R4L and R4H alternately each underflow.
Timer 4 generates the PWM signal (PWMOUT) of the “L” interval
set as reload register R4L, and the “H” interval set as reload register R4H. The PWM signal (PWMOUT) is output from CNTR1 pin.
When bit 2 of register W4 is set to “1” at this time, the interval
(PWM signal “H” interval) set to reload register R4H for the counter
of timer 4 is extended for a half period of count source.
In this case, when a value set in reload register R4H is n, timer 4
divides the count source signal by n + 1.5 (n = 1 to 255).
When this function is used, set “1” or more to reload register R4H.
When bit 1 of register W6 is set to “1”, the PWM signal output to
CNTR1 pin is switched to valid/invalid each timer 3 underflow.
However, when timer 3 is stopped (bit 2 of register W3 is cleared to
“0”), this function is canceled.
Even when bit 1 of a register W4 is cleared to “0” in the “H” interval
of PWM signal, timer 4 does not stop until it next timer 4 underflow.
When clearing bit 1 of register W4 to “0” to stop timer 4, avoid a
timing when timer 4 underflows.
1-39
HARDWARE
4524 Group
(7) Timer 5 (interrupt function)
Timer 5 is a 16-bit binary down counter.
Timer 5 starts counting after the following process;
➀ set count value by bits 0 and 1 of register W5, and
➁ set the bit 2 of register W5 to “1.”
Count source for timer 5 is the sub-clock input (XCIN).
Once count is started, when timer 5 underflows (the set count
value is counted), the timer 5 interrupt request flag (T5F) is set to
“1,” and count continues.
Bit 4 of timer 5 can be used as the timer LC count source for the
LCD clock generating.
When bit 2 of register W5 is cleared to “0”, timer 5 is initialized to
“FFFF16” and count is stopped.
Timer 5 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When
timer 5 underflow occurs at clock operating mode, system returns
from the power down state.
(8) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC reload
register (RLC). Data can be set simultaneously in timer LC and the
reload register (RLC) with the TLCA instruction. Data cannot be
read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data.
Timer LC starts counting after the following process;
➀ set data in timer LC,
➁ select the count source with the bit 2 of register W6, and
➂ set the bit 3 of register W6 to “1.”
FUNCTION BLOCK OPERATIONS
(9) Timer input/output pin
(D7/CNTR0 pin, C/CNTR1 pin)
CNTR0 pin is used to input the timer 1 count source and output the
timer 1 and timer 2 underflow signal divided by 2.
CNTR1 pin is used to input the timer 3 count source and output the
PWM signal generated by timer 4. When the PWM signal is output
from C/CNTR1 pin, set “0” to the output latch of port C.
The D7/CNTR0 pin function can be selected by bit 0 of register W6.
The selection of CNTR1 output signal can be controlled by bit 3 of
register W4.
When the CNTR0 input is selected for timer 1 count source, timer
1 counts the rising waveform of CNTR0 input.
When the CNTR1 input is selected for timer 3 count source, timer
3 counts the rising waveform of CNTR1 input. Also, when the
CNTR1 input is selected, the output of port C is invalid (high-impedance state).
(10) Timer interrupt request flags
(T1F, T2F, T3F, T4F, T5F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2, SNZT3, SNZT4, SNZT5).
Use the interrupt control register V1, V2 to select an interrupt or a
skip instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.
When a value set in reload register RLC is n, timer LC divides the
count source signal by n + 1 (n = 0 to 15).
Once count is started, when timer LC underflows (the next count
pulse is input after the contents of timer LC becomes “0”), new data
is loaded from reload register RLC, and count continues (auto-reload function).
Timer LC underflow signal divided by 2 can be used for the LCD
clock.
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HARDWARE
4524 Group
(11) Count start synchronization circuit (timer 1,
timer 3)
Timer 1 and timer 3 have the count start synchronous circuit which
synchronizes the input of INT0 pin and INT1 pin, and can start the
timer count operation.
Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to “1” and the control by INT0 pin input
can be performed.
Timer 3 count start synchronous circuit function is selected by setting the bit 0 of register I2 to “1” and the control by INT1 pin input
can be performed.
When timer 1 or timer 3 count start synchronous circuit is used, the
count start synchronous circuit is set, the count source is input to
each timer by inputting valid waveform to INT0 pin or INT1 pin.
The valid waveform of INT0 pin or INT1 pin to set the count start
synchronous circuit is the same as the external interrupt activated
condition.
Once set, the count start synchronous circuit is cleared by clearing
the bit I10 or I20 to “0” or reset.
However, when the count auto-stop circuit is selected, the count
start synchronous circuit is cleared (auto-stop) at the timer 1 or
timer 3 underflow.
(12) Count auto-stop circuit (timer 1, timer 3)
Timer 1 has the count auto-stop circuit which is used to stop timer
1 automatically by the timer 1 underflow when the count start synchronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 3 of register W1
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.
Timer 3 has the count auto-stop circuit which is used to stop timer
3 automatically by the timer 3 underflow when the count start synchronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 3 of register W3
to “1”. It is cleared by the timer 3 underflow and the count source to
timer 3 is stopped.
This function is valid only when the timer 3 count start synchronous
circuit is selected.
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FUNCTION BLOCK OPERATIONS
(13) Precautions
Note the following for the use of timers.
• Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
• Timer count source
Stop timer 1, 2, 3, 4 and LC counting to change its count source.
• Reading the count value
Stop timer 1, 2, 3 or 4 counting and then execute the data read
instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
• Writing to the timer
Stop timer 1, 2, 3, 4 or LC counting and then execute the data
write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its
data.
• Writing to reload register R1, R3, R4H
When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating,
avoid a timing when timer 1, timer 3 or timer 4 underflows.
• Timer 4
Avoid a timing when timer 4 underflows to stop timer 4.
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R4H.
• Timer 5
Stop timer 5 counting to change its count source.
• Timer input/output pin
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
1-41
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
● CNTR1 output: invalid (W43 = “0”)
Timer 4 count source
Timer 4 count value
(Reload register)
0316
0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
(R4L)
(R4L)
(R4L)
(R4L)
(R4L)
Timer 4 underflow signal
PWM signal (output invalid)
PWM signal “L” fixed
Timer 4 start
● CNTR1 output: valid (W43 = “1”)
PWM signal “H” interval extension function: invalid (W42 = “0”)
Timer 4 count source
Timer 4 count value
(Reload register)
0316
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
(R4L)
(R4H)
(R4L)
(R4H)
(R4L)
(R4H)
Timer 4 underflow signal
3 clock
PWM signal
3 clock
PWM period 7 clock
PWM period 7 clock
Timer 4 start
● CNTR1 output: valid (W43 = “1”)
PWM signal “H” interval extension function: valid (W42 = “1”) (Note)
Timer 4 count source
Timer 4 count value
(Reload register)
0316
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
0216
0116 0016 0316 0216 0116 0016 0216
(R4L)
(R4H)
(R4L)
(R4H)
(R4L)
(R4H)
Timer 4 underflow signal
3.5 clock
PWM signal
Timer 4 start
PWM period 7.5 clock
3.5 clock
PWM period 7.5 clock
Note: At PWM signal “H” interval extension function: valid, set “0116” or more to reload register R4H.
Fig. 27 Timer 4 operation (reload register R4L: “0316”, R4H: “0216”)
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1-42
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
CNTR1 output auto-control circuit by timer 3 is selected.
● CNTR1 output: valid (W43 = “1”)
CNTR1 output auto-control circuit selected (W61 = “1”)
PWM signal
Timer 3 underflow signal
Timer 3 start
CNTR1 output
CNTR1 output start
● CNTR1 output auto-control function
PWM signal
Timer 3 underflow signal
Timer 3 start
➀
➁
Timer 3 stop
➂
Register W61
CNTR1 output
CNTR1 output start
➀
➁
➂
CNTR1 output stop
When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid,
the CNTR1 output invalid state is retained.
When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid,
the CNTR1 output valid state is retained.
When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid.
Note: When the PWM signal is output from C/CNTR1 pin, set the output latch of port C to “0”.
Fig. 28 CNTR1 output auto-control function by timer 3
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
●Waveform extension function of CNTR1 output “H” interval: Invalid (W42 = “0”),
CNTR1 output: valid (W43 = “1”),
Count source: XIN input selected (W40 = “0”),
Reload register R4L: “0316”
Reload register R4H: “0216”
Timer 4 count start timing
Machine cycle
Mi
Mi+1
Mi+2
TW4A instruction execution cycle (W41) ¨ 1
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Register W41
Timer 4 count value
(Reload register)
0316
0216 0116 0016 0216 0116 0016 0316 0216 0116
(R4L)
(R4H)
(R4L)
Timer 4
underflow signal
PWM signal
Timer 4 count start timing
Timer 4 count stop timing
Machine cycle
Mi
Mi+1
Mi+2
TW4A instruction execution cycle (W41) ¨ 0
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Register W41
Timer 4 count value
(Reload register)
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016
(R4H)
(R4L)
0216
(R4H)
Timer 4
underflow signal
PWM signal
(Note 1)
Timer 4 count stop timing
Notes 1: In order to stop timer 4 at CNTR1 output valid (W43 = “1”), avoid a timing when timer 4 underflows.
If these timings overlap, a hazard may occur in a CNTR1 output waveform.
2: At CNTR1 output valid, timer 4 stops after “H” interval of PWM signal set by reload register R4H is output.
Fig. 29 Timer 4 count start/stop timing
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “0000 16,” the next
count pulse is input), the WDF1 flag is set to “1.”
If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to
“1,” and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of less than 65534
machine cycle by software when using watchdog timer to keep the
microcomputer operating normally.
When the WEF flag is set to “1” after system is released from reset,
the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
The WEF flag is set to "1" at system reset or RAM back-up mode.
The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is
cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is “0”,
the next instruction is not skipped.
The skip function of the WRST instruction can be used even when
the watchdog timer function is invalid.
FFFF 1 6
Value of 16-bit timer (WDT)
000016
➁
WDF1 flag
➁
65534 count
(Note)
➃
WDF2 flag
RESET pin output
➀ Reset
released
➂ WRST instruction
executed
(skip executed)
➄ System reset
➀ After system is released from reset (= after program is started), timer WDT starts count down.
➁ When timer WDT underflow occurs, WDF1 flag is set to “1.”
➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped.
➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the
watchdog reset signal is output.
➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of cycle because the count source of watchdog timer
is the instruction clock.
Fig. 30 Watchdog timer function
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HARDWARE
FUNCTION BLOCK OPERATIONS
; WDF1 flag cleared
•••
WRST
; Watchdog timer function enabled/disabled
; WEF and WDF1 flags cleared
•••
DI
DWDT
WRST
•••
Fig. 31 Program example to start/stop watchdog timer
WRST
; WDF1 flag cleared
NOP
DI
; Interrupt disabled
EPOF
; POF instruction enabled
POF
↓
Oscillation stop
•••
When the watchdog timer is used, clear the WDF1 flag at a cycle of
less than 65534 machine cycles with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 31).
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the
power down mode.
When using the watchdog timer and the power down mode, initialize the WDF1 flag with the WRST instruction just before the system
enters the power down state (refer to Figure 32).
The watchdog timer function is valid after system is returned from
the power down. When not using the watchdog timer function, stop
the watchdog timer function with the DWDT instruction and the
WRST instruction continuously every system is returned from the
power down.
•••
4524 Group
Fig. 32 Program example to enter the mode when using the
watchdog timer
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
A/D CONVERTER (Comparator)
Table 11 A/D converter characteristics
Characteristics
Parameter
Successive comparison method
Conversion format
The 4524 Group has a built-in A/D conversion circuit that performs
conversion by 10-bit successive comparison method. Table 11
shows the characteristics of this A/D converter. This A/D converter
can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values.
Resolution
Relative accuracy
10 bits
Linearity error: ±2LSB
Differential non-linearity error: ±0.9LSB
31 µs (High-speed through-mode at 6.0
MHz oscillation frequency)
8
Conversion speed
Analog input pin
Register B (4)
Register A (4)
4
4
IAP2
(P20–P23)
IAP3
(P30–P33)
OP2A
(P20–P23)
OP3A
(P30–P33)
TAQ1
TQ1A
Q13 Q12 Q11 Q10
4
TAQ2
TQ2A
Q23 Q22 Q21 Q20
4
4
TAQ3
TQ3A
Q33 Q32 Q31 Q30
4
4
2
8
TALA
TABAD
8
TADAB
Instruction clock
1/6
3
Q13
P20/AIN0
P21/AIN1
P22/AIN2
P23/AIN3
P30/AIN4
P31/AIN5
P32/AIN6
P33/AIN7
8-channel multi-plexed analog switch
0
A/D control circuit
1
ADF
(1)
A/D
interrupt
1
Comparator
Successive comparison
register (AD) (10)
0
Q13
Q13
0
8
10
10
DAC
operation
signal
0
1
1
1
Q13
8
DA converter
8
8
VDD
(Note 1)
VSS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1).
The value of the comparator register is retained even when the mode is switched to the A/D conversion
mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 33 A/D conversion circuit structure
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FUNCTION BLOCK OPERATIONS
4524 Group
Table 12 A/D control registers
A/D control register Q1
Q13
A/D operation mode selection bit
Q12
Q11
Analog input pin selection bits
Q10
at reset : 00002
A/D conversion mode
Comparator mode
Q12 Q11 Q10
0
0
0 AIN0
0
0
1 AIN1
0
1
0 AIN2
0
1
1 AIN3
1
0
0 AIN4
1
0
1 AIN5
1
1
0 AIN6
1
1
1 AIN7
A/D control register Q2
Q23
P23/AIN3 pin function selection bit
Q22
P22/AIN2 pin function selection bit
Q21
P21/AIN1 pin function selection bit
Q20
P20/AIN0 pin function selection bit
at reset : 00002
0
1
0
1
0
1
0
1
A/D control register Q3
Q33
P33/AIN7 pin function selection bit
Q32
P32/AIN6 pin function selection bit
Q31
P31/AIN5 pin function selection bit
Q30
P30/AIN4 pin function selection bit
R/W
TAQ1/TQ1A
Analog input pins
at power down : state retained
R/W
TAQ2/TQ2A
at power down : state retained
R/W
TAQ3/TQ3A
P23
AIN3
P22
AIN2
P21
AIN1
P20
AIN0
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
P33
AIN7
P32
AIN6
P31
AIN5
P30
AIN4
Note: “R” represents read enabled, and “W” represents write enabled.
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(1) A/D control register
(4) A/D conversion completion flag (ADF)
• A/D control register Q1
Register Q1 controls the selection of A/D operation mode and the
selection of analog input pins. Set the contents of this register
through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register
A.
• A/D control register Q2
Register Q2 controls the selection of P20/AIN0–P23/AIN3. Set the
contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of
register Q2 to register A.
• A/D control register Q3
Register Q3 controls the selection of P30/AIN4–P33/AIN7. Set the
contents of this register through register A with the TQ3A instruction. The TAQ3 instruction can be used to transfer the contents of
register Q3 to register A.
A/D conversion completion flag (ADF) is set to “1” when A/D conversion completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(2) Operating at A/D conversion mode
The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”
(3) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute these instructions during A/D conversion.
When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can
be obtained with the reference voltage VDD by the following formula:
(5) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(6) Operation description
A/D conversion is started with the A/D conversion start instruction
(ADST). The internal operation during A/D conversion is as follows:
➀ When the A/D conversion starts, the register AD is cleared to
“00016.”
➁ Next, the topmost bit of the register AD is set to “1,” and the comparison voltage V ref is compared with the analog input voltage
VIN.
➂ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is Vref
> VIN, it is cleared to “0.”
The 4524 Group repeats this operation to the lowermost bit of the
register AD to convert an analog value to a digital value. A/D conversion stops after 62 machine cycles (31 µs when f(X IN) = 6.0
MHz in high-speed through mode) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated
condition is satisfied and the ADF flag is set to “1” as soon as A/D
conversion completes (Figure 34).
Logic value of comparison voltage Vref
Vref =
V DD
✕n
1024
n: The value of register AD (n = 0 to 1023)
Table 13 Change of successive comparison register AD during A/D conversion
At starting conversion
-------------
1st comparison
2nd comparison
3rd comparison
After 10th comparison
completes
✼1: 1st comparison result
✼3: 3rd comparison result
✼9: 9th comparison result
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Comparison voltage (Vref) value
Change of successive comparison register AD
1
✼1
✼1
0
1
✼2
0
0
-----
0
0
0
-------------
2
-------------
VDD
-----
-------------
0
0
0
2
-------------
1
-----
-------------
0
0
0
VDD
-------------
✼2
✼3
-----
-------------
✼8
✼9
✼A
VDD
±
4
VDD
2
A/D conversion result
✼1
VDD
2
VDD
±
±
VDD
±
4
○
○
○
○
±
8
VDD
1024
✼2: 2nd comparison result
✼8: 8th comparison result
✼A: 10th comparison result
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(7) A/D conversion timing chart
Figure 34 shows the A/D conversion timing chart.
ADST instruction
62 machine cycles
A/D conversion
completion flag (ADF)
DAC operation signal
Fig. 34 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P30/AIN4 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y)
= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),
and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.
The A/D interrupt is not used in this example.
➀ Select the AIN4 pin function with the bit 0 of the register Q3. Select the A IN4 pin function and A/D conversion mode with the
register Q1 (refer to Figure 35).
➁ Execute the ADST instruction and start A/D conversion.
➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion.
➃ Transfer the low-order 2 bits of converted data to the high-order
2 bits of register A (TALA instruction).
➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➅ Transfer the high-order 8 bits of converted data to registers A
and B (TABAD instruction).
➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➇ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
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(Bit 3)
✕
(Bit 0)
✕
✕
1
A/D control register Q2
A IN4 pin function selected
(Bit 3)
0
(Bit 0)
1
0
0
A/D control register Q1
A IN4 pin selected
A/D conversion mode
✕: Set an arbitrary value.
Fig. 35 Setting registers
1-50
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the
register Q1 to “1.”
Below, the operation at comparator mode is described.
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the
8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in
the low-order 4 bits of the comparator register with the TADAB instruction.
When changing from A/D conversion mode to comparator mode,
the result of A/D conversion (register AD) is undefined.
However, because the comparator register is separated from register AD, the value is retained even when changing from comparator
mode to A/D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
n: The value of register AD (n = 0 to 255)
(12) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator operating.
The comparator stops 8 machine cycles after it has started (4 µs at
f(XIN) = 6.0 MHz in high-speed through mode). When the analog
input voltage is lower than the comparison voltage, the ADF flag is
set to “1.”
(13) Notes for the use of A/D conversion
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
• Operation mode of A/D converter
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
Clear the bit 2 of register V2 to “0” to change the operating mode
of the A/D converter from the comparator mode to A/D conversion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is
lower than the comparison voltage, the ADF flag is set to “1.” The
state of ADF flag can be examined with the skip instruction
(SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
ADST instruction
8 machine cycles
Comparison result
store flag(ADF)
DAC operation signal
→
Comparator operation completed.
(The value of ADF is determined)
Fig. 36 Comparator operation timing chart
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FUNCTION BLOCK OPERATIONS
4524 Group
(14) Definition of A/D converter accuracy
Vn: Analog input voltage when the output data changes from “n” to
“n+1” (n = 0 to 1022)
The A/D conversion accuracy is defined below (refer to Figure 37).
• 1LSB at relative accuracy →
• Relative accuracy
➀ Zero transition voltage (V0T)
This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D conversion output data changes from “1023” to “1022.”
➂ Linearity error
This means a deviation from the line between V0T and VFST of
a converted value between V0T and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.
VFST–V0T
(V)
1022
• 1LSB at absolute accuracy →
VDD
1024
(V)
• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A/D conversion characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error = b–a [LSB]
a
Linearity error = c [LSB]
a
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB by relative accuracy
b: Vn+1–Vn
c: Difference between ideal Vn
and actual Vn
Ideal line of A/D conversion
between V0–V1022
1
0
V0
V1
Zero transition voltage (V0T)
Vn
Vn+1
V1022
VDD
Analog voltage
Fig. 37 Definition of A/D conversion accuracy
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
SERIAL I/O
Table 14 Serial I/O pins
The 4524 Group has a built-in clock synchronous serial I/O which
can serially transmit or receive 8-bit data.
Serial I/O consists of;
• serial I/O register SI
• serial I/O control register J1
• serial I/O transmit/receive completion flag (SIOF)
• serial I/O counter
Registers A and B are used to perform data transfer with internal
CPU, and the serial I/O pins are used for external data transfer.
The pin functions of the serial I/O pins can be set with the register
J1.
1/8
1/4
1/2
INSTCK
Pin
D6/SCK
D5/SOUT
D4/SIN
Pin function when selecting serial I/O
Clock I/O (SCK)
Serial data output (SOUT)
Serial data input (SIN)
Note: Even when the SCK, S OUT, SIN pin functions are used, the input of
D6, D5, D4 are valid.
J13J12
00
01
10
Synchronous
circuit
Serial I/O counter (3)
SIOF
Serial I/O
interrupt
11
D6/SCK
D5/SOUT
D4/SIN
SCK
Q
S
SST
instruction
R
Internal reset signal
SOUT
SIN
MSB Serial I/O register (8) LSB
TABSI
TSIAB
Register B (4)
TABSI
Register A (4)
J11 J10
Fig. 38 Serial I/O structure
Table 15 Serial I/O control register
Serial I/O control register J1
J13
J12
J11
J10
at reset : 00002
at power down : state retained
R/W
TAJ1/TJ1A
J13 J12
Synchronous clock
0 Instruction clock (INSTCK) divided by 8
0
Serial I/O synchronous clock selection bits 0
1 Instruction clock (INSTCK) divided by 4
0 Instruction clock (INSTCK) divided by 2
1
1 External clock (SCK input)
1
J11 J10
Port function
0 D6, D5, D4 selected/SCK, SOUT, SIN not selected
0
Serial I/O port function selection bits
1 SCK, SOUT, D4 selected/D6, D5, SIN not selected
0
0 SCK, D5, SIN selected/D6, SOUT, D4 not selected
1
1 SCK, SOUT, SIN selected/D6, D5, D4 not selected
1
Note: “R” represents read enabled, and “W” represents write enabled.
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FUNCTION BLOCK OPERATIONS
4524 Group
At transmit (D7–D0: transfer data)
At receive
SIN pin
Serial I/O register (SI)
SOUT pin
SOUT pin
SIN pin
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
*D
7 D6 D5 D4 D3 D2 D1
* ** * * ** *
Transfer data set
Transfer start
* *D
7 D6 D5 D4 D3 D2
* ** * * ** *
Serial I/O register (SI)
* ** * * ** *
D0
** * * ** *
D1 D0
Transfer complete
* * * ** *
D7 D6 D5 D4 D3 D2 D1 D0
Fig. 39 Serial I/O register state when transfer
(1) Serial I/O register SI
(3) Serial I/O start instruction (SST)
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and
B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of
register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When register SI is used as a work register without using serial I/O,
do not select the SCK pin.
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial I/O transmission/reception is started.
(4) Serial I/O control register J1
Register J1 controls the synchronous clock, D6/SCK, D5/SOUT and
D4/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to
transfer the contents of register J1 to register A.
(2) Serial I/O transmit/receive completion flag
(SIOF)
Serial I/O transmit/receive completion flag (SIOF) is set to “1” when
serial data transmit or receive operation completes. The state of
SIOF flag can be examined with the skip instruction (SNZSI). Use
the interrupt control register V2 to select the interrupt or the skip
instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
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FUNCTION BLOCK OPERATIONS
4524 Group
(5) How to use serial I/O
wiring between each pin with a resistor. Figure 40 shows the data
transfer timing and Table 16 shows the data transfer sequence.
Figure 40 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the
Master (clock control)
Slave (external clock)
SRDY signal
D3
(Bit 3)
0
0
1
(Bit 0)
1
D3
SCK
SCK
SOUT
SIN
SIN
SOUT
(Bit 0)
(Bit 3)
Serial I/O control
register J1
Serial I/O port
SCK,SOUT,SIN
1
1
1
Serial I/O control
register J1
Serial I/O port
SCK,SOUT,SIN
1
Instruction clock/8 selected
as synchronous clock
External clock selected
as synchronous clock
(Bit 0)
(Bit 3)
✕
0
✕
✕
(Bit 0)
(Bit 3)
Interrupt control
register V2
0
✕
✕
Interrupt control
register V2
✕
Serial I/O interrupt
enable bit
Serial I/O interrupt
enable bit
(SNZSI instruction valid)
(SNZSI instruction valid)
✕: Set an arbitrary value.
Fig. 40 Serial I/O connection example
Master
SOUT
M7’
SIN
M0
S7 ’
M1
S0
M2
S1
M3
S2
M4
S3
M5
S4
M6
S5
M7
S6
S7
SST instruction
SCK
Slave
SST instruction
SRDY signal
SOUT
SI N
S0
S7 ’
M7’
S1
M0
S2
M1
S3
M2
S4
M3
S5
M4
S6
M5
S7
M6
M7
M0–M7: Contents of master serial I/O register
S0–S7: Contents of slave serial I/O register
Rising of SCK: Serial input
Falling of SCK: Serial output
Fig. 41 Timing of serial I/O data transfer
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
Table 16 Processing sequence of data transfer from master to slave
Slave (reception)
Master (transmission)
[Initial setting]
[Initial setting]
• Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 40.
• Setting serial I/O mode register J1, and interrupt control register V2 shown in
Figure 40.
TJ1A and TV2A instructions
• Setting the port received the reception enable
signal (SRDY) to the input mode.
TJ1A and TV2A instructions
• Setting the port transmitted the reception enable signal (SRDY) and outputting
“H” level (reception impossible).
(Port D3 is used in this example)
SD instruction
* [Transmission enable state]
• Storing transmission data to serial I/O register SI.
TSIAB instruction
(Port D3 is used in this example)
SD instruction
*[Reception enable state]
• The SIOF flag is cleared to “0.”
SST instruction
• “L” level (reception possible) is output from port D3.
RD instruction
[Transmission]
•Check port D3 is “L” level.
[Reception]
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
• Check reception completes.
SNZSI instruction
•Wait (timing when continuously transferring)
SNZSI instruction
• “H” level is output from port D3.
SD instruction
[Data processing]
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally because serial transmit/receive is performed as long as clock is
externally input. (Unlike an internal clock, an external clock is not
stopped when serial transfer is completed.) However, the SIOF flag
is set to “1” when the clock is counted 8 times after executing the
SST instruction. Be sure to set the initial level of the external clock
to “H.”
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
LCD FUNCTION
(2) LCD clock control
The 4524 Group has an LCD (Liquid Crystal Display) controller/
driver. When the proper voltage is applied to LCD power supply input pins (VLC1 –V LC3 ) and data are set in timer control register
(W6), timer LC, LCD control registers (L1, L2), and LCD RAM, the
LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias.
4 common signal output pins and 20 segment signal output pins
can be used to drive the LCD. By using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled
to display. The LCD power input pins (VLC1–VLC3) are also used as
pins SEG0–SEG2. When SEG0–SEG2. The internal power (VDD) is
used for the LCD power.
The LCD clock is determined by the timer LC count source selection bit (W6 2 ), timer LC control bit (W6 3 ), and timer LC.
Accordingly, the LCD clock frequency (F) is obtained by the following formula. Numbers (➀ to ➂) shown below the formula
correspond to numbers in Figure 42, respectively.
(1) Duty and bias
• When using the bit 4 of timer 5 as timer LC count source (W62=“0”)
• When using the prescaler output (ORCLK) as timer LC count
source (W62=“1”)
F = ORCLK ✕
➀
There are 3 combinations of duty and bias for displaying data on
the LCD. Use bits 0 and 1 of LCD control register (L1) to select the
proper display method for the LCD panel being used.
• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias
1
✕
LC + 1
F = T54
➁
✕
➁
1
2
➂
[LC: 0 to 15]
The frame frequency and frame period for each display method
can be obtained by the following formula:
Table 17 Duty and maximum number of displayed pixels
Duty
1/2
1/3
1/4
➂
1
✕ LC + 1
➀
1
2
F
n
Frame frequency =
Maximum number of displayed pixels
Used COM pins
40 segments
COM0, COM1 (Note)
60 segments
COM0–COM2 (Note)
80 segments
COM0–COM3
n
F
Frame period =
(Hz)
(s)
F: LCD clock frequency
1/n: Duty
Note: Leave unused COM pins open.
(Note)
W63
W62
T54
0
ORCLK
1
➀
0
➁
Timer LC
➂
(4)
1
Reload register RLC
(TLCA)
1/2
LCD clock
(4)
(TLCA)
Register A
Note: Count source is stopped by setting “0” to this bit.
Fig. 42 LCD clock control circuit structure
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
VLC3/SEG0
VLC1/SEG2
VLC2/
SEG1
COM3
COM1
COM2
COM0
SEG3
to
SEG19
r
r
SEG0 to SEG2
output
r
.........
r
Multiplexer
r
r
Control
signal
Bias control
Common driver
Segment
driver
Selector
Decoder
RAM
...
Segment
driver
... Selector
...
RAM
LCD clock
(from timer block)
1/2,1/3,1/4 counter
LCD
ON/OFF
control
L13 L12 L11 L10
L23 L22 L21 L20
Register A
Fig. 43 LCD controller/driver
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(3) LCD RAM
(4) LCD drive waveform
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed.
When “1” is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to
the bit automatically becomes lV LC3l and the display pixel at the
cross section turns on.
When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common
output pin becomes VLC3 level.
Z
X
1
Bits
Y
8
9
10
11
12
13
14
15
COM
3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM3
2
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM2
Note: The area marked “
12
1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM1
13
0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM0
3
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM3
2
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM2
1
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM1
0
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM0
3
SEG16
SEG17
SEG18
SEG19
14
2
1
SEG16 SEG16
SEG17 SEG17
SEG18 SEG18
SEG19 SEG19
0
SEG16
SEG17
SEG18
SEG19
COM3 COM2 COM1 COM0
” is not the LCD display RAM.
Fig. 44 LCD RAM map
Table 18 LCD control registers
at reset : 00002
LCD control register L1
L13
Internal dividing resistor for LCD power
supply selection bit (Note 2)
L12
LCD control bit
L11
LCD duty and bias selection bits
L10
VLC3/SEG0 pin function switch bit (Note 3)
L22
VLC2/SEG1 pin function switch bit (Note 4)
L21
VLC1/SEG2 pin function switch bit (Note 4)
L20
Internal dividing resistor for LCD power
supply control bit
Duty
L11 L10
0
0
0
1
1
0
1
1
Bias
Not available
1/2
1/3
1/4
at reset : 11112
0
1
0
1
0
1
0
1
R/W
TAL1/TL1A
2r ✕ 3, 2r ✕ 2
r ✕ 3, r ✕ 2
Off
On
0
1
0
1
LCD control register L2
L23
at power down : state retained
1/2
1/3
1/3
at power down : state retained
W
TL2A
SEG0
VLC3
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
3: VLC3 is connected to VDD internally when SEG0 pin is selected.
4: Use internal dividing resistor when SEG1 and SEG 2 pins are selected.
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FUNCTION BLOCK OPERATIONS
4524 Group
1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 14, 8) in RAM.
1 flame (2/F)
M (1, 14, 8)
COM0
0 (bit 0)
COM1
1/F
Voltage level
VLC3
VLC1=VLC2
VSS
COM1
1
X
COM0
X (bit 3)
VLC3
VLC1=VLC2
VSS
SEG16
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM.
1 flame (3/F)
M (1, 14, 8)
COM0
1/F
Voltage level
1 (bit 0)
COM1
0
COM2
VLC3
VLC2
VLC1
VSS
COM2
1
X (bit 3)
COM1
SEG16
COM0
SEG16
COM2
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
ON
VLC3
VLC2
VLC1
VSS
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM.
1 flame (4/F)
M (1, 14, 8)
COM0
COM1
COM2
COM3
1 /F
Voltage level
0 (bit 0)
1
VLC3
VLC2
VLC1
VSS
COM3
0
1 (bit 3)
COM2
SEG16
COM1
COM0
F : LCD clock frequency
SEG16
X: Set an arbitrary value.
(These bits are not related to
set the drive waveform at each duty.)
COM3
SEG16
ON
COM2
SEG16
COM1
SEG16
OFF
ON
COM0
SEG16
VLC3
VLC2
VLC1
VSS
OFF
Fig. 45 LCD controller/driver structure
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(5) LCD power supply circuit
Select the LCD power circuit suitable for the LCD panel.
The LCD control circuit structure is fixed by the following setting.
➀ Set the control of internal dividing resistor by bit 0 of register L2.
➁ Select the internal dividing resistor by bit 3 of register L1.
➂ Select the bias condition by bits 0 and 1 of register L1.
• Internal dividing resistor
The 4524 Group has the internal dividing resistor for LCD power
supply.
When bit 0 of register L2 is set to “0”, the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2
of register L1 to “0”, the internal dividing resistor is turned off.
The same six resistor (r) is prepared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and
using bias condition, the resistor is prepared as follows;
• L13 = “0”, 1/3 bias used: 2r ✕ 3 = 6r
• L13 = “0”, 1/2 bias used: 2r ✕ 2 = 4r
• L13 = “1”, 1/3 bias used: r ✕ 3 = 3r
• L13 = “1”, 1/2 bias used: r ✕ 2 = 2r
• VLC3/SEG0 pin
The selection of VLC3/SEG0 pin function is controlled with the bit 3
of register L2.
When the VLC3 pin function is selected, apply voltage of V LC3 <
VDD to the pin externally.
When the SEG0 pin function is selected, VLC3 is connected to VDD
internally.
• VLC2/SEG1, VLC1/SEG2 pin
The selection of VLC2/SEG1 pin function is controlled with the bit 2
of register L2.
The selection of VLC1/SEG2 pin function is controlled with the bit 1
of register L2.
When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of
0<VLC1<VLC2<VLC3 to these pins. Short the VLC2 pin and VLC1 pin
at 1/2 bias.
When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is used, the dividing voltage value
generated internally is output from the VLC1 pin and VLC2 pin. The
VLC2 pin and VLC1 pin has the same electric potential at 1/2 bias.
When SEG1 and SEG2 pin function is selected, use the internal dividing resistor. In this time, V LC2 and VLC1 are connected to the
generated dividingg voltage.
VLC3
SEG0
VLC3
VLC3
VLC2
SEG1
VLC2
SEG1
VLC1
VLC1
SEG2
SEG2
b) Register L2 = (1000)2
a) Register L2 = (0000)2
VLC3
VLC2
VLC1
VLC3
VLC2
VLC1
c) Register L2 = (1110)2
VLC3
VLC2
VLC1
VLC3
VLC2
VLC1
d) Register L2 = (1111)2
Fig. 46 LCD power source circuit example (1/3 bias condition selected)
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
RESET FUNCTION
System reset is performed by applying “L” level to RESET pin for
1 machine cycle or more when the following condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
Then when “H” level is applied to RESET pin, program starts from
address 0 in page 0.
f(XIN)
RESET
On-chip oscillator (internal oscillator)
Program starts
(address 0 in page 0)
is counted 5400 to 5424 times.
Note: The number of clock cycles depends on the internal state of
the microcomputer when reset is performed.
Fig. 47 Reset release timing
=
Reset input
On-chip oscillator (internal oscillator) is
1 machine cycle or more
counted 5400 to 5424 times.
0.85VDD
Program starts
(address 0 in page 0)
RESET
0.3VDD
(Note)
Note: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 48 RESET pin input waveform and reset operation
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(1) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, the time for the supply voltage to
rise from 0 V must be set to 100 µs or less. If the rising time ex-
ceeds 100 µs, connect a capacitor between the RESET pin and
VSS at the shortest distance, and input “L” level to RESET pin until
the value of supply voltage reaches the minimum operating voltage.
100 µs or less
Pull-up transistor
VDD (Note 3)
Power-on reset circuit output
(Note 1)
(Note 2)
RESET pin
Internal reset signal
Power-on reset circuit
(Note 1)
Voltage drop detection circuit
Internal reset signal
Watchdog reset signal
WEF
Reset
state
Power-on
Reset released
This symbol represents a parasitic diode.
Notes 1:
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 49 Structure of reset pin and its peripherals, and power-on reset operation
Table 19 Port state at reset
Name
State
Function
D0–D3
D0–D3
High-impedance (Notes 1, 2)
D4/SIN, D5/SOUT, D6/SCK
D7/CNTR0
D4–D6
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
D8/INT0, D9/INT1
D7
D8, D9
P00–P03
P00–P03
High-impedance (Notes 1, 2, 3)
P10–P13
P10–P13
High-impedance (Notes 1, 2, 3)
P20/AIN0–P23/AIN3
P20–P23
High-impedance (Note 1)
P30/AIN4–P33/AIN7
P40–P43
P30–P33
High-impedance (Note 1)
High-impedance (Notes 1, 2)
C/CNTR1
P40–P43
C
High-impedance (Note 1)
“L” (VSS) level
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
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HARDWARE
4524 Group
FUNCTION BLOCK OPERATIONS
(2) Internal state at reset
Figure 50 and 51 show internal state at reset (they are the same after system is released from reset). The contents of timers, registers,
flags and RAM except shown in Figure 50 are undefined, so set the
initial value to them.
• Program counter (PC) ..........................................................................................................
0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
0
• Interrupt enable flag (INTE) .................................................................................................. 0
(Interrupt disabled)
0
0
0
0
0
0
0
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• External 1 interrupt request flag (EXF1) .............................................................................. 0
• Interrupt control register V1 ..................................................................................................
0 0 0 0
• Interrupt control register V2 ..................................................................................................
0 0 0 0
(Interrupt disabled)
(Interrupt disabled)
• Interrupt control register I1 ...................................................................................................
0 0 0 0
• Interrupt control register I2 ...................................................................................................
0 0 0 0
• Interrupt control register I3 ................................................................................................... 0
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Timer 3 interrupt request flag (T3F) ..................................................................................... 0
• Timer 4 interrupt request flag (T4F) ..................................................................................... 0
• Timer 5 interrupt request flag (T5F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0
• Timer control register W1 .....................................................................................................
0 0 0 0
(Prescaler stopped)
• Timer control register W2 .....................................................................................................
0 0 0 0
(Timer 1 stopped)
(Timer 2 stopped)
• Timer control register W3 .....................................................................................................
0 0 0 0
(Timer 3 stopped)
• Timer control register W4 .....................................................................................................
0 0 0 0
• Timer control register W5 .....................................................................................................
0 0 0 0
• Timer control register W6 .....................................................................................................
0 0 0 0
(Timer 4 stopped)
(Timer 5 stopped)
(Timer LC stopped)
• Clock control register MR .....................................................................................................
1 1 0 0
• Serial I/O transmit/receive complation flag (SIOF) .............................................................. 0
• Serial I/O mode register J1 ..................................................................................................
0 0 0 0
(External clock selected,
serial I/O port not selected)
• Serial I/O register SI .............................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• A/D conversion completion flag (ADF) ................................................................................. 0
• A/D control register Q1 .........................................................................................................
0 0 0 0
• A/D control register Q2 .........................................................................................................
0 0 0 0
• A/D control register Q3 .........................................................................................................
0 0 0 0
• Successive approximation register AD ................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Comparator register ..............................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• LCD control register L1 ........................................................................................................
0 0 0 0
• LCD control register L2 ........................................................................................................
1 1 1 1
“✕” represents undefined.
Fig. 50 Internal state at reset
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HARDWARE
4524 Group
FUNCTION BLOCK OPERATIONS
0 0 0 0
• Key-on wakeup control register K0 ......................................................................................
0 0 0 0
• Key-on wakeup control register K1 ......................................................................................
0 0 0 0
• Key-on wakeup control register K2 ......................................................................................
0 0 0 0
• Pull-up control register PU0 .................................................................................................
0 0 0 0
• Pull-up control register PU1 .................................................................................................
0 0 0 0
• Port output structure control register FR0 ...........................................................................
0 0 0 0
• Port output structure control register FR1 ...........................................................................
0 0 0 0
• Port output structure control register FR2 ...........................................................................
0 0 0 0
• Port output structure control register FR3 ...........................................................................
0
• Carry flag (CY) ......................................................................................................................
0 0 0 0
• Register A .............................................................................................................................
0 0 0 0
• Register B .............................................................................................................................
✕ ✕ ✕
• Register D .............................................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register E .............................................................................................................................
0 0 0 0
• Register X .............................................................................................................................
0 0 0 0
• Register Y .............................................................................................................................
✕ ✕
• Register Z .............................................................................................................................
1 1 1
• Stack pointer (SP) ................................................................................................................
• Operation source clock .......................................................... On-chip oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
• RC oscillation circuit ...................................................................................................... Stop
• Quarts-crystal oscillator ........................................................................................ Operating
“✕” represents undefined.
Fig. 51 Internal state at reset
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
The voltage drop detection circuit is valid when CPU is active while
the VDCE pin is “H”.
Even after system goes into the power down mode, the voltage
drop detection circuit is also valid with the SVDE instruction.
Execution of SVDE instruction is valid only at once.
In order to release the execution of the SVDE instruction, system
reset is not required.
EPOF instruction +POF instruction
EPOF instruction +POF2 instruction
S
Q
R
Q
S
SVDE instruction
R
Internal reset signal
Internal reset signal
T5F flag
Key-on wakeup signal
VDCE
Voltage drop detection circuit
Reset signal
–
VRST
+
Voltage drop detection circuit
Fig. 52 Voltage drop detection reset circuit
VDD
VRST (detection
voltage)
Voltage drop detection circuit
Reset signal
Microcomupter starts operation after
on-chip oscillator (internal oscillator)
clock is counted 5400 to 5424 times.
RESET pin
Note: Detection voltage of voltage drop detection circuit does not have hysteresis.
Fig. 53 Voltage drop detection circuit operation waveform
Table 20 Voltage drop detection circuit operation state
VDCE pin
At CPU operating
“L”
“H”
Invalid
Valid
At power down
(SVDE instruction is not executed)
Invalid
Invalid
■ Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 54);
supply voltage does not fall below to VRST, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST and re-goes up after that.
At power down
(SVDE instruction is executed)
Invalid
Valid
VDD
Recommended
operatng condition
min.value
VRST
No reset
Program failure may occur.
→ Normal operation
VDD
Recommended
operatng condition
min.value
VRST
Reset
Fig. 54 VDD and VRST
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1-66
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
POWER DOWN FUNCTION
The 4524 Group has 2-type power down functions.
System enters into each power down state by executing the following instructions.
• Clock operating mode ...................... EPOF and POF instructions
• RAM back-up mode ....................... EPOF and POF2 instructions
When the EPOF instruction is not executed before the POF or
POF2 instruction is executed, these instructions are equivalent to
the NOP instruction.
Table 21 Functions and states retained at power down
Power down mode
Function
Clock
operating
RAM
back-up
✕
✕
Contents of RAM
O
O
Interrupt control registers V1, V2
✕
✕
Interrupt control registers I1 to I3
Selected oscillation circuit
O
O
O
O
O
(Note 3)
O
(Note 3)
O
O
O
(Note 3)
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Clock control register MR
Timer 1 to timer 4 functions
(1) Clock operating mode
Timer 5 function
The following functions and states are retained.
• RAM
• Reset circuit
• XCIN–XCOUT oscillation
• LCD display
• Timer 5
Timer LC function
(2) RAM back-up mode
The following functions and states are retained.
• RAM
• Reset circuit
(3) Warm start condition
The system returns from the power down state when;
• External wakeup signal is input
• Timer 5 underflow occurs
in the power down mode.
In either case, the CPU starts executing the program from address
0 in page 0. In this case, the P flag is “1.”
Watchdog timer function
Timer control registers PA, W4
✕
✕
Serial I/O function
O
✕
O
✕
Serial I/O control register J1
O
O
A/D function
✕
✕
A/D control registers Q1 to Q3
LCD display function
O
O
O
(Note 5)
Voltage drop detection circuit
O
(Note 6)
O
(Note 6)
Port level
Timer control registers W1 to W3, W5, W6
LCD control registers L1, L2
(Note 7)
(Note 7)
Pull-up control registers PU0, PU1
O
O
Key-on wakeup control registers K0 to K2
Port output format control registers
O
O
O
O
✕
✕
FR0 to FR3
External interrupt request flags
(EXF0, EXF1)
(Note 3)
(Note 3)
Timer interrupt request flag (T5F)
A/D conversion completion flag (ADF)
O
O
✕
✕
Serial I/O transmit/receive completion flag
✕
✕
✕
✕
Timer interrupt request flags (T1F to T4F)
(4) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• reset pulse is input to RESET pin,
• reset by watchdog timer is performed, or
• reset by the voltage drop detection circuit is performed.
In this case, the P flag is “0.”
(5) Identification of the start condition
Warm start or cold start can be identified by examining the state of
the power down flag (P) with the SNZP instruction. The warm start
condition from the clock operating mode can be identified by examining the state of T5F flag.
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✕ (Note 4) ✕ (Note 4)
SIOF
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
✕ (Note 4) ✕ (Note 4)
Watchdog timer enable flag (WEF)
✕ (Note 4) ✕ (Note 4)
Notes 1:“O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at power
down, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at power down.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
go into the power down state.
5: LCD is turned off.
6: When the SVDE instruction is executed and “H” level is applied to
the VDCE pin, this function is valid at power down.
7: In the power down mode, C/CNTR1 pin outputs “L” level.
However, when the CNTR input is selected (W11, W10=“11”), C/
CNTR1 pin is in an input enabled state (output=high-impedance).
Other ports retain their respective output levels.
1-67
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(6) Return signal
An external wakeup signal or timer 5 interrupt request flag (T5F) is
used to return from the clock operating mode.
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped.
Table 22 shows the return condition for each return source.
(7) Control registers
• Key-on wakeup control register K0
Register K0 controls the port P0 key-on wakeup function. Set the
contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the
contents of register K0 to register A.
• Key-on wakeup control register K1
Register K1 controls the port P1 key-on wakeup function. Set the
contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the
contents of register K0 to register A.
• Key-on wakeup control register K2
Register K2 controls the INT0 and INT1 pin key-on wakeup function. Set the contents of this register through register A with the
TK2A instruction. In addition, the TAK2 instruction can be used to
transfer the contents of register K2 to register A.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the
TPU0A instruction. In addition, the TAPU0 instruction can be
used to transfer the contents of register PU0 to register A.
• Pull-up control register PU1
Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the
TPU1A instruction. In addition, the TAPU1 instruction can be
used to transfer the contents of register PU1 to register A.
• External interrupt control register I1
Register I1 controls the valid waveform of the external 0 interrupt, the input control of INT0 pin and the return input level. Set
the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer
the contents of register I1 to register A.
• External interrupt control register I2
Register I2 controls the valid waveform of the external 1 interrupt, the input control of INT1 pin and the return input level. Set
the contents of this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer
the contents of register I2 to register A.
External wakeup signal
Table 22 Return source and return condition
Remarks
Return source
Return condition
Ports P00–P03 Return by an external “L” level in- The key-on wakeup function can be selected by one port unit. Set the port
using the key-on wakeup function to “H” level before going into the power
Ports P10–P13 put.
down state.
Return by an external “H” level or Select the return level (“L” level or “H” level) with register I1 (I2) and return
INT0 pin
“L” level input, or rising edge condition (return by level or edge) with register K2 according to the external
INT1 pin
( “ L ” → “ H ” ) o r f a l l i n g e d g e state before going into the power down state.
(“H”→“L”).
Timer 5 interrupt
request flag (T5F)
When the return signal is input, the
interrupt request flag (EXF0,
EXF1) is not set to “1”.
Return by timer 5 underflow or by Clear T5F with the SNZT5 instruction before system enters into the power
setting T5F to “1”.
down state.
It can be used in the clock operat- When system enters into the power down state while T5F is “1”, system reing mode.
turns from the state immediately because it is recognized as return condition.
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
High-speed mode
E
Clock operating mode
B
POF instruction
execution
• Operation source clock: f(XIN)
• Oscillation circuit:
Ceramic resonator
T5F
Wakeup
(Stabilizing time c )
F
POF2 instruction
execution
Operation state
RAM back-up mode
Wakeup
(Stabilizing time c )
• On-chip oscillator: Stop
• RC oscillation circuit: Stop
CMCK instruction
execution (Note 3)
A
Reset
POF instruction
execution
(Stabilizing time a )
T5F
Wakeup
(Stabilizing time b )
Operation state
• Operation source clock:
f(RING)
• Oscillation circuit:
On-chip oscillator
• Ceramic resonator:
Operating (Note 2)
• RC oscillation circuit: Stop
POF2 instruction
execution
Wakeup
(Stabilizing time b )
CRCK instruction
execution (Note 3)
POF instruction
execution
T5F
Wakeup
(Stabilizing time d )
C
Operation state
• Operation source clock: f(XIN)
• Oscillation circuit:
RC oscillation
• On-chip oscillator: Stop
• Ceramic resontor: Stop
Low-speed
mode
POF instruction
execution
Main clock: stop
Sub-clock: operating
T5F
Wakeup
(Stabilizing time e )
MR0¨1
(Note 4)
POF2 instruction
execution
Wakeup
(Stabilizing time d )
MR0¨0
(Note 4)
D
Operation state
• Operation clock: f(XCIN)
• Oscillation circuit:
Quartz-crystal oscillation
POF2 instruction
execution
Wakeup
(Stabilizing time e )
Main clock: stop
Sub-clock: stop
Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5400 to 5424 times.
Stabilizing time b : In high-speed through-mode, microcomputer starts its operation after counting the f(RING) 675 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(RING) 1350 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(RING) 2700 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(RING) 5400 times.
Stabilizing time c : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 675 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 1350 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 2700 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 5400 times.
Stabilizing time d : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 21 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 42 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 84 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 168 times.
Stabilizing time e : In low-speed through-mode, microcomputer starts its operation after counting the f(XCIN) 675 times.
In low-speed/2 mode, microcomputer starts its operation after counting the f(XCIN) 1350 times.
In low-speed/4 mode, microcomputer starts its operation after counting the f(XCIN) 2700 times.
In low-speed/8 mode, microcomputer starts its operation after counting the f(XCIN) 5400 times.
Notes 1: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock.
3: The oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped.
4: The main clock (f(XIN) or f(RING)) or sub-clock (f(XCIN)) is selected for operation source clock by the bit 0 of clock control register MR.
5: The sub-clock (quartz-crystal oscillation) is operating except in state F.
Fig. 55 State transition
Program start
POF or
EPOF instruction + POF2
instruction
Reset input
Power down flag P
S
Q
R
POF or
● Set source • • • • • • • EPOF instruction + POF2
instruction
● Clear source • • • • • • Reset input
Fig. 56 Set source and clear source of the P flag
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P = “ 1”
?
Yes
Warm start
No
Cold start
T5F = “1”
?
Yes
No
Return from
timer 5 underflow
Return from
external wakeup signal
Fig. 57 Start condition identified example using the SNZP instruction
1-69
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
Table 23 Key-on wakeup control register, pull-up control register and interrupt control register
at reset : 00002
Key-on wakeup control register K0
K03
K02
K01
K00
Port P03 key-on wakeup
0
1
Key-on wakeup not used
control bit
Port P02 key-on wakeup
0
control bit
1
Key-on wakeup not used
Key-on wakeup used
Port P01 key-on wakeup
control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port P00 key-on wakeup
0
1
Key-on wakeup not used
control bit
Key-on wakeup control register K1
K13
K12
K11
K10
K22
K21
K20
R/W
TAK0/
TK0A
Key-on wakeup used
Key-on wakeup used
at reset : 00002
at power down : state retained
Port P13 key-on wakeup
0
Key-on wakeup used
control bit
Port P12 key-on wakeup
1
Key-on wakeup not used
0
Key-on wakeup not used
control bit
1
Key-on wakeup used
Port P11 key-on wakeup
Key-on wakeup not used
control bit
0
1
Port P10 key-on wakeup
0
Key-on wakeup used
Key-on wakeup not used
control bit
1
Key-on wakeup used
Key-on wakeup control register K2
K23
at power down : state retained
at reset : 00002
at power down : state retained
INT1 pin
return condition selection bit
0
Return by level
1
Return by edge
INT1 pin
0
Key-on wakeup not used
key-on wakeup control bit
Key-on wakeup used
INT0 pin
1
0
return condition selection bit
1
Return by level
Return by edge
INT0 pin
key-on wakeup control bit
0
Key-on wakeup not used
1
Key-on wakeup used
R/W
TAK1/
TK1A
R/W
TAK2/
TK2A
Note: “R” represents read enabled, and “W” represents write enabled.
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HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
at reset : 00002
Pull-up control register PU0
PU03
PU02
PU01
PU00
Port P03 pull-up transistor
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Port P02 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
Port P01 pull-up transistor
0
1
Pull-up transistor OFF
control bit
Port P00 pull-up transistor
0
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Pull-up control register PU1
PU13
PU12
PU11
PU10
at reset : 00002
0
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
control bit
Port P11 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Port P10 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
Pull-up transistor ON
Interrupt control register I1
I13
I12
I11
I10
INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
circuit selection bit
0
1
0
1
0
1
Interrupt control register I2
I23
I22
INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 2)
I21
INT1 pin edge detection circuit control bit
I20
INT1 pin Timer 3 count start synchronous
circuit selection bit
0
1
0
1
0
1
R/W
TAPU1/
TPU1A
at power down : state retained
R/W
TAI1/TI1A
INT0 pin input disabled
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
at reset : 00002
0
1
at power down : state retained
Pull-up transistor OFF
at reset : 00002
0
1
R/W
TAPU0/
TPU0A
Pull-up transistor ON
Port P13 pull-up transistor
Port P12 pull-up transistor
at power down : state retained
at power down : state retained
R/W
TAI2/TI2A
INT1 pin input disabled
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
instruction)
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
Timer 3 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.
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1-71
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
CLOCK CONTROL
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 58 shows the structure of the clock control circuit.
The 4524 Group operates by the on-chip oscillator clock (f(RING))
which is the internal oscillator after system is released from reset.
Also, the ceramic resonator or the RC oscillation can be used for
the main clock (f(XIN)) of the 4524 Group. The CMCK instruction or
CRCK instruction is executed to select the ceramic resonator or
RC oscillator, respectively.
The quartz-crystal oscillator can be used for sub-clock (f(XCIN)).
The clock control circuit consists of the following circuits.
• On-chip oscillator (internal oscillator)
• Ceramic resonator
• RC oscillation circuit
• Quartz-crystal oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit
Division circuit
Divided by 8
On-chip oscillator
(internal oscillator)
(Note 1)
Divided by 4
MR0
0
Multi-plexer
MR3, MR2
11
System clock (STCK)
10
Internal clock
generating circuit
(divided by 3)
01
Divided by 2
00
Instruction clock
(INSTCK)
Wait time
control circuit
(Note 2)
1
Q S
Program start
signal
Q R
RC oscillation
circuit
Q S
XIN
XOUT
Ceramic
oscillation circuit
R
Q S
MR1
XCIN
XCOUT
Quartz-crystal
oscillation circuit
CRCK instruction
Q S
R
CMCK instruction
R
Internal reset signal
T5F flag
Key-on wakeup signal
EPOF instruction + POF instruction
Q S
R
EPOF instruction + POF2 instruction
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed
after system is released from reset.
2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) or f(XCIN) oscillation.
After the certain oscillation stabilizing wait time elapses, the program start signal is output.
This circuit operates when system is released from reset or returned from power down.
Fig. 58 Clock control circuit structure
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1-72
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(1) Main clock generating circuit (f(XIN))
The ceramic resonator or RC oscillation can be used for the main
clock of this MCU.
After system is released from reset, the MCU starts operation by
the clock output from the on-chip oscillator which is the internal oscillator.
When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK
instruction. The oscillation circuit by the CMCK or CRCK instruction
is valid only at once. The oscillation circuit corresponding to the first
executed one of these two instructions is valid. Other oscillation circuit and the on-chip oscillator stop.
Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is
recommended). Also, when the CMCK or the CRCK instruction is
not executed in program, this MCU operates by the on-chip oscillator.
Reset
On-chip oscillator
operation
CMCK instruction
• Ceramic resonator valid
• On-chip oscillator stop
• RC oscillation stop
M34524
not use the CMCK instruction
* Do
and CRCK instruction in program.
XIN
XOUT
Fig. 60 Handling of XIN and XOUT when operating on-chip oscillator
M34524
the CMCK instruc* Execute
tion in program.
(3) Ceramic resonator
XIN
When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. Then, execute the CMCK instruction.
A feedback resistor is built in between pins XIN and XOUT (Figure
61).
XOUT
Note: Externally connect a damping
resistor Rd depending on the
Rd
oscillation frequency.
(A feedback resistor is built-in.)
Use the resonator manufacturer’s recommended value
COUT
because constants such as capacitance depend on the
resonator.
CI N
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect
the XIN pin to the external circuit of resistor R and the capacitor C
at the shortest distance and leave XOUT pin open. Then, execute
the CRCK instruction (Figure 62).
The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency
limits.
• RC oscillation valid
• On-chip oscillator stop
• Ceramic resonator stop
Fig. 59 Switch to ceramic oscillation/RC oscillation
(2) On-chip oscillator operation
When the MCU operates by the on-chip oscillator as the main clock
(f(XIN)) without using the ceramic resonator or the RC oscillation,
connect XIN pin to VSS and leave XOUT pin open (Figure 60).
The clock frequency of the on-chip oscillator depends on the supply
voltage and the operation temperature range.
Be careful that margin of frequencies when designing application
products.
CRCK instruction
Fig. 61 Ceramic resonator external circuit
M34524
R
XIN
XOUT
* EinxsetrcuuctteiotnheinCpRroCgKram.
C
Fig. 62 External RC oscillation circuit
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1-73
HARDWARE
FUNCTION BLOCK OPERATIONS
4524 Group
(5) External clock
When the external clock signal is used as the main clock (f(XIN)),
connect the XIN pin to the clock source and leave XOUT pin open.
Then, execute the CMCK instruction (Figure 63).
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using the
ceramic resonator (refer to the recommended operating condition).
Also, note that the power down function (POF or POF2 instruction)
cannot be used when using the external clock.
XIN
External oscillation circuit
M34524
XCIN
(7) Clock control register MR
Register MR controls system clock. Set the contents of this register
through register A with the TMRA instruction. In addition, the TAMR
instruction can be used to transfer the contents of register MR to
register A.
at reset : 11002
Clock control register MR
MR1
Main clock oscillation circuit control bit
MR0
System clock selection bit
CIN
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
XCOUT
(A feedback resistor is built-in.)
Use the quartz-crystal manufacturer’s recommended value
Rd
because constants such as capacitance depend on the
resonator.
COUT
Fig. 64 External quartz-crystal circuit
Table 24 Clock control register MR
MR2
VD D
VSS
The quartz-crystal oscillator can be used for the sub-clock signal
f(XCIN). Connect a quartz-crystal oscillator and this external circuit
to pins XCIN and XCOUT at the shortest distance. A feedback resistor is built in between pins XCIN and XCOUT (Figure 64).
Operation mode selection bits
XOUT
Fig. 63 External clock input circuit
(6) Sub-clock generating circuit f(XCIN)
MR3
* EinxsetrcuuctteiotnheinCpMroCgKram.
M34524
MR3 MR2
0
0
0
1
1
0
1
1
at power down : state retained
R/W
TAMR/
TMRA
Operation mode
Through mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
0
1
Main clock oscillation enabled
Main clock oscillation stop
0
Main clock (f(XIN) or f(RING))
1
Sub-clock (f(XCIN))
Note : “R” represents read enabled, and “W” represents write enabled.
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
✽For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/en/rom).
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1-74
HARDWARE
LIST OF PRECAUTIONS
4524 Group
LIST OF PRECAUTIONS
➀Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to V SS
through a resistor about 5 kΩ (connect this resistor to CNVSS/
VPP pin as close as possible).
➁Register initial values 1
The initial value of the following registers are undefined after system is released from reset. After system is released from reset,
set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
➂Register initial values 2
The initial value of the following registers are undefined at power
down. After system is returned from power down, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
➃ Stack registers (SKS)
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these
operations together.
➄Prescaler
Stop counting and then execute the TABPS instruction to read
from prescaler data.
Stop counting and then execute the TPSAB instruction to set
prescaler data.
➈Writing to reload register R1, R3, R4H
When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating,
avoid a timing when timer 1, timer 3 or timer 4 underflows.
10
Timer 4
Avoid a timing when timer 4 underflows to stop timer 4.
When “H” interval extension function of the PWM signal is set to
be “valid”, set “1” or more to reload register R4H.
11
Timer 5
Stop timer 5 counting to change its count source.
12
Timer input/output pin
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
13 Watchdog timer
• The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function, stop the
watchdog timer function and execute the DWDT instruction, the
WRST instruction continuously, and clear the WEF flag to “0”.
• The watchdog timer function is valid after system is returned from
the power down state. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT
instruction and the WRST instruction continuously every system
is returned from the power down state.
• When the watchdog timer function and power down function are
used at the same time, initialize the flag WDF1 with the WRST
instruction before system enters into the power down state.
14 Multifunction
• Be careful that the output of ports D8 and D9 can be used even
when INT0 and INT1 pins are selected.
• Be careful that the input of ports D4–D6 can be used even when
SIN, SOUT and SCK pins are selected.
• Be careful that the input/output of port D 7 can be used even
when input of CNTR0 pin are selected.
• Be careful that the input of port D7 can be used even when output of CNTR0 pin are selected.
• Be careful that the “H” output of port C can be used even when
output of CNTR1 pin are selected.
15
➅Timer count source
Stop timer 1, 2, 3, 4 and LC counting to change its count source.
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
➆Reading the count value
Stop timer 1, 2, 3 or 4 counting and then execute the data read
instruction (TAB1, TAB2, TAB3, TAB4) to read its data.
➇Writing to the timer
Stop timer 1, 2, 3, 4 or LC counting and then execute the data
write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its
data.
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1-75
HARDWARE
LIST OF PRECAUTIONS
4524 Group
D8/INT0 pin
❶ Note [1] on bit 3 of register I1
When the input of the INT0 pin is controlled with the bit 3 of register I1 in program, be careful about the following notes.
❸ Note on bit 2 of register I1
When the interrupt valid waveform of the D8/INT0 pin is changed
with the bit 2 of register I1 in program, be careful about the following notes.
• Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 65➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
65➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 65➂).
• Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 67➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
67➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 67➂).
•••
•••
16
LA
4
TV1A
LA
8
TI1A
NOP
SNZ0
LA
4
TV1A
LA
12
TI1A
NOP
SNZ0
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT0 pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 65 External 0 interrupt program example-1
Fig. 67 External 0 interrupt program example-3
❷ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared, the power down function
is selected and the input of INT0 pin is disabled, be careful about
the following notes.
•••
• When the input of INT0 pin is disabled, invalidate the key-on
wakeup function of INT0 pin (register K20 = “0”) before system
goes into the power down mode. (refer to Figure 66➀).
; (✕✕✕02)
; INT0 key-on wakeup invalid ........... ➀
; RAM back-up
•••
LA
0
TK2A
DI
EPOF
POF2
✕ : these bits are not used here.
Fig. 66 External 0 interrupt program example-2
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1-76
HARDWARE
LIST OF PRECAUTIONS
4524 Group
D9/INT1 pin
❶ Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of register I2 in program, be careful about the following notes.
❸ Note on bit 2 of register I2
When the interrupt valid waveform of the D9/INT1 pin is changed
with the bit 2 of register I2 in program, be careful about the following notes.
• Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 68➀)
and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
68➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 68➂).
• Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 70➀)
and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
70➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 70➂).
•••
•••
17
LA
4
TV1A
LA
8
TI2A
NOP
SNZ1
LA
4
TV1A
LA
12
TI2A
NOP
SNZ1
•••
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
•••
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT1 pin input is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
✕ : these bits are not used here.
Fig. 68 External 1 interrupt program example-1
❷ Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared, the power down function
is selected and the input of INT1 pin is disabled, be careful about
the following notes.
•••
• When the input of INT1 pin is disabled, invalidate the key-on
wakeup function of INT1 pin (register K2 2 = “0”) before system
goes into the power down mode. (refer to Figure 69➀).
; (✕0✕✕2)
; INT1 key-on wakeup invalid ........... ➀
18 A/D converter-1
• When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.”
• Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
• Clear the bit 2 of register V2 to “0” to change the operating mode
of the A/D converter from the comparator mode to A/D conversion mode.
• The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a
value to the register Q1, and execute the SNZAD instruction to
clear the ADF flag.
✕ : these bits are not used here.
Fig. 69 External 1 interrupt program example-2
•••
; RAM back-up
•••
LA
0
TK2A
DI
EPOF
POF2
Fig. 70 External 1 interrupt program example-3
LA
8
TV2A
LA
0
TQ1A
; (✕0✕✕2)
; The SNZAD instruction is valid ........ ➀
; (0✕✕✕2)
; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
•••
SNZAD
NOP
✕ : these bits are not used here.
Fig. 71 A/D converter program example-3
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HARDWARE
LIST OF PRECAUTIONS
4524 Group
19
A/D converter-2
Each analog input pin is equipped with a capacitor which is used
to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A/D accuracy may
not be obtained. Therefore, reduce the impedance or, connect a
capacitor (0.01 µF to 1 µF) to analog input pins (Figure 72).
When the overvoltage applied to the A/D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 73. In addition, test
the application products sufficiently.
Sensor
21
POF and POF2 instructions
When the POF or POF2 instruction is executed continuously after the EPOF instruction, system enters the power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF or POF2
instruction continuously.
22
Power-on reset
When the built-in power-on reset circuit is used, the time for the
supply voltage to rise from 0 V to 2.0 V must be set to 100 µs or
less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input
“L” level to RESET pin until the value of supply voltage reaches
the minimum operating voltage.
23
Clock control
Execute the CMCK or the CRCK instruction in the initial setting routine
of program (executing it in address 0 in page 0 is recommended).
The oscillation circuit by the CMCK or CRCK instruction can be
selected only at once. The oscillation circuit corresponding to the
first executed one of these two instruction is valid. Other oscillation circuits and the on-chip oscillator stop.
24
On-chip oscillator
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range.
Be careful that margin of frequencies when designing application
products.
Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the
oscillation stabilize wait time after system is released from reset, be
careful that the margin of frequency of the on-chip oscillator clock.
AIN
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 72 Analog input external circuit example-1
About 1kΩ
Sensor
AIN
Fig. 73 Analog input external circuit example-2
20
Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor
added to the power supply pin, the following case may cause
program failure (Figure 74);
supply voltage does not fall below to VRST, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage
is once reduced below to VRST and re-goes up after that.
25
26
Difference between Mask ROM version and One Time PROM version
Mask ROM version and One Time PROM version have some difference of the following characteristics within the limits of an
electrical property by difference of a manufacture process, builtin ROM, and a layout pattern.
• a characteristic value
• the amount of noise-proof
• a margin of operation
• noise radiation, etc.,
Accordingly, be careful of them when swithcing.
27
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
VDD
Recommended
operatng condition
min.value
VRST
No reset
Program failure may occur.
→ Normal operation
VDD
Recommended
operatng condition
min.value
VRST
Reset
Fig. 74 VDD and VRST
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REJ09B0107-0200Z
External clock
When the external clock signal is used as the main clock (f(XIN)), note
that the power down mode (POF or POF2 instruction) cannot be used.
1-78
HARDWARE
CONTROL REGISTERS
4524 Group
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
External 1 interrupt enable bit
V10
External 0 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V2
V23
Timer 4, serial I/O interrupt enable bit
V22
A/D interrupt enable bit
V21
Timer 5 interrupt enable bit
V20
Timer 3 interrupt enable bit
0
1
0
1
0
1
0
1
I12
I11
I10
INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
circuit selection bit
0
1
0
1
0
1
Interrupt control register I2
I23
I22
I21
I20
INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 2)
INT1 pin edge detection circuit control bit
INT1 pin Timer 3 count start synchronous
circuit selection bit
0
1
0
1
0
1
0
1
Timer 4, serial I/O interrupt source selection
bit
at power down : state retained
R/W
TAI1/TI1A
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
instruction)
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
at power down : state retained
R/W
TAI2/TI2A
INT1 pin input disabled
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
instruction)
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
Timer 3 count start synchronous circuit selected
at reset : 02
0
1
R/W
TAV2/TV2A
INT0 pin input disabled
at reset : 00002
Interrupt control register I3
I30
at power down : 00002
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
at reset : 00002
0
1
R/W
TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
Interrupt control register I1
I13
at power down : 00002
at power down : state retained
R/W
TAI3/TI3A
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set to “1”.
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1-79
HARDWARE
CONTROL REGISTERS
4524 Group
Clock control register MR
at reset : 11002
MR3 MR2
MR3
Operation mode selection bits
MR2
MR1
Main clock oscillation circuit control bit
MR0
System clock selection bit
0
0
1
1
0
1
0
1
Prescaler control bit
Timer 1 count auto-stop circuit selection
bit (Note 2)
W12
Timer 1 control bit
W11
Timer 1 count source selection bits
W10
CNTR0 output control bit
W22
Timer 2 control bit
W21
Timer 2 count source selection bits
W20
1
Sub-clock (f(XCIN))
Timer 3 count auto-stop circuit selection
bit (Note 3)
W32
Timer 3 control bit
W31
W30
Timer 3 count source selection bits
(Note 4)
at power down : 02
W
TPAA
at power down : state retained
R/W
TAW1/TW1A
at reset : 02
Stop (state initialized)
Operating
at reset : 00002
0
1
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
W11 W10
Count source
0
Instruction clock (INSTCK)
0
0
Prescaler output (ORCLK)
1
1
Timer 5 underflow signal (T5UDF)
0
1
CNTR0 input
1
at reset : 00002
at power down : state retained
R/W
TAW2/TW2A
0
1
0
1
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating
W21 W20
Count source
0
System clock (STCK)
0
0
Prescaler output (ORCLK)
1
1
Timer 1 underflow signal (T1UDF)
0
1
PWM signal (PWMOUT)
1
Timer control register W3
W33
Frequency divided by 8 mode
Main clock oscillation stop
Main clock (f(XIN) or f(RING))
Timer control register W2
W23
Frequency divided by 4 mode
Main clock oscillation enabled
Timer control register W1
W13
Frequency divided by 2 mode
1
0
0
1
R/W
TAMR/
TMRA
Operation mode
Through mode (frequency not divided)
0
Timer control register PA
PA0
at power down : state retained
at reset : 00002
at power down : state retained
R/W
TAW3/TW3A
0
1
0
1
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating
W31 W30
Count source
0
PWM signal (PWMOUT)
0
0
Prescaler output (ORCLK)
1
1
Timer 2 underflow signal (T2UDF)
0
1
CNTR1 input
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
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1-80
HARDWARE
CONTROL REGISTERS
4524 Group
Timer control register W4
W43
CNTR1 output control bit
W42
PWM signal
“H” interval expansion function control bit
W41
Timer 4 control bit
W40
Timer 4 count source selection bit
0
1
0
1
0
1
0
1
Timer control register W5
W53
Not used
W52
Timer 5 control bit
W51
Timer 5 count value selection bits
W50
Timer LC control bit
0
1
0
1
W62
Timer LC count source selection bit
W61
W60
CNTR1 output auto-control circuit
selection bit
D7/CNTR0 pin function selection bit
(Note 2)
at power down : state retained
R/W
TAW5/TW5A
This bit has no function, but read/write is enabled.
Stop (state initialized)
Operating
W51 W50
0
0
0
1
1
0
1
1
Count value
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAW4/TW4A
CNTR1 output invalid
CNTR1 output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK) divided by 2
at reset : 00002
Timer control register W6
W63
at power down : 00002
at reset : 00002
at power down : state retained
R/W
TAW6/TW6A
Stop (state retained)
Operating
Bit 4 (T54) of timer 5
Prescaler output (ORCLK)
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
D7(I/O)/CNTR0 input
CNTR0 input/output/D7 (input)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
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1-81
HARDWARE
CONTROL REGISTERS
4524 Group
Serial I/O control register J1
J13
J12
J11
J10
at reset : 00002
A/D operation mode selection bit
Q12
Q11
R/W
TAJ1/TJ1A
Synchronous clock
J13 J12
0 Instruction clock (INSTCK) divided by 8
0
Serial I/O synchronous clock selection bits 0
1 Instruction clock (INSTCK) divided by 4
0 Instruction clock (INSTCK) divided by 2
1
1 External clock (SCK input)
1
Port function
J11 J10
0 D6, D5, D4 selected/SCK, SOUT, SIN not selected
0
Serial I/O port function selection bits
1 SCK, SOUT, D4 selected/D6, D5, SIN not selected
0
0 SCK, D5, SIN selected/D6, SOUT, D4 not selected
1
1 SCK, SOUT, SIN selected/D6, D5, D4 not selected
1
A/D control register Q1
Q13
at power down : state retained
Analog input pin selection bits
Q10
at reset : 00002
A/D conversion mode
Comparator mode
Q12 Q11 Q10
0
0
0 AIN0
0
0
1 AIN1
0
1
0 AIN2
0
1
1 AIN3
1
0
0 AIN4
1
0
1 AIN5
1
1
0 AIN6
1
1
1 AIN7
A/D control register Q2
Q23
P23/AIN3 pin function selection bit
Q22
P22/AIN2 pin function selection bit
Q21
P21/AIN1 pin function selection bit
Q20
P20/AIN0 pin function selection bit
at reset : 00002
0
1
0
1
0
1
0
1
A/D control register Q3
Q33
P33/AIN7 pin function selection bit
Q32
P32/AIN6 pin function selection bit
Q31
P31/AIN5 pin function selection bit
Q30
P30/AIN4 pin function selection bit
R/W
TAQ1/TQ1A
Analog input pins
at power down : state retained
R/W
TAQ2/TQ2A
at power down : state retained
R/W
TAQ3/TQ3A
P23
AIN3
P22
AIN2
P21
AIN1
P20
AIN0
at reset : 00002
0
1
0
1
0
1
0
1
at power down : state retained
P33
AIN7
P32
AIN6
P31
AIN5
P30
AIN4
Note: “R” represents read enabled, and “W” represents write enabled.
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1-82
HARDWARE
CONTROL REGISTERS
4524 Group
at reset : 00002
LCD control register L1
L13
Internal dividing resistor for LCD power
supply selection bit (Note 2)
L12
LCD control bit
L11
LCD duty and bias selection bits
L10
VLC3/SEG0 pin function switch bit (Note 3)
L22
VLC2/SEG1 pin function switch bit (Note 4)
L21
VLC1/SEG2 pin function switch bit (Note 4)
L20
Internal dividing resistor for LCD power
supply control bit
PU02
PU01
PU00
PU12
PU11
PU10
1/2
1/3
1/4
1/2
1/3
1/3
at power down : state retained
Port P03 pull-up transistor
0
Pull-up transistor OFF
control bit
Port P02 pull-up transistor
1
Pull-up transistor ON
0
Pull-up transistor OFF
control bit
1
Port P01 pull-up transistor
0
Pull-up transistor ON
Pull-up transistor OFF
control bit
1
0
Pull-up transistor ON
Port P00 pull-up transistor
control bit
1
Pull-up transistor ON
at reset : 00002
0
Pull-up transistor OFF
1
Pull-up transistor ON
Port P12 pull-up transistor
0
control bit
1
Pull-up transistor OFF
Pull-up transistor ON
Port P11 pull-up transistor
0
1
Pull-up transistor OFF
0
Pull-up transistor OFF
1
Pull-up transistor ON
Port P10 pull-up transistor
control bit
at power down : state retained
R/W
TAPU0/
TPU0A
at power down : state retained
R/W
TAPU1/
TPU1A
Pull-up transistor OFF
Port P13 pull-up transistor
control bit
control bit
W
TL2A
SEG0
VLC3
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
at reset : 00002
Pull-up control register PU1
PU13
Bias
Not available
at reset : 11112
Pull-up control register PU0
PU03
Duty
L11 L10
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
R/W
TAL1/TL1A
2r ✕ 3, 2r ✕ 2
r ✕ 3, r ✕ 2
Off
On
0
1
0
1
LCD control register L2
L23
at power down : state retained
Pull-up transistor ON
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
3: VLC3 is connected to VDD internally when SEG0 pin is selected.
4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-83
HARDWARE
CONTROL REGISTERS
4524 Group
Port output structure control register FR0
FR03
FR02
FR01
FR00
Ports P12, P13 output structure selection
at reset : 00002
0
1
N-channel open-drain output
Ports P10, P11 output structure selection
bit
0
N-channel open-drain output
1
CMOS output
Ports P02, P03 output structure selection
0
bit
1
N-channel open-drain output
CMOS output
Ports P00, P01 output structure selection
0
1
bit
bit
FR13
Port D3 output structure selection bit
FR12
Port D2 output structure selection bit
FR10
Port D1 output structure selection bit
Port D0 output structure selection bit
FR23
Port D7/CNTR0 output structure selection bit
FR22
Port D6/SCK output structure selection bit
FR21
Port D5/SOUT output structure selection bit
FR20
Port D4/SIN output structure selection bit
Port P43 output structure selection bit
FR32
Port P42 output structure selection bit
FR31
FR30
Port P41 output structure selection bit
Port P40 output structure selection bit
CMOS output
at power down : state retained
N-channel open-drain output
1
0
CMOS output
1
CMOS output
0
N-channel open-drain output
1
0
CMOS output
N-channel open-drain output
1
CMOS output
at power down : state retained
0
N-channel open-drain output
1
CMOS output
N-channel open-drain output
0
W
TFR1A
N-channel open-drain output
at reset : 00002
1
0
CMOS output
1
CMOS output
0
N-channel open-drain output
1
CMOS output
Port output structure control register FR3
FR33
N-channel open-drain output
0
Port output structure control register FR2
W
TFR0A
CMOS output
at reset : 00002
Port output structure control register FR1
FR11
at power down : state retained
W
TFR2A
N-channel open-drain output
at reset : 00002
at power down : state retained
0
N-channel open-drain output
1
0
CMOS output
1
CMOS output
0
N-channel open-drain output
1
0
CMOS output
N-channel open-drain output
1
CMOS output
W
TFR3A
N-channel open-drain output
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-84
HARDWARE
CONTROL REGISTERS
4524 Group
Key-on wakeup control register K0
K03
K02
Port P03 key-on wakeup control bit
Port P02 key-on wakeup control bit
K01
Port P01 key-on wakeup control bit
K00
Port P00 key-on wakeup control bit
at reset : 00002
0
Key-on wakeup not used
1
0
Key-on wakeup used
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
0
Key-on wakeup used
1
Key-on wakeup used
Key-on wakeup control register K1
K13
Port P13 key-on wakeup control bit
K12
Port P12 key-on wakeup control bit
K11
Port P11 key-on wakeup control bit
K10
Port P10 key-on wakeup control bit
K22
K21
K20
INT1 pin return condition selection bit
INT1 pin key-on wakeup control bit
INT0 pin return condition selection bit
INT0 pin key-on wakeup control bit
R/W
TAK0/
TK0A
Key-on wakeup not used
at reset : 00002
at power down : state retained
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
0
Key-on wakeup used
1
Key-on wakeup not used
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
at reset : 00002
Key-on wakeup control register K2
K23
at power down : state retained
0
Returned by level
1
Returned by edge
0
1
Key-on wakeup invalid
0
Key-on wakeup valid
Returned by level
1
Returned by edge
0
Key-on wakeup invalid
1
Key-on wakeup valid
at power down : state retained
R/W
TAK1/
TK1A
R/W
TAK2/
TK2A
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-85
HARDWARE
INSTRUCTIONS
4524 Group
INSTRUCTIONS
SYMBOL
The 4524 Group has the 136 instructions. Each instruction is described as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
The symbols shown below are used in the following list of instruction function and the machine instructions.
Symbol
A
B
DR
E
V1
V2
I1
I2
I3
MR
PA
W1
W2
W3
W4
W5
W6
J1
Q1
Q2
Q3
L1
L2
PU0
PU1
FR0
FR1
FR2
FR3
K0
K1
K2
X
Y
Z
DP
PC
PCH
PCL
SK
SP
CY
RPS
R1
R2
R3
R4L
R4H
RLC
Contents
Register A (4 bits)
Register B (4 bits)
Register DR (3 bits)
Register E (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Interrupt control register I2 (4 bits)
Interrupt control register I3 (1 bit)
Clock control register MR (4 bits)
Timer control register PA (1 bit)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
Timer control register W5 (4 bits)
Timer control register W6 (4 bits)
Serial I/O control register J1 (4 bits)
A/D control register Q1 (4 bits)
A/D control register Q2 (4 bits)
A/D control register Q3 (4 bits)
LCD control register L1 (4 bits)
LCD control register L2 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Port output format control register FR0 (4 bits)
Port output format control register FR1 (4 bits)
Port output format control register FR2 (4 bits)
Port output format control register FR3 (4 bits)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
Carry flag
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer 3 reload register (8 bits)
Timer 4 reload register (8 bits)
Timer 4 reload register (8 bits)
Timer LC reload register (4 bits)
Symbol
PS
T1
T2
T3
T4
T5
TLC
T1F
T2F
T3F
T4F
T5F
WDF1
WEF
INTE
EXF0
EXF1
P
ADF
SIOF
Contents
Prescaler
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer LC
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Timer 4 interrupt request flag
Timer 5 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
External 1 interrupt request flag
Power down flag
A/D conversion completion flag
Serial I/O transmit/receive completion flag
D
P0
P1
P2
P3
P4
C
Port D (10 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (4 bits)
Port P3 (4 bits)
Port P4 (4 bits)
Port C (1 bit)
x
y
z
p
n
i
j
A 3A 2A 1A 0
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
←
↔
?
( )
—
M(DP)
a
p, a
Direction of data movement
Data exchange between a register and memory
Decision of state shown before “?”
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p5 p4 p3 p2 p1 p0
Hex. C + Hex. number x
C
+
x
Note : Some instructions of the 4524 Group has the skip function to unexecute the next described instruction. The 4524 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip
is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-86
HARDWARE
INSTRUCTIONS
4524 Group
INDEX LIST OF INSTRUCTION FUNCTION
Register to register transfer
TAB
Function
(A) ← (B)
Page
GroupMnemonic
ing
111, 132
TBA
(B) ← (A)
121, 132
TAY
(A) ← (Y)
120, 132
TYA
(Y) ← (A)
130, 132
TEAB
(E7–E4) ← (B)
121, 132
XAMI j
RAM to register transfer
GroupMnemonic
ing
(E3–E0) ← (A)
TABE
(B) ← (E7–E4)
Function
(A) ← → (M(DP))
Page
131, 132
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
(M(DP)) ← (A)
125, 132
(X) ← (X)EXOR(j)
j = 0 to 15
LA n
(A) ← n
n = 0 to 15
98, 134
TABP p
(SP) ← (SP) + 1
113, 134
112, 132
(A) ← (E3–E0)
(SK(SP)) ← (PC)
TDA
TAD
(DR2–DR0) ← (A2–A0)
(A2–A0) ← (DR2–DR0)
121, 132
(PCH) ← p
113, 132
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A3) ← 0
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
TAZ
(A1, A0) ← (Z1, Z0)
121, 132
(SP) ← (SP) – 1
(A3, A2) ← 0
(A) ← (X)
120, 132
TASP
(A2–A0) ← (SP2–SP0)
118, 132
(A3) ← 0
LXY x, y
(X) ← x x = 0 to 15
98, 132
RAM addresses
(Y) ← y y = 0 to 15
LZ z
(Z) ← z z = 0 to 3
99, 132
INY
(Y) ← (Y) + 1
98, 132
DEY
(Y) ← (Y) – 1
95, 132
TAM j
(A) ← (M(DP))
116, 132
RAM to register transfer
(X) ← (X)EXOR(j)
AM
(A) ← (A) + (M(DP))
92, 134
AMC
(A) ← (A) + (M(DP)) + (CY)
92, 134
(CY) ← Carry
Arithmetic operation
TAX
An
(A) ← (A) + n
n = 0 to 15
92, 134
AND
(A) ← (A) AND (M(DP))
93, 134
OR
(A) ← (A) OR (M(DP))
100, 134
SC
(CY) ← 1
104, 134
RC
(CY) ← 0
102, 134
SZC
(CY) = 0 ?
109, 134
CMA
(A) ← (A)
95, 134
RAR
→ CY → A3A2A1A0
101, 134
j = 0 to 15
XAM j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
131, 132
j = 0 to 15
XAMD j
(A) ← → (M(DP))
131, 132
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
Note: p is 0 to 63 for M34524M8,
p is 0 to 95 for M34524MC and
p is 0 to 127 for M34524ED.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-87
HARDWARE
INSTRUCTIONS
4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Bit operation
GroupMnemonic
ing
Function
Page
GroupMnemonic
ing
DI
(INTE) ← 0
96, 138
EI
(INTE) ← 1
96, 138
SNZ0
V10 = 0: (EXF0) = 1 ?
105, 138
SB j
(Mj(DP)) ← 1
j = 0 to 3
103, 134
RB j
(Mj(DP)) ← 0
101, 134
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
109, 134
SEAM
(A) = (M(DP)) ?
105, 134
SEA n
(A) = n ?
105, 134
Page
After skipping, (EXF0) ← 0
V10 = 1: NOP
SNZ1
Comparison
operation
Function
V11 = 0: (EXF1) = 1 ?
105, 138
After skipping, (EXF1) ← 0
V11 = 1: NOP
SNZI0
n = 0 to 15
I12 = 1 : (INT0) = “H” ?
106, 138
Ba
(PCL) ← a6–a0
93, 136
BL p, a
(PCH) ← p
93, 136
SNZI1
(PCL) ← a6–a0
BLA p
(PCH) ← p
93, 136
(PCL) ← (DR2–DR0, A3–A0)
BM a
(SP) ← (SP) + 1
Interrupt operation
Branch operation
I12 = 0 : (INT0) = “L” ?
94, 136
I22 = 1 : (INT1) = “H” ?
106, 138
I22 = 0 : (INT1) = “L” ?
TAV1
(A) ← (V1)
118, 138
TV1A
(V1) ← (A)
128, 138
TAV2
(A) ← (V2)
118, 138
TV2A
(V2) ← (A)
128, 138
TAI1
(A) ← (I1)
114, 138
TI1A
(I1) ← (A)
123, 138
TAI2
(A) ← (I2)
114, 138
TI2A
(I2) ← (A)
123, 138
TAI3
(A0) ← (I30), (A3–A1) ← 0
114, 138
TI3A
(I30) ← (A0)
123, 138
TPAA
(PA0) ← (A0)
126, 138
TAW1
(A) ← (W1)
119, 138
TW1A
(W1) ← (A)
129, 138
TAW2
(A) ← (W2)
119, 138
TW2A
(W2) ← (A)
129, 138
TAW3
(A) ← (W3)
119, 138
TW3A
(W3) ← (A)
129, 138
(SK(SP)) ← (PC)
Subroutine operation
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
(SP) ← (SP) + 1
94, 136
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
BMLA p
(SP) ← (SP) + 1
94, 136
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
RTI
(PC) ← (SK(SP))
103, 136
(SP) ← (SP) – 1
RT
(PC) ← (SK(SP))
103, 136
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
103, 136
Timer operation
Return operation
(SP) ← (SP) – 1
Note: p is 0 to 63 for M34524M8, p is 0 to 95 for M34524MC and p is 0 to 127 for M34524ED.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-88
HARDWARE
INSTRUCTIONS
4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic
Function
Page
TAW4
(A) ← (W4)
119, 138
TW4A
(W4) ← (A)
129, 138
TAW5
(A) ← (W5)
120, 140
TW5A
(W5) ← (A)
130, 140
GroupMnemonic
ing
T4HAB
Function
(R4H7–R4H4) ← (B)
Page
110, 140
(R4H3–R4H0) ← (A)
TR1AB
(R17–R14) ← (B)
127, 140
(R13–R10) ← (A)
TR3AB
(R37–R34) ← (B)
128, 140
(R33–R30) ← (A)
TAW6
(A) ← (W6)
121, 140
TW6A
(W6) ← (A)
130, 140
TABPS
(B) ← (TPS7–TPS4)
113, 140
T4R4L
TPSAB
(RPS7–RPS4) ← (B)
126, 140
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
TAB1
(B) ← (T17–T14)
TLCA
(LC) ← (A)
125, 140
SNZT1
V12 = 0: (T1F) = 1 ?
107, 142
After skipping, (T1F) ← 0
SNZT2
Timer operation
(R17–R14) ← (B)
V13 = 0: (T2F) = 1 ?
107, 142
After skipping, (T2F) ← 0
111, 140
SNZT3
(A) ← (T13–T10)
T1AB
111, 140
(T43–T40) ← (R4L3–R4L0)
Timer operation
(A) ← (TPS3–TPS0)
(T47–T44) ← (R4L7–R4L4)
V20 = 0: (T3F) = 1 ?
107, 142
After skipping, (T3F) ← 0
109, 140
SNZT4
(T17–T14) ← (B)
V23 = 0: (T4F) = 1 ?
108, 142
After skipping, (T4F) ← 0
(R13–R10) ← (A)
(T13–T10) ← (A)
SNZT5
V21 = 0: (T5F) = 1 ?
108, 142
After skipping, (T5F) ← 0
TAB2
T2AB
(B) ← (T27–T24)
(A) ← (T23–T20)
111, 140
(R27–R24) ← (B)
110, 140
IAP0
(A) ← (P0)
97, 142
OP0A
(P0) ← (A)
99, 142
IAP1
(A) ← (P1)
97, 142
OP1A
(P1) ← (A)
99, 142
IAP2
(A) ← (P2)
97, 142
OP2A
(P2) ← (A)
100, 142
IAP3
(A) ← (P3)
97, 142
OP3A
(P3) ← (A)
100, 142
IAP4
(A) ← (P4)
98, 142
OP4A
(P4) ← (A)
100, 142
(T27–T24) ← (B)
(R23–R20) ← (A)
TAB3
(B) ← (T37–T34)
112, 140
(A) ← (T33–T30)
T3AB
(R37–R34) ← (B)
110, 140
(T37–T34) ← (B)
(R33–R30) ← (A)
(T33–T30) ← (A)
TAB4
(B) ← (T47–T44)
112, 140
(A) ← (T43–T40)
T4AB
(R4L7–R4L4) ← (B)
Input/Output operation
(T23–T20) ← (A)
110, 140
(T47–T44) ← (B)
(R4L3–R4L0) ← (A)
(T43–T40) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-89
HARDWARE
INSTRUCTIONS
4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Function
Page
CLD
(D) ← 1
94, 142
RD
(D(Y)) ← 0
102, 142
(Y) = 0 to 9
SD
SZD
(D(Y)) ← 1
(Y) = 0 to 9
104, 142
(D(Y)) = 0 ?
109, 142
GroupMnemonic
ing
LCD operation
Grouping Mnemonic
Function
Page
TAL1
(A) ← (L1)
116, 144
TL1A
(L1) ← (A)
124, 144
TL2A
(L2) ← (A)
124, 144
TABSI
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
113, 144
TSIAB
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
128, 144
SST
(SIOF) ← 0
108, 144
Input/Output operation
RCP
(C) ← 0
102, 142
SCP
(C) ← 1
104, 142
TAPU0
(A) ← (PU0)
117, 142
TPU0A
(PU0) ← (A)
126, 142
TAPU1
(A) ← (PU1)
117, 142
TPU1A
(PU1) ← (A)
126, 142
TAK0
(A) ← (K0)
124, 144
TK0A
(K0) ← (A)
115, 144
TAK1
(A) ← (K1)
124, 144
Serial I/O operation
(Y) = 0 to 9
Serial I/O starting
SNZSI
V23=0: (SIOF)=1?
107, 144
After skipping, (SIOF) ← 0
TAJ1
(A) ← (J1)
115, 144
TJ1A
(J1) ← (A)
123, 144
TABAD
In A/D conversion mode ,
(B) ← (AD9–AD6)
112, 146
(A) ← (AD5–AD2)
In comparator mode,
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TALA
(A3, A2) ← (AD1, AD0)
116, 146
(A1, A0) ← 0
TK1A
(K1) ← (A)
115, 144
TAK2
(A) ← (K2)
124, 144
TK2A
(K2) ← (A)
115, 144
Clock operation
TADAB
(AD7–AD4) ← (B)
114, 146
A/D operation
(AD3–AD0) ← (A)
ADST
(ADF) ← 0
92, 146
A/D conversion starting
TFR0A
(FR0) ← (A)
122, 144
TFR1A
(FR1) ← (A)
122, 144
TFR2A
(FR2) ← (A)
122, 144
TAQ1
(A) ← (Q1)
117, 146
TFR3A
(FR3) ← (A)
122, 144
TQ1A
(Q1) ← (A)
127, 146
CMCK
Ceramic resonator selected
95, 144
TAQ2
(A) ← (Q2)
117, 146
CRCK
RC oscillator selected
95, 144
TQ2A
(Q2) ← (A)
127, 146
TAMR
(A) ← (MR)
116, 144
TAQ3
(A) ← (Q3)
118, 146
TMRA
(MR) ← (A)
125, 144
TQ3A
(Q3) ← (A)
127, 146
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
SNZAD
V22 = 0: (ADF) = 1 ?
106, 146
After skipping, (ADF) ← 0
1-90
HARDWARE
INSTRUCTIONS
4524 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Other operation
GroupMnemonic
ing
Function
Page
NOP
(PC) ← (PC) + 1
POF
Transition to clock operating mode 101, 146
POF2
Transition to RAM back-up mode
EPOF
POF, POF2 instructions valid
SNZP
(P) = 1 ?
DWDT
Stop of watchdog timer function
enabled
WRST
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
RBK*
When TABP p instruction is ex- 102, 146
ecuted, P6 ← 0
SBK*
When TABP p instruction is ex- 104, 146
ecuted, P6 ← 1
SVDE
At power down mode, voltage 108, 146
drop detection circuit valid
99, 146
101, 146
96, 146
106, 146
96, 146
130, 146
Note: *(RBK, SBK) cannot be used in the M34524M8.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-91
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
0
n
n
n
n
2
0
6
n
16
(A) ← (A) + n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Overflow = 0
Grouping:
Arithmetic operation
Description: Adds the value n in the immediate field to
register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
Executes the next instruction when there is
overflow as the result of operation.
ADST (A/D conversion STart)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
1
1
2
2
9
F
16
(ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting
(Q13 : bit 3 of A/D control register Q1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Clears (0) to A/D conversion completion
flag ADF, and the A/D conversion at the A/D
conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13
= 1) is started.
AM (Add accumulator and Memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
0
1
0
2
0
0
A
16
(A) ← (A) + (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
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REJ09B0107-0200Z
0
1
1
2
0
0
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in register A and carry flag CY.
1-92
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
AND (logical AND between accumulator and memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
0
0
0
2
0
1
8
16
(A) ← (A) AND (M(DP))
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the AND operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
B a (Branch to address a)
Instruction
code
Operation:
D0
D9
0
1
1
a6 a5 a4 a3 a2 a1 a0
2
1
8
+a
a
16
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
Note:
Specify the branch address within the page
including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction
code
D9
0
1
Operation:
D0
0
1
1
1
p4 p3 p2 p1 p0
2
p6 p5 a6 a5 a4 a3 a2 a1 a0 2
0
E
+p
p
2
+p
p
+a
a 16
16
(PCH) ← p
(PCL) ← a6 to a0
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
a in page p.
Note:
p is 0 to 63 for M34524M8, and p is 0 to 95
for M34524MC, and p is 0 to 127 for
M34524ED.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction
code
D9
0
1
Operation:
D0
0
0
0
0
p6 p5 p4 0
1
0
0
0
0
2
p3 p2 p1 p0 2
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
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REJ09B0107-0200Z
0
0
1
0
2
+p
p
p 16
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
(DR2 DR 1 DR 0 A3 A 2 A 1 A 0)2 specified by
registers D and A in page p.
Note:
p is 0 to 63 for M34524M8, and p is 0 to 95
for M34524MC, and p is 0 to 127 for
M34524ED.
1-93
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BM a (Branch and Mark to address a in page 2)
Instruction
code
Operation:
D9
0
D0
1
0
a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
Grouping:
Subroutine call operation
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
Note:
Subroutine extending from page 2 to another page can also be called with the BM
instruction when it starts on page 2.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BML p, a (Branch and Mark Long to address a in page p)
Instruction
code
D9
0
1
Operation:
D0
0
1
1
0
p4 p3 p2 p1 p0
2
p6 p5 a6 a5 a4 a3 a2 a1 a0 2
0
C
+p
p
2
+p
p
+a
a 16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note:
p is 0 to 63 for M34524M8, and p is 0 to 95
for M34524MC, and p is 0 to 127 for
M34524ED.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction
code
D9
0
1
Operation:
D0
0
0
0
1
p6 p5 p4 0
1
0
0
0
0
0
2
p3 p2 p1 p0 2
0
3
0
2
+p
p
p 16
16
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
Note:
p is 0 to 63 for M34524M8, and p is 0 to 95 for
M34524MC, and p is 0 to 127 for M34524ED.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
CLD (CLear port D)
Instruction
code
Operation:
D9
0
D0
0
0
(D) ← 1
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REJ09B0107-0200Z
0
0
1
0
0
0
1
2
0
1
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to port D.
1-94
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CMA (CoMplement of Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
1
1
0
0 2
0
1
C 16
(A) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Stores the one’s complement for register
A’s contents in register A.
CMCK (Clock select: ceraMic oscillation ClocK)
Instruction
code
Operation:
D0
D9
1
0
1
0
0
1
1
0
1
0
2
2
9
A
16
Ceramic oscillation circuit selected
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Selects the ceramic oscillation circuit and
stops the on-chip oscillator.
CRCK (Clock select: Rc oscillation ClocK)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
0
1
1
2
2
9
B
16
RC oscillation circuit selected
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Selects the RC oscillation circuit and stops
the on-chip oscillator.
DEY (DEcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
(Y) ← (Y) – 1
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REJ09B0107-0200Z
0
0
1
0
1
1
1
2
0
1
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
1-95
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DI (Disable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
0
0
2
0
0
4
16
(INTE) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Clears (0) to interrupt enable flag INTE, and
disables the interrupt.
Note:
Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
0
0
2
2
9
C
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Stops the watchdog timer function by the
WRST instruction after executing the
DWDT instruction.
Stop of watchdog timer function enabled
EI (Enable Interrupt)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
0
1
2
0
0
5
16
(INTE) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt control operation
Description: Sets (1) to interrupt enable flag INTE, and
enables the interrupt.
Note:
Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
1
0
1
POF instruction, POF2 instruction valid
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
2
0
5
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Makes the immediate after POF or POF2
instruction valid by executing the EPOF instruction.
1-96
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP0 (Input Accumulator from port P0)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
0
0
2
2
6
0
16
(A) ← (P0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
0
0
0
0
1
2
2
6
1
16
(A) ← (P1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P1 to register A.
IAP2 (Input Accumulator from port P2)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
0
1
0
2
2
6
2
16
(A) ← (P2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P2 to register A.
IAP3 (Input Accumulator from port P3)
Instruction
code
Operation:
D9
1
D0
0
0
(A) ← (P3)
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REJ09B0107-0200Z
1
1
0
0
0
1
1
2
2
6
3
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P3 to register A.
1-97
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP4 (Input Accumulator from port P4)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
0
0
1
0
0 2
2
6
4 16
(A) ← (P4)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the input of port P4 to register A.
INY (INcrement register Y)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
1
0
0
1
1
2
0
1
3
16
(Y) ← (Y) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
1
1
1
n
n
n
n
2
0
7
n
16
(A) ← n
n = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
Arithmetic operation
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA instruction is executed and other LA
instructions coded continuously are
skipped.
LXY x, y (Load register X and Y with x and y)
Instruction
code
Operation:
D9
1
D0
1
x3 x2 x1 x0 y3 y2 y1 y0
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
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REJ09B0107-0200Z
2
3
x
y
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
RAM addresses
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instructions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
1-98
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LZ z (Load register Z with z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
1
0
z1 z0 2
0
4
8
+z 16
(Z) ← z z = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM addresses
Description: Loads the value z in the immediate field to
register Z.
NOP (No OPeration)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
0
0
0
0
2
0
0
0
16
(PC) ← (PC) + 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: No operation; Adds 1 to program counter
value, and others remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
0
0
2
2
2
0
16
(P0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P0.
OP1A (Output port P1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
(P1) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
1
0
0
0
0
1
2
2
2
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P1.
1-99
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP2A (Output port P2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
1
0
2
2
2
2
16
(P2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P2.
OP3A (Output port P3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
0
1
1
2
2
2
3 16
(P3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P3.
OP4A (Output port P4 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
0
1
0
0
2
2
2
4 16
(P4) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port
P4.
OR (logical OR between accumulator and memory)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
(A) ← (A) OR (M(DP))
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REJ09B0107-0200Z
1
1
0
0
1
2
0
1
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Takes the OR operation between the contents of register A and the contents of
M(DP), and stores the result in register A.
1-100
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
POF (Power OFf1)
Instruction
code
Operation:
D9
D0
0
0
0
0
0
0
0
0
1
0
2
0
0
2
16
Transition to clock operating mode
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Puts the system in clock operating state by
executing the POF instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed before
executing this instruction, this instruction is
equivalent to the NOP instruction.
POF2 (Power OFf2)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
1
0
0
0
2
0
0
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Puts the system in RAM back-up state by
executing the POF2 instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed before
executing this instruction, this instruction is
equivalent to the NOP instruction.
Transition to RAM back-up mode
RAR (Rotate Accumulator Right)
Instruction
code
D9
D0
0
0
0
0
0
1
1
1
0
1
2
0
1
D
16
→ CY → A3A2A1A0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the
right.
RB j (Reset Bit)
Instruction
code
Operation:
D9
0
D0
0
0
(Mj(DP)) ← 0
j = 0 to 3
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
0
1
1
j
j
2
0
4
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
1-101
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RBK (Reset Bank flag)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
0
0
0
2
0
4
0 16
When TABP p instruction is executed, P6 ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Sets referring data area to pages 0 to 63
when the TABP p instruction is executed.
Note: This instruction cannot be used in M34524M8.
RC (Reset Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
0
2
0
0
6 16
(CY) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
–
Grouping:
Arithmetic operation
Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
1
1
0
0
2
2
8
C 16
(C) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to port C.
RD (Reset port D specified by register Y)
Instruction
code
Operation:
D9
0
D0
0
0
(D(Y)) ← 0
However,
(Y) = 0 to 9
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
0
1
0
1
0
0 2
0
1
4 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y.
1-102
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RT (ReTurn from subroutine)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
0
2
0
4
4
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
–
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine.
RTI (ReTurn from Interrupt)
Instruction
code
Operation:
D0
D9
0
0
0
1
0
0
0
1
1
0
2
0
4
6
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Return operation
Description: Returns from interrupt service routine to
main routine.
Returns each value of data pointer (X, Y, Z),
carry flag, skip status, NOP mode status by
the continuous description of the LA/LXY instruction, register A and register B to the
states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
1
0
1
2
0
4
5
16
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
Skip at uncondition
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instruction
code
Operation:
D9
0
D0
0
0
(Mj(DP)) ← 1
j = 0 to 3
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REJ09B0107-0200Z
1
0
1
1
1
j
j
2
0
5
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
1-103
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SBK (Set Bank flag)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
0
0
0
0
1
2
0
4
1 16
When TABP p instruction is executed, P6 ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Sets referring data area to pages 64 to 127
when the TABP p instruction is executed.
Note: This instruction cannot be used in M34524M8.
In M34524MC, referring data area is pages 64 to 95.
SC (Set Carry flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
0
1
1
1
2
0
0
7
16
(CY) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
1
–
Grouping:
Arithmetic operation
Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
1
1
0
1
2
2
8
D
16
(C) ← 1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to port C.
SD (Set port D specified by register Y)
Instruction
code
Operation:
D9
0
D0
0
0
(D(Y)) ← 1
(Y) = 0 to 9
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REJ09B0107-0200Z
0
0
1
0
1
0
1
2
0
1
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
1-104
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction
code
D9
0
0
Operation:
D0
0
0
0
0
0
1
1
1
0
1
0
n
1
n
0
n
1
2
n 2
0
0
2
7
(A) = n ?
n = 0 to 15
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(A) = n
n 16
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the value n in
the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n
in the immediate field.
SEAM (Skip Equal, Accumulator with Memory)
Instruction
code
Operation:
D0
D9
0
0
0
0
1
0
0
1
1
0
2
0
2
6
16
(A) = (M(DP)) ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(A) = (M(DP))
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the contents of
M(DP).
Executes the next instruction when the contents of register A is not equal to the
contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
0
0
2
0
3
8
16
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
(V10 : bit 0 of the interrupt control register V1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V10 = 0: (EXF0) = 1
Grouping:
Interrupt operation
Description: When V10 = 0 : Skips the next instruction
when external 0 interrupt request flag EXF0
is “1.” After skipping, clears (0) to the EXF0
flag. When the EXF0 flag is “0,” executes
the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction.
SNZ1 (Skip if Non Zero condition of external 1 interrupt request flag)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
0
1
2
V11 = 0: (EXF1) = 1 ?
After skipping, (EXF1) ← 0
V11 = 1: SNZ1 = NOP
(V11 : bit 1 of the interrupt control register V1)
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0
3
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V11 = 0: (EXF1) = 1
Grouping:
Interrupt operation
Description: When V11 = 0 : Skips the next instruction
when external 1 interrupt request flag EXF1
is “1.” After skipping, clears (0) to the EXF1
flag. When the EXF1 flag is “0,” executes
the next instruction.
When V11 = 1 : This instruction is equivalent to the NOP instruction.
1-105
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
1
1
1
2
2
8
7
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V22 = 0: (ADF) = 1
16
V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0
V22 = 1: SNZAD = NOP
(V22 : bit 2 of the interrupt control register V2)
Grouping:
A/D conversion operation
Description: When V22 = 0 : Skips the next instruction
when A/D conversion completion flag ADF
is “1.” After skipping, clears (0) to the ADF
flag. When the ADF flag is “0,” executes the
next instruction.
When V2 2 = 1 : This instruction is equivalent to the NOP instruction.
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
1
0
2
0
3
A 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
I12 = 0 : (INT0) = “L”
I12 = 1 : (INT0) = “H”
Grouping:
Interrupt operation
Description: When I1 2 = 0 : Skips the next instruction
when the level of INT0 pin is “L.” Executes
the next instruction when the level of INT0
pin is “H.”
When I1 2 = 1 : Skips the next instruction
when the level of INT0 pin is “H.” Executes
the next instruction when the level of INT0
pin is “L.”
I12 = 0 : (INT0) = “L” ?
I12 = 1 : (INT0) = “H” ?
(I12 : bit 2 of the interrupt control register I1)
SNZI1 (Skip if Non Zero condition of external 1 Interrupt input pin)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
0
1
1
2
0
3
B 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
I22 = 0 : (INT1) = “L”
I22 = 1 : (INT1) = “H”
Grouping:
Interrupt operation
Description: When I2 2 = 0 : Skips the next instruction
when the level of INT1 pin is “L.” Executes
the next instruction when the level of INT1
pin is “H.”
When I2 2 = 1 : Skips the next instruction
when the level of INT1 pin is “H.” Executes
the next instruction when the level of INT1
pin is “L.”
I22 = 0 : (INT1) = “L” ?
I22 = 1 : (INT1) = “H” ?
(I22 : bit 2 of the interrupt control register I2)
SNZP (Skip if Non Zero condition of Power down flag)
Instruction
code
Operation:
D9
0
D0
0
0
(P) = 1 ?
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REJ09B0107-0200Z
0
0
0
0
0
1
1
2
0
0
3
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(P) = 1
Grouping:
Other operation
Description: Skips the next instruction when the P flag is
“1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P
flag is “0.”
1-106
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZSI (Skip if Non Zero condition of Serial I/o interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
1
0
0
0
2
2
8
8
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V23 = 0: (SIOF) = 1
16
V23 = 0: (SIOF) = 1 ?
After skipping, (SIOF) ← 0
V23 = 1: SNZSI = NOP
(V23 = bit 3 of interrupt control register V2)
Grouping:
Serial I/O operation
Description: When V23 = 0 : Skips the next instruction
when serial I/O interrupt request flag SIOF
is “1.” After skipping, clears (0) to the SIOF
flag. When the SIOF flag is “0,” executes
the next instruction.
When V2 3 = 1 : This instruction is equivalent to the NOP instruction.
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction
code
Operation:
D0
D9
1
0
1
0
0
0
0
0
0
0
2
2
8
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V12 = 0: (T1F) = 1
16
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1: SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
Grouping:
Timer operation
Description: When V12 = 0 : Skips the next instruction
when timer 1 interrupt request flag T1F is
“1.” After skipping, clears (0) to the T1F
flag. When the T1F flag is “0,” executes the
next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
0
1
2
2
8
1
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V13 = 0: (T2F) = 1
16
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1: SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
Grouping:
Timer operation
Description: When V13 = 0 : Skips the next instruction
when timer 2 interrupt request flag T2F is
“1.” After skipping, clears (0) to the T2F
flag. When the T2F flag is “0,” executes the
next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction.
SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
1
0
V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0
V20 = 1: SNZT3 = NOP
(V20 = bit 0 of interrupt control register V2)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2
2
8
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V20 = 0: (T3F) = 1
Grouping:
Timer operation
Description: When V20 = 0 : Skips the next instruction
when timer 3 interrupt request flag T3F is
“1.” After skipping, clears (0) to the T3F
flag. When the T3F flag is “0,” executes the
next instruction.
When V20 = 1 : This instruction is equivalent to the NOP instruction.
1-107
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
0
1
1
2
2
8
3 16
V23 = 0: (T4F) = 1 ?
After skipping, (T4F) ← 0
V23 = 1: SNZT4 = NOP
(V23 = bit 3 of interrupt control register V2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V23 = 0: (T4F) = 1
Grouping:
Timer operation
Description: When V23 = 0 : Skips the next instruction
when timer 4 interrupt request flag T4F is
“1.” After skipping, clears (0) to the T4F
flag. When the T4F flag is “0,” executes the
next instruction.
When V23 = 1 : This instruction is equivalent to the NOP instruction.
SNZT5 (Skip if Non Zero condition of Timer 5 inerrupt request flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
0
0
1
0
0
2
2
8
4
16
V21 = 0: (T5F) = 1 ?
After skipping, (T5F) ← 0
V21 = 1: SNZT5 = NOP
(V21 = bit 1 of interrupt control register V2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
V21 = 0: (T5F) = 1
Grouping:
Timer operation
Description: When V21 = 0 : Skips the next instruction
when timer 5 interrupt request flag T5F is
“1.” After skipping, clears (0) to the T5F
flag. When the T5F flag is “0,” executes the
next instruction.
When V21 = 1 : This instruction is equivalent to the NOP instruction.
SST (Serial i/o transmission/reception STart)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
1
1
1
0
2
2
9
E
16
(SIOF) ← 0
Serial I/O transmission/reception start
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Clears (0) to SIOF flag and starts serial I/O.
SVDE (Set Voltage Detector Enable flag)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
0
1
1
2
2
9
3
At power down mode, voltage drop detection circuit valid
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Validates the voltage drop detection circuit
at power down (clock operating mode and
RAM back-up mode) when VDCE pin is “H”.
1-108
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZB j (Skip if Zero, Bit)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
0
0
j
j
2
0
2
j
16
(Mj(DP)) = 0 ?
j = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Mj(DP)) = 0
j = 0 to 3
Grouping:
Bit operation
Description: Skips the next instruction when the contents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
SZC (Skip if Zero, Carry flag)
Instruction
code
Operation:
D0
D9
0
0
0
0
1
0
1
1
1
1
2
0
2
F
16
(CY) = 0 ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(CY) = 0
Grouping:
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag CY is “0.”
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY flag is “1.“
SZD (Skip if Zero, port D specified by register Y)
Instruction
code
Operation:
D9
D0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1 2
2
0
2
4
0
2
B 16
16
Number of
words
Number of
cycles
Flag CY
2
2
–
Skip condition
(D(Y)) = 0
(Y) = 0 to 7
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
(D(Y)) = 0 ?
(Y) = 0 to 7
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
(T17–T14) ← (B)
(R17–R14) ← (B)
(T13–T10) ← (A)
(R13–R10) ← (A)
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REJ09B0107-0200Z
1
1
0
0
0
0
2
2
3
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1.
1-109
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
0
1
2
2
3
1
16
(T27–T24) ← (B)
(R27–R24) ← (B)
(T23–T20) ← (A)
(R23–R20) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2.
T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
1
0 2
2
3
2 16
(T37–T34) ← (B)
(R37–R34) ← (B)
(T33–T30) ← (A)
(R33–R30) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 3 and timer 3 reload register R3. Transfers the contents of
register A to the low-order 4 bits of timer 3
and timer 3 reload register R3.
T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
0
1
1 2
2
3
3 16
(T47–T44) ← (B)
(R4L7–R4L4) ← (B)
(T43–T40) ← (A)
(R4L3–R4L0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 4 and timer 4 reload register R4L. Transfers the contents of
register A to the low-order 4 bits of timer 4
and timer 4 reload register R4L.
T4HAB (Transfer data to register R4H from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
(R4H7–R4H4) ← (B)
(R4H3–R4H0) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
1
1
1
2
2
3
7 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 4 and timer 4 reload register R4H. Transfers the contents of
register A to the low-order 4 bits of timer 4
and timer 4 reload register R4H.
1-110
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T4R4L (Transfer data to timer 4 from register R4L)
Instruction
code
Operation:
D9
1
D0
0
1
0
0
1
0
1
1
1
2
2
9
7 16
(T47–T44) ← (R4L7–R4L4)
(T43–T40) ← (R4L3–R4L0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of reload register
R4L to timer 4.
TAB (Transfer data to Accumulator from register B)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
1
1
1
1
0
2
0
1
E
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(A) ← (B)
Grouping:
Register to register transfer
Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
0
0
0
2
2
7
0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T17–T14)
(A) ← (T13–T10)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
Operation:
D9
1
D0
0
0
1
(B) ← (T27–T24)
(A) ← (T23–T20)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
1
0
0
0
1
2
2
7
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
1-111
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB3 (Transfer data to Accumulator and register B from timer 3)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
0
1
0
2
2
7
2
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T37–T34)
(A) ← (T33–T30)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T37–T34) of
timer 3 to register B.
Transfers the low-order 4 bits (T33–T30) of
timer 3 to register A.
TAB4 (Transfer data to Accumulator and register B from timer 4)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
0
0
1
1
2
2
7
3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T47–T44)
(A) ← (T43–T40)
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (T47–T44) of
timer 4 to register B.
Transfers the low-order 4 bits (T43–T40) of
timer 4 to register A.
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
1
0
0
1
2
2
7
9
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD 9 –AD 6 ) of
register AD to register B, and the middle-order 4 bits (AD 5 –AD 2 ) of register AD to
register A. In the comparator mode (Q13 = 1),
transfers the middle-order 4 bits (AD7–AD4)
of register AD to register B, and the low-order
4 bits (AD3–AD0) of register AD to register A.
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
Operation:
D9
0
D0
0
0
0
(B) ← (E7–E4)
(A) ← (E3–E0)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
1
0
1
0
2
0
2
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E 7 –E4) of
register E to register B, and low-order 4 bits
of register E to register A.
1-112
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
Operation:
D9
0
D0
0
1
0
p5 p4 p3 p2 p1 p0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
2
0
8
+p
p 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
3
–
–
Grouping:
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0
are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
after system is released from reset or returned from power down: 0 to 63.
Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED.
When this instruction is executed, be careful not to over the stack because 1 stage of
stack register is used.
TABPS (Transfer data to Accumulator and register B from PreScaler)
Instruction
code
Operation:
D0
D9
1
0
0
1
1
1
0
1
0
1
2
2
7
5 16
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the high-order 4 bits (TPS 7 –
TPS 4 ) of prescaler to register B, and
transfers the low-order 4 bits (TPS3–TPS0)
of prescaler to register A.
TABSI (Transfer data to Accumulator and register B from register SI)
Instruction
code
Operation:
D9
1
D0
0
0
1
1
1
1
0
0
0
2
2
7
8 16
(B) ← (SI7–SI4)
(A) ← (SI3–SI0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Transfers the high-order 4 bits (SI7–SI4) of
serial I/O register SI to register B, and
transfers the low-order 4 bits (SI 3–SI0) of
serial I/O register SI to register A.
TAD (Transfer data to Accumulator from register D)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
(A2–A0) ← (DR2–DR0)
(A3) ← 0
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
0
0
1
2
0
5
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
1-113
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TADAB (Transfer data to register AD from Accumulator from register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
0
0
1
2
2
3
9 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
In the comparator mode (Q1 3 = 1), transfers the contents of register B to the
high-order 4 bits (AD7–AD4) of comparator
register, and the contents of register A to
the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
TAI1 (Transfer data to Accumulator from register I1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
1
1
2
2
5
3
16
(A) ← (I1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I1 to register A.
TAI2 (Transfer data to Accumulator from register I2)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
1
0
0
2
2
5
4
16
(A) ← (I2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I2 to register A.
TAI3 (Transfer data to Accumulator from register I3)
Instruction
code
Operation:
D9
1
D0
0
0
(A0) ← (I30)
(A3–A1) ← 0
1
0
1
0
1
0
1
2
2
5
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register I3 to the lowermost bit (A0) of register A.
Note: When the TAI3 instruction is executed, “0” is stored
to the high-order 3 bits (A3–A1) of register A.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-114
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAJ1 (Transfer data to Accumulator from register J1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
0
1
0
2
2
4
2
16
(A) ← (J1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Transfers the contents of serial I/O control
register J1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction
code
Operation:
D0
D9
1
0
0
1
0
1
0
1
1
0
2
2
5
6
16
(A) ← (K0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K0 to register A.
TAK1 (Transfer data to Accumulator from register K1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
1
0
0
1
2
2
5
9
16
(A) ← (K1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K1 to register A.
TAK2 (Transfer data to Accumulator from register K2)
Instruction
code
Operation:
D9
1
D0
0
0
(A) ← (K2)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
1
1
0
1
0
2
2
5
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of key-on wakeup
control register K2 to register A.
1-115
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAL1 (Transfer data to Accumulator from register L1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
1
0
2
2
4
A
16
(A) ← (L1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD control operation
Description: Transfers the LCD control register L1 to
register A.
TALA (Transfer data to Accumulator from register LA)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
0
1
2
2
4
9
16
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the low-order 2 bits (AD1, AD0) of
register AD to the high-order 2 bits (A3, A2)
of register A.
Note:
After this instruction is executed, “0” is
stored to the low-order 2 bits (A 1 , A 0 ) of
register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
0
j
j
j
j
2
2
C
j
16
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the result in register X.
TAMR (Transfer data to Accumulator from register MR)
Instruction
code
Operation:
D9
1
D0
0
0
(A) ← (MR)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
1
0
0
1
0
2
2
5
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Clock operation
Description: Transfers the contents of clock control register MR to register A.
1-116
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAPU0 (Transfer data to Accumulator from register PU0)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
1
1
1
2
2
5
7
16
(A) ← (PU0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU0 to register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction
code
Operation:
D0
D9
1
0
0
1
0
1
1
1
1
0
2
2
5
E 16
(A) ← (PU1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of pull-up control
register PU1 to register A.
TAQ1 (Transfer data to Accumulator from register Q1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
1
0
0
2
2
4
4
16
(A) ← (Q1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of A/D control register Q1 to register A.
TAQ2 (Transfer data to Accumulator from register Q2)
Instruction
code
Operation:
D9
1
D0
0
0
(A) ← (Q2)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
0
0
1
0
1
2
2
4
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of A/D control register Q2 to register A.
1-117
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAQ3 (Transfer data to Accumulator from register Q3)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
0
1
1
0
2
2
4
6 16
(A) ← (Q3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of A/D control register Q3 to register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
0
0
2
0
5
0
16
(A2–A0) ← (SP2–SP0)
(A3) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of stack pointer (SP)
to the low-order 3 bits (A2–A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
1
0
0
2
0
5
4
16
(A) ← (V1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V1 to register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction
code
Operation:
D9
0
D0
0
0
(A) ← (V2)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
1
0
1
0
1
2
0
5
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of interrupt control
register V2 to register A.
1-118
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW1 (Transfer data to Accumulator from register W1)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
0
1
1
2
2
4
B
16
(A) ← (W1)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction
code
Operation:
D0
D9
1
0
0
1
0
0
1
1
0
0
2
2
4
C
16
(A) ← (W2)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W2 to register A.
TAW3 (Transfer data to Accumulator from register W3)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
0
1
2
2
4
D
16
(A) ← (W3)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W3 to register A.
TAW4 (Transfer data to Accumulator from register W4)
Instruction
code
Operation:
D9
1
D0
0
0
(A) ← (W4)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
0
0
1
1
1
0
2
2
4
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W4 to register A.
1-119
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW5 (Transfer data to Accumulator from register W5)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
0
1
1
1
1
2
2
4
F
16
(A) ← (W5)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W5 to register A.
TAW6 (Transfer data to Accumulator from register W6)
Instruction
code
Operation:
D9
1
D0
0
0
1
0
1
0
0
0
0
2
2
5
0
16
(A) ← (W6)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of timer control register W6 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
1
0
2
0
5
2
16
(A) ← (X)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register X to register A.
TAY (Transfer data to Accumulator from register Y)
Instruction
code
Operation:
D9
0
D0
0
0
(A) ← (Y)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
0
1
1
1
1
1
2
0
1
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Y to register A.
1-120
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAZ (Transfer data to Accumulator from register Z)
Instruction
code
Operation:
D9
0
D0
0
0
1
0
1
0
0
1
1 2
0
5
3 16
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Z to the
low-order 2 bits (A1, A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 2 bits (A3, A2 ) of
register A.
TBA (Transfer data to register B from Accumulator)
Instruction
code
Operation:
D0
D9
0
0
0
0
0
0
1
1
1
0
2
0
0
E
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (A)
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
0
1
0
0
1
2
0
2
9
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(DR2–DR0) ← (A2–A0)
Grouping:
Register to register transfer
Description: Transfers the contents of the low-order 3
bits (A2–A0) of register A to register D.
TEAB (Transfer data to register E from Accumulator and register B)
Instruction
code
Operation:
D9
0
D0
0
0
0
(E7–E4) ← (B)
(E3–E0) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
1
1
0
1
0
2
0
1
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register B to the
high-order 4 bits (E7–E4) of register E, and
the contents of register A to the low-order 4
bits (E3–E0) of register E.
1-121
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TFR0A (Transfer data to register FR0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
0
0 2
2
2
8 16
(FR0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR0.
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
0
1
2
2
2
9
16
(FR1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR1.
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
0
1
0
2
2
2
A
16
(FR2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR2.
TFR3A (Transfer data to register FR3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
(FR3) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
1
0
1
0
1
1
2
2
2
B
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to the
port output structure control register FR3.
1-122
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TI1A (Transfer data to register I1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
1
1
2
2
1
7
16
(I1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register I1.
TI2A (Transfer data to register I2 from Accumulator)
Instruction
code
Operation:
D0
D9
1
0
0
0
0
1
1
0
0
0
2
2
1
8 16
(I2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register I2.
TI3A (Transfer data to register I3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
1
0
1
0
2
2
1
A 16
(I30) ← (A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of the lowermost bit
(A0) of register A to interrupt control register
I1.
TJ1A (Transfer data to register J1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
(J1) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
0
0
0
0
1
0
2
2
0
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Serial I/O operation
Description: Transfers the contents of register A to serial
I/O control register J1.
1-123
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK0A (Transfer data to register K0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
1
0
1
1
2
2
1
B
16
(K0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
0
0
2
2
1
4
16
(K1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K1.
TK2A (Transfer data to register K2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
1
0
1
2
2
1
5
16
(K2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to keyon wakeup control register K2.
TL1A (Transfer data to register L1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
(L1) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
0
0
1
0
1
0
2
2
0
A
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD operation
Description: Transfers the contents of register A to LCD
control register L1.
1-124
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TL2A (Transfer data to register L2 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
0
1
1 2
2
0
B 16
(L2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
LCD operation
Description: Transfers the contents of register A to LCD
control register L2.
TLCA (Transfer data to timer LC and register RLC from Accumulator)
Instruction
code
Operation:
D0
D9
1
0
0
0
0
0
1
1
0
1
2
2
0
D
16
(LC) ← (A)
(RLC) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
LC and reload register RLC.
TMA j (Transfer data to Memory from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
1
j
j
j
j
2
2
B
j
16
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of register A
to M(DP), an exclusive OR operation is performed between register X and the value j
in the immediate field, and stores the result
in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
(MR) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
0
1
0
1
1
0
2
2
1
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to clock
control register MR.
1-125
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPAA (Transfer data to register PA from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
1
0
1
0
2
2
A
A
16
(PA0) ← (A0)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of lowermost bit (A0)
register A to timer control register PA.
TPSAB (Transfer data to Pre-Scaler from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
0
1
0
1
2
2
3
5
16
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of prescaler and prescaler
reload register RPS, and transfers the contents of register A to the low-order 4 bits of
prescaler and prescaler reload register
RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
0
1
1
0
1
2
2
2
D
16
(PU0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
(PU1) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
1
0
1
1
1
0
2
2
2
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of register A to pullup control register PU1.
1-126
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TQ1A (Transfer data to register Q1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
1
0
0
2
2
0
4
16
(Q1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q1.
TQ2A (Transfer data to register Q2 from Accumulator)
Instruction
code
Operation:
D0
D9
1
0
0
0
0
0
0
1
0
1
2
2
0
5 16
(Q2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q2.
TQ3A (Transfer data to register Q3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
0
1
1
0
2
2
0
6
16
(Q3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
A/D conversion operation
Description: Transfers the contents of register A to A/D
control register Q3.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
(R17–R14) ← (B)
(R13–R10) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1
1
1
1
1
1
2
2
3
F
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (R17–R14) of reload register R1, and the contents of register A to the
low-order 4 bits (R13–R10) of reload register R1.
1-127
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TR3AB (Transfer data to register R3 from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
0
1
1
2
2
3
B 16
(R37–R34) ← (B)
(R33–R30) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (R37–R34) of reload register R3, and the contents of register A to the
low-order 4 bits (R33–R30) of reload register R3.
TSIAB (Transfer data to register SI from Accumulator and register B)
Instruction
code
Operation:
D9
1
D0
0
0
0
1
1
1
0
0
0
2
2
3
8
16
(SI7–SI4) ← (B)
(SI3–SI0) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits (SI7–SI4) of serial I/O register SI, and transfers the contents of
register A to the low-order 4 bits (SI3–SI0) of
serial I/O register SI.
TV1A (Transfer data to register V1 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
1
1
1
1
1
1
2
0
3
F
16
(V1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
(V2) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
1
1
1
1
1
0 2
0
3
E 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Interrupt operation
Description: Transfers the contents of register A to interrupt control register V2.
1-128
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW1A (Transfer data to register W1 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
0
1
1
1
0 2
2
0
E 16
(W1) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W1.
TW2A (Transfer data to register W2 from Accumulator)
Instruction
code
Operation:
D0
D9
1
0
0
0
0
0
1
1
1
1 2
2
0
F 16
(W2) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W2.
TW3A (Transfer data to register W3 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
0
0
2
2
1
0
16
(W3) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W3.
TW4A (Transfer data to register W4 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
(W4) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
0
1
0
0
0
1
2
2
1
1 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W4.
1-129
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW5A (Transfer data to register W5 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
1
0
2
2
1
2
16
(W5) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W5.
TW6A (Transfer data to register W6 from Accumulator)
Instruction
code
Operation:
D9
1
D0
0
0
0
0
1
0
0
1
1
2
2
1
3 16
(W6) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to timer
control register W6.
TYA (Transfer data to register Y from Accumulator)
Instruction
code
Operation:
D9
0
D0
0
0
0
0
0
1
1
0
0
2
0
0
C
16
(Y) ← (A)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register Y.
WRST (Watchdog timer ReSeT)
Instruction
code
Operation:
D9
1
D0
0
1
0
1
0
0
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
0
0
0
2
2
A
0
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(WDF1) = 1
Grouping:
Other operation
Description: Skips the next instruction when watchdog
timer flag WDF1 is “1.” After skipping, clears
(0) to the WDF1 flag. When the WDF1 flag
is “0,” executes the next instruction. Also,
stops the watchdog timer function when executing the WRST instruction immediately
after the DWDT instruction.
1-130
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
XAM j (eXchange Accumulator and Memory data)
Instruction
code
Operation:
D9
1
D0
0
1
1
0
1
j
j
j
j
2
2
D
j
16
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction
code
Operation:
D0
D9
1
0
1
1
1
1
j
j
j
j
2
2
F
j
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction
code
D9
1
D0
0
1
1
Operation:
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
Instruction
code
D9
1
0
j
j
j
j
2
E
j
16
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped. when the contents of register Y is
not 0, the next instruction is executed.
Number of
words
D0
2
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2
Number of
words
Number of
cycles
Flag CY
Skip condition
16
1-131
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of
words
Number of
cycles
Instruction code
TAB
0
0
0
0
0
1
1
1
1
0
0 1 E
1
1
(A) ← (B)
TBA
0
0
0
0
0
0
1
1
1
0
0 0 E
1
1
(B) ← (A)
TAY
0
0
0
0
0
1
1
1
1
1
0 1 F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
0
1
1
0
0
0 0 C
1
1
(Y) ← (A)
TEAB
0
0
0
0
0
1
1
0
1
0
0 1 A
1
1
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0 2 A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0 2 9
1
1
(DR2–DR0) ← (A2–A0)
TAD
0
0
0
1
0
1
0
0
0
1
0 5 1
1
1
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0 5 3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0 5 2
1
1
(A) ← (X)
TASP
0
0
0
1
0
1
0
0
0
0
0 5 0
1
1
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3 x y
1
1
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LZ z
0
0
0
1
0
0
1
0
z1 z0
0 4 8
+z
1
1
(Z) ← z z = 0 to 3
INY
0
0
0
0
0
1
0
0
1
1
0 1 3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
0
1
0
1
1
1
0 1 7
1
1
(Y) ← (Y) – 1
TAM j
1
0
1
1
0
0
j
j
j
j
2 C j
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
1
0
1
1
1
1
j
j
j
j
2 F j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
1
0
1
1
1
0
j
j
j
j
2 E j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
1
0
1
0
1
1
j
j
j
j
2 B j
1
1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Parameter
Mnemonic
RAM to register transfer
RAM addresses
Register to register transfer
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Hexadecimal
notation
Function
1-132
HARDWARE
INSTRUCTIONS
Skip condition
Carry flag CY
4524 Group
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E.
–
–
Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits (E3–E0) of register E
to register A.
–
–
Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D.
–
–
Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A.
–
–
Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
–
–
Transfers the contents of register X to register A.
–
–
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Datailed description
1-133
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Arithmetic operation
Bit operation
Comparison
operation
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
notation
Number of
cycles
Mnemonic
Type of
instructions
Number of
words
Instruction code
Parameter
0 7 n
1
1
(A) ← n
n = 0 to 15
Hexadecimal
Function
LA n
0
0
0
1
1
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
0 8 p
+p
1
3
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
n = 0 to 15
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A) AND (M(DP))
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
SB j
0
0
0
1
0
1
1
1
j
j
0 5 C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
0
0
0
1
0
0
1
1
j
j
0 4 C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
SZB j
0
0
0
0
1
0
0
0
j
j
0 2 j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
SEAM
0
0
0
0
1
0
0
1
1
0
0 2 6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
0
1
0
0
1
0
1
0 2 5
2
2
(A) = n ?
n = 0 to 15
0
0
0
1
1
1
n
n
n
n
0 7 n
1
n
n
n
n
Note: p is 0 to 63 for M34524M8,
p is 0 to 95 for M34524MC and
p is 0 to 127 for M34524ED.
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REJ09B0107-0200Z
1-134
HARDWARE
INSTRUCTIONS
Skip condition
Carry flag CY
4524 Group
Datailed description
Continuous
description
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
–
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.
When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
after system is released from reset or returned from power down: 0 to 63.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
–
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
–
–
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
–
–
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one’s complement for register A’s contents in register A.
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
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REJ09B0107-0200Z
1-135
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (continued)
Number of
words
Number of
cycles
Instruction code
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
BL p, a
0
0
1
1
p4 p3 p2 p1 p0
0 E p
+p
2
2
(PCH) ← p (Note)
(PCL) ← a6–a0
1
p6 p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+p +a
0
0
0
1
0
0 1 0
2
2
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
1
p6 p5 p4 0
0
p3 p2 p1 p0
2 p p
+p
BM a
0
1
0
a6 a5 a4 a3 a2 a1 a0
1 a a
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
p4 p3 p2 p1 p0
0 C p
+p
2
2
1
p6 p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+p +a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
0
0
1
1
0
0 3 0
2
2
1
p6 p5 p4 0
0
p3 p2 p1 p0
2 p p
+p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0,A3–A0)
RTI
0
0
0
1
0
0
0
1
1
0
0 4 6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
0
1
0
0
0
1
0
0
0 4 4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4 5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Parameter
Mnemonic
Return operation
Subroutine operation
Branch operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BLA p
BMLA p
0
0
0
0
1
0
0
0
0
0
0
0
Hexadecimal
notation
Function
Note: p is 0 to 63 for M34524M8,
p is 0 to 95 for M34524MC and
p is 0 to 127 for M34524ED.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-136
HARDWARE
INSTRUCTIONS
Skip condition
Carry flag CY
4524 Group
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Datailed description
1-137
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
DI
0
0
0
0
0
0
0
1
0
0
0 0 4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
0
1
0
1
0 0 5
1
1
(INTE) ← 1
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3 8
1
1
V10 = 0: (EXF0) = 1 ?
After skipping, (EXF0) ← 0
V10 = 1: SNZ0 = NOP
SNZ1
0
0
0
0
1
1
1
0
0
1
0 3 9
1
1
V11 = 0: (EXF1) = 1 ?
After skipping, (EXF1) ← 0
V11 = 1: SNZ1 = NOP
SNZI0
0
0
0
0
1
1
1
0
1
0
0 3 A
1
1
I12 = 1 : (INT0) = “H” ?
Parameter
Mnemonic
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
Function
Timer operation
Interrupt operation
I12 = 0 : (INT0) = “L” ?
SNZI1
0
0
0
0
1
1
1
0
1
1
0 3 B
1
1
I22 = 1 : (INT1) = “H” ?
I22 = 0 : (INT1) = “L” ?
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
TAI2
1
0
0
1
0
1
0
1
0
0
2 5 4
1
1
(A) ← (I2)
TI2A
1
0
0
0
0
1
1
0
0
0
2 1 8
1
1
(I2) ← (A)
TAI3
1
0
0
1
0
1
0
1
0
1
2 5 5
1
1
(A0) ← (I30), (A3–A1) ← 0
TI3A
1
0
0
0
0
1
1
0
1
0
2 1 A
1
1
(I30) ← (A0)
TPAA
1
0
1
0
1
0
1
0
1
0
2 A A
1
1
(PA0) ← (A0)
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
TAW3
1
0
0
1
0
0
1
1
0
1
2 4 D
1
1
(A) ← (W3)
TW3A
1
0
0
0
0
1
0
0
0
0
2 1 0
1
1
(W3) ← (A)
TAW4
1
0
0
1
0
0
1
1
1
0
2 4 E
1
1
(A) ← (W4)
TW4A
1
0
0
0
0
1
0
0
0
1
2 1 1
1
1
(W4) ← (A)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-138
HARDWARE
INSTRUCTIONS
Skip condition
Carry flag CY
4524 Group
–
–
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
–
–
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
V10 = 0: (EXF0) = 1
–
When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,
clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1)
V11 = 0: (EXF1) = 1
–
When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is “1.” After skipping,
clears (0) to the EXF1 flag. When the EXF1 flag is “0,” executes the next instruction.
When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1)
(INT0) = “H”
However, I12 = 1
–
When I12 = 1 : Skips the next instruction when the level of INT0 pin is “H.” (I12: bit 2 of interrupt control register I1)
(INT0) = “L”
However, I12 = 0
–
When I12 = 0 : Skips the next instruction when the level of INT0 pin is “L.”
(INT1) = “H”
However, I22 = 1
–
When I22 = 1 : Skips the next instruction when the level of INT1 pin is “H.” (I22: bit 2 of interrupt control register I2)
(INT1) = “L”
However, I22 = 0
–
When I22 = 0 : Skips the next instruction when the level of INT1 pin is “L.”
–
–
Transfers the contents of interrupt control register V1 to register A.
–
–
Transfers the contents of register A to interrupt control register V1.
–
–
Transfers the contents of interrupt control register V2 to register A.
–
–
Transfers the contents of register A to interrupt control register V2.
–
–
Transfers the contents of interrupt control register I1 to register A.
–
–
Transfers the contents of register A to interrupt control register I1.
–
–
Transfers the contents of interrupt control register I2 to register A.
–
–
Transfers the contents of register A to interrupt control register I2.
–
–
Transfers the contents of interrupt control register I3 to the lowermost bit (A0) of register A.
–
–
Transfers the contents of the lowermost bit (A0) of register A to interrupt control register I3.
–
–
Transfers the contents of register A to timer control register PA.
–
–
Transfers the contents of timer control register W1 to register A.
–
–
Transfers the contents of register A to timer control register W1.
–
–
Transfers the contents of timer control register W2 to register A.
–
–
Transfers the contents of register A to timer control register W2.
–
–
Transfers the contents of timer control register W3 to register A.
–
–
Transfers the contents of register A to timer control register W3.
–
–
Transfers the contents of timer control register W4 to register A.
–
–
Transfers the contents of register A to timer control register W4.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Datailed description
1-139
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TAW5
1
0
0
1
0
0
1
1
1
1
2 4 F
1
1
(A) ← (W5)
TW5A
1
0
0
0
0
1
0
0
1
0
2 1 2
1
1
(W5) ← (A)
TAW6
1
0
0
1
0
1
0
0
0
0
2 5 0
1
1
(A) ← (W6)
TW6A
1
0
0
0
0
1
0
0
1
1
2 1 3
1
1
(W6) ← (A)
TABPS
1
0
0
1
1
1
0
1
0
1
2 7 5
1
1
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TPSAB
1
0
0
0
1
1
0
1
0
1
2 3 5
1
1
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
TAB1
1
0
0
1
1
1
0
0
0
0
2 7 0
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
TAB2
1
0
0
1
1
1
0
0
0
1
2 7 1
1
1
(B) ← (T27–T24)
(A) ← (T23–T20)
T2AB
1
0
0
0
1
1
0
0
0
1
2 3 1
1
1
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
TAB3
1
0
0
1
1
1
0
0
1
0
2 7 2
1
1
(B) ← (T37–T34)
(A) ← (T33–T30)
T3AB
1
0
0
0
1
1
0
0
1
0
2 3 2
1
1
(R37–R34) ← (B)
(T37–T34) ← (B)
(R33–R30) ← (A)
(T33–T30) ← (A)
TAB4
1
0
0
1
1
1
0
0
1
1
2 7 3
1
1
(B) ← (T47–T44)
(A) ← (T43–T40)
T4AB
1
0
0
0
1
1
0
0
1
1
2 3 3
1
1
(R4L7–R4L4) ← (B)
(T47–T44) ← (B)
(R4L3–R4L0) ← (A)
(T43–T40) ← (A)
T4HAB
1
0
0
0
1
1
0
1
1
1
2 3 7
1
1
(R4H7–R4H4) ← (B)
(R4H3–R4H0) ← (A)
TR1AB
1
0
0
0
1
1
1
1
1
1
2 3 F
1
1
(R17–R14) ← (B)
(R13–R10) ← (A)
TR3AB
1
0
0
0
1
1
1
0
1
1
2 3 B
1
1
(R37–R34) ← (B)
(R33–R30) ← (A)
T4R4L
1
0
1
0
0
1
0
1
1
1
2 9 7
1
1
(T47–T40) ← (R4L7–R4L0)
TLCA
1
0
0
0
0
0
1
1
0
1
2 0 D
1
1
(LC) ← (A)
(RLC) ← (A)
Parameter
Mnemonic
Timer operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Hexadecimal
notation
Function
1-140
HARDWARE
INSTRUCTIONS
Skip condition
Carry flag CY
4524 Group
Datailed description
–
–
Transfers the contents of timer control register W5 to register A.
–
–
Transfers the contents of register A to timer control register W5.
–
–
Transfers the contents of timer control register W6 to register A.
–
–
Transfers the contents of register A to timer control register W6.
–
–
Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to
register A.
–
–
Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS,
and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register
RPS.
–
–
Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and
transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
–
–
Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2, and
transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
–
–
Transfers the high-order 4 bits of timer 3 to register B, and transfers the low-order 4 bits of timer 3 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3, and
transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3.
–
–
Transfers the high-order 4 bits of timer 4 to register B, and transfers the low-order 4 bits of timer 4 to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L, and
transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 4 reload register R4H, and transfers the
contents of register A to the low-order 4 bits of timer 4 reload register R4H.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the
contents of register A to the low-order 4 bits of timer 1 reload register R1.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3, and transfers the
contents of register A to the low-order 4 bits of timer 3 reload register R3.
–
–
Transfers the contents of timer 4 reload register R4L to timer 4.
–
–
Transfers the contents of register A to timer LC and timer LC reload register RLC.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-141
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
SNZT1
1
0
1
0
0
0
0
0
0
0
2 8 0
1
1
V12 = 0: (T1F) = 1 ?
After skipping, (T1F) ← 0 V12 = 1: NOP
SNZT2
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
V13 = 0: (T2F) = 1 ?
After skipping, (T2F) ← 0 V13 = 1: NOP
SNZT3
1
0
1
0
0
0
0
0
1
0
2 8 2
1
1
V20 = 0: (T3F) = 1 ?
After skipping, (T3F) ← 0 V20 = 1: NOP
SNZT4
1
0
1
0
0
0
0
0
1
1
2 8 3
1
1
V23 = 0: (T4F) = 1 ?
After skipping, (T4F) ← 0 V23 = 1: NOP
SNZT5
1
0
1
0
0
0
0
1
0
0
2 8 4
1
1
V21 = 0: (T5F) = 1 ?
After skipping, (T5F) ← 0 V21 = 1: NOP
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A) ← (P2)
OP2A
1
0
0
0
1
0
0
0
1
0
2 2 2
1
1
(P2) ← (A)
IAP3
1
0
0
1
1
0
0
0
1
1
2 6 3
1
1
(A) ← (P3)
OP3A
1
0
0
0
1
0
0
0
1
1
2 2 3
1
1
(P3) ← (A)
IAP4
1
0
0
1
1
0
0
1
0
0
2 6 4
1
1
(A) ← (P4)
OP4A
1
0
0
0
1
0
0
1
0
0
2 2 4
1
1
(P4) ← (A)
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 9
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 9
SZD
0
0
0
0
1
0
0
1
0
0
0 2 4
1
1
(D(Y)) = 0 ?
(Y) = 0 to 7
0
0
0
0
1
0
1
0
1
1
0 2 B
1
1
RCP
1
0
1
0
0
0
1
1
0
0
2 8 C
1
1
(C) ← 0
SCP
1
0
1
0
0
0
1
1
0
1
2 8 D
1
1
(C) ← 1
TAPU0
1
0
0
1
0
1
0
1
1
1
2 5 7
1
1
(A) ← (PU0)
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
TAPU1
1
0
0
1
0
1
1
1
1
0
2 5 E
1
1
(A) ← (PU1)
TPU1A
1
0
0
0
1
0
1
1
1
0
2 2 E
1
1
(PU1) ← (A)
Parameter
Mnemonic
Input/Output operation
Timer operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Hexadecimal
notation
Function
1-142
HARDWARE
INSTRUCTIONS
Skip condition
Carry flag CY
4524 Group
V12 = 0: (T1F) = 1
–
Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is “0” and the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag.
V13 = 0: (T2F) =1
–
Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is “0” and the contents of T2F flag is “1.” After skipping, clears (0) to T2F flag.
V20 = 0: (T3F) = 1
–
Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is “0” and the contents of T3F flag is “1.” After skipping, clears (0) to T3F flag.
V23 = 0: (T4F) =1
–
Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and the contents of T4F flag is “1.” After skipping, clears (0) to T4F flag.
V21 = 0: (T5F) =1
–
Skips the next instruction when the contents of bit 1 (V21) of interrupt control register V2 is “0” and the contents of T5F flag is “1.” After skipping, clears (0) to T5F flag.
–
–
Transfers the input of port P0 to register A.
–
–
Outputs the contents of register A to port P0.
–
–
Transfers the input of port P1 to register A.
–
–
Outputs the contents of register A to port P1.
–
–
Transfers the input of port P2 to register A.
–
–
Outputs the contents of register A to port P2.
–
–
Transfers the input of port P3 to register A.
–
–
Outputs the contents of register A to port P3.
–
–
Transfers the input of port P4 to register A.
–
–
Outputs the contents of register A to port P4.
–
–
Sets (1) to all port D.
–
–
Clears (0) to a bit of port D specified by register Y.
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
However, (Y)=0 to 7
–
Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction
when a bit of port D specified by register Y is “1.”
–
–
Clears (0) to port C.
–
–
Sets (1) to port C.
–
–
Transfers the contents of pull-up control register PU0 to register A.
–
–
Transfers the contents of register A to pull-up control register PU0.
–
–
Transfers the contents of pull-up control register PU1 to register A.
–
–
Transfers the contents of register A to pull-up control register PU1.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Datailed description
1-143
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TAK0
1
0
0
1
0
1
0
1
1
0
2 5 6
1
1
(A) ← (K0)
TK0A
1
0
0
0
0
1
1
0
1
1
2 1 B
1
1
(K0) ← (A)
TAK1
1
0
0
1
0
1
1
0
0
1
2 5 9
1
1
(A) ← (K1)
TK1A
1
0
0
0
0
1
0
1
0
0
2 1 4
1
1
(K1) ← (A)
TAK2
1
0
0
1
0
1
1
0
1
0
2 5 A
1
1
(A) ← (K2)
TK2A
1
0
0
0
0
1
0
1
0
1
2 1 5
1
1
(K2) ← (A)
TFR0A
1
0
0
0
1
0
1
0
0
0
2 2 8
1
1
(FR0) ← (A)
TFR1A
1
0
0
0
1
0
1
0
0
1
2 2 9
1
1
(FR1) ← (A)
TFR2A
1
0
0
0
1
0
1
0
1
0
2 2 A
1
1
(FR2) ← (A)
TFR3A
1
0
0
0
1
0
1
0
1
1
2 2 B
1
1
(FR3) ← (A)
TAL1
1
0
0
1
0
0
1
0
1
0
2 4 A
1
1
(A) ← (L1)
TL1A
1
0
0
0
0
0
1
0
1
0
2 0 A
1
1
(L1) ← (A)
TL2A
1
0
0
0
0
0
1
0
1
1
2 0 B
1
1
(L2) ← (A)
TABSI
1
0
0
1
1
1
1
0
0
0
2 7 8
1
1
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
TSIAB
1
0
0
0
1
1
1
0
0
0
2 3 8
1
1
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
SST
1
0
1
0
0
1
1
1
1
0
2 9 E
1
1
(SIOF) ← 0
Serial I/O starting
SNZSI
1
0
1
0
0
0
1
0
0
0
2 8 8
1
1
V23=0: (SIOF)=1?
After skipping, (SIOF) ← 0 V23 = 1: NOP
TAJ1
1
0
0
1
0
0
0
0
1
0
2 4 2
1
1
(A) ← (J1)
TJ1A
1
0
0
0
0
0
0
0
1
0
2 0 2
1
1
(J1) ← (A)
CMCK
1
0
1
0
0
1
1
0
1
0
2 9 A
1
1
Ceramic resonator selected
CRCK
1
0
1
0
0
1
1
0
1
1
2 9 B
1
1
RC oscillator selected
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR)
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR) ← (A)
Parameter
Mnemonic
Clock operation
Serial I/O operation
LCD operation
Input/Output operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Hexadecimal
notation
Function
1-144
HARDWARE
INSTRUCTIONS
Skip condition
Carry flag CY
4524 Group
–
–
Transfers the contents of key-on wakeup control register K0 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K0 .
–
–
Transfers the contents of key-on wakeup control register K1 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K1.
–
–
Transfers the contents of key-on wakeup control register K2 to register A.
–
–
Transfers the contents of register A to key-on wakeup control register K2.
–
–
Transferts the contents of register A to port output format control register FR0.
–
–
Transferts the contents of register A to port output format control register FR1.
–
–
Transferts the contents of register A to port output format control register FR2.
–
–
Transferts the contents of register A to port output format control register FR3.
–
–
Transfers the contents of LCD control register L1 to register A.
–
–
Transfers the contents of register A to LCD control register L1.
–
–
Transfers the contents of register A to LCD control register L2.
–
–
Transfers the high-order 4 bits of serial I/O register SI to register B, and transfers the low-order 4 bits of serial I/O register SI to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of serial I/O register SI, and transfers the contents of register A to the low-order 4 bits of serial I/O register SI.
–
–
Clears (0) to SIOF flag and starts serial I/O.
V23 = 0: (SIOF) = 1
–
Skips the next instruction when the contents of bit 3 (V23) of interrupt control register V2 is “0” and contents
of SIOF flag is “1.” After skipping, clears (0) to SIOF flag.
–
–
Transfers the contents of serial I/O control register J1 to register A.
–
–
Transfers the contents of register A to serial I/O control register J1.
–
–
Selects the ceramic resonator for main clock, stops the on-chip oscillator (internal oscillator).
–
–
Selects the RC oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator).
–
–
Transfers the contents of clock control regiser MR to register A.
–
–
Transfers the contents of register A to clock control register MR.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Datailed description
1-145
HARDWARE
INSTRUCTIONS
4524 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of
words
Number of
cycles
Instruction code
TABAD
1
0
0
1
1
1
1
0
0
1
2 7 9
1
1
Q13 = 0:
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1:
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TALA
1
0
0
1
0
0
1
0
0
1
2 4 9
1
1
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
TADAB
1
0
0
0
1
1
1
0
0
1
2 3 9
1
1
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
ADST
1
0
1
0
0
1
1
1
1
1
2 9 F
1
1
(ADF) ← 0
A/D conversion starting
SNZAD
1
0
1
0
0
0
0
1
1
1
2 8 7
1
1
V22 = 0: (ADF) = 1 ?
After skipping, (ADF) ← 0 V22 = 1: NOP
TAQ1
1
0
0
1
0
0
0
1
0
0
2 4 4
1
1
(A) ← (Q1)
TQ1A
1
0
0
0
0
0
0
1
0
0
2 0 4
1
1
(Q1) ← (A)
TAQ2
1
0
0
1
0
0
0
1
0
1
2 4 5
1
1
(A) ← (Q2)
TQ2A
1
0
0
0
0
0
0
1
0
1
2 0 5
1
1
(Q2) ← (A)
TAQ3
1
0
0
1
0
0
0
1
1
0
2 4 6
1
1
(A) ← (Q3)
TQ3A
1
0
0
0
0
0
0
1
1
0
2 0 6
1
1
(Q3) ← (A)
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
0
0
0
1
0
0 0 2
1
1
Transition to clock operating mode
POF2
0
0
0
0
0
0
1
0
0
0
0 0 8
1
1
Transition to RAM back-up mode
EPOF
0
0
0
1
0
1
1
0
1
1
0 5 B
1
1
POF, POF2 instructions valid
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF1) = 1 ?
After skipping, (WDF1) ← 0
DWDT
1
0
1
0
0
1
1
1
0
0
2 9 C
1
1
Stop of watchdog timer function enabled
RBK*
0
0
0
1
0
0
0
0
0
0
0 4 0
1
1
When TABP p instruction is executed, P6 ← 0
SBK*
0
0
0
1
0
0
0
0
0
1
0 4 1
1
1
When TABP p instruction is executed, P6 ← 1
SVDE
1
0
1
0
0
1
0
0
1
1
2 9 3
1
1
At power down mode, voltage drop detection
circuit valid
Parameter
Mnemonic
Other operation
A/D conversion operation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
Function
Note: * (SBK, RBK) cannot be used in the M34524M8.
The pages which can be referred by the TABP instruction after the SBK instruction is executed are
64 to 95 in the M34524MC.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-146
HARDWARE
INSTRUCTIONS
Skip condition
Carry flag CY
4524 Group
–
–
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B,
and the low-order 4 bits (AD3–AD0) of register AD to register A.
(Q13: bit 3 of A/D control register Q1)
–
–
Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
–
–
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
–
–
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
V22 = 0: (ADF) = 1
–
When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. (V22: bit 2 of interrupt control register V2)
–
–
Transfers the contents of A/D control register Q1 to register A.
–
–
Transfers the contents of register A to A/D control register Q1.
–
–
Transfers the contents of A/D control register Q2 to register A.
–
–
Transfers the contents of register A to A/D control register Q2.
–
–
Transfers the contents of A/D control register Q3 to register A.
–
–
Transfers the contents of register A to A/D control register Q3.
–
–
No operation; Adds 1 to program counter value, and others remain unchanged.
–
–
Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction.
–
–
Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction.
–
–
Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
(P) = 1
–
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
(WDF1) = 1
–
Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT
instruction.
–
–
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
–
–
Sets referring data area to pages 0 to 63 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
–
–
Sets referring data area to pages 64 to 127 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
–
–
Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode)
when VDCE pin is “H”.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Datailed description
1-147
HARDWARE
INSTRUCTIONS
4524 Group
INSTRUCTION CODE TABLE
D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011001100 001101 001110 001111
010000 011000
010111 011111
Hex.
D3–D0 notation
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10–17 18–1F
0000
0
NOP
BLA
SZB
BMLA RBK** TASP
0
A
0
LA
0
TABP TABP TABP TABP
BML
32* 48*
0
16
BML
BL
BL
BM
B
0001
1
–
CLD
SZB
1
–
A
1
LA
1
TABP TABP TABP TABP
BML
33* 49*
1
17
BML
BL
BL
BM
B
0010
2
POF
–
SZB
2
–
–
TAX
A
2
LA
2
TABP TABP TABP TABP
BML
34* 50*
2
18
BML
BL
BL
BM
B
0011
3
SNZP INY
SZB
3
–
–
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML
35* 51*
3
19
BML
BL
BL
BM
B
0100
4
DI
RD
SZD
–
RT
TAV1
A
4
LA
4
TABP TABP TABP TABP
BML
36* 52*
4
20
BML
BL
BL
BM
B
0101
5
EI
SD
SEAn
–
RTS TAV2
A
5
LA
5
TABP TABP TABP TABP
BML
37* 53*
5
21
BML
BL
BL
BM
B
0110
6
RC
–
SEAM
–
RTI
–
A
6
LA
6
TABP TABP TABP TABP
BML
38* 54*
6
22
BML
BL
BL
BM
B
0111
7
SC
DEY
–
–
–
–
A
7
LA
7
TABP TABP TABP TABP
BML
39* 55*
7
23
BML
BL
BL
BM
B
1000
8
POF2 AND
–
SNZ0
LZ
0
–
A
8
LA
8
TABP TABP TABP TABP
BML
40* 56*
8
24
BML
BL
BL
BM
B
1001
9
–
TDA SNZ1
LZ
1
–
A
9
LA
9
TABP TABP TABP TABP
BML
41* 57*
9
25
BML
BL
BL
BM
B
1010
A
AM
TEAB TABE SNZI0
LZ
2
–
A
10
LA
10
TABP TABP TABP TABP
BML
42* 58*
10
26
BML
BL
BL
BM
B
1011
B
AMC
–
–
SNZI1
LZ
3
EPOF
A
11
LA
11
TABP TABP TABP TABP
BML
43* 59*
11
27
BML
BL
BL
BM
B
1100
C
TYA
CMA
–
–
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
BML
44* 60*
12
28
BML
BL
BL
BM
B
1101
D
–
RAR
–
–
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
BML
45* 61*
13
29
BML
BL
BL
BM
B
1110
E
TBA
TAB
–
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
BML
46* 62*
14
30
BML
BL
BL
BM
B
1111
F
–
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
BML
47* 63*
15
31
BML
BL
BL
BM
B
OR
SBK** TAD
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
1p paaa aaaa
1p paaa aaaa
1p pp00 pppp
1p pp00 pppp
00 0111 nnnn
00 0010 1011
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
• ** (SBK and RBK instructions) cannot be used in the M34524M8.
• * cannot be used after the SBK instruction is executed in the M34524MC.
• A page referred by the TABP instruction can be switched by the SBK and RBK instructions in the
M34524MC/ED.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to
95 in the M34524MC.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to
127 in the M34524ED.
(Ex. TABP 0 → TABP 64)
• The pages which can be referred by the TABP instruction after the RBK instruction is executed are 0 to 63.
• When the SBK instruction is not used, the pages which can be referred by the TABP instruction are 0 to 63.
1-148
HARDWARE
INSTRUCTIONS
4524 Group
INSTRUCTION CODE TABLE (continued)
D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111
110000
111111
Hex.
D3–D0 notation
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
–
WRST
TMA
0
TAM
0
XAM XAMI XAMD LXY
0
0
0
IAP1 TAB2 SNZT2
–
–
TMA
1
TAM
1
XAM XAMI XAMD LXY
1
1
1
TJ1A TW5A OP2A T3AB TAJ1 TAMR IAP2 TAB3 SNZT3
–
–
TMA
2
TAM
2
XAM XAMI XAMD LXY
2
2
2
2E
2F
30–3F
IAP3 TAB4 SNZT4 SVDE
–
TMA
3
TAM
3
XAM XAMI XAMD LXY
3
3
3
IAP4
–
SNZT5
–
–
TMA
4
TAM
4
XAM XAMI XAMD LXY
4
4
4
–
TABPS
–
–
–
TMA
5
TAM
5
XAM XAMI XAMD LXY
5
5
5
–
–
–
–
–
TMA
6
TAM
6
XAM XAMI XAMD LXY
6
6
6
–
–
TMA
7
TAM
7
XAM XAMI XAMD LXY
7
7
7
0000
0
–
TW3A OP0A T1AB
–
0001
1
–
TW4A OP1A T2AB
–
0010
2
0011
3
0100
4
TQ1A TK1A OP4A
0101
5
TQ2A TK2A
–
0110
6
TQ3A TMRA
–
–
0111
7
–
TI1A
–
T4HAB
–
TAPU0
–
1000
8
–
TI2A TFR0A TSIAB
–
–
–
TABSI SNZSI
–
–
TMA
8
TAM
8
XAM XAMI XAMD LXY
8
8
8
1001
9
–
–
TABAD
–
–
–
TMA
9
TAM
9
XAM XAMI XAMD LXY
9
9
9
1010
A
TL1A TI3A TFR2A
–
–
–
CMCK TPAA
TMA
10
TAM
10
XAM XAMI XAMD LXY
10
10
10
1011
B
TL2A TK0A TFR3ATR3AB TAW1
–
–
–
–
CRCK
–
TMA
11
TAM
11
XAM XAMI XAMD LXY
11
11
11
1100
C
–
–
–
–
TAW2
–
–
–
RCP DWDT
–
TMA
12
TAM
12
XAM XAMI XAMD LXY
12
12
12
1101
D
TLCA
–
TPU0A
–
TAW3
–
–
–
SCP
–
–
TMA
13
TAM
13
XAM XAMI XAMD LXY
13
13
13
1110
E
TW1A
–
TPU1A
–
TAW4 TAPU1
–
–
–
SST
–
TMA
14
TAM
14
XAM XAMI XAMD LXY
14
14
14
1111
F
TW2A
–
–
–
–
–
ADST
–
TMA
15
TAM
15
XAM XAMI XAMD
LXY
15
15
15
–
TW6A OP3A T4AB
–
–
–
TAW6 IAP0 TAB1 SNZT1
2D
–
TAI1
TAQ1 TAI2
TPSAB TAQ2 TAI3
TAQ3 TAK0
TFR1ATADAB TALA TAK1
–
TAL1 TAK2
TR1AB TAW5
–
SNZAD T4R4L
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BLA
BMLA
SEA
SZD
The second word
1p paaa aaaa
1p paaa aaaa
1p pp00 pppp
1p pp00 pppp
00 0111 nnnn
00 0010 1011
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-149
HARDWARE
BUILT-IN PROM VERSION
4524 Group
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4524 Group has the
One Time PROM versions whose PROMs can only be written to
and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM versions, but it has PROM mode that enables writing to
built-in PROM.
Table 25 shows the product of built-in PROM version. Figure 75
shows the pin configurations of built-in PROM versions.
The One Time PROM version has pin-compatibility with the mask
ROM version.
Table 25 Product of built-in PROM version
PROM size
Part number
(✕ 10 bits)
M34524EDFP
16384 words
RAM size
(✕ 4 bits)
512 words
Package
ROM type
64P6N-A
One Time PROM [shipped in blank]
D3
D2
P13
D0
D1
P12
P11
P03
P10
P02
P01
P00
COM3
COM2
COM1
COM0
PIN CONFIGURATION (TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VLC3/SEG0
VLC2/ SEG1
VLC1/SEG2
SEG3
SEG4
SEG5
SEG6
49
32
D4/SIN
50
31
51
30
52
29
D5/SOUT
D6/SCK
CNVSS
VDCE
SEG7
SEG8
SEG9
56
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
53
28
54
27
55
26
M34524EDFP
25
58
23
59
22
60
21
61
20
62
19
63
18
64
17
7
8
VDD
VSS
XOUT
XIN
RESET
D7/CNTR0
C/CNTR1
D8/INT0
D9/INT1
9 10 11 12 13 14 15 16
P20/ AIN0
6
P21/ AIN1
5
P22/ AIN2
4
P30/ AIN4
P23/ AIN3
3
P33/ AIN7
P32/ AIN6
P31/ AIN5
2
P41
P40
1
SEG17
SEG18
SEG19
P43
P42
24
SEG16
57
XCIN
XCOUT
Outline 64P6N-A
Fig. 75 Pin configuration of built-in PROM version
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-150
HARDWARE
BUILT-IN PROM VERSION
4524 Group
(1) PROM mode
The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read
from the built-in PROM.
In the PROM mode, the programming adapter can be used with a
general-purpose PROM programmer to write to or read from the
built-in PROM as if it were M5M27C256K.
Programming adapter is listed in Table 26. Contact addresses at
the end of this data sheet for the appropriate PROM programmer.
• Writing and reading of built-in PROM
Programming voltage is 12.5 V. Write the program in the PROM of
the built-in PROM version as shown in Figure 76.
(2) Notes on handling
➀A high-voltage is used for writing. Take care that overvoltage is
not applied. Take care especially at turning on the power.
➁For the One Time PROM version shipped in blank, Renesas
Technology corp. does not perform PROM writing test and
screening in the assembly process and following processes. In
order to improve reliability after writing, performing writing and
test according to the flow shown in Figure 77 before using is recommended (Products shipped in blank: PROM contents is not
written in factory when shipped).
Table 26 Programming adapter
Part number
Name of Programming Adapter
PCA7448
M34524EDFP
Address
000016
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
3FFF16
400016
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
7FFF16
Fig. 76 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 77 Flow of writing and test of the product shipped in blank
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
1-151
CHAPTER 2
APPLICATION
2.1 I/O pins
2.2 Interrupts
2.3 Timers
2.4 A/D converter
2.5 Serial I/O
2.6 LCD function
2.7 Reset
2.8 Voltage drop detection circuit
2.9 Power down
2.10 Oscillation circuit
APPLICATION
4524 Group
2.1 I/O pins
2.1 I/O pins
The 4524 Group has twenty-eight I/O pins and three output pins.
Port P2 is also used as analog input pins A IN0–A IN3 .
Port P3 is also used as analog input pins A IN4–A IN7 .
Ports D 4–D 6 are also used as Serial I/O pins S IN , S OUT , S CK.
Port D7 is also used as CNTR0 I/O pin.
Port D8 is also used as INT0 input pin.
Port D9 is also used as INT1 input pin.
Port C is also used as CNTR1 I/O pin.
This section describes each port I/O function, related registers, application example using each port function
and notes.
2.1.1 I/O ports
(1) Port P0
Port P0 is a 4-bit I/O port.
Port P0 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor
which turns ON/OFF with register PU0.
● Input
In the following conditions, the pin state of port P0 is transferred as input data to register A when
the IAP0 instruction is executed.
• Set bit FR0 0 or bit FR0 1 of register FR0 to “0” according to the port to be used.
• Set the output latch of specified port P0i (i=0, 1, 2 or 3) to “1” with the OP0A instruction.
If FR0 0 or FR0 1 is “0” and the output latch is “0”, “0” is output to specified port P0.
If FR0 0 or FR0 1 is “1”, the output latch value is output to specified port P0.
● Output
The contents of register A is set to the output latch with the OP0A instruction, and is output to port
P0.
N-channel open-drain or CMOS can be selected as the output structure of port P0 in 2 bits unit
by setting FR0 0 or FR0 1.
(2) Port P1
Port P1 is a 4-bit I/O port.
Port P1 has the key-on wakeup function which turns ON/OFF with register K1 and pull-up transistor
which turns ON/OFF with register PU1.
● Input
In the following conditions, the pin state of port P1 is transferred as input data to register A when
the IAP1 instruction is executed.
• Set bit FR0 2 or bit FR0 3 of register FR0 to “0” according to the port to be used.
• Set the output latch of specified port P1i (i=0, 1, 2 or 3) to “1” with the OP1A instruction.
If FR0 2 or FR0 3 is “0” and the output latch is “0”, “0” is output to specified port P1.
If FR0 2 or FR0 3 is “1”, the output latch value is output to specified port P1.
● Output
The contents of register A is set to the output latch with the OP1A instruction, and is output to port
P1.
N-channel open-drain or CMOS can be selected as the output structure of port P1 in 2 bits unit
by setting FR0 2 or FR0 3.
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2.1 I/O pins
(3) Port P2
Port P2 is a 4-bit I/O port.
P2 0–P2 3 are also used as analog input pins A IN0–AIN3 .
● Input
In the following condition, the pin state of port P2 is transferred as input data to register A when
the IAP2 instruction is executed.
• Set the output latch of specified port P2i (i=0, 1, 2 or 3) to “1” with the OP2A instruction.
If the output latch is “0”, “0” is output to specified port P2.
● Output
The contents of register A is set to the output latch with the OP2A instruction, and is output to port
P2.
The output structure is an N-channel open-drain.
Note: Ports P20–P23 are used as input/output port P2, set the corresponding bit of register Q2 to “0”.
(4) Port P3
Port P3 is a 4-bit I/O port.
P3 0–P3 3 are also used as analog input pins A IN4–AIN7 .
● Input
In the following condition, the pin state of port P3 is transferred as input data to register A when
the IAP3 instruction is executed.
• Set the output latch of specified port P3i (i=0, 1, 2 or 3) to “1” with the OP3A instruction.
If the output latch is “0”, “0” is output to specified port P3.
● Output
The contents of register A is set to the output latch with the OP3A instruction, and is output to port
P3.
The output structure is an N-channel open-drain.
Note: Ports P30–P33 are used as input/output port P3, set the corresponding bit of register Q3 to “0”.
(5) Port P4
Port P4 is a 4-bit I/O port.
● Input
In the following conditions, the pin state of port P4 is transferred as input data to register A when
the IAP4 instruction is executed.
• Set bit i (i=0,1,2 or 3) of register FR3 to “0” according to the port to be used.
• Set the output latch of specified port P4i (i=0, 1, 2 or 3) to “1” with the OP4A instruction.
If FR3 i is “0” and the output latch is “0”, “0” is output to specified port P4.
If FR3 i is “1”, the output latch value is output to specified port P4.
● Output
The contents of register A is set to the output latch with the OP4A instruction, and is output to port
P4.
N-channel open-drain or CMOS can be selected as the output structure of port P4 in 1 bit unit by
setting register FR3.
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2.1 I/O pins
(6) Port D
Ports D 0–D 7 are eight independent I/O ports, and ports D 8 and D9 are two independent output ports.
Ports D 4 –D 6 are also used as Serial I/O pins S IN, S OUT, S CK. Port D 7 is also used as CNTR0 I/O
pin. Port D8 is also used as INT0 input pin. Port D9 is also used as INT1 input pin. Also, as for INT0
and INT1, its key-on wakeup function is switched to ON/OFF by the register K2 0 and K2 2.
■ Input/output of port D
Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D0–D7 and output
of D 8 and D 9 , select one of port D with the register Y of the data pointer first.
● Input
The pin state of port D can be obtained with the SZD instruction.
In the following conditions, if the pin state of port Dj (j=0, 1, 2, 3, 4, 5, 6 or 7) is “0” when the
SZD instruction is executed, the next instruction is skipped. If it is “1” when the SZD instruction
is executed, the next instruction is executed.
• Set bit i (i=0,1,2 or 3) of register FR1 or FR2 to “0” according to the port to be used.
• Set the output latch of specified port Dj to “1” with the SD instruction.
If FR1 i or FR2 i is “0” and the output latch is “0”, “0” is output to specified port D.
If FR1 i or FR2 i is “1”, the output latch value is output to specified port D.
● Output
Set the output level to the output latch with the SD, CLD and RD instructions.
The state of pin enters the high-impedance state when the SD instruction is executed.
All port D enter the high-impedance state or “H” level state when the CLD instruction is executed.
The state of pin becomes “L” level when the RD instruction is executed.
N-channel open-drain or CMOS can be selected as the output structure of ports D0–D7 in 1 bit unit
by setting registers FR1, FR2.
The output structure of ports D 8 and D 9 is N-channel open-drain.
Notes 1: When the SD and RD instructions are used, do not set “1010 2” or more to register Y.
2: Port D4 is also used as serial I/O pin S IN. Accordingly, when using port D4, set bit 1 (J11)
and bit 0 (J1 0 ) of register J1 to “002 ” or “01 2 .”
3: Port D 5 is also used as serial I/O pin S OUT. Accordingly, when using port D 5, set bit J1 1
and bit J1 0 to “00 2” or “10 2.”
4: Port D6 is also used as serial I/O pin SCK. Accordingly, when using port D6, set bit J11 and
bit J1 0 to “00 2 .” Also, set bit J13 and bit J1 2 to “00 2 ”, “01 2” or “10 2.”
5: Port D 7 is also used as CNTR0 pin. Accordingly, when using port D 7 , set bit 0 (W6 0) of
register W6 to “0.”
(7) Port C
Port C is a 1-bit output port. Port C is also used as CNTR0 pin.
■ Output
● Data output from port C
Set the output level to the output latch with the SCP and RCP instructions.
The state of pin becomes “H” level when the SCP instruction is executed.
The state of pin becomes “L” level when the RCP instruction is executed.
The output structure is CMOS.
Note: Port C is also used as CNTR1.
Accordingly, when using port C, set bit W31 and bit W30 to “002”, “012” or “102.” Also, set bit
W4 3 and bit W6 1 to “0.”
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4524 Group
2.1.2 Related registers
(1) Timer control register W3
Table 2.1.1 shows the timer control register W3.
Set the contents of this register through register A with the TW3A instruction.
The contents of register W3 is transferred to register A with the TAW3 instruction.
Table 2.1.1 Timer control register W3
Timer control register W3
W33
Timer 3 count auto-stop circuit
selection bit (Note 2)
at reset : 0000 2
at power down : state retained
0
Timer 3 count auto-stop circuit not selected
1
Timer 3 count auto-stop circuit selected
R/W
Stop (state retained)
0
Operating
1
Count source
W3 1W3 0
PWM
signal
(PWMOUT)
0 0
W31
Timer 3 count source selection
0 1 Prescaler output (ORCLK)
bits (Note 3)
1 0 Timer 2 underflow signal (T2UDF)
W30
1 1 CNTR1 input
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 3 count start synchronous circuit is selected (I2 0 =“1”).
3: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
4: When setting the port, W3 3–W3 2 are not used.
W32
Timer 3 control bit
(2) Timer control register W4
Table 2.1.2 shows the timer control register W4.
Set the contents of this register through register A with the TW4A instruction.
The contents of register W4 is transferred to register A with the TAW4 instruction.
Table 2.1.2 Timer control register W4
Timer control register W4
W43
CNTR1 output control bit
W42
PWM signal “H” interval
expansion function control bit
W41
Timer 4 control bit
W40
Timer 4 count source selection bit
at reset : 0000 2
at power down : state retained
R/W
0
1
CNTR1 output invalid
0
1
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
0
Stop (state retained)
1
Operating
0
1
X IN input
CNTR1 output valid
Prescaler output (ORCLK) divided by 2
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When setting the port, W4 2 –W4 0 are not used.
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(3) Timer control register W6
Table 2.1.3 shows the timer control register W6.
Set the contents of this register through register A with the TW6A instruction.
The contents of register W6 is transferred to register A with the TAW6 instruction.
Table 2.1.3 Timer control register W6
Timer control register W6
at reset : 0000 2
at power down : state retained
0
Stop (state retained)
1
Operating
Timer LC count source
selection bit
0
1
Bit 4 (T5 4) of timer 5
W6 1
CNTR1 output auto-control circuit
selection bit
0
1
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
W6 0
D7/CNTR0 pin function selection
bit (Note 2)
0
D7 (I/O)/CNTR0 input
1
CNTR0 input/output/D 7 (input)
W6 3
Timer LC control bit
W6 2
R/W
Prescaler output (ORCLK)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
3: When setting the port, W6 3 –W6 2 are not used.
(4) Serial I/O control register J1
Table 2.1.4 shows the serial I/O control register J1.
Set the contents of this register through register A with the TJ1A instruction.
The contents of register J1 is transferred to register A with the TAJ1 instruction.
Table 2.1.4 Serial I/O control register J1
Serial I/O control register J1
J1 3
J1 2
J1 1
J1 0
at reset : 0000 2
J1 3
0
Serial I/O synchronous clock
0
selection bits
1
1
J1 1
Serial I/O port function selection 0
0
bits
1
1
J1 2
0
1
0
1
J1 0
0
1
0
1
at power down : state retained
R/W
Synchronous clock
Instruction clock (INSTCK) divided by 8
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 2
External clock (S CK input)
Port function
D 6 , D5, D 4 selected/S CK, S OUT, S IN not selected
S CK, S OUT, D 4 selected/D 6, D 5, S IN not selected
S CK, D5 , S IN selected/D 6, S OUT, D 4 not selected
S CK, S OUT, S IN selected/D 6 , D5, D 4 not selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When setting the port, J1 3–J1 2 are not used.
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(5) A/D control register Q2
Table 2.1.5 shows the A/D control register Q2.
Set the contents of this register through register A with the TQ2A instruction.
The contents of register Q2 is transferred to register A with the TAQ2 instruction.
Table 2.1.5 A/D control register Q2
AD control register Q2
Q23
P23/AIN3 pin function selection bit
Q22
P22/AIN2 pin function selection bit
Q21
P21/AIN1 pin function selection bit
Q20
P20/AIN0 pin function selection bit
at reset : 0000 2
0
P2 3
1
AIN3
0
1
P2 2
0
1
P2 1
AIN1
0
P2 0
1
AIN0
at power down : state retained
R/W
AIN2
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: In order to select A IN3 –A IN0 , set register Q1 after setting register Q2.
(6) A/D control register Q3
Table 2.1.6 shows the A/D control register Q3.
Set the contents of this register through register A with the TQ3A instruction.
The contents of register Q3 is transferred to register A with the TAQ3 instruction.
Table 2.1.6 A/D control register Q3
AD control register Q3
Q33
P33/AIN7 pin function selection bit
Q32
P32/AIN6 pin function selection bit
Q31
P31/AIN5 pin function selection bit
Q30
P30/AIN4 pin function selection bit
at reset : 0000 2
0
P3 3
1
AIN7
0
P3 2
1
0
AIN6
1
0
AIN5
P3 0
1
AIN4
at power down : state retained
R/W
P3 1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: In order to select A IN7 –A IN4 , set register Q1 after setting regsiter Q3.
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(7) Pull-up control register PU0
Table 2.1.7 shows the pull-up control register PU0.
Set the contents of this register through register A with the TPU0A instruction.
The contents of register PU0 is transferred to register A with the TAPU0 instruction.
Table 2.1.7 Pull-up control register PU0
Pull-up control register PU0
PU03
PU02
PU01
PU00
at reset : 0000 2
at power down : state retained
Port P0 3
0
Pull-up transistor OFF
pull-up transistor control bit
1
Pull-up transistor ON
Port P0 2
0
pull-up transistor control bit
1
0
Pull-up transistor OFF
Pull-up transistor ON
Port P0 1
pull-up transistor control bit
Port P0 0
R/W
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
Pull-up transistor ON
pull-up transistor control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
(8) Pull-up control register PU1
Table 2.1.8 shows the pull-up control register PU1.
Set the contents of this register through register A with the TPU1A instruction.
The contents of register PU1 is transferred to register A with the TAPU1 instruction.
Table 2.1.8 Pull-up control register PU1
Pull-up control register PU1
PU1 3
PU1 2
PU1 1
at reset : 00002
Port P1 3
0
pull-up transistor control bit
1
0
Port P1 2
at power down : state retained
R/W
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
pull-up transistor control bit
Port P1 1
1
Pull-up transistor ON
0
Pull-up transistor OFF
pull-up transistor control bit
1
Pull-up transistor ON
Port P1 0
0
Pull-up transistor OFF
Pull-up transistor ON
pull-up transistor control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
PU1 0
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(9) Port output structure control register FR0
Table 2.1.9 shows the port output structure control register FR0.
Set the contents of this register through register A with the TFR0A instruction.
Table 2.1.9 Port output structure control register FR0
Port output structure control register FR0
FR0 3
FR0 2
FR0 1
at reset : 0000 2
at power down : state retained
Ports P1 2, P1 3
output structure selection bit
0
N-channel open-drain output
1
CMOS output
Ports P1 0, P1 1
0
N-channel open-drain output
output structure selection bit
1
Ports P0 2, P0 3
0
1
CMOS output
N-channel open-drain output
output structure selection bit
Ports P0 1, P0 0
output structure selection bit
Note: “W” represents write enabled.
FR0 0
W
CMOS output
0
N-channel open-drain output
1
CMOS output
(10) Port output structure control register FR1
Table 2.1.10 shows the port output structure control register FR1.
Set the contents of this register through register A with the TFR1A instruction.
Table 2.1.10 Port output structure control register FR1
Port output structure control register FR1
FR13
FR12
FR11
FR10
at reset : 0000 2
Port D 3
0
output structure selection bit
1
0
Port D 2
output structure selection bit
at power down : state retained
N-channel open-drain output
CMOS output
N-channel open-drain output
1
CMOS output
Port D 1
0
N-channel open-drain output
output structure selection bit
1
CMOS output
Port D 0
0
N-channel open-drain output
CMOS output
output structure selection bit
Note: “W” represents write enabled.
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4524 Group
(11) Port output structure control register FR2
Table 2.1.11 shows the port output structure control register FR2.
Set the contents of this register through register A with the TFR2A instruction.
Table 2.1.11 Port output structure control register FR2
Port output structure control register FR2
FR2 3
FR2 2
FR2 1
at reset : 0000 2
at power down : state retained
Port D 7/CNTR0
output structure selection bit
0
N-channel open-drain output
1
CMOS output
Port D 6/S CK
0
N-channel open-drain output
output structure selection bit
1
Port D 5/SOUT
0
1
CMOS output
N-channel open-drain output
output structure selection bit
Port D 4/S IN
output structure selection bit
Note: “W” represents write enabled.
FR2 0
W
CMOS output
0
N-channel open-drain output
1
CMOS output
(12) Port output structure control register FR3
Table 2.1.12 shows the port output structure control register FR3.
Set the contents of this register through register A with the TFR3A instruction.
Table 2.1.12 Port output structure control register FR3
Port output structure control register FR3
FR3 3
FR3 2
FR3 1
FR3 0
at reset : 0000 2
Port P4 3
0
output structure selection bit
1
0
Port P4 2
output structure selection bit
at power down : state retained
N-channel open-drain output
CMOS output
N-channel open-drain output
1
CMOS output
Port P4 1
0
N-channel open-drain output
output structure selection bit
1
CMOS output
Port P4 0
0
N-channel open-drain output
CMOS output
output structure selection bit
Note: “W” represents write enabled.
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4524 Group
(13) Key-on wakeup control register K0
Table 2.1.13 shows the key-on wakeup control register K0.
Set the contents of this register through register A with the TK0A instruction.
The contents of register K0 is transferred to register A with the TAK0 instruction.
Table 2.1.13 Key-on wakeup control register K0
Key-on wakeup control register K0
K0 3
K0 2
K0 1
at reset : 0000 2
at power down : state retained
0
1
Key-on wakeup not used
0
Key-on wakeup not used
key-on wakeup control bit
1
Key-on wakeup used
Port P0 1
0
Key-on wakeup not used
key-on wakeup control bit
1
Key-on wakeup used
Key-on wakeup not used
Port P0 3
key-on wakeup control bit
Port P0 2
Port P0 0
R/W
Key-on wakeup used
0
Key-on wakeup used
key-on wakeup control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
K0 0
(14) Key-on wakeup control register K1
Table 2.1.14 shows the key-on wakeup control register K1.
Set the contents of this register through register A with the TK1A instruction.
The contents of register K1 is transferred to register A with the TAK1 instruction.
Table 2.1.14 Key-on wakeup control register K1
Key-on wakeup control register K1
K13
K12
K11
K10
at reset : 0000 2
at power down : state retained
Port P1 3
0
Key-on wakeup not used
key-on wakeup control bit
Port P1 2
1
Key-on wakeup used
0
Key-on wakeup not used
key-on wakeup control bit
1
Key-on wakeup used
Port P1 1
0
key-on wakeup control bit
1
0
Key-on wakeup not used
Key-on wakeup used
Port P1 0
R/W
Key-on wakeup not used
Key-on wakeup used
key-on wakeup control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
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(15) Key-on wakeup control register K2
Table 2.1.15 shows the key-on wakeup control register K2.
Set the contents of this register through register A with the TK2A instruction.
The contents of register K2 is transferred to register A with the TAK2 instruction.
Table 2.1.15 Key-on wakeup control register K2
Key-on wakeup control register K2
at reset : 0000 2
at power down : state retained
K23
INT1 pin return condition
selection bit
0
Return by level
1
K22
INT1 pin key-on wakeup control
bit
0
1
Return by edge
Key-on wakeup invalid
K21
INT0 pin return condition
selection bit
0
Returned by level
1
Returned by edge
K20
INT0 pin key-on wakeup control
bit
0
Key-on wakeup invalid
1
Key-on wakeup valid
R/W
Key-on wakeup valid
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When setting the port, K2 2 and K23 are not used.
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2.1.3 Port application examples
(1) Key input by key scan
Key matrix can be set up by connecting keys externally because port D output structure is an Nchannel open-drain and port P0 has the pull-up resistor.
Outline: The connecting required external part is just keys.
Specifications: Port D is used to output “L” level and port P0 is used to input 16 keys.
Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing.
M34524
SW4
SW3
SW2
SW1
SW8
SW7
SW6
SW5
SW12
SW11
SW10
SW9
SW16
SW15
SW14
SW13
D0
D1
D2
D3
P00
P01
P02
P03
Fig. 2.1.1 Key input by key scan
Switching key input selection port (D 0 →D 1)
Stabilizing wait time for input
Reading port (key input)
Key input period
D0
D1
D2
“H ”
“L”
“H ”
“L ”
“H ”
“L ”
D3
“H ”
“L ”
IAP0
Input to
SW1–SW4
IAP0
Input to
SW5–SW8
IAP0
IAP0
Input to
SW9–SW12
Input to
SW13–SW16
IAP0
Input to
SW1–SW4
Note: “H” output of port D becomes high-impedance state.
Fig. 2.1.2 Key scan input timing
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2.1 I/O pins
2.1.4 Notes on use
(1) Note when ports P0, P1, P4 and D0 –D 7 are used as an input port
In the following conditions, the pin state of port P0, P1, P4 or D0–D 7 is transferred as input data to
register A when the corresponding input instruction is executed.
• Set bit i (i=0, 1, 2 or 3) of register FR0, FR1, FR2 or FR3 to “0” according to the port to be used.
• Set the output latch of the specified port to “1” with the corresponding output instruction.
If bit i of FR0, FR1, FR2 or FR3 is “0” and the output latch is set to “0,” “0” is output to specified
port.
If bit i of FR0, FR1, FR2 or FR3 is “1”, the output latch value is output to specified port.
(2) Note when ports P2 and P3 are used as an input port
In the following condition, the pin state of port P2 or P3 is transferred as input data to register A when
the IAP2 or IAP3 instruction is executed.
• Set the output latch of specified port P2i or P3i (i=0, 1, 2 or 3) to “1” with the OP2A or OP3A
instruction.
If the output latch is “0”, “0” is output to specified port P2 or P3.
(3) Noise and latch-up prevention
Connect an approximate 0.1 µF bypass capacitor directly to the V SS line and the VDD line with the
thickest possible wire at the shortest distance, and equalize its wiring in width and length.
The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the One Time PROM
version.
Connect the CNVSS/VPP pin to VSS through an approximate 5 kΩ resistor which is connected to the
CNVSS/VPP pin at the shortest distance.
(4) Multifunction
• Be careful that the output of ports D8 and D 9 can be used even when INT0 and INT1 pins are selected.
• Be careful that the input of ports D4–D6 can be used even when SIN, SOUT and SCK pins are selected.
• Be careful that the input/output of port D7 can be used even when input of CNTR0 pin is selected.
• Be careful that the input of port D 7 can be used even when output of CNTR0 pin is selected.
• Be careful that the “H” output of port C can be used even when output of CNTR1 pin is selected.
(5) Connection of unused pins
Table 2.1.16 shows the connections of unused pins.
(6) SD, RD, SZD instructions
When the SD and RD instructions are used, do not set “1010 2” or more to register Y.
When the SZD instructions is used, do not set “1000 2” or more to register Y.
(7) Port D 8/INT0 pin
When the power down mode is used by clearing the bit 3 of register I1 to “0” and setting the input
of INT0 pin to be disabled, be careful about the following note.
• When the input of INT0 pin is disabled (register I1 3 = “0”), clear bit 0 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(8) Port D 9/INT1 pin
When the power down mode is used by clearing the bit 3 of register I2 to “0” and setting the input
of INT1 pin to be disabled, be careful about the following note.
• When the input of INT1 pin is disabled (register I2 3 = “0”), clear bit 2 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
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2.1 I/O pins
Table 2.1.16 Connections of unused pins
Connection
Pin
Usage condition
Connect to V SS. Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1)
XIN
Sub-clock input is selected for system clock (MR 0=1).
(Note 2)
Open.
XOUT
Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1)
RC oscillator is selected (CRCK instruction is executed)
External clock input is selected for main clock (CMCK instruction is executed). (Note 3)
Sub-clock input is selected for system clock (MR 0=1).
(Note 2)
Connect to V SS. Sub-clock is not used.
XCIN
Open.
XCOUT
Sub-clock is not used.
Open.
D0–D 3
Connect to V SS. N-channel open-drain is selected for the output structure.
(Note 4)
Open.
D4/S IN
S IN pin is not selected.
Connect to V SS. N-channel open-drain is selected for the output structure.
Open.
D5/SOUT
Connect to V SS. N-channel open-drain is selected for the output structure.
Open.
D6/SCK
S CK pin is not selected.
Connect to V SS. N-channel open-drain is selected for the output structure.
Open.
D7/CNTR0
CNTR0 input is not selected for timer 1 count source.
Connect to V SS. N-channel open-drain is selected for the output structure.
Open.
D8/INT0
“0” is set to output latch.
Connect to V SS.
Open.
D9/INT1
“0” is set to output latch.
Connect to V SS.
Open.
C/CNTR1
CNTR1 input is not selected for timer 3 count source.
Open.
P00–P0 3
The key-on wakeup function is not selected.
(Note 4)
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 5)
The pull-up function is not selected.
(Note 4)
The key-on wakeup function is not selected.
(Note 4)
Open.
P10–P1 3
The key-on wakeup function is not selected.
(Note 4)
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 5)
The pull-up function is not selected.
(Note 4)
The key-on wakeup function is not selected.
(Note 4)
Open.
P20/AIN0 –
Connect to Vss.
P23/AIN3
Open.
P30/AIN4 –
Connect to Vss.
P33/AIN7
Open.
P40–P4 3
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 4)
COM0–COM 3 Open.
Open.
VLC3/SEG0
SEG 0 pin is selected.
Open.
VLC2/SEG1
SEG 1 pin is selected.
Open.
VLC1/SEG2
SEG 2 pin is selected.
SEG3–SEG19 Open.
Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator)
is selected for main clock.
2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting “1” to bit 1 (MR1)
of clock control register MR, main clock is stopped.
3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input
for the main clock.
4: Be sure to select the output structure of ports D 0–D 3 and P40 –P43 and the pull-up function and
key-on wakeup function of P00–P03 and P1 0–P1 3 with every one port. Set the corresponding bits
of registers for each port.
5: Be sure to select the output structure of ports P0 0–P03 and P10–P13 with every two ports. If only
one of the two pins is used, leave another one open.
(Note when connecting unused pins to V SS or V DD)
● Connect the unused pins to V SS or V DD using the thickest wire at the shortest distance against noise.
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2.2 Interrupts
2.2 Interrupts
The 4524 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 5, A/
D and timer 4 or serial I/O.
This section describes individual types of interrupts, related registers, application examples using interrupts
and notes.
2.2.1 Interrupt functions
(1) External 0 interrupt (INT0)
The interrupt request occurs by the change of input level of INT0 pin.
The interrupt valid waveform can be selected by the bits 1 and 2, and the INT0 pin input is controlled
by the bit 3 of the interrupt control register I1.
■ External 0 interrupt INT0 processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the external 0 interrupt occurs, the interrupt
processing is executed from address 0 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZ0 instruction is valid when the bit 0 of register V1 is set
to “0.”
(2) External 1 interrupt (INT1)
The interrupt request occurs by the change of input level of INT1 pin.
The interrupt valid waveform can be selected by the bits 1 and 2, and the INT1 pin input is controlled
by the bit 3 of the interrupt control register I2.
■ External 1 interrupt INT1 processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 1 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the external 1 interrupt occurs, the interrupt
processing is executed from address 2 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZ1 instruction is valid when the bit 1 of register V1 is set
to “0.”
(3) Timer 1 interrupt
The interrupt request occurs by the timer 1 underflow.
■ Timer 1 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 1 interrupt occurs, the interrupt processing
is executed from address 4 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set
to “0.”
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2.2 Interrupts
(4) Timer 2 interrupt
The interrupt request occurs by the timer 2 underflow.
■ Timer 2 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 2 interrupt occurs, the interrupt processing
is executed from address 6 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set
to “0.”
(5) Timer 3 interrupt
The interrupt request occurs by the timer 3 underflow.
■ Timer 3 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 0 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the timer 3 interrupt occurs, the interrupt processing
is executed from address 8 in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT3 instruction is valid when the bit 0 of register V2 is set
to “0.”
(6) Timer 5 interrupt
The interrupt request occurs by the timer 5 underflow.
■ Timer 5 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 1 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the timer 5 interrupt occurs, the interrupt processing
is executed from address A in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT5 instruction is valid when the bit 1 of register V2 is set
to “0.”
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2.2 Interrupts
(7) A/D interrupt
The interrupt request occurs by the completion of A/D conversion.
■ A/D interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the A/D interrupt occurs, the interrupt processing
is executed from address C in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set
to “0.”
(8) Timer 4 interrupt
The interrupt request occurs by the timer 4 underflow.
■ Timer 4 interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the timer 4 interrupt occurs, the interrupt processing
is executed from address E in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZT4 instruction is valid when the bit 3 of register V2 is set
to “0.”
(9) Serial I/O interrupt
The interrupt request occurs by the completion of serial I/O transmit/receive.
However, set the timer 4, serial I/O interrupt source selection bit (I3 0) to “1.”
■ Serial I/O interrupt processing
● When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the serial I/O interrupt occurs, the interrupt
processing is executed from address E in page 1.
● When the interrupt is not used
The interrupt is disabled and the SNZSI instruction is valid when the bit 3 of register V2 is set
to “0.”
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2.2 Interrupts
4524 Group
2.2.2 Related registers
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable.
Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE
flag is cleared to “0” with the DI instruction.
When any interrupt occurs while the INTE flag is “1”, the INTE flag is automatically cleared to “0,”
so that other interrupts are disabled until the EI instruction is executed.
Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more
instruction.
(2) Interrupt request flag
The activated condition for each interrupt is examined. Each interrupt request flag is set to “1” when
the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt
enable bit.
Each interrupt request flag is cleared to “0” when either;
•an interrupt occurs, or
•the next instruction is skipped with a skip instruction.
(3) Interrupt control register V1
Table 2.2.1 shows the interrupt control register V1.
Set the contents of this register through register A with the TV1A instruction.
In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A.
Table 2.2.1 Interrupt control register V1
Interrupt control register V1
V1 3
Timer 2 interrupt enable bit
V1 2
Timer 1 interrupt enable bit
V1 1
External 1 interrupt enable bit
V1 0
External 0 interrupt enable bit
at reset : 0000 2
at power down : 0000 2
R/W
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
0
1
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
0
Interrupt disabled (SNZ1 instruction is valid)
1
Interrupt enabled (SNZ1 instruction is invalid) (Note 2)
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
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4524 Group
(4) Interrupt control register V2
Table 2.2.2 shows the interrupt control register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.2.2 Interrupt control register V2
Interrupt control register V2
V2 3
Timer 4, serial I/O interrupt
enable bit (Note 2)
V2 2
A/D interrupt enable bit
V2 1
Timer 5 interrupt enable bit
V2 0
Timer 3 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
at power down : 0000 2
R/W
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 3)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 3)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid) (Note 3)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid) (Note 3)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source
selection bit (I3 0).
3: These instructions are equivalent to the NOP instruction.
(5) Interrupt control register I1
Table 2.2.3 shows the interrupt control register I1.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.2.3 Interrupt control register I1
Interrupt control register I1
I1 3
INT0 pin input control bit (Note 2)
I1 2
Interrupt valid waveform for INT0
pin/return level selection bit
(Note 2)
at reset : 0000 2
at power down : state retained
R/W
0
INT0 pin input disabled
1
INT0 pin input enabled
0
Falling waveform /“L” level (“L” level is recognized with
the SNZI0 instruction)
1
Rising waveform /“H” level (“H” level is recognized with
the SNZI0 instruction)
One-sided edge detected
INT0 pin edge detection circuit
0
Both edges detected
control bit
1
Timer 1 count start synchronous circuit not selected
INT0 pin Timer 1 count start
0
I1 0
synchronous circuit selection bit
Timer 1 count start synchronous circuit selected
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I1 3 are changed, the external interrupt request flag EXF0 may be
set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to
“0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
I1 1
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2.2 Interrupts
4524 Group
(6) Interrupt control register I2
Table 2.2.4 shows the interrupt control register I2.
Set the contents of this register through register A with the TI2A instruction.
In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 2.2.4 Interrupt control register I2
Interrupt control register I2
at reset : 0000 2
0
1
at power down : state retained
R/W
INT1 pin input disabled
I23
INT1 pin input control bit (Note 2)
0
I22
Interrupt valid waveform for INT1
pin/return level selection bit
Falling waveform /“L” level (“L” level is recognized with
the SNZI1 instruction)
(Note 2)
1
Rising waveform /“H” level (“H” level is recognized with
the SNZI1 instruction)
INT1 pin edge detection circuit
control bit
0
One-sided edge detected
1
INT1 pin Timer 3 count start
0
Both edges detected
Timer 3 count start synchronous circuit not selected
I21
I20
INT1 pin input enabled
Timer 3 count start synchronous circuit selected
synchronous circuit selection bit
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I2 2 and I2 3 are changed, the external interrupt request flag EXF1 may be
set. Accordingly, clear EXF1 flag with the SNZ1 instruction when the bit 1 (V1 1) of register V1 to
“0”. In this time, set the NOP instruction after the SNZ1 instruction, for the case when a skip is
performed with the SNZ1 instruction.
(7) Interrupt control register I3
Table 2.2.5 shows the interrupt control register I3.
Set the contents of this register through register A with the TI3A instruction.
In addition, the TAI3 instruction can be used to transfer the contents of register I3 to register A.
Table 2.2.5 Interrupt control register I3
Interrupt control register I3
I30
Timer 4, serial I/O interrupt
source selection bit
at reset : 0 2
0
at power down : state retained
R/W
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
1
Note: “R” represents read enabled, and “W” represents write enabled.
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2.2 Interrupts
2.2.3 Interrupt application examples
(1) External 0 interrupt
The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can
recognize the change of falling edge (“H”→“L”), rising edge (“L”→“H”) and both edges (“H”→“L” or
“L”→“H”).
Outline: An external 0 interrupt can be used by dealing with the falling edge (“H”→“L”), rising edge
(“L”→“H”) and both edges (“H”→“L” or “L”→“H”) as a trigger.
Specifications: An interrupt occurs by the change of an external signals edge (“H”→“L” or “L”→“H”).
Figure 2.2.1 shows an operation example of an external 0 interrupt, and Figure 2.2.2 shows a setting
example of an external 0 interrupt.
(2) External 1 interrupt
The INT1 pin is used for external 1 interrupt, of which valid waveforms can be chosen, which can
recognize the change of falling edge (“H”→“L”), rising edge (“L”→“H”) and both edges (“H”→“L” or
“L”→“H”).
Outline: An external 1 interrupt can be used by dealing with the falling edge (“H”→“L”), rising edge
(“L”→“H”) and both edges (“H”→“L” or “L”→“H”) as a trigger.
Specifications: An interrupt occurs by the change of an external signals edge (“H”→“L” or “L”→“H”).
Figure 2.2.3 shows an operation example of an external 1 interrupt, and Figure 2.2.4 shows a setting
example of an external 1 interrupt.
(3) Timer 1 interrupt
Constant period interrupts by a setting value to timer 1 can be used.
Outline: The constant period interrupts by the timer 1 underflow signal can be used.
Specifications: Timer 1 divides the system clock frequency = 2.0 MHz, and the timer 1 interrupt
occurs every 0.25 ms.
Figure 2.2.5 shows a setting example of the timer 1 constant period interrupt.
(4) Timer 2 interrupt
Constant period interrupts by a setting value to timer 2 can be used.
Outline: The constant period interrupts by the timer 2 underflow signal can be used.
Specifications: Timer 2 and prescaler divide the system clock frequency (= 4.0 MHz), and the timer
2 interrupt occurs every 1 ms.
Figure 2.2.6 shows a setting example of the timer 2 constant period interrupt.
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(5) Timer 3 interrupt
Constant period interrupts by a setting value to timer 3 can be used.
Outline: The constant period interrupts by the timer 3 underflow signal can be used.
Specifications: Prescaler and timer 3 divide the system clock frequency = 4.0 MHz, and the timer
3 interrupt occurs every 1 ms.
Figure 2.2.7 shows a setting example of the timer 3 constant period interrupt.
(6) Timer 4 interrupt
Constant period interrupts by a setting value to timer 4 can be used.
Outline: The constant period interrupts by the timer 4 underflow signal can be used.
Specifications: Timer 4 and prescaler divide the system clock frequency (= 4.0 MHz), and the timer
4 interrupt occurs every 50 ms.
Figure 2.2.8 shows a setting example of the timer 4 constant period interrupt.
(7) Timer 5 interrupt
Timer 5 is a fixed dividing frequency timer. Constant period interrupts which count source is divided
2 13, 2 14, 2 15 or 2 16 can be used.
Outline: The constant period interrupts by the timer 5 underflow signal can be used.
Specifications: Timer 5 divides the sub-clock frequency ((f(X CIN ) = 32.768 kHz), and the timer 5
interrupt occurs every 500 ms.
Figure 2.2.9 shows a setting example of the timer 5 constant period interrupt.
D8/INT0
“H”
“L”
D8/INT0
“H”
“L”
An interrupt occurs after the valid waveform “falling” is detected.
An interrupt occurs after the valid waveform “rising” is detected.
Fig. 2.2.1 External 0 interrupt operation example
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2.2 Interrupts
4524 Group
➀ Disable Interrupts
External 0 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V1
✕
b0
✕
✕
0
b0: External 0 interrupt occurrence disabled [TV1A]
↓
➁ Set Port
Port used for external 0 interrupt is set to input port.
b3
Register Y
Port D 8 output latch
1
1
b0
0
0
0
Specify bit position of port D [TYA]
Set to input [SD]
b0
[TI1A]
b3: INT0 pin input enabled
b1: Both edges detection selected
↓
➂ Set Valid Waveform
Valid waveform of INT0 pin is selected.
b3
Interrupt control register I1
✕
1
✕
1
↓
➃ Execute NOP Instruction
[NOP]
↓
➄ Clear Interrupt Request
External 0 interrupt activated condition is cleared.
External 0 interrupt request flag EXF0
0
External 0 interrupt activated condition cleared [SNZ0]
↓
(
)
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction
according to the interrupt request flag EXF0,
insert the NOP instruction after the SNZ0 instruction.
↓
➅ Enable Interrupts
The External 0 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V1
Interrupt enable flag INTE
✕
1
b0
✕
✕
1
b0: External 0 interrupt occurrence enabled [TV1A]
All interrupts enabled [EI]
↓
External 0 interrupt enabled state
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.2 External 0 interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
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2.2 Interrupts
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D9/INT1
“H”
“L”
D9/INT1
“H”
An interrupt occurs after the valid waveform “falling” is detected.
“L”
Fig. 2.2.3 External 1 interrupt operation example
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2.2 Interrupts
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➀ Disable Interrupts
External 1 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V1
✕
b0
✕
✕
0
b1: External 1 interrupt occurrence disabled [TV1A]
↓
➁ Set Port
Port used for external 1 interrupt is set to input port.
b3
Register Y
Port D 9 output latch
1
1
b0
0
0
1
Specify bit position of port D [TYA]
Set to input [SD]
b0
[TI2A]
b3: INT1 pin input enabled
b2, b1: One-sided edge detection and
falling waveform selected
↓
➂ Set Valid Waveform
Valid waveform of INT1 pin is selected.
b3
Interrupt control register I2
1
0
✕
0
↓
➃ Execute NOP Instruction
[NOP]
↓
➄ Clear Interrupt Request
External 1 interrupt activated condition is cleared.
External 1 interrupt request flag EXF1
0
External 1 interrupt activated condition cleared [SNZ1]
↓
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction
according to the interrupt request flag EXF1,
insert the NOP instruction after the SNZ1 instruction.
(
)
↓
➅ Enable Interrupts
The External 1 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V1
Interrupt enable flag INTE
✕
1
b0
✕
✕
1
b1: External 1 interrupt occurrence enabled [TV1A]
All interrupts enabled [EI]
↓
External 1 interrupt enabled state
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.4 External 1 interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
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➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V1
✕
b0
0
✕
✕
b2: Timer 1 interrupt occurrence disabled [TV1A]
b0
[TW1A]
b3: Timer 1 count auto-stop circuit not selected
b2: Timer 1 stop
b1, b0: Instruction clock (INSTCK) selected for
Timer 1 count source
↓
➁ Stop Timer Operation
Timer 1 is temporarily stopped.
Timer 1 count source is selected.
b3
Timer control register W1
0
0
0
0
↓
➂ Set Timer Value
Timer 1 count time is set. (The formula is shown *A below.)
Timer 1 reload register R1 “A6 16”
Timer count value 166 set [T1AB]
↓
➃ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F
0
Timer 1 interrupt activated condition cleared
[SNZT1]
↓
(
)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction
according to the interrupt request flag T1F,
insert the NOP instruction after the SNZT1 instruction.
↓
➄ Start Timer Operation
Timer 1 temporarily stopped is restarted.
b3
Timer control register W1
0
b0
1
0
0
b2: Timer 1 operation start [TW1A]
↓
➅ Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V1
Interrupt enable flag INTE
✕
1
b0
1
✕
✕
b2: Timer 1 interrupt occurrence enabled [TV1A]
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The timer 1 count value to make the interrupt occur every 0.25 ms is set as follows.
0.25 ms ≅ (2.0 MHz) -1 ✕ 3 ✕ (166+1)
System clock
Instruction
clock
Timer 1 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.5 Timer 1 constant period interrupt setting example
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2.2 Interrupts
4524 Group
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V1
0
b0
✕
✕
✕
b3: Timer 2 interrupt occurrence disabled [TV1A]
↓
➁ Stop Timer and Prescaler Operation
Timer 2 and prescaler are temporarily stopped.
Timer 2 count source is selected.
b3
Timer control register W2
✕
b0
0
0
1
b0
Timer control register PA
0
[TW2A]
b2: Timer 2 stop
b1, b0: Prescaler output (ORCLK) selected for
Timer 2 count source
Prescaler stop [TPAA]
↓
➂ Set Timer Value and Prescaler Value
Timer 2 and prescaler count times are set. (The formula is shown *A below.)
Timer 2 reload register R2 “5216 ”
Timer count value 82 set [T2AB]
Prescaler reload register RPS “0F 16”
Prescaler count value 15 set [TPSAB]
↓
➃ Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F
0
Timer 2 interrupt activated condition cleared [SNZT2]
↓
(
)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction
according to the interrupt request flag T2F,
insert the NOP instruction after the SNZT2 instruction.
↓
➄ Start Timer Operation and Prescaler Operation
Timer 2 and prescaler temporarily stopped are restarted.
b3
Timer control register W2
✕
b0
1
0
1
b2: Timer 2 operation start [TW2A]
b0
Timer control register PA
1
Prescaler start [TPAA]
↓
➅ Enable Interrupts
The Timer 2 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V1
Interrupt enable flag INTE
1
1
b0
✕
✕
✕
b3: Timer 2 interrupt occurrence enabled [TV1A]
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The prescaler count value and timer 2 count value to make the interrupt occur every 1 ms are set as follows.
1 ms ≅ (4.0 MHz) -1 ✕ 3 ✕ (15 +1) ✕ (82 +1)
System clock
Instruction
clock
Prescaler
count value
Timer 2 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.6 Timer 2 constant period interrupt setting example
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2.2 Interrupts
4524 Group
➀ Disable Interrupts
Timer 3 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V2
b0
✕ ✕
✕
0
b0: Timer 3 interrupt occurrence disabled [TV2A]
↓
➁ Stop Timer Operation
Timer 3 and prescaler are temporarily stopped.
Timer 3 count source is selected.
b3
Timer control register W3
0
b0
0
0
1
b0
Timer control register PA
0
[TW3A]
b3: Timer 3 count auto-stop circuit not selected
b2: Timer 3 stop
b1, b0: Prescaler output (ORCLK) selected for
Timer 3 count source
Prescaler stop [TPAA]
↓
➂ Set Timer Value and Prescaler Value
Timer 3 and prescaler count times are set. (The formula is shown *A below.)
Timer 3 reload register R3 “52 16”
Timer count value 82 set [T3AB]
Prescaler count value 15 set [TPSAB]
Prescaler reload register RPS “0F 16”
↓
➃ Clear Interrupt Request
Timer 3 interrupt activated condition is cleared.
Timer 3 interrupt request flag T3F
0
Timer 3 interrupt activated condition cleared [SNZT3]
↓
(
)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction
according to the interrupt request flag T3F,
insert the NOP instruction after the SNZT3 instruction.
↓
➄ Start Timer Operation and Prescaler Operation
Timer 3 and prescaler temporarily stopped are restarted.
b3
Timer control register W3
0
b0
1
0
1
b2: Timer 3 operation start [TW3A]
b0
Timer control register PA
1
Prescaler start [TPAA]
↓
➅ Enable Interrupts
The Timer 3 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V2
Interrupt enable flag INTE
✕ ✕
1
b0
✕
1
b0: Timer 3 interrupt occurrence enabled [TV2A]
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The prescaler count value and timer 3 count value to make the interrupt occur every 1 ms are set as follows.
1 ms ≅ (4.0 MHz) -1 ✕ 3 ✕ (15 +1) ✕ (82 +1)
System clock
Instruction
clock
Prescaler
count value
Timer 3 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.7 Timer 3 constant period interrupt setting example
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2.2 Interrupts
4524 Group
➀ Disable Interrupts
Timer 4 and serial I/O interrupts are temporarily disabled.
Interrupt enable flag INTE
0
b3
Interrupt control register V2
0
All interrupts disabled [DI]
b0
✕
✕
✕
b3: Timer 4 and serial I/O interrupts occurrence disabled
[TV2A]
↓
➁ Stop Timer and Prescaler Operation
Timer 4 and prescaler are temporarily stopped.
Timer 4 count source is selected.
b3
Timer control register W4
0
b0
0
0
1
b0
Timer control register PA
0
[TW4A]
b3: CNTR1 output invalid
b2: PWM signal “H” interval expansion function invalid
b1: Timer 4 stop
b0: Prescaler output (ORCLK) divided by 2 selected
for Timer 4 count source
Prescaler stop [TPAA]
↓
➂ Select Timer 4 Interrupt
Timer 4 is selected for the interrupt source.
b0
Interrupt control register I3
0
Timer 4 interrupt valid [TI3A]
↓
➃ Set Timer Value and Prescaler Value
Timer 4 and prescaler count times are set. (The formula is shown *A below.)
Timer count value 221 set [T4AB]
Timer 4 reload register R4L “DD 16 ”
Prescaler reload register RPS “9516 ”
Prescaler count value 149 set [TPSAB]
↓
➄ Clear Interrupt Request
Timer 4 interrupt activated condition is cleared.
Timer 4 interrupt request flag T4F
0
Timer 4 interrupt activated condition cleared [SNZT4]
↓
(
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction
according to the interrupt request flag T4F,
insert the NOP instruction after the SNZT4 instruction.
)
↓
➅ Start Timer Operation and Prescaler Operation
Timer 4 and prescaler temporarily stopped are restarted.
b3
Timer control register W4
0
b0
0
1
1
b1: Timer 4 operation start [TW4A]
b0
Timer control register PA
1
Prescaler start [TPAA]
↓
➆ Enable Interrupts
The Timer 4 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V2
Interrupt enable flag INTE
1
1
b0
✕
✕
✕
b3: Timer 4 interrupt occurrence enabled [TV2A]
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The prescaler count value and timer 4 count value to make the interrupt occur every 50 ms are set as follows.
50 ms ≅ (4.0 MHz) -1 ✕ 3 ✕ (149 +1) ✕ 2 ✕ (221 +1)
System clock
Instruction
clock
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Prescaler
count value
Timer 4
count
source
Timer 4 count value
Fig. 2.2.8 Timer 4 constant period interrupt setting example
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2.2 Interrupts
4524 Group
➀ Disable Interrupts
Timer 5 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V2
b0
✕ ✕
✕
0
b1: Timer 5 interrupt occurrence disabled [TV2A]
↓
➁ Set Timer Value
Timer 5 is temporarily stopped.
Timer 5 count time is set.
(The formula is shown *A below.)
Timer control register W5
b3
✕
b0
0
0
1
[TW5A]
b2: Timer 5 stop
Timer 5 count value initialized
b1,b0: Timer count value 2 14 set
↓
➂ Clear Interrupt Request
Timer 5 interrupt activated condition is cleared.
Timer 5 interrupt request flag T5F
0
Timer 5 interrupt activated condition cleared [SNZT5]
↓
(
)
Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction
according to the interrupt request flag T5F,
insert the NOP instruction after the SNZT5 instruction.
↓
➃ Start Timer Operation
Timer 5 temporarily stopped is restarted.
b3
Timer control register W5
✕
b0
1
0
1
b2: Timer 5 operation start [TW5A]
↓
➄ Enable Interrupts
The Timer 5 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V2
Interrupt enable flag INTE
✕ ✕
1
b0
✕
1
b1: Timer 5 interrupt occurrence enabled [TV2A]
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The timer 5 count value to make the interrupt occur every 500 ms is set as follows.
500 ms = (32.768 kHz) –1 ✕ 2 14
Sub-clock
Timer 5 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.2.9 Timer 5 constant period interrupt setting example
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4524 Group
2.2 Interrupts
2.2.4 Notes on use
(1) Setting of INT0 interrupt valid waveform
Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction.
Depending on the input state of D 8/INT0 pin, the external interrupt request flag (EXF0) may be set
to “1” when the bit 2 of register I1 is changed.
(2) Setting of INT0 pin input control
Set a value to the bit 3 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction.
Depending on the input state of D 8/INT0 pin, the external interrupt request flag (EXF0) may be set
to “1” when the bit 3 of register I1 is changed.
(3) Setting of INT1 interrupt valid waveform
Set a value to the bit 2 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction.
Depending on the input state of D 9/INT1 pin, the external interrupt request flag (EXF1) may be set
to “1” when the bit 2 of register I2 is changed.
(4) Setting of INT1 pin input control
Set a value to the bit 3 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction.
Depending on the input state of D 9/INT1 pin, the external interrupt request flag (EXF1) may be set
to “1” when the bit 3 of register I2 is changed.
(5) Multiple interrupts
Multiple interrupts cannot be used in the 4524 Group.
(6) Notes on interrupt processing
When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt
disable state). In order to enable the interrupt at the same time when system returns from the
interrupt, write EI and RTI instructions continuously.
(7) D 8/INT0 pin
When the external interrupt input pin INT0 is used, set the bit 3 of register I1 to “1”.
Even in this case, port D 8 output function is valid.
Also, the EXF0 flag is set to “1” when bit 3 of register I1 is set to “1” by input of a valid waveform
(valid waveform causing external 0 interrupt) even if it is used as an output port D 8.
(8) D 9/INT1 pin
When the external interrupt input pin INT1 is used, set the bit 3 of register I2 to “1”.
Even in this case, port D 9 output function is valid.
Also, the EXF1 flag is set to “1” when bit 3 of register I2 is set to “1” by input of a valid waveform
(valid waveform causing external 1 interrupt) even if it is used as an output port D 9.
(9) POF instruction, POF2 instruction
When the POF or POF2 instruction is executed continuously after the EPOF instruction, system
enters the power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction
and the POF or POF2 instruction continuously.
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4524 Group
2.3 Timers
2.3 Timers
The 4524 Group has four 8-bit timers (each has a reload register), a 4-bit timer and a 16-bit fixed dividing
frequency timer which has the watchdog timer function.
This section describes individual types of timers, related registers, application examples using timers and
notes.
2.3.1 Timer functions
(1) Timer 1
■ Timer operation
(Timer 1 has the timer 1 count start trigger function from D 8/INT0 pin input)
(2) Timer 2
■ Timer operation
(3) Timer 3
■ Timer operation
(Timer 3 has the timer 3 count start trigger function from D 9/INT1 pin input)
(4) Timer 4
■ Timer operation
(Timer 4 has the PWM output function)
(5) Timer 5 (16-bit timer)
■ Timer operation
(Timer 5 has the function to return from the clock operating mode (POF instruction execution))
(6) Timer LC
■ LCD clock generating
(7) 16-bit timer
■ Watchdog function
Watchdog timer provides a method to reset the system when a program run-away occurs.
System operates after it is released from reset. When the timer count value underflows, the WDF1
flag is set to “1.” Then, if the WRST instruction is never executed until timer WDT counts 65534,
WDF2 flag is set to “1,” and system reset occurs.
When the DWDT instruction and the WRST instruction are executed continuously, the watchdog timer
function is invalid.
The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1
flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped.
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4524 Group
2.3.2 Related registers
(1) Interrupt control register V1
Table 2.3.1 shows the interrupt control register V1.
Set the contents of this register through register A with the TV1A instruction.
In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A.
Table 2.3.1 Interrupt control register V1
Interrupt control register V1
V1 3
Timer 2 interrupt enable bit
V1 2
Timer 1 interrupt enable bit
V1 1
External 1 interrupt enable bit
V1 0
External 0 interrupt enable bit
at reset : 00002
at power down : 0000 2
R/W
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ1 instruction is valid)
0
1
0
Interrupt enabled (SNZ1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When timer is used, V1 1 and V1 0 are not used.
(2) Interrupt control register V2
Table 2.3.2 shows the interrupt control register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.3.2 Interrupt control register V2
Interrupt control register V2
V2 3
Timer 4, serial I/O interrupt
enable bit
V2 2
A/D interrupt enable bit
V2 1
Timer 5 interrupt enable bit
at reset : 00002
at power down : 0000 2
R/W
0
1
Interrupt disabled (SNZT4, SNZSI instruction is valid)
0
Interrupt disabled (SNZAD instruction is valid)
1
Interrupt enabled (SNZTAD instruction is invalid) (Note 3)
0
Interrupt disabled (SNZT5 instruction is valid)
1
Interrupt enabled (SNZT5 instruction is invalid) (Note 3)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 3)
0
Interrupt enabled (SNZT3 instruction is invalid) (Note 3)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When timer is used, V2 1 is not used.
V2 0
Timer 3 interrupt enable bit
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2.3 Timers
4524 Group
(3) Interrupt control register I3
Table 2.3.3 shows the interrupt control register I3.
Set the contents of this register through register A with the TI3A instruction.
In addition, the TAI3 instruction can be used to transfer the contents of register I3 to register A.
Table 2.3.3 Interrupt control register I3
Interrupt control register I3
I30
Timer 4, serial I/O interrupt
source selection bit
at reset : 0 2
0
at power down : state retained
R/W
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
1
Note: “R” represents read enabled, and “W” represents write enabled.
(4) Timer control register PA
Table 2.3.4 shows the timer control register PA.
Set the contents of this register through register A with the TPAA instruction.
Table 2.3.4 Timer control register PA
Timer control register PA
PA 0
Prescaler control bit
at reset : 0 2
0
1
at power down : state retained
W
Stop (state initialized)
Operating
Note: “W” represents write enabled.
(5) Timer control register W1
Table 2.3.5 shows the timer control register W1.
Set the contents of this register through register A with the TW1A instruction.
In addition, the TAW1 instruction can be used to transfer the contents of register W1 to register A.
Table 2.3.5 Timer control register W1
Timer control register W1
W1 3
Timer 1 count auto-stop circuit
control bit (Note 2)
W1 2
Timer 1 control bit
at reset : 0000 2
at power down : state retained
0
Timer 1 count auto-stop circuit not selected
1
Timer 1 count auto-stop circuit selected
0
Stop (state retained)
R/W
Operating
1
Count source
W11 W10
W1 1
0
0 Instruction clock (INSTCK)
Timer 1 count source selection
0
1 Prescaler output (ORCLK)
bits
1
0 Timer 5 underflow signal (T5UDF)
W1 0
1
1 CNTR0 input
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I1 0 =“1”).
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4524 Group
(6) Timer control register W2
Table 2.3.6 shows the timer control register W2.
Set the contents of this register through register A with the TW2A instruction.
In addition, the TAW2 instruction can be used to transfer the contents of register W2 to register A.
Table 2.3.6 Timer control register W2
Timer control register W2
W2 3
CNTR0 output selection bit
W2 2
Timer 2 control bit
at reset : 0000 2
0
1
0
at power down : state retained
R/W
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating
1
Count source
W21 W20
W2 1 Timer 2 count source selection 0
0 System clock (STCK)
0
1 Prescaler output (ORCLK)
bits
1
0 Timer 1 underflow signal (T1UDF)
W2 0
1
1 PWM signal (PWMOUT)
Note: “R” represents read enabled, and “W” represents write enabled.
(7) Timer control register W3
Table 2.3.7 shows the timer control register W3.
Set the contents of this register through register A with the TW3A instruction.
In addition, the TAW3 instruction can be used to transfer the contents of register W3 to register A.
Table 2.3.7 Timer control register W3
Timer control register W3
W3 3
W3 2
W3 1
W3 0
Timer 3 count auto-stop circuit
control bit (Note 2)
Timer 3 control bit
at reset : 0000 2
at power down : state retained
0
1
Timer 3 count auto-stop circuit not selected
0
Stop (state retained)
1
W31 W30
0
Timer 3 count source selection 0
0
1
bits (Note 3)
1
0
1
1
R/W
Timer 3 count auto-stop circuit selected
Operating
Count source
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 2 underflow signal (T2UDF)
CNTR1 input
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 3 count start synchronous circuit is selected (I2 0 =“1”).
3: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
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4524 Group
(8) Timer control register W4
Table 2.3.8 shows the timer control register W4.
Set the contents of this register through register A with the TW4A instruction.
In addition, the TAW4 instruction can be used to transfer the contents of register W4 to register A.
Table 2.3.8 Timer control register W4
Timer control register W4
W43
CNTR1 output control bit
W42
PWM signal “H” interval
expansion function control bit
W41
Timer 4 control bit
at reset : 0000 2
at power down : 0000 2
R/W
0
CNTR1 output invalid
1
CNTR1 output valid
0
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
1
0
1
Stop (state retained)
Operating
XIN input
0
Timer 4 count source selection
Prescaler output (ORCLK) divided by 2
bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
W40
(9) Timer control register W5
Table 2.3.9 shows the timer control register W5.
Set the contents of this register through register A with the TW5A instruction.
In addition, the TAW5 instruction can be used to transfer the contents of register W5 to register A.
Table 2.3.9 Timer control register W5
Timer control register W5
W53
Not used
W52
Timer 5 control bit
W51
W50
at reset : 0000 2
at power down : state retained
R/W
0
1
This bit has no function, but read/write is enabled.
0
Stop (state initialized)
1
W51 W50
0
Timer 5 count value selection bits 0
0
1
1
0
1
1
Operating
Count value
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When timer is used, W5 3 is not used.
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(10) Timer control register W6
Table 2.3.10 shows the timer control register W6.
Set the contents of this register through register A with the TW6A instruction.
In addition, the TAW6 instruction can be used to transfer the contents of register W6 to register A.
Table 2.3.10 Timer control register W6
Timer control register W6
W6 3
W6 2
W6 1
W6 0
Timer LC control bit
Timer LC count source selection
bit
CNTR1 output auto-control circuit
selection bit
D7/CNTR0 pin function selection
bit (Note 2)
at reset : 0000 2
0
1
0
at power down : state retained
Stop (state retained)
Operating
Bit 4 (T5 4) of timer 5
1
Prescaler output (ORCLK)
0
CNTR1 output auto-control circuit not selected
1
CNTR1 output auto-control circuit selected
0
D 7(I/O)/CNTR0 input
CNTR0 input/output/D 7 (input)
1
R/W
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
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2.3.3 Timer application examples
(1) Timer operation: measurement of constant period
The constant period by the setting timer count value can be measured.
Outline: The constant period by the timer 1 underflow signal can be measured.
Specifications: Timer 1 and prescaler divide the system clock frequency f(XIN ) = 4.0 MHz, and the
timer 1 interrupt request occurs every 3 ms.
Figure 2.3.4 shows the setting example of the constant period measurement.
(2) CNTR0 output operation: buzzer output
Outline: Square wave output from timer 2 can be used for buzzer output.
Specifications: 4 kHz square wave is output from the CNTR0 pin at system clock frequency f(XIN)
= 4.0 MHz. Also, timer 2 interrupt occurs simultaneously.
Figure 2.3.1 shows the peripheral circuit example, and Figure 2.3.5 shows the setting example of
CNTR0 output.
In order to reduce the current dissipation, output is high-impedance state during buzzer output stop.
4524
125 µs 125 µs
CNTR0
Set dividing ratio for timer 2 underflow cycle to 125 µs.
Fig. 2.3.1 Peripheral circuit example
(3) CNTR0 input operation: event count
Outline: Count operation can be performed by using the signal (rising waveform) input from CNTR0
pin as the event.
Specifications: The low-frequency pulse from external as the timer 1 count source is input to CNTR0
pin, and the timer 1 interrupt request occurs every 100 counts.
Figure 2.3.6 shows the setting example of CNTR0 input.
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2.3 Timers
4524 Group
(4) Timer operation: timer start by external input
Outline: The constant period can be measured by external input.
Specifications: Timer 3 operates by INT1 input as a trigger and an interrupt occurs after 1 ms.
Figure 2.3.7 shows the setting example of timer start.
(5) CNTR1 output control: PWM output control
Outline: The PWM output from CNTR1 pin can be performed by timer 4.
Specifications: Timer 4 divides the main clock frequency f(XIN) = 4.0 MHz and the waveform, which
“H” period is 0.875 µs of the 1.875 µs PWM periods, is output from CNTR1 pin.
Figure 2.3.2 shows the timer 4 operation and Figure 2.3.8 shows the setting example of PWM output
control.
(6) Timer operation: constant period counter by timer 5
Constant period time by the timer count value can be measured.
Outline: A clock with high accuracy can be set up by using a 32.768 kHz quartz-crystal oscillator.
Specifications: Timer 5 divides the sub-clock frequency f(XCIN) = 32.768 kHz and timer 5 interrupt
occurs every 250 ms.
Figure 2.3.9 shows the setting example of constant period counter by timer 5.
● CNTR1 output: valid (W43 = “1”)
PWM signal “H” interval extension function: valid (W42 = “1”) (Note)
Reload register R4L = “0316”
Reload register R4H = “0216”
Timer 4 count source
Timer 4 count value
(Reload register)
0316
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
0216
0116 0016 0316 0216 0116 0016 0216
(R4L)
(R4H)
(R4L)
(R4H)
(R4L)
(R4H)
Timer 4 underflow signal
3.5 clock
PWM signal
Timer 4 start
PWM period 7.5 clock
3.5 clock
PWM period 7.5 clock
Note: At PWM signal “H” interval extension function: valid, set “0116” or more to reload register R4H.
Fig. 2.3.2 Timer 4 operation
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2.3 Timers
4524 Group
(7) Watchdog timer
Watchdog timer provides a method to reset the system when a program run-away occurs.
Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at
a certain period which consists of 16-bit timers’ 65534 counts or less (execute WRST instruction at
less than 65534 machine cycles).
Outline: Execute the WRST instruction in 16-bit timer’s 65534 counts at the normal operation. If a
program runs incorrectly, the WRST instruction is not executed and system reset occurs.
Specifications: System clock frequency f(XIN) = 4.0 MHz is used, and program run-away is detected
by executing the WRST instruction in 49 ms.
Figure 2.3.3 shows the watchdog timer function, and Figure 2.3.10 shows the example of watchdog
timer.
FFFF 1 6
Value of 16-bit timer (WDT)
000016
➁
WDF1 flag
➁
65534 count
(Note)
➃
WDF2 flag
RESET pin output
➀ Reset
released
➂ WRST instruction
executed
(skip executed)
➄ System reset
➀ After system is released from reset (= after program is started), timer WDT starts count down.
➁ When timer WDT underflow occurs, WDF1 flag is set to “1.”
➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped.
➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the
watchdog reset signal is output.
➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of cycle because the count source of watchdog timer
is the instruction clock.
Fig. 2.3.3 Watchdog timer function
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APPLICATION
2.3 Timers
4524 Group
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V1
✕
b0
0
✕
✕
b2: Timer 1 interrupt occurrence disabled [TV1A]
↓
➁ Stop Timer and Prescaler Operation
Timer 1 and prescaler are temporarily stopped.
Timer 1 count source is selected.
b3
Timer control register W1
0
b0
0
0
1
b0
Timer control register PA
0
[TW1A]
b3: Timer 1 count auto-stop circuit not selected
b2: Timer 1 stop
b1, b0: Prescaler output (ORCLK) selected for
Timer 1 count source
Prescaler stop [TPAA]
↓
➂ Set Timer and Prescaler Values
Timer 1 and prescaler count times are set. (The formula is shown *A below.)
Timer 1 reload register R1 “F9 16”
Timer count value 249 set [T1AB]
Prescaler reload register RPS “0F 16”
Prescaler count value 15 set [TPSAB]
↓
➃ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F
0
Timer 1 interrupt activated condition cleared [SNZT1]
↓
(
)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction
according to the interrupt request flag T1F,
insert the NOP instruction after the SNZT1 instruction.
↓
➄ Start Timer and Prescaler Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3
Timer control register W1
0
b0
1
0
1
b2: Timer 1 operation start [TW1A]
b0
Timer control register PA
1
Prescaler operation start [TPAA]
↓
➅ Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V1
Interrupt enable flag INTE
✕
1
b0
1
✕
✕
b2: Timer 1 interrupt occurrence enabled [TV1A]
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The prescaler count value and timer 1 count value to make the interrupt occur every 3 ms is set as follows.
3 ms = (4.0 MHz) -1 ✕ 3 ✕ (15+1) ✕ (249+1)
System clock
Instruction
clock
Prescaler
count
value
Timer 1 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.3.4 Constant period measurement setting example
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2.3 Timers
4524 Group
➀ Disable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V1
0
b0
✕
✕
✕
b3: Timer 2 interrupt occurrence disabled [TV1A]
↓
➁ Stop Timer and Prescaler Operation
Timer 2 and prescaler are temporarily stopped.
Timer 2 count source and CNTR0 output are selected.
b3
Timer control register W2
1
b0
0
0
1
b0
Timer control register PA
0
[TW2A]
b3: Timer 2 underflow signal divided by 2 selected for
CNTR0 output
b2: Timer 2 stop
b1, b0: Prescaler output (ORCLK) selected for
Timer 2 count source
Prescaler stop [TPAA]
↓
➂ Set CNTR0 Output
The output structure of the CNTR0 pin is set to N-channel open-drain output.
b3
Port output structure control register FR2
0
b0
✕
✕
b3
✕ ✕
Timer control register W6
✕
b3: N-channel open-drain output selected [TFR2A]
b0
✕
1
b0: CNTR0 output port set [TW6A]
↓
➃ Set Timer Value and Prescaler Value
Timer 2 and prescaler count times are set. (The formula is shown *A below.)
Timer 2 reload register R2 “29 16”
Timer count value 41 set [T2AB]
Prescaler reload register RPS “03 16”
Prescaler count value 3 set [TPSAB]
↓
➄ Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F
0
Timer 2 interrupt activated condition cleared [SNZT2]
↓
(
)
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the interrupt request flag T2F,
insert the NOP instruction after the SNZT2 instruction.
↓
➅ Start Timer Operation and Prescaler Operation
Timer 2 and prescaler temporarily stopped are restarted.
b3
Timer control register W2
1
b0
1
0
1
b2: Timer 2 operation start [TW2A]
b0
Timer control register PA
1
Prescaler start [TPAA]
↓
⑦ Enable Interrupts
The Timer 2 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V1
Interrupt enable flag INTE
1
1
b0
✕
✕
✕
b3: Timer 2 interrupt occurrence enabled [TV1A]
All interrupts enabled [EI]
↓
Buzzer output
start
..
.
↓
➇ Stop CNTR0 Output
CNTR0 I/O port is set to CNTR0 input port and is set to be high-impedance state.
b3
Register Y
Port D 7 output latch
0
1
b0
1
1
✕ ✕
✕
b3
Timer control register W6
1
Specify bit position of port D [TYA]
Set to input [SD]
b0
0
b0: Set to CNTR0 input port [TW6A]
*A: The prescaler count value and timer 2 count value to make the underflow occur every 125 µs are set as follows.
125 µs ≅ (4.0 MHz) -1 ✕ 3 ✕ (3 +1) ✕ (41 +1)
System clock
Instruction
clock
Presclaer
count value
Timer 2 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.3.5 CNTR0 output setting example
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2.3 Timers
4524 Group
➀ Disable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
b0
✕
Interrupt control register V1
0
✕
✕
b2: Timer 1 interrupt occurrence disabled [TV1A]
b0
[TW1A]
b2: Timer 1 stop
b1, b0: CNTR0 input for Timer 1 count source
↓
➁ Stop Timer Operation
Timer 1 is temporarily stopped.
Timer 1 count source is selected.
b3
Timer control register W1
0
0
1
1
↓
➂ Set Port
CNTR0 I/O port is set to CNTR0 input port.
b3
Register Y
Port D 7 output latch
b0
0
1
1
1
✕
✕
b3
Port output structure control register FR2
0
✕
Specify bit position of port D [TYA]
Set to input [SD]
b0
b3
Timer control register W6
1
✕
b3: N-channel open-drain output selected [TFR2A]
b0
✕
✕
0
b0: Set to CNTR0 input port [TW6A]
↓
➃ Set Timer Values
Timer 1 count time is set.
Timer 1 reload register R1
“6316 ”
Timer count value 99 set [T1AB]
↓
➄ Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F
0
Timer 1 interrupt activated condition cleared [SNZT1]
↓
(
)
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction
according to the interrupt request flag T1F,
insert the NOP instruction after the SNZT1 instruction.
↓
➅ Start Timer Operation
Timer 1 temporarily stopped is restarted.
b3
Timer control register W1
0
b0
1
1
1
b2: Timer 1 operation start [TW1A]
↓
⑦ Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V1
Interrupt enable flag INTE
✕
1
b0
1
✕
✕
b2: Timer 1 interrupt occurrence enabled [TV1A]
All interrupts enabled [EI]
↓
Input signal count started
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.3.6 CNTR0 input setting example
However, specify the pulse width input to CNTR0 pin, CNTR1 pin. Refer to section “3.1 Electrical characteristics”
for the timer external input period condition.
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2.3 Timers
4524 Group
➀ Disable Interrupts
Timer 3 interrupt and external interrupt are temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V1
b0
✕ ✕
b3
Interrupt control register V2
✕
0
b1: External 1 interrupt occurrence disabled [TV1A]
b0
✕ ✕
✕
0
b0: Timer 3 interrupt occurrence disabled [TV2A]
b0
[TI2A]
b3: INT1 pin input disabled
b2: Rising waveform
b1: One-sided edge detected
b0: Timer 3 count start synchronous circuit not selected
↓
➁ Initialize Valid Waveform
INT1 pin is initialized.
b3
Interrupt control register I2
0
1
0
0
↓
➂ Stop Timer 3 and Prescaler Operation
Timer 3 and prescaler are temporarily stopped.
Timer 3 count source is selected.
b3
Timer control register W3
0
b0
0
0
1
b0
Timer control register PA
0
[TW3A]
b3: Timer 3 count auto-stop circuit not selected
b2: Timer 3 stop
b1, b0: Prescaler output (ORCLK) selected for
Timer 3 count source
Prescaler stop [TPAA]
↓
➃ Set Port
INT1 pin is set to input.
b3
Register Y
Port D 9 output latch
1
1
b0
0
0
1
Specify bit position of port D [TYA]
Set to input [SD]
↓
➄ Set Timer Value and Prescaler Value
Timer 3 and prescaler count times are set. (The formula is shown *A below.)
Timer count value 82 set [T3AB]
Timer 3 reload register R3 “52 16”
Prescaler reload register RPS “0F 16”
Prescaler count value 15 set [TPSAB]
↓
➅ Clear Interrupt Request
Timer 3 interrupt activated condition is cleared.
Timer 3 interrupt request flag T3F
0
Timer 3 interrupt activated condition cleared [SNZT3]
↓
(
)
Note when the interrupt request is cleared
When ➅ is executed, considering the skip of the next instruction according to the interrupt request flag T3F,
insert the NOP instruction after the SNZT3 instruction.
↓
⑦ Set INT1 Input
INT1 pin input is set to be valid.
b3
Interrupt control register I2
1
b0
1
0
1
b3: INT1 pin input enabled [TI2A]
b0: Timer 3 count start synchronous circuit selected
↓
➇ Start Timer Operation and Prescaler Operation
Timer 3 and prescaler temporarily stopped are restarted.
Timer 3 count auto-stop circuit is selected.
b3
b0
Timer control register W3
1 1 0 1
[TW3A]
b3: Timer 3 count auto-stop circuit selected
b2: Timer 3 operation start
b0
Timer control register PA
1
Prescaler start [TPAA]
↓
➈ Enable Interrupts
The Timer 3 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V2
Interrupt enable flag INTE
✕ ✕
1
b0
✕
1
b0: Timer 3 interrupt occurrence enabled [TV2A]
All interrupts enabled [EI]
↓
Ready for timer start by external input completed
*A: The prescaler count value and timer 3 count value to make the interrupt occur every 1 ms are set as follows.
1 ms ≅ (4.0 MHz) -1 ✕ 3 ✕ (15 +1) ✕ (82 +1)
System clock
Instruction
clock
Presclaer
count value
Timer 3 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.3.7 Timer start by external input setting example
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APPLICATION
2.3 Timers
4524 Group
➀ Disable Interrupts (Note 1)
Timer 4 and serial I/O interrupts are temporarily disabled.
Interrupt enable flag INTE
0
b3
Interrupt control register V2
0
All interrupts disabled [DI]
b0
✕
✕
✕
b3: Timer 4 and serial I/O interrupts occurrence disabled
[TV2A]
↓
➁ Select Timer 4 Interrupt (Note 1)
Timer 4 is selected for the interrupt source.
b0
Interrupt control register I3
0
Timer 4 interrupt valid [TI3A]
↓
➂ Stop Timer Operation
Timer 4 is temporarily stopped.
Timer 4 count source is selected.
PWM signal “H” interval expansion function control is set.
b3
Timer control register W4
b0
0
1
0
0
[TW4A]
b2: PWM signal “H” interval expansion function valid
b1: Timer 4 stop
b0: X IN selected for Timer 4 count source
↓
➃ Set Port
PWM signal output from CNTR1 pin is set.
b3
Timer control register W6
Port C output latch
✕
0
b0
✕
0
✕
0
b3
Timer control register W3
✕
✕
b1: CNTR1 output auto-control circuit not selected [TW6A]
[RCP]
b0
1
b1, b0: Timer 3 count source selected (Note 2) [TW3A]
↓
➄ Set Timer Value
Timer 4 count time is set.
Timer 4 reload register R4L
Timer 4 reload register R4H
“0316 ”
“0216 ”
Timer count value 3 set [T4AB]
Timer count value 2 set [T4HAB]
↓
➅ Start Timer Operation
Timer 4 temporarily stopped is restarted.
CNTR1 output control is set to be valid.
Timer control register W4
b3
1
b0
1
1
0
[TW4A]
b3: CNTR1 output valid
b1: Timer 4 operation start
↓
➆ Set Interrupts (Note 1)
Interrupts except Timer 4 interrupt is enabled.
[EI]
↓
PWM output started
Notes 1: ➀ and ➆ are not required when serial I/O interrupt is used.
2: Set the count sources except the CNTR1 input as the timer 3 count source.
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.3.8 PWM output control setting example
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2.3 Timers
4524 Group
➀ Disable Interrupts
Timer 5 interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V2
✕
b0
✕
✕
0
b1: Timer 5 interrupt occurrence disabled [TV2A]
↓
➁ Stop Timer Value
Timer 5 interrupt is temporarily disabled.
Timer 5 count time is set.
(The formula is shown *A below.)
Timer control register W5
b3
✕
b0
0
0
0
[TW5A]
b2: Timer 5 stop
Timer 5 count value initialized
b1,b0: Timer count value 2 13 set
↓
➂ Clear Interrupt Request
Timer 5 interrupt activated condition is cleared.
Timer 5 interrupt request flag T5F
0
Timer 5 interrupt activated condition cleared [SNZT5]
↓
(
)
Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction
according to the interrupt request flag T5F,
insert the NOP instruction after the SNZT5 instruction.
↓
➃ Start Timer Operation
Timer 5 temporarily stopped is restarted.
b3
Timer control register W5
✕
b0
1
0
0
b2: Timer 5 operation start [TW5A]
↓
➄ Enable Interrupts
The Timer 5 interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V2
Interrupt enable flag INTE
✕
1
b0
✕
✕
1
b1: Timer 5 interrupt occurrence enabled [TV2A]
All interrupts enabled [EI]
↓
Constant period interrupt execution started
*A: The timer 5 count value to make the interrupt occur every 250 ms is set as follows.
250 ms ≅ (32.768 kHz) -1 ✕ 2 13
Sub-clock
Timer 5 count value
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.3.9 Constant period counter by timer 5 setting example
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APPLICATION
2.3 Timers
4524 Group
Main Routine (every 20 ms)
➀ Reset Flag WDF1
Watchdog timer flag WDF1 is reset.
0
Watchdog timer flag WDF1 cleared. [WRST]
↓
(
)
Note when the watchdog timer flag is cleared
When ➀ is executed, considering the skip of the next instruction according to the watchdog timer flag WDF1,
insert the NOP instruction after the WRST instruction.
↓
Main Routine Execution
↓
Repeat
In the interrupt service routine, do not clear watchdog timer flag WDF1.
Interrupt may be executed even if program run-away occurs.
When going to RAM back-up mode
:
:
WRST
; WDF flag cleared
NOP
DI
; Interrupt disabled
EPOF
; POF instruction enabled
POF
↓
Oscillation stop (RAM back-up mode)
In the RAM back-up mode, WEF, WDF1 and WDF2 flags are initialized.
However, when WDF2 flag is set to “1”, at the same time, system goes into RAM back-up mode, microcomputer may
be reset.
When watchdog timer and RAM back-up mode are used, execute the WRST instruction to initialize WDF1 flag before
system goes into the RAM back-up mode.
Fig. 2.3.10 Watchdog timer setting example
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APPLICATION
4524 Group
2.3 Timers
2.3.4 Notes on use
(1) Prescaler
Stop counting and then execute the TABPS instruction to read from prescaler data.
Stop counting and then execute the TPSAB instruction to set prescaler data.
(2) Count source
Stop timer 1, 2, 3, 4 or LC counting to change its count source.
(3) Reading the count values
Stop timer 1, 2, 3 or 4 counting and then execute the TAB1, TAB2, TAB3 or TAB4 instruction to
read its data.
(4) Writing to the timer
Stop timer 1, 2, 3, 4 or LC counting and then execute the T1AB, T2AB, T3AB, T4AB or TLCA
instruction to write its data.
(5) Writing to reload register R1, reload register R3 and reload register R4H
When writing data to reload register R1 while timer 1 is operating respectively, avoid a timing when
timer 1 underflows.
When writing data to reload register R3 while timer 3 is operating respectively, avoid a timing when
timer 3 underflows.
When writing data to reload register R4H while timer 4 is operating respectively, avoid a timing when
timer 4 underflows.
(6) Timer 4
• Avoid a timing when timer 4 underflows to stop timer 4.
• When “H” interval extension function of the PWM signal is set to be “valid”, set “01 16 ” or more to
reload register R4H.
(7) Timer 5
Stop timer 5 counting to change its count source.
(8) Timer input/output pin
• Set the port C output latch to “0” to output the PWM signal from C/CNTR1 pin.
(9) Watchdog timer
• The watchdog timer function is valid after system is released from reset. When not using the
watchdog timer function, stop the watchdog timer function and execute the DWDT instruction, the
WRST instruction continuously, and clear the WEF flag to “0”.
• The watchdog timer function is valid after system is returned from the power down state. When not
using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction
and the WRST instruction continuously every system is returned from the power down state.
• When the watchdog timer function and power down function are used at the same time, initialize
the flag WDF1 with the WRST instruction before system enters into the power down state.
(10) Pulse width input to CNTR0 pin, CNTR1 pin
Refer to section “3.1 Electrical characteristics” for rating value of pulse width input to CNTR0 pin,
CNTR1 pin.
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2.4 A/D converter
4524 Group
2.4 A/D converter
The 4524 Group has an 8-channel A/D converter with the 10-bit successive comparison method.
This A/D converter can also be used as a comparator to compare analog voltages input from the analog
input pin with preset values.
This section describes the related registers, application examples using the A/D converter and notes.
Figure 2.4.1 shows the A/D converter block diagram.
Register B (4)
Register A (4)
4
4
IAP2
(P20–P23)
IAP3
(P30–P33)
OP2A
(P20–P23)
OP3A
(P30–P33)
TAQ1
TQ1A
4
TAQ2
TQ2A
Q23 Q22 Q21 Q20
Q13 Q12 Q11 Q10
4
4
TAQ3
TQ3A
Q33 Q32 Q31 Q30
4
4
2
8
TALA
TABAD
8
TADAB
Instruction clock
1/6
3
Q13
P20/AIN0
P21/AIN1
P22/AIN2
P23/AIN3
P30/AIN4
P31/AIN5
P32/AIN6
P33/AIN7
8-channel multi-plexed analog switch
0
A/D control circuit
1
ADF
(1)
A/D
interrupt
1
Comparator
Successive comparison
register (AD) (10)
0
Q13
Q13
0
8
10
10
DAC
operation
signal
0
1
1
1
Q13
8
DA converter
8
8
VDD
(Note 1)
VSS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1).
The value of the comparator register is retained even when the mode is switched to the A/D conversion
mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 2.4.1 A/D converter structure
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APPLICATION
2.4 A/D converter
4524 Group
2.4.1 Related registers
(1) Interrupt control register V2
Table 2.4.1 shows the interrupt control register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.4.1 Interrupt control register V2
Interrupt control register V2
V2 3
Timer 4, serial I/O interrupt
enable bit (Note 2)
V2 2
A/D interrupt enable bit
V2 1
Timer 5 interrupt enable bit
V2 0
Timer 3 interrupt enable bit
at reset : 00002
0
at power down : 0000 2
R/W
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 3)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 3)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid) (Note 3)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid) (Note 3)
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source
selection bit (I30).
3: These instructions are equivalent to the NOP instruction.
4: When setting the A/D converter, V2 3, V2 1 and V2 0 are not used.
(2) A/D control register Q1
Table 2.4.2 shows the A/D control register Q1.
Set the contents of this register through register A with the TQ1A instruction.
In addition, the TAQ1 instruction can be used to transfer the contents of register Q1 to register A.
Table 2.4.2 A/D control register Q1
A/D control register Q1
Q13
A/D operation mode control bit
Q12
Q11
Analog input pin selection bits
at reset : 0000 2
0
at power down : state retained
R/W
A/D conversion mode
1
Comparator mode
Q12 Q11 Q10
0
0
0 AIN0
0
0
1
AIN1
0
1
0
0
1
1
AIN2
AIN3
1
0
0
AIN4
1
0
1
AIN5
Analog input pins
1
1
0 AIN6
1
1
1 AIN7
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: In order to select A IN7–A IN0, set register Q1 after setting regsiter Q2, Q3.
Q10
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2.4 A/D converter
4524 Group
(3) A/D control register Q2
Table 2.4.3 shows the A/D control register Q2.
Set the contents of this register through register A with the TQ2A instruction.
The contents of register Q2 is transferred to register A with the TAQ2 instruction.
Table 2.4.3 A/D control register Q2
AD control register Q2
Q2 3
P23/AIN3 pin function selection bit
Q2 2
P22/AIN2 pin function selection bit
Q2 1
P21/AIN1 pin function selection bit
Q2 0
P20/AIN0 pin function selection bit
at reset : 0000 2
0
P2 3
1
AIN3
0
1
P2 2
0
1
P2 1
AIN1
0
P2 0
1
AIN0
at power down : state retained
R/W
AIN2
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: In order to select A IN3–A IN0, set register Q1 after setting regsiter Q2.
(4) A/D control register Q3
Table 2.4.4 shows the A/D control register Q3.
Set the contents of this register through register A with the TQ3A instruction.
The contents of register Q3 is transferred to register A with the TAQ3 instruction.
Table 2.4.4 A/D control register Q3
AD control register Q3
Q3 3
at reset : 0000 2
P33/AIN7 pin function selection bit
Q3 2
P32/AIN6 pin function selection bit
Q3 1
P31/AIN5 pin function selection bit
Q3 0
P30/AIN4 pin function selection bit
0
P3 3
1
AIN7
0
P3 2
1
AIN6
0
1
P3 1
0
AIN5
P3 0
1
AIN4
at power down : state retained
R/W
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: In order to select A IN7–A IN4, set register Q1 after setting regsiter Q3.
2.4.2 A/D converter application examples
(1) A/D conversion mode
Outline: Analog input signal from a sensor can be converted into digital values.
Specifications: Analog voltage values from a sensor is converted into digital values by using a 10bit successive comparison method. Use the AIN0 pin for this analog input.
Figure 2.4.2 shows the A/D conversion mode setting example.
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APPLICATION
2.4 A/D converter
4524 Group
➀ Disable Interrupts
A/D interrupt is temporarily disabled.
Interrupt enable flag INTE
0
All interrupts disabled [DI]
b3
Interrupt control register V2
✕
b0
0
✕
✕
b2: A/D interrupt occurrence disabled [TV2A]
↓
➁ Set A/D Converter
A/D conversion mode is selected to A/D operation mode.
Analog input pin A IN0 is selected.
b3
A/D control register Q2
✕
b0
✕
✕
b3
A/D control register Q1
0
1
b0: A IN0 pin function selected [TQ2A]
b0
0
0
0
A/D conversion selected, A IN0 selected [TQ1A]
↓
➂ Clear Interrupt Request
A/D interrupt activated condition is cleared.
A/D conversion completion flag ADF
0
A/D interrupt activated condition cleared [SNZAD]
↓
(
)
Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction
according to the flag ADF, insert the NOP instruction after the SNZAD instruction.
↓
↓
↓
When interrupt is not used
➃ Set Interrupt
Interrupts except A/D conversion is enabled. [EI]
When interrupt is used
➃ Set Interrupt
A/D interrupt temporarily disabled is enabled.
b3
b0
Interrupt control register V2
✕ 1 ✕ ✕
b2: A/D interrupt occurrence enabled [TV2A]
Interrupt enable flag INTE
All interrupt enabled [EI]
↓
1
↓
↓
➄ Start A/D Conversion
A/D conversion operation is started [ADST]
↓
↓
↓
When interrupt is not used
➅ Check A/D Interrupt Request
A/D conversion completion flag is checked [SNZAD]
↓
➆ Execute A/D Conversion
High-order 8 bits of register AD
Low-order 2 bits of register AD
When interrupt is used
➅ A/D Interrupt Occur
↓
→
→
↓
Register A and register B [TABAD]
High-order 2 bits of register A [TALA]
“0” is set to low-order 2 bits of register A
↓
When A/D conversion is executed by the same channel, repeat ➄ to ➆.
When A/D conversion is executed by another channel, repeat ➀ to ➆.
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.4.2 A/D conversion mode setting example
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APPLICATION
2.4 A/D converter
4524 Group
2.4.3 Notes on use
(1) Note when the A/D conversion starts again
When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous
input data is invalidated and the A/D conversion starts again.
(2) A/D converter-1
Each analog input pin is equipped with a capacitor which is used to compare the analog voltage.
Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce
the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins.
Figure 2.4.3 shows the analog input external circuit example-1.
When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit
in order to keep the voltage within the rated range as shown the Figure 2.4.4. In addition, test the
application products sufficiently.
Sensor
About 1kΩ
AIN
Sensor
AIN
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 2.4.4 Analog input external circuit example-2
Fig. 2.4.3 Analog input external circuit example-1
(3) Notes for the use of A/D conversion 2
Do not change the operating mode of the A/D converter by bit 3 of register Q1 during A/D conversion
(A/D conversion mode and comparator mode).
(4) Notes for the use of A/D conversion 3
When the operating mode of the A/D converter is changed from the comparator mode to the A/D
conversion mode with bit 3 of register Q1 in a program, be careful about the following notes.
• Clear bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the
comparator mode to the A/D conversion mode (refer to Figure 2.4.5➀).
• The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D
converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a
value to bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag to “0”.
•
•
•
Clear bit 2 of register V2 to “0”.......➀
↓
Change of the operating mode of the A/D converter
from the comparator mode to the A/D conversion mode
↓
Clear the ADF flag to “0” with the SNZAD instruction
↓
Execute the NOP instruction for the case when a skip is
performed with the SNZAD instruction
•
•
•
Fig. 2.4.5 A/D converter operating mode program example
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APPLICATION
2.4 A/D converter
4524 Group
(5) A/D converter is used at the comparator mode
The analog input voltage is higher than the comparison voltage as a result of comparison, the
contents of ADF flag retains “0,” not set to “1.”
In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled.
Accordingly, consider the time until the comparator operation is completed, and examine the state
of ADF flag by software. The comparator operation is completed after 8 machine cycles.
(6) Analog input pins
When P2 0/AIN0–P23/AIN3, P30/AIN4–P33/AIN7 are set to pins for analog input, they cannot be used as
I/O ports P2 and P3.
(7) TALA instruction
When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is “0.”
(8) Recommended operating conditions when using A/D converter
The recommended operating conditions of supply voltage and system clock frequency when using A/
D converter are different from those when not using A/D converter.
Table 2.4.5 shows the recommended operating conditions when using A/D converter.
Table 2.4.5 Recommended operating conditions (when using A/D converter)
Parameter
Condition
System clock frequency V DD = 4.0 to 5.5 V (through mode)
(at ceramic resonance) V DD = 2.7 to 5.5 V (through mode)
(Note 2)
V DD = 2.7 to 5.5 V (Frequency/2 mode)
0.1
3.0
0.1
0.1
1.5
5.5 V (through mode)
0.1
4.4
5.5 V (Frequency/2 mode)
0.1
5.5 V (Frequency/4 mode)
5.5 V (Frequency/8 mode)
0.1
2.2
1.1
0.1
0.5
5.5 V (through mode)
0.1
0.1
4.8
0.1
2.4
0.1
1.2
0.6
V DD = 2.7 to 5.5 V (Frequency/4 mode)
V DD = 2.7 to 5.5 V (Frequency/8 mode)
System clock frequency V DD = 2.7 to
(at RC oscillation)
V DD = 2.7 to
(Note 2)
V DD = 2.7 to
V DD = 2.7 to
System clock frequency V DD = 4.0 to
Limits
Unit
Min. Typ. Max.
0.1
6.0 MHz
0.1
4.4
( c e r a m i c r e s o n a n c e V DD = 2.7 to 5.5 V (through mode)
selected, at external V DD = 2.7 to 5.5 V (Frequency/2 mode)
clock input)
V DD = 2.7 to 5.5 V (Frequency/4 mode)
0.7
MHz
MHz
3.2
0.1
V DD = 2.7 to 5.5 V (Frequency/8 mode)
Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set
the constants within the range of the frequency limits.
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APPLICATION
2.5 Serial I/O
4524 Group
2.5 Serial I/O
The 4524 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data.
This section describes serial I/O functions, related registers, application examples using serial I/O and
notes.
2.5.1 Carrier functions
Serial I/O consists of the serial I/O register SI, serial I/O control register J1, serial I/O transmit/receive
completion flag SIOF and serial I/O counter.
A clock-synchronous serial I/O uses the shift clock generated by the clock control circuit as a synchronous
clock. Accordingly, the data transmit and receive operations are synchronized with this shift clock.
In transmit operation, data is transmitted bit by bit from the SOUT pin synchronously with the falling edges
of the shift clock.
In receive operation, data is received bit by bit from the SIN pin synchronously with the rising edges of the
shift clock.
Note: 4524 Group only supports LSB-first transmit and receive.
■
Shift clock
When using the internal clock of 4524 Group as a synchronous clock, eight shift clock pulses are
output from the S CK pin when a transfer operation is started. Also, when using some external clock
as a synchronous clock, the clock that is input from the S CK pin is used as the shift clock.
■
Data transfer rate (baudrate)
When using the internal clock, the data transfer rate can be determined by selecting the instruction
clock divided by 2, 4 or 8.
When using an external clock, the clock frequency input to the SCK pin determines the data transfer
rate.
Figure 2.5.1 shows the serial I/O block diagram.
1/8
1/4
1/2
INSTCK
J13J12
00
01
10
Synchronous
circuit
Serial I/O counter (3)
SIOF
Serial I/O
interrupt
11
D6/SCK
D5/SOUT
D4/SIN
SCK
Q
S
SST
instruction
R
Internal reset signal
SOUT
SIN
MSB Serial I/O register (8) LSB
TABSI
TSIAB
Register B (4)
TABSI
Register A (4)
J11 J10
Fig. 2.5.1 Serial I/O block diagram
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2.5 Serial I/O
4524 Group
2.5.2 Related registers
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to
register SI through registers A and B with the TSIAB instruction.
Also, the low-order 4 bits of register SI is transferred to register A, and the high-order 4 bits of
register SI is transferred to register B with the TABSI instruction.
(2) Serial I/O transmit/receive completion flag (SIOF)
Serial I/O transmit/receive completion flag (SIOF) is set to “1” when serial data transmit or receive
operation completes. The state of SIOF flag can be examined with the skip instruction (SNZSI).
(3) Interrupt control register V2
Table 2.5.1 shows the interrupt control register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.5.1 Interrupt control register V2
Interrupt control register V2
V23
Timer 4, serial I/O interrupt
enable bit (Note 2)
V22
A/D interrupt enable bit
V21
Timer 5 interrupt enable bit
V20
Timer 3 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
R/W
at power down : 0000 2
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 3)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 3)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid) (Note 3)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid) (Note 3)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source
selection bit (I3 0).
3: These instructions are equivalent to the NOP instruction.
4: When setting the Serial I/O, V2 3, V2 1 and V2 0 are not used.
(4) Interrupt control register I3
Table 2.5.2 shows the interrupt control register I3.
Set the contents of this register through register A with the TI3A instruction.
In addition, the TAI3 instruction can be used to transfer the contents of register I3 to register A.
Table 2.5.2 Interrupt control register I3
Interrupt control register I3
I30
Timer 4, serial I/O interrupt
source selection bit
at reset : 0 2
0
at power down : state retained
R/W
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
1
Note: “R” represents read enabled, and “W” represents write enabled.
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2.5 Serial I/O
4524 Group
(5) Serial I/O mode register J1
Table 2.5.3 shows the serial I/O mode register J1.
Set the contents of this register through register A with the TJ1A instruction.
In addition, the TAJ1 instruction can be used to transfer the contents of register J1 to register A.
Table 2.5.3 Serial I/O mode register J1
Serial I/O control register J1
J13
J12
J1 1
J1 0
at reset : 00002
J13
0
Serial I/O synchronous clock
0
selection bits
1
1
J11
Serial I/O port function selection 0
0
bits
1
1
J1 2
0
1
0
1
J1 0
0
1
0
1
at power down : state retained
R/W
Synchronous clock
Instruction clock (INSTCK) divided by 8
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 2
External clock (S CK input)
Port function
D 6, D 5, D4 selected/S CK, S OUT, S IN not selected
SCK, S OUT, D 4 selected/D 6, D5, S IN not selected
SCK, D5, S IN selected/D 6, S OUT, D 4 not selected
SCK, S OUT, S IN selected/D 6, D 5, D 4 not selected
Note: “R” represents read enabled, and “W” represents write enabled.
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2.5 Serial I/O
4524 Group
2.5.3 Operation description
Figure 2.5.2 shows the serial I/O connection example, Figure 2.5.3 shows the serial I/O register state, and
Figure 2.5.4 shows the serial I/O transfer timing.
Master (internal clock selected)
Slave (external clock selected)
4524
4524
Control signal
D3
D3
SCK
SCK
SOUT
SIN
SIN
SOUT
Note: The control signal is used to inform the master by the pin level
that the slave is in a ready state to receive.
The 4524 Group does not have a control pin exclusively
used for serial I/O.
Accordingly, if a control signal is required, use the normal input/output ports.
Fig. 2.5.2 Serial I/O connection example
Slave (S7–S0: transfer data)
Master (M7–M0 : transfer data)
SIN pin
Serial I/O register (SI)
M7 M6 M5 M4 M3 M2 M1 M0
SOUT pin
SOUT pin
SIN pin
Transfer data set
Serial I/O register (SI)
S7 S6 S5 S4 S3 S2 S1 S0
S7 S6 S5 S4 S3 S2 S1 S0
Transfer start
M7 M6 M5 M4 M3 M2 M1
Falling of clock
S0 M7 M6 M5 M4 M3 M2 M1
Rising of clock
S0 M7 M6 M5 M4 M3 M2
Falling of clock
*
*
S7 S6 S5 S4 S3 S2 S1 S0
Transfer complete
*
S7 S6 S5 S4 S3 S2 S1
M0 S7 S6 S5 S4 S3 S2 S1
*
M0 S7 S6 S5 S4 S3 S2
M7 M6 M5 M4 M3 M2 M1 M0
Fig. 2.5.3 Serial I/O register state when transfer
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APPLICATION
2.5 Serial I/O
4524 Group
Master
SOUT
M7’
SIN
S7’
S0
M3
M2
M1
M0
S1
S2
M4
S3
M5
S4
M6
S5
M7
S6
S7
SST instruction
SCK
Slave
SST instruction
Control signal
SOUT
SIN
S0
S7’
M7’
S2
S1
M0
M1
S3
M2
S4
M3
S5
M4
S6
M5
S7
M6
M7
M0–M7: Contents of master serial I/O register
S0–S7: Contents of slave serial I/O register
Rising of SCK: Serial input
Falling of SCK: Serial output
M7’, S7’: Contents of previous master, slave MSB
Fig. 2.5.4 Serial I/O transfer timing
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APPLICATION
4524 Group
2.5 Serial I/O
The full duplex communication of master and slave is described using the connection example shown in
Figure 2.5.2.
(1) Transmit/receive operation of master
➀ Set the transmit data to the serial I/O register SI with the TSIAB instruction.
When the TSIAB instruction is executed, the contents of register A are transferred to the low-order
4 bits of register SI and the contents of register B are transferred to the high-order 4 bits of register
SI.
➁ Check whether the microcomputer on the slave side is ready to transmit/receive or not.
In the connection example in Figure 2.5.2, check that the input level of control signal is “L” level.
➂ Start serial transmit/receive with the SST instruction.
When the SST instruction is executed, the serial I/O transmit/receive completion flag (SIOF) is
cleared to “0.”
➃ The transmit data is output from the S OUT pin synchronously with the falling edges of the shift
clock.
➄ The transmit data is output bit by bit beginning with the LSB of register SI. Each time one bit is
output, the contents of register SI is shifted one bit position toward the LSB.
➅ Also, the receive data is input from the S IN pin synchronously with the rising edges of the shift
clock.
➆ The receive data is input bit by bit to the MSB of register SI.
➇ A serial I/O interrupt request occurs when the transmit/receive data is completed, and the SIOF
flag is set to “1.”
➈ The receive data is taken in within the serial I/O interrupt service routine; or the data is taken in
after examining the completion of the transmit/receive operation with the SNZSI instruction without
using an interrupt.
Also, the SIOF flag is cleared to “0” when an interrupt occurs or the SNZSI instruction is executed.
Notes 1: Repeat steps ➀ through ➈ to transmit/receive multiple data in succession.
2: For the program on the master side, start to transmit the next data at the next timing
(control signal turns “L”). Do not start to transmit the next data during the previous data
transfer (control signal = “L”).
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4524 Group
2.5 Serial I/O
(2) Transmit/receive operation of slave
➀ Set the transmit data into the serial I/O register SI with the TSIAB instruction.
When the TSIAB instruction is executed, the contents of register A are transferred to the loworder bits of register SI and the contents of register B are transferred to the high-order bits of
register SI. At this time, the SCK pin must be at the “H” level.
➁ Start serial transmit/receive with the SST instruction. However, in Figure 2.5.2 where an external
clock is selected, transmit/receive is not started until the clock is input. When the SST instruction
is executed, the serial I/O transmit/receive completion flag (SIOF) is cleared to “0.”
➂ The microcomputer on the master side is informed that the receiving side is ready to receive.
In the connection example in Figure 2.5.2, the control signal “L” level is output.
➃ The transmit data is output from the S OUT pin synchronously with the falling edges of the shift
clock.
➄ The transmit data is output bit by bit beginning with the LSB of register SI. Each time one bit is
output, the contents of register SI are shifted to one bit position toward the LSB.
➅ Also, the receive data is input from the SIN pin synchronously with the rising edges of the shift
clock.
➆ The receive data is input bit by bit to the MSB of register SI.
➇ A serial I/O interrupt request occurs when the transmit/receive is completed, and the SIOF flag
is set to “1.”
➈ Read the receive data within the serial I/O interrupt service routine; or read the data after examining
the completion of the transmit/receive operation with the SNZSI instruction without using an interrupt.
Also, the SIOF flag is cleared to “0” when an interrupt occurs or the SNZSI instruction is executed.
➉ Set the control signal pin level to “H” after the receive operation is completed.
Note: Repeat steps ➀ through ➉ to transmit/receive multiple data in succession.
2.5.4 Serial I/O application example
(1) Serial I/O
Outline: The 4524 Group can communicate with peripheral ICs.
Specifications: Figure 2.5.2 Serial I/O connection example.
Figure 2.5.5 shows the setting example when a serial I/O interrupt of master side is not used, and
Figure 2.5.6 shows the slave serial I/O setting example.
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2.5 Serial I/O
4524 Group
➀ Disable Interrupts (Note)
Timer 4 and serial I/O interrupt are temporarily disabled.
Interrupt enable flag INTE
0
b3
Interrupt control register V2
0
All interrupts disabled [DI]
b0
✕
✕
✕
b3: Timer 4 and serial I/O interrupts occurrence disabled [TV2A]
↓
➁ Select Serial I/O Interrupt (Note)
Serial I/O is selected for the interrupt source.
b0
Interrupt control register I3
1
Serial I/O interrupt valid [TI3A]
↓
➂ Set Port
Port for control signal is set to input.
b3
Register Y
Port D 3 output latch
0
1
b0
0
1
✕
✕
b3
Port output structure control register FR1
0
1
Specify bit position of port D [TYA]
Set to input [SD]
b0
✕
b3: Port D 3 N-channel open-drain output selected
↓
➃ Set Serial I/O
b3
Serial I/O control regsiter JI
0
b0
1
1
1
[TJ1A]
b3, b2: Instruction clock divided by 4 is selected for
synchronous clock
b1, b0: Serial I/O ports S CK , S OUT , S IN selected
↓
➄ Clear Interrupt Request
Serial I/O interrupt activated condition is cleared.
Serial I/O transmit/receive completion flag SIOF 0
Serial I/O interrupt activated condition cleared [SNZSI]
↓
(
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the flag SIOF,
insert the NOP instruction after the SNZSI instruction.
)
↓
➅ Set Interrupts (Note)
Interrupts except serial I/O interrupt is enabled.
[EI]
↓
⑦ Set Transmit Data
Transmit data is set to serial I/O register.
Serial I/O register SI ✕✕16
[TSIAB]
↓
➇ Check Start Condition of Serial I/O Operation
Whether the transmit/receive of the slave side can be performed (pin level of control signal = “L”) or not is checked.
b3
Register Y
Port D 3 output latch
Port D 3 input level check
0
1
b0
0
1
1
Specify bit position of port D [TYA]
Set to input [SD]
[SZD]
↓
➈ Start Serial I/O Operation
If the transmit/receive of the slave side can be performed, serial transfer is started. [SST]
↓
➉ Check Serial I/O Interrupt Request
SIOF flag is checked. [SNZSI]
↓
11
Receive Data Processing
Data processing received by serial transfer is executed.
Register SI → register A, register B [TABSI]
↓
When serial communication is executed, repeat ⑦ to
Note: ➀, ➁ and ➅ are not required when timer 4 interrupt is used.
“✕”: it can be “0” or “1.”
“[ ]”: instruction
11
.
Fig. 2.5.5 Setting example when a serial I/O of master side is not used
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APPLICATION
2.5 Serial I/O
4524 Group
➀ Disable Interrupts
Timer 4 and serial I/O interrupt are temporarily disabled.
Interrupt enable flag INTE
0
b3
Interrupt control register V2
0
All interrupts disabled [DI]
b0
✕
✕
✕
b3: Timer 4 and serial I/O interrupts occurrence disabled [TV2A]
↓
➁ Select Serial I/O Interrupt
Serial I/O is selected for the interrupt source.
b0
Interrupt control register I3
1
Serial I/O interrupt valid [TI3A]
↓
➂ Set Port
Port for control signal is set to “H” output.
b3
Register Y
Port D 3 output latch
0
1
b0
0
1
✕
✕
1
b3
Port output structure control register FR1
1
Specify bit position of port D [TYA]
Set to “H” output [SD]
b0
✕
b3: Port D 3 CMOS output selected
b0
[TJ1A]
b3, b2: External clock is selected for synchronous clock
b1, b0: Serial I/O ports S CK , S OUT , S IN selected
↓
➃ Set Serial I/O
b3
Serial I/O control regsiter JI
1
1
1
1
↓
➄ Clear Interrupt Request
Serial I/O interrupt activated condition is cleared.
Serial I/O transmit/receive completion flag SIOF 0
Serial I/O interrupt activated condition cleared [SNZSI]
↓
(
Note when the interrupt request is cleared
When ➄ is executed, considering the skip of the next instruction according to the flag SIOF,
insert the NOP instruction after the SNZSI instruction.
)
↓
➅ Set Interrupts
The Serial I/O interrupt which is temporarily disabled is enabled.
b3
Interrupt control register V2
Interrupt enable flag INTE
1
1
b0
✕
✕
✕
b3: Serial I/O interrupt occurrence enabled [TV2A]
All interrupts enabled [EI]
↓
⑦ Set Transmit Data
Transmit data is set to serial I/O register.
Serial I/O register SI ✕✕ 16
[TSIAB]
↓
➇ Set Start of Serial I/O Operation
Serial I/O operation enabled state (serial transfer started, control signal “L” level output) is set.
Serial transfer start
[SST]
b3
Register Y
Port D 3 output latch
0
0
b0
0
1
1
Specify bit position of port D [TYA]
Set to “L” output [RD]
:
↓
Serial transmit/receive by clock of master side
:
↓
➈ Receive Data Processing by Serial I/O interrupt
Serial I/O operation disabled state (control signal “H” level output) is set and received data processing is performed..
b3
Register Y
Port D 3 output latch
Register SI
0
1
→
b0
0
1
1
Specify bit position of port D [TYA]
Set to “H” output [SD]
register A, register B [TABSI]
↓
When serial communication is executed, repeat ⑦ to ➈.
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.5.6 Setting example when a serial I/O interrupt of slave side is used
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APPLICATION
4524 Group
2.5 Serial I/O
2.5.5 Notes on use
(1) Note when an external clock is used as a synchronous clock:
• An external clock is selected as the synchronous clock, the clock is not controlled internally.
• Serial transmit/receive is continued as long as an external clock is input. If an external clock is input
9 times or more and serial transmit/receive is continued, the receive data is transferred directly as
transmit data, so that be sure to control the clock externally.
Note also that the SIOF flag is set to “1” when a clock is counted 8 times.
• Be sure to set the initial input level on the external clock pin to “H” level.
• Refer to section “3.1 Electrical characteristics” when using serial I/O with an external clock.
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APPLICATION
2.6 LCD function
4524 Group
2.6 LCD function
The 4524 Group has an LCD (Liquid Crystal Display) controller/driver.
4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using
these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display.
This section describes the LCD operation description, related registers, application examples using the LCD
and notes.
2.6.1 Operation description
(1) LCD duty and bias control
Table 2.6.1 shows the duty and maximum number of displayed pixels. Use bits 0 and 1 of LCD
control register (L1) to select the proper display method for the LCD panel being used.
The LCD power input pins (V LC1–V LC3) are also used as pins SEG 0–SEG2. The internal power (V DD)
is used for the LCD power.
Table 2.6.1 Duty and maximum number of
displayed pixels
Maximum number
Used COM pins
of displayed pixels
40 segments
COM0, COM 1 (Note)
1/2 1/2
COM 0–COM 2 (Note)
60 segments
1/3 1/3
COM 0–COM3
1/4 1/3
80 segments
Note: Leave unused COM pins open.
Duty Bias
W62
T54
ORCLK
0
(Note)
W63
0
1
➁
Timer LC (4)
➂
1/2
1
LCD
clock
➀
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
Note: Count source is stopped by setting “0” to this bit.
Fig. 2.6.1 LCD clock control circuit structure
(2) LCD drive timing
The LCD clock frequency (F) and frame frequency generating the LCD drive timing are shown below.
Figure 2.6.1 shows the structure of the LCD clock circuit.
● When the prescaler output (ORCLK) is used for the timer LC count source (W6 2 = “1”)
F = ORCLK ✕
1
✕
LC + 1
➀
1
2
➁
➂
● When bit 4 (T5 4) of timer 5 is used for the timer LC count source (W6 2 = “0”)
F = T5 4 ✕
➀
1
✕
LC + 1
➁
1
2
➂
The frame frequency for each display method can be obtained by the following formula.
Frame frequency =
F
n
(Hz)
Frame period = n
F
(s)
[F: Frame frequency, 1/n: Duty]
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APPLICATION
2.6 LCD function
4524 Group
(3) LCD display method
The 4524 Group has the LCD RAM area for the LCD display.
When “1” is written to a bit in the LCD RAM data, the display pixel which correspond to the bit
automatically turns on.
Figure 2.6.2 shows the LCD RAM map.
Z
X
1
Bits
Y
8
9
10
11
12
13
14
15
COM
3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM3
2
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM2
Note: The area marked “
12
1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM1
13
0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM0
3
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM3
2
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM2
1
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM1
0
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM0
3
SEG16
SEG17
SEG18
SEG19
14
2
1
SEG16 SEG16
SEG17 SEG17
SEG18 SEG18
SEG19 SEG19
0
SEG16
SEG17
SEG18
SEG19
COM3 COM2 COM1 COM0
” is not the LCD display RAM.
Fig. 2.6.2 LCD RAM map
2.6.2 Related registers
(1) LCD control register L1
Table 2.6.2 shows the LCD control register L1.
Set the contents of this register through register A with the TL1A instruction. The TAL1 instruction
can be used to transfer the contents of register L1 to register A.
Table 2.6.2 LCD control register L1
LCD control register L1
L13
Internal dividing resistor for LCD
power supply selection bit (Note 2)
L12
LCD on/off bit
L11
L10
at reset : 0000 2
0
2r ✕ 3, 2r ✕ 2
1
r ✕ 3, r ✕ 2
Off
0
On
1
L11 L10
0
0
LCD duty and bias selection bits 0
1
at power down : state retained
Duty
R/W
Bias
Not available
1
1/2
1/2
0
1/3
1/3
1
1
1/4
1/3
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
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2.6 LCD function
4524 Group
(2) LCD control register L2
Table 2.6.3 shows the LCD control register L2.
Set the contents of this register through register A with the TL2A instruction.
Table 2.6.3 LCD control register L2
LCD control register L2
L23
L22
L21
at reset : 1111 2
VLC3/SEG 0 function switch bit
0
SEG0
(Note 2)
1
VLC2/SEG 1 function switch bit
0
1
VLC3
SEG1
(Note 3)
VLC1/SEG 2 function switch bit
(Note 3)
at power down : state retained
W
VLC2
0
SEG2
1
VLC1
Internal dividing resistor valid
0
Internal dividing resistor for LCD
Internal dividing resistor invalid
power supply control bit
1
Notes 1: “W” represents write enabled.
2: V LC3 is connected to V DD internally when SEG 0 pin is selected.
3: Use internal dividing resistor when SEG 1 and SEG 2 pins are selected.
L20
(3) Timer control register W6
Table 2.6.4 shows the timer control register W6.
Set the contents of this register through register A with the TW6A instruction.
In addition, the TAW6 instruction can be used to transfer the contents of register W6 to register A.
Table 2.6.4 Timer control register W6
Timer control register W6
at reset : 00002
at power down : state retained
0
Stop (state retained)
1
Operating
Timer LC count source selection
bit
0
Bit 4 (T5 4) of timer 5
1
W6 1
CNTR1 output auto-control circuit
selection bit
0
1
Prescaler output (ORCLK)
CNTR1 output auto-control circuit not selected
W6 0
D7/CNTR0 pin function selection
bit (Note 2)
0
D7(I/O)/CNTR0 input
1
CNTR0 input/output/D7 (input)
W6 3
Timer LC control bit
W6 2
R/W
CNTR1 output auto-control circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
3: When setting the LCD, W6 1, W6 0 are not used.
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APPLICATION
2.6 LCD function
4524 Group
2.6.3 LCD application examples
(1) LCD display
LCD display function can be used to display 80 pixels (maximum 4 common ✕ 20 segment).
Outline: LCD can be displayed easily by using the LCD display function.
Specifications: 1/4 duty and 1/3 bias LCD is displayed by using LCD display panel example. Bit 4
of timer 5 is used for the LCD clock source, the sub-clock f(X CIN) = 32.768 kHz is
used for the timer 5 clock source, and the frame frequency is set to 85.3 Hz.
Figure 2.6.3 shows the LCD display panel example, Figure 2.6.4 shows the segment assignment example,
Figure 2.6.5 shows the LCD RAM assignment example, and Table 2.6.6 shows the initial setting example.
Every
Program Su. Mo. Tu. We. Th. Fr. Sa. weeks SP EP
Start Stop
BS
A.M.
CH
.M.
P.M.
Fig. 2.6.3 LCD display panel example
Every
Program Su. Mo. Tu. We. Th. Fr. Sa. weeks SP EP
Start Stop
BS
A.M.
P.M.
CH
➀
➁
➂
➃
➄
➅
➆
➇
Fig. 2.6.4 Segment assignment example
1
Z
X
0
Bit
Y
8
9
10
11
12
13
14
15
COM
Note:
a
1
3
2
1
0
➀-g
➁-g
➂-g
➃-g
➄-g
➅-g
➆-g
➇-g
➀-e
➁-e
➂-f
➃-e
➄-e
➅-e
➆-e
➇-e
➀-d
➁-d
➂-d
➃-d
➄-d
➅-d
➆-d
➇-d
➀-c
➁-c
➂-c
➃-c
➄-c
➅-c
➆-c
➇-c
3
Start
Stop
•
•
Unused
•
•
Unused
Unused
Unused
2
2
1
0
➀-f
➁-f
➂-f
➃-f
➄-f
➅-f
➆-f
➇-f
➀-b
➁-b
➂-b
➃-b
➄-b
➅-b
➆-b
➇-b
➀-a
➁-a
➂-a
➃-a
➄-a
➅-a
➆-a
➇-a
3
We.
Every
weeks
BS
2
Tu.
1
Mo.
0
Su.
f
Sa.
CH
Fr.
EP
Tu.
SP
e
P.M.
g
d
b
c
A.M. Program
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
LCD display RAM is not assigned.
Fig. 2.6.5 LCD RAM assignment example
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APPLICATION
2.6 LCD function
4524 Group
➀ Stop Timer 5
Timer 5 operation is stopped.
Timer control register W5
b3
b0
✕
0
✕
✕
b2: Timer 5 operation stop [TW5A]
b0
[TW6A]
b3: Timer LC stop
b2: Bit 4 of timer 5 selected for timer LC count source
↓
➁ Stop Timer LC
Timer LC operation is stopped.
Timer LC count source is selected.
b3
Timer control register W6
0
0
✕
✕
↓
➂ Set SEG 0 –SEG 2
SEG pins are selected.
Internal dividing resistor is set to be valid.
b3
LCD control register L2
b0
0
0
0
0
[TL2A]
b3, b2, b1: SEG pins selected
b0: Internal dividing resistor valid
↓
➃ Set Timer LC
Timer LC value is set. (The formula is shown *A below.)
Timer LC reload register RLC
“2 16”
Timer LC
Timer count value 2 set [TLCA]
↓
➄ Initialize LCD Display RAM
LCD display RAM is initialized.
LCD display RAM
Initial data is set.
↓
➅ Set LCD Display Method
LCD duty and bias are set.
b3
LCD control register L1
b0
1
0
1
1
[TL1A]
b3: Internal dividing resistor r ✕ 3 selected
b1, b0: 1/4 duty, 1/3 bias set
↓
➆ Start Timer 5 Operation
Timer 5 operation is started.
b3
Timer control register W5
b0
✕
1
✕
✕
b2: Timer 5 operation start [TW5A]
↓
➇ Start Timer LC Operation
Timer LC operation is started.
b3
Timer control register W6
b0
1
0
✕
✕
b3: Timer LC operation start [TW6A]
↓
➈ Display LCD
LCD display function is set to be valid.
b3
LCD control register L1
b0
1
1
1
1
b2: LCD turned ON [TL1A]
↓
Display changed by rewriting LCD display RAM
*A: The timer LC count value when the frequency is set to 85.3 Hz is set as follows.
85.3 Hz ≅ (32.768 kHz) ✕
Sub-clock
1
16
✕
Bit 4 of
timer 5
1
(2+1)
Timer LC
count value
✕
1
2
✕
1
4
Duty
“✕”: it can be “0” or “1.”
“[ ]”: instruction
Fig. 2.6.6 Initial setting example
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APPLICATION
4524 Group
2.6 LCD function
2.6.4 Notes on use
(1) Timer LC count source
Stop timer LC counting to change timer LC count source.
(2) Writing to timer LC
Stop timer LC counting and then execute the data write instruction (TLCA).
(3) VLC3/SEG0 pin
When the V LC3 pin function is selected, apply voltage of V LC3 < V DD to the pin externally.
(4) V LC2/SEG1 pin, VLC1/SEG 2 pin
• When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used;
Apply voltage of 0<V LC1<V LC2<V LC3 to these pins.
Short the V LC2 pin and V LC1 pin at 1/2 bias.
• When SEG 1 and SEG 2 pin function is selected;
Use the internal dividing resistor.
(5) LCD power circuit
Select the LCD power circuit suitable for LCD panel and evaluate the display state on the actual
system.
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APPLICATION
2.7 Reset
4524 Group
2.7 Reset
System reset is performed by applying “L” level to the RESET pin for 1 machine cycle or more when the
following conditions are satisfied:
● the value of supply voltage is the minimum value or more of the recommended operating conditions.
Then when “H” level is applied to RESET pin, the program starts from address 0 in page 0 after elapsing
of the internal oscillation stabilizing time (On-chip oscillator (internal oscillator) clock is counted for 5400 to
5424 times). Figure 2.7.2 shows the oscillation stabilizing time.
2.7.1 Reset circuit
The 4524 Group has the voltage drop detection circuit.
(1) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset
circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from
0 V to the minimum rating value of the recommended operating conditions must be set to 100 µs or
less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the
shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the
minimum rating value of the recommended operating conditions.
100 µs or less
Pull-up transistor
VDD (Note 3)
Power-on reset circuit output
(Note 1)
(Note 2)
RESET pin
Internal reset signal
Power-on reset circuit
(Note 1)
Voltage drop detection circuit
Internal reset signal
Watchdog reset signal
WEF
Reset
state
Power-on
Reset released
This symbol represents a parasitic diode.
Notes 1:
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 2.7.1 Structure of reset pin and its peripherals, and power-on reset operation
=
Reset input
1 machine cycle or more
0.85VDD
On-chip oscillator (internal oscillator) is
(Note 2)
counted 5400 to 5424 times.
Program starts
(address 0 in page 0)
RESET
0.3VDD
(Note 1)
Notes 1: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
2: It depends on the internal state at reset.
Fig. 2.7.2 Oscillation stabilizing time after system is released from reset
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APPLICATION
2.7 Reset
4524 Group
2.7.2 Internal state at reset
Figure 2.7.3 shows the internal state at reset. The contents of timers, registers, flags and RAM other than
shown in Figure 2.7.3 are undefined, so that set them to initial values.
0 0 0 0 0 0 0 0 0 0 0 0 0 0
• Program counter (PC) .................................................................................
Address 0 in page 0 is set to program counter.
0 (Interrupt disabled)
• Interrupt enable flag (INTE) .......................................................................
0
• Power down flag (P) ...................................................................................
0
• External 0 interrupt request flag (EXF0) ..................................................
0
• External 1 interrupt request flag (EXF1) ..................................................
0 0 0 0 (Interrupt disabled)
• Interrupt control register V1 .......................................................................
0 0 0 0 (Interrupt disabled)
• Interrupt control register V2 .......................................................................
0 0 0 0
• Interrupt control register I1 .........................................................................
0 0 0 0
• Interrupt control register I2 .........................................................................
0
• Interrupt control register I3 .........................................................................
0
• Timer 1 interrupt request flag (T1F) .........................................................
0
• Timer 2 interrupt request flag (T2F) .........................................................
0
• Timer 3 interrupt request flag (T3F) .........................................................
0
• Timer 4 interrupt request flag (T4F) .........................................................
0
• Timer 5 interrupt request flag (T5F) .........................................................
0
• Watchdog timer flags (WDF1, WDF2) ......................................................
1
• Watchdog timer enable flag (WEF) ...........................................................
0 (Prescaler stopped)
• Timer control register PA ...........................................................................
0 0 0 0 (Timer 1 stopped)
• Timer control register W1 ...........................................................................
0 0 0 0 (Timer 2 stopped)
• Timer control register W2 ...........................................................................
0 0 0 0 (Timer 3 stopped)
• Timer control register W3 ...........................................................................
0 0 0 0 (Timer 4 stopped)
• Timer control register W4 ...........................................................................
0 0 0 0 (Timer 5 stopped)
• Timer control register W5 ...........................................................................
0 0 0 0 (Timer LC stopped)
• Timer control register W6 ...........................................................................
1 1 0 0
• Clock control register MR ...........................................................................
0
• Serial I/O transmit/receive completion flag (SIOF) .................................
0 0 0 0 (External clock selected,
• Serial I/O mode register J1 ........................................................................
serial I/O port not selected)
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Serial I/O register SI ...................................................................................
0
• A/D conversion completion flag (ADF) .....................................................
0
0
0
0
• A/D control register Q1 ...............................................................................
0 0 0 0
• A/D control register Q2 ...............................................................................
0 0 0 0
• A/D control register Q3 ...............................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Successive approximation register AD .....................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Comparator register .....................................................................................
0 0 0 0
• LCD control register L1 ..............................................................................
1 1 1 1
• LCD control register L2 ..............................................................................
“✕” represents undefined.
Fig. 2.7.3 Internal state at reset
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APPLICATION
4524 Group
2.7 Reset
• Key-on wakeup control register K0 ...........................................................
0 0 0 0
• Key-on wakeup control register K1 ...........................................................
0 0 0 0
• Key-on wakeup control register K2 ...........................................................
0 0 0 0
• Pull-up control register PU0 .......................................................................
0 0 0 0
• Pull-up control register PU1 .......................................................................
0 0 0 0
• Port output structure control register FR0 ...............................................
0 0 0 0
• Port output structure control register FR1 ...............................................
0 0 0 0
• Port output structure control register FR2 ...............................................
0 0 0 0
• Port output structure control register FR3 ...............................................
0 0 0 0
• Carry flag (CY) .............................................................................................
0
• Register A .....................................................................................................
0 0 0 0
• Register B .....................................................................................................
0 0 0 0
• Register D .....................................................................................................
✕ ✕ ✕
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register E .....................................................................................................
• Register X .....................................................................................................
0 0 0 0
• Register Y .....................................................................................................
0 0 0 0
• Register Z .....................................................................................................
✕ ✕
• Stack pointer (SP) .......................................................................................
1 1 1
• Operation source clock ............................ On-chip oscillator (operating)
• Ceramic resonator circuit ........................................................... Operating
• RC oscillation circuit ............................................................................ Stop
• Quartz-crystal oscillator .............................................................. Operating
“✕” represents undefined.
Fig. 2.7.4 Internal state at reset
2.7.3 Notes on use
(1) Register initial value
The initial value of the following registers are undefined after system is released from reset. After
system is released from reset, set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
(2) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset
circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from
0 V to the minimum rating value of the recommended operating conditions must be set to 100 µs or
less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and V SS at the
shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the
minimum rating value of the recommended operating conditions.
Refer to section “3.1 Electrical characteristics” for the reset voltage of the recommended operating
conditions.
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2.8 Voltage drop detection circuit
4524 Group
2.8 Voltage drop detection circuit
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer
if the supply voltage drops below a set value.
Figure 2.8.1 shows the voltage drop detection circuit, and Figure 2.8.2 shows the operation waveform example
of the voltage drop detection circuit. Table 2.8.1 shows the voltage drop detection circuit operation state.
Refer to section “3.1 Electrical characteristics” for the reset voltage of the voltage drop detection circuit.
EPOF instruction +POF instruction
EPOF instruction +POF2 instruction
S
Q
R
Q
S
SVDE instruction
R
Internal reset signal
Internal reset signal
T5F flag
Key-on wakeup signal
VDCE
Voltage drop detection circuit
Reset signal
–
VRST
+
Voltage drop detection circuit
Fig. 2.8.1 Voltage drop detection circuit
VDD
VRST (detection
voltage)
Voltage drop detection circuit
Reset signal
Microcomupter starts operation after
on-chip oscillator (internal oscillator)
clock is counted 5400 to 5424 times.
RESET pin
Note: Detection voltage of voltage drop detection circuit does not have hysteresis.
Fig. 2.8.2 Voltage drop detection circuit operation waveform example
Table 2.8.1 Voltage drop detection circuit operation state
VDCE pin
At CPU operating
“L”
Invalid
“H”
Valid
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At power down
At power down
(SVDE instruction is not executed)
(SVDE instruction is executed)
Invalid
Invalid
Invalid
Valid
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APPLICATION
2.8 Voltage drop detection circuit
4524 Group
2.8.1 Note on use
The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value
of the supply voltage of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the minimum value of recommended operating
conditions and re-goes up (ex. battery exchange of an application product), depending on the capacity
value of the bypass capacitor added to the power supply pin, the following case may cause program failure
(Figure 2.8.3);
• supply voltage does not fall below to V RST, and
• its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is once reduced below to V RST and re-goes
up after that.
VDD
Recommended
operatng condition
min.value
VRST
No reset
Program failure may occur.
→ Normal operation
VDD
Recommended
operatng condition
min.value
VRST
Reset
Fig. 2.8.3 V DD and V RST
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2.9 Power down
4524 Group
2.9 Power down
The 4524 Group has the clock operating mode and RAM back-up mode for the power down function.
In this section, the state transition, each power down function related register and application example for
the power down function are described.
Figure 2.9.1 shows the state transition.
High-speed mode
E
Clock operating mode
B
POF instruction
execution
POF2 instruction
execution
Operation state
• Operation source clock: f(XIN)
• Oscillation circuit:
Ceramic resonator
T5F
Wakeup
(Stabilizing time c )
• On-chip oscillator: Stop
• RC oscillation circuit: Stop
F
RAM back-up mode
Wakeup
(Stabilizing time c )
CMCK instruction
execution (Note 3)
A
Reset
POF instruction
execution
(Stabilizing time a )
T5F
Wakeup
(Stabilizing time b )
Operation state
• Operation source clock:
f(RING)
• Oscillation circuit:
On-chip oscillator
• Ceramic resonator:
Operating (Note 2)
• RC oscillation circuit: Stop
POF2 instruction
execution
Wakeup
(Stabilizing time b )
CRCK instruction
execution (Note 3)
POF instruction
execution
T5F
Wakeup
(Stabilizing time d )
C
Operation state
• Operation source clock: f(XIN)
• Oscillation circuit:
RC oscillation
• On-chip oscillator: Stop
• Ceramic resontor: Stop
Low-speed
mode
POF instruction
execution
Main clock: stop
Sub-clock: operating
T5F
Wakeup
(Stabilizing time e )
MR0←1
(Note 4)
POF2 instruction
execution
Wakeup
(Stabilizing time d )
MR0←0
(Note 4)
D
Operation state
• Operation clock: f(XCIN)
• Oscillation circuit:
Quartz-crystal oscillation
POF2 instruction
execution
Wakeup
(Stabilizing time e )
Main clock: stop
Sub-clock: stop
Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5400 to 5424 times.
Stabilizing time b : In high-speed through-mode, microcomputer starts its operation after counting the f(RING) 675 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(RING) 1350 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(RING) 2700 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(RING) 5400 times.
Stabilizing time c : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 675 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 1350 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 2700 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 5400 times.
Stabilizing time d : In high-speed through-mode, microcomputer starts its operation after counting the f(XIN) 21 times.
In high-speed/2 mode, microcomputer starts its operation after counting the f(XIN) 42 times.
In high-speed/4 mode, microcomputer starts its operation after counting the f(XIN) 84 times.
In high-speed/8 mode, microcomputer starts its operation after counting the f(XIN) 168 times.
Stabilizing time e : In low-speed through-mode, microcomputer starts its operation after counting the f(XCIN) 675 times.
In low-speed/2 mode, microcomputer starts its operation after counting the f(XCIN) 1350 times.
In low-speed/4 mode, microcomputer starts its operation after counting the f(XCIN) 2700 times.
In low-speed/8 mode, microcomputer starts its operation after counting the f(XCIN) 5400 times.
Notes 1: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock.
3: The oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped.
4: The main clock (f(XIN) or f(RING)) or sub-clock (f(XCIN)) is selected for operation source clock by the bit 0 of clock control register MR.
5: The sub-clock (quartz-crystal oscillation) is operating except in state F.
Fig. 2.9.1 State transition
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4524 Group
2.9 Power down
2.9.1 Power down mode
The system goes into power down mode when the POF or POF2 instruction is executed immediately after
the EPOF instruction is executed. Table 2.9.1 shows the function and state retained at power down mode.
Also, Table 2.9.2 shows the return source from this state.
(1) Clock operating mode
The system goes into clock operating mode when the POF instruction is executed immediately after
the EPOF instruction is executed.
As main clock oscillation (XIN-XOUT) and system clock stop with RAM, the state of reset circuit, subclock oscillation circuit (X CIN-XCOUT ), LCD display and timer 5 retained, current dissipation can be
reduced.
(2) RAM back-up mode
The system goes into RAM back-up mode when the POF2 instruction is executed immediately after
the EPOF instruction is executed.
As oscillation stops with RAM and the state of reset circuit retained, current dissipation can be
reduced without losing the contents of RAM.
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2.9 Power down
4524 Group
Table 2.9.1 Functions and states retained at power down mode
Function
Power down mode
Clock operating
RAM back-up
✕
✕
Contents of RAM
O
O
Interrupt control registers V1, V2
Interrupt control registers I1 to I3
✕
✕
O
O
O
O
O
O
(Note 3)
(Note 3)
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Selected oscillation circuit
Clock control register MR
Timer 1 to timer 4 functions
Timer 5 function
O
O
Timer LC function
Watchdog timer function
O
(Note 3)
✕ (Note 4)
✕ (Note 4)
Timer control registers W1 to W3, W5, W6
✕
O
✕
O
Serial I/O function
✕
✕
Serial I/O control register J1
O
O
A/D function
A/D control registers Q1 to Q3
✕
✕
O
O
LCD control registers L1, L2
O
O
(Note 5)
O
Voltage drop detection circuit
(Note 6)
(Note 6)
Port level
Pull-up control registers PU0, PU1
(Note 7)
(Note 7)
O
O
Key-on wakeup control registers K0 to K2
O
O
Port output format control registers FR0 to FR3
O
✕
O
✕
(Note 3)
(Note 3)
Timer interrupt request flag (T5F)
A/D conversion completion flag (ADF)
O
O
✕
✕
Serial I/O transmit/receive completion flag SIOF
✕
✕
Watchdog timer flags (WDF1, WDF2)
✕
✕ (Note 4)
✕
✕ (Note 4)
Watchdog timer enable flag (WEF)
✕ (Note 4)
✕ (Note 4)
Timer control registers PA, W4
LCD display function
External interrupt request flags (EXF0, EXF1)
Timer interrupt request flags (T1F to T4F)
Interrupt enable flag (INTE)
Notes 1: “O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at power down, and set an initial value
after returning.
2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at power down.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction, and then go into the power down state.
5: LCD is turned off.
6: When the SVDE instruction is executed and the “H“ level is applied to the VDCE pin, this function
is valid at power down.
7: In the power down mode, C/CNTR1 pin outputs “L” level. However, when the CNTR input is
selected (W1 1, W1 0=“11”), C/CNTR1 pin is in an input enabled state (output=high-impedance).
Other ports retain their respective output levels.
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2.9 Power down
4524 Group
External wakeup signal
Table 2.9.2 Return source and return condition
Remarks
Return source
Return condition
Ports P00–P0 3 Return by an external “L” level The key-on wakeup function can be selected by one
port unit. Set the port using the key-on wakeup function
Ports P10–P1 3 input.
to “H” level before going into the power down state.
Return by an external “H” level Select the return level (“L” level or “H” level) with register
INT0 pin
or “L” level input, or rising edge I1 (I2) and return condition (return by level or edge)
INT1 pin
( “ L ” → “ H ” ) o r f a l l i n g e d g e with register K2 according to the external state before
(“H”→“L”).
going into the power down state.
When the return signal is input,
the interrupt request flag (EXF0,
EXF1) is not set to “1”.
Timer 5 interrupt
Return by timer 5 underflow or Clear T5F to “0” with the SNZT5 instruction before
request flag (T5F) by setting T5F to “1”.
system goes into the power down state.
It can be used in the clock When system goes into the power down state while
operating mode.
T5F is “1”, system returns from the state immediately
because it is recognized as return condition.
(3) Start condition identification
When system returns from both power down mode and reset, program is started from address 0 in
page 0.
The start condition (warm start or cold start) can be identified by examining the state of the power
down flag (P) with the SNZP instruction.
The warm start condition (Timer 5 or external wakeup signal) can be identified by examining the state
of T5F flag with the SNZT5 instruction.
Table 2.9.3 Start condition identification
Warm start
Cold start
(Reset)
Start condition
External wakeup signal input
Timer 5 underflow
Reset pulse input to RESET pin
Reset by watchdog timer
Reset by voltage drop detection circuit
P flag
1
1
0
Timer 5 interrupt request flag
0
1
0
Program start
P = “ 1”
?
Yes
Warm start
No
Cold start
T5F = “1”
?
Yes
No
Return from
timer 5 underflow
Return from
external wakeup signal
Fig. 2.9.2 Start condition identified example
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2.9 Power down
4524 Group
2.9.2 Related registers
(1) Interrupt control register I1
Table 2.9.4 shows the interrupt control register I1.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.9.4 Interrupt control register I1
Interrupt control register I1
at power down : state retained
R/W
0
INT0 pin input disabled
1
INT0 pin input enabled
Interrupt valid waveform for INT0
pin/return level selection bit
0
Falling waveform/“L” level (“L” level is recognized with
the SNZI0 instruction)
(Note 2)
1
Rising waveform/“H” level (“H” level is recognized with
the SNZI0 instruction)
INT0 pin edge detection circuit
control bit
0
I13
INT0 pin input control bit (Note 2)
I12
I11
at reset : 0000 2
1
One-sided edge detected
Both edges detected
Timer 1 count start synchronous circuit not selected
INT0 pin Timer 1 count start
0
Timer 1 count start synchronous circuit selected
synchronous circuit selection bit
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I1 2 and I1 3 are changed, the external interrupt request flag EXF0 may be
set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to
“0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
3: When setting the power down, I1 1–I1 0 are not used.
I10
(2) Interrupt control register I2
Table 2.9.5 shows the interrupt control register I2.
Set the contents of this register through register A with the TI2A instruction.
In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 2.9.5 Interrupt control register I2
Interrupt control register I2
at reset : 0000 2
0
at power down : state retained
R/W
INT1 pin input disabled
INT1 pin input enabled
I23
INT1 pin input control bit (Note 2)
0
I22
Interrupt valid waveform for INT1
pin/return level selection bit
Falling waveform/“L” level (“L” level is recognized with
the SNZI1 instruction)
(Note 2)
1
Rising waveform/“H” level (“H” level is recognized with
the SNZI1 instruction)
INT1 pin edge detection circuit
control bit
0
1
I21
1
One-sided edge detected
Both edges detected
Timer 3 count start synchronous circuit not selected
INT1 pin Timer 3 count start
0
Timer 3 count start synchronous circuit selected
synchronous circuit selection bit
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I2 2 and I2 3 are changed, the external interrupt request flag EXF1 may be
set. Accordingly, clear EXF1 flag with the SNZ1 instruction when the bit 1 (V1 1) of register V1 to
“0”. In this time, set the NOP instruction after the SNZ1 instruction, for the case when a skip is
performed with the SNZ1 instruction.
3: When setting the power down, I2 1–I2 0 are not used.
I20
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2.9 Power down
4524 Group
(3) Clock control register MR
Table 2.9.6 shows the clock control register MR.
Set the contents of this register through register A with the TMRA instruction.
The contents of register MR is transferred to register A with the TAMR instruction.
Table 2.9.6 Clock control register MR
Clock control register MR
MR3
Operation mode selection bits
MR2
MR 1
Main clock oscillation circuit
control bit
MR 0
System clock selection bit
at reset : 1100 2
MR3 MR2
0 0
0 1
1 0
1 1
at power down : state retained
R/W
Operation mode
Through-mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
0
Main clock oscillation enabled
1
Main clock oscillation stop
0
Main clock (f(XIN) or f(RING))
1
Sub-clock (f(X CIN))
Note: “R” represents read enabled, and “W” represents write enabled.
(4) Pull-up control register PU0
Table 2.9.7 shows the pull-up control register PU0.
Set the contents of this register through register A with the TPU0A instruction.
The contents of register PU0 is transferred to register A with the TAPU0 instruction.
Table 2.9.7 Pull-up control register PU0
Pull-up control register PU0
PU03
PU02
PU01
PU00
at reset : 0000 2
at power down : state retained
Port P0 3
0
Pull-up transistor OFF
pull-up transistor control bit
1
Pull-up transistor ON
Port P0 2
0
pull-up transistor control bit
1
0
Pull-up transistor OFF
Pull-up transistor ON
Port P0 1
pull-up transistor control bit
Port P0 0
R/W
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
pull-up transistor control bit
Pull-up transistor ON
1
Note: “R” represents read enabled, and “W” represents write enabled.
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2.9 Power down
4524 Group
(5) Pull-up control register PU1
Table 2.9.8 shows the pull-up control register PU1.
Set the contents of this register through register A with the TPU1A instruction.
The contents of register PU1 is transferred to register A with the TAPU1 instruction.
Table 2.9.8 Pull-up control register PU1
Pull-up control register PU1
PU1 3
PU1 2
PU1 1
at reset : 00002
at power down : state retained
Port P1 3
0
Pull-up transistor OFF
pull-up transistor control bit
1
Port P1 2
0
1
Pull-up transistor ON
Pull-up transistor OFF
pull-up transistor control bit
Port P1 1
pull-up transistor control bit
R/W
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
Pull-up transistor OFF
0
pull-up transistor control bit
Pull-up transistor ON
1
Note: “R” represents read enabled, and “W” represents write enabled.
PU1 0
Port P1 0
(6) Key-on wakeup control register K0
Table 2.9.9 shows the key-on wakeup control register K0.
Set the contents of this register through register A with the TK0A instruction.
The contents of register K0 is transferred to register A with the TAK0 instruction.
Table 2.9.9 Key-on wakeup control register K0
Key-on wakeup control register K0
K0 3
K0 2
K0 1
K0 0
at reset : 0000 2
at power down : state retained
Port P0 3
0
Key-on wakeup not used
key-on wakeup control bit
1
Port P0 2
0
1
Key-on wakeup used
Key-on wakeup not used
key-on wakeup control bit
R/W
Key-on wakeup used
Port P0 1
key-on wakeup control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port P0 0
0
Key-on wakeup not used
key-on wakeup control bit
Key-on wakeup used
1
Note: “R” represents read enabled, and “W” represents write enabled.
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4524 Group
(7) Key-on wakeup control register K1
Table 2.9.10 shows the key-on wakeup control register K1.
Set the contents of this register through register A with the TK1A instruction.
The contents of register K1 is transferred to register A with the TAK1 instruction.
Table 2.9.10 Key-on wakeup control register K1
Key-on wakeup control register K1
K1 3
K1 2
K1 1
at reset : 0000 2
at power down : state retained
Port P1 3
key-on wakeup control bit
0
Key-on wakeup not used
1
Key-on wakeup used
Port P1 2
0
Key-on wakeup not used
key-on wakeup control bit
1
Port P1 1
0
1
Key-on wakeup used
Key-on wakeup not used
key-on wakeup control bit
R/W
Key-on wakeup used
Key-on wakeup not used
Port P1 0
0
key-on wakeup control bit
Key-on wakeup used
1
Note: “R” represents read enabled, and “W” represents write enabled.
K1 0
(8) Key-on wakeup control register K2
Table 2.9.11 shows the key-on wakeup control register K2.
Set the contents of this register through register A with the TK2A instruction.
The contents of register K2 is transferred to register A with the TAK2 instruction.
Table 2.9.11 Key-on wakeup control register K2
Key-on wakeup control register K2
at reset : 0000 2
at power down : state retained
K2 3
INT1 pin return condition
selection bit
0
Return by level
1
Return by edge
K2 2
INT1 pin key-on wakeup control
bit
0
Key-on wakeup invalid
Key-on wakeup valid
K2 1
INT0 pin return condition
selection bit
K2 0
INT0 pin key-on wakeup control
bit
1
0
R/W
Returned by level
1
Returned by edge
0
Key-on wakeup invalid
1
Key-on wakeup valid
Note: “R” represents read enabled, and “W” represents write enabled.
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4524 Group
2.9.3 Power down function application example
(1) Clock display
A clock which is high-accuracy and low-power dissipation can be set up by using a 32.768 kHz
quartz-crystal oscillator as a sub-clock and executing the POF instruction.
Outline: The power dissipation can be reduced by using the POF instruction.
Specifications: Time is displayed by the LCD and a 32.768 kHz quartz-crystal oscillator. The main
routine is executed by key input.
Figure 2.9.3 shows the software setting example.
Address 0 in page 0
Software start
Initialization of register Z
Yes
P = “1” ?
No
Cold start initial setting
T5F = “1” ?
Warm start initiai setting
Yes
No
Clock counter + 1
Time display renewed
Key input ?
No
Yes
Main routine initial setting
DI
EPOF
POF
To main routine
Fig. 2.9.3 Software setting example
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2.9 Power down
2.9.4 Notes on use
(1) POF instruction, POF2 instruction
Execute the POF or POF2 instruction immediately after executing the EPOF instruction to enter the
power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction
and the POF or POF2 instruction.
(2) Key-on wakeup function
After checking none of the return condition for ports (P0, P1, INT0 and INT1 specified with register
K0–K2) with valid key-on wakeup function is satisfied, execute the POF or POF2 instruction.
If at least one of return condition for ports with valid key-on wakeup function is satisfied, system
returns from the power downn state immediately after the POF or POF2 instruction is executed.
(3) Timer 5 interrupt request flag
When POF or POF2 instruction is executed while T5F is “1”, system returns from the power down
state immediately.
(4) Return from power down mode
After system returns from power down mode, set the undefined registers and flags.
The initial value of the following registers are undefined at power down. After system is returned from
power down mode, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
(5) Watchdog timer
• The watchdog timer function is valid after system is returned from the power down state. When not
using the watchdog timer function, stop the watchdog timer function with the DWDT instruction and
the WRST instruction continuously every system is returned from the power down.
• When the watchdog timer function and power down function are used at the same time, initialize
the flag WDF1 with the WRST instruction before system goes into the power down state.
(6) Port D 8/INT0 pin
When the power down mode is used by clearing the bit 3 of register I1 to “0” and setting the input
of INT0 pin to be disabled, be careful about the following note.
• When the input of INT0 pin is disabled (register I1 3 = “0”), clear bit 0 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(7) Port D 9/INT1 pin
When the power down mode is used by clearing the bit 3 of register I2 to “0” and setting the input
of INT1 pin to be disabled, be careful about the following note.
• When the input of INT1 pin is disabled (register I2 3 = “0”), clear bit 2 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(8) External clock
When the external clock signal is used as the main clock (f(XIN)), note that the power down mode
(POF or POF2 instruction) cannot be used.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-86
APPLICATION
2.10 Oscillation circuit
4524 Group
2.10 Oscillation circuit
The 4524 Group has an internal oscillation circuit to produce the clock required for microcomputer operation.
The ceramic resonator or the RC oscillation can be used for the main clock (f(X IN)).
After system is released from reset, the 4524 Group starts operation by the clock output from the on-chip
oscillator which is the internal oscillator.
2.10.1 Oscillation circuit
Reset
(1) Main clock generating circuit (f(X IN))
The ceramic resonator or RC oscillation can
be used for the main clock (f(X IN )).
After system is released from reset, the 4524
Group starts operation by the clock output from
the on-chip oscillator which is the internal
oscillator.
When the ceramic resonator is used, execute
the CMCK instruction. When the RC oscillation
is used, execute the CRCK instruction. The
selection of oscillation circuit by the CMCK or
CRCK instruction is valid only at once. The
oscillation circuit corresponding to the first
executed one of these two instructions is valid.
Another oscillation circuit and the on-chip
oscillator stop.
Execute the CMCK or the CRCK instruction
in the initial setting routine of program
(executing it in address 0 in page 0 is
recommended). Also, when the CMCK or the
CRCK instruction is not executed in program,
the 4524 Group operates by the on-chip
oscillator.
On-chip oscillator
operation
CMCK instruction
CRCK instruction
• Ceramic resonator valid • RC oscillation valid
• On-chip oscillator stop
• On-chip oscillator stop
• Ceramic resonator stop
• RC oscillation stop
Fig. 2.10.1 Switch to ceramic oscillation/RC oscillation
M34524
XIN
* DanodnCotRuCsKe itnhsetrCuMctiCoKn iinnsptrrougctriaomn .
XOUT
Fig. 2.10.2 Handling of XIN and XOUT when operating
on-chip oscillator
(2) On-chip oscillator operation
When the MCU operates by the on-chip
oscillator as the main clock (f(X IN )) without
using the ceramic resonator or the RC
oscillation, connect XIN pin to VSS and leave
XOUT pin open (Figure 2.10.2).
The clock frequency of the on-chip oscillator
depends on the supply voltage and the
operation temperature range.
Be careful that margin of frequencies when
designing application products.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-87
APPLICATION
2.10 Oscillation circuit
4524 Group
(3) Ceramic resonator
When the ceramic resonator is used as the
main clock (f(X IN )), connect the ceramic
resonator and the external circuit to pins XIN
and X OUT at the shortest distance. Then,
execute the CMCK instruction. A feedback
resistor is built in between pins XIN and XOUT
(Figure 2.10.3).
(4) RC oscillation
When the RC oscillation is used as the main
clock (f(XIN)), connect the XIN pin to the external
circuit of resistor R and the capacitor C at the
shortest distance and leave X OUT pin open.
Then, execute the CRCK instruction (Figure
2.10.4).
The frequency is affected by a capacitor, a
resistor and a microcomputer.
So, set the constants within the range of the
frequency limits.
(5) External clock
When the external clock signal is used as the
main clock (f(XIN)), connect the XIN pin to the
clock source and leave XOUT pin open. Then,
execute the CMCK instruction (Figure 2.10.5).
Be careful that the maximum value of the
oscillation frequency when using the external
clock differs from the value when using the
ceramic resonator (refer to section “3.1
Electrical characteristics”).
Also, note that the power down function (POF
or POF2 instruction) cannot be used when
using the external clock.
Execute the CMCK instruction in
program.
M34524
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
(A feedback resistor is built-in.)
Rd
Use the resonator manufacturer’s
recommended value because
COUT
constants such as capacitance
depend on the resonator.
XIN
XOUT
CIN
Fig. 2.10.3 Ceramic resonator external circuit
M34524
R
XIN
XOUT
* EinxsetrcuuctteiotnheinCpRroCgKram.
C
Fig. 2.10.4 External RC oscillation circuit
the CMCK
* Execute
instruction in program.
M34524
XIN
XOUT
VDD
VSS
External oscillation circuit
Fig. 2.10.5 External clock input circuit
(6) Sub-clock generating circuit f(XCIN)
The quartz-crystal oscillator can be used for
the sub-clock f(XCIN). Connect a quartz-crystal
oscillator and this external circuit to pins X CIN
and XCOUT at the shortest distance. A feedback
resistor is built in between pins XCIN and XCOUT
(Figure 2.10.6).
M34524
XCIN
CI N
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
XCOUT
(A feedback resistor is built-in.)
Use the quartz-crystal
manufacturer’s recommended
Rd
value because constants such
as capacitance depend on the
COUT resonator.
Fig. 2.10.6 External quartz-crystal circuit
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-88
APPLICATION
2.10 Oscillation circuit
4524 Group
2.10.2 Oscillation operation
System clock is supplied to CPU and peripheral device as the base clock for the microcomputer operation.
For the 4524 Group, the clock supplied is selected from the following;
● on-chip oscillator (internal oscillator),
● the ceramic oscillation circuit, and
● divided clock supplied from RC oscillation circuit. Its division ratio is selected from the following with the
register MR;
• through mode (f(X IN )) (not divided),
• frequency divided by 2 mode (f(X IN)/2),
• frequency divided by 4 mode (f(X IN )/4) or
• frequency divided by 8 mode (f(X IN)/8).
Figure 2.10.7 shows the structure of the clock control circuit.
Division circuit
Divided by 8
On-chip oscillator
(internal oscillator)
(Note 1)
Divided by 4
MR0
0
Multi-plexer
MR3, MR2
11
System clock (STCK)
10
Internal clock
generating circuit
(divided by 3)
01
Divided by 2
00
Instruction clock
(INSTCK)
Wait time
control circuit
(Note 2)
1
Q S
Program start
signal
Q R
RC oscillation
circuit
Q S
XIN
XOUT
Ceramic
oscillation circuit
R
Q S
MR1
XCIN
XCOUT
Quartz-crystal
oscillation circuit
CRCK instruction
Q S
R
CMCK instruction
R
Internal reset signal
T5F flag
Key-on wakeup signal
EPOF instruction + POF instruction
Q S
R
EPOF instruction + POF2 instruction
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed
after system is released from reset.
2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) or f(XCIN) oscillation.
After the certain oscillation stabilizing wait time elapses, the program start signal is output.
This circuit operates when system is released from reset or returned from power down.
Fig. 2.10.7 Structure of clock control circuit
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-89
APPLICATION
2.10 Oscillation circuit
4524 Group
2.10.3 Related register
(1) Clock control register MR
Table 2.10.1 shows the clock control register MR.
Set the contents of this register through register A with the TMRA instruction.
The contents of register MR is transferred to register A with the TAMR instruction.
Table 2.10.1 Clock control register MR
Clock control register MR
MR3
Operation mode selection bits
MR2
MR 1
Main clock oscillation circuit
control bit
MR 0
System clock selection bit
at reset : 1100 2
MR3 MR2
0 0
0 1
1 0
1 1
at power down : state retained
R/W
Operation mode
Through-mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
0
1
Main clock oscillation enabled
Main clock oscillation stop
0
Main clock (f(XIN) or f(RING))
1
Sub-clock (f(X CIN))
Note: “R” represents read enabled, and “W” represents write enabled.
2.10.4 Notes on use
(1) Clock control
Execute the CMCK or the CRCK instruction to select the main clock (f(X IN )) in the initial setting
routine of program (executing it in address 0 in page 0 is recommended).
The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation
circuit corresponding to the first executed one of these two instructions is valid. Another oscillation
circuits and the on-chip oscillator stop.
(2) On-chip oscillator
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation
temperature range.
Be careful that margin of frequencies when designing application products.
Also, the oscillation stabilize wait time after system is released from reset is generated by the onchip oscillator clock. When considering the oscillation stabilize wait time after system is released
from reset, be careful that the margin of frequencies of the on-chip oscillator clock.
(3) External clock
When the external clock signal is used as the main clock (f(XIN)), note that the power down mode
(POF or POF2 instruction) cannot be used.
(4) Value of a part connected to an oscillator
Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and
the board. Accordingly, consult the oscillator manufacturer for values of each part connected the
oscillator.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2-90
CHAPTER 3
APPENDIX
3.1
3.2
3.3
3.4
3.5
Electrical characteristics
Typical characteristics
List of precautions
Notes on noise
Package outline
APPENDIX
4524 Group
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
VDD
VI
VI
VI
VO
VO
VO
Pd
Topr
Tstg
Parameter
Conditions
Supply voltage
Input voltage
P0, P1, P2, P3, P4, D0–D7, RESET, XIN, XCIN, VDCE
Input voltage SCK, SIN, CNTR0, CNTR1, INT0, INT1
Input voltage AIN0–AIN7
Output voltage
Output transistors in cut-off state
P0, P1, P2, P3, P4, D 0–D9, RESET, SCK, SOUT, CNTR0, CNTR1
Output voltage C, XOUT, XCOUT
Output voltage SEG0–SEG19, COM0–COM3
Power dissipation
Ta = 25 °C
Operating temperature range
Storage temperature range
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
Ratings
–0.3 to 6.5
–0.3 to VDD+0.3
Unit
V
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
V
V
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
300
–20 to 85
–40 to 125
V
V
mW
°C
°C
3-2
APPENDIX
3.1 Electrical characteristics
4524 Group
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
VDD
Parameter
Supply voltage
(when ceramic resonator is used)
Conditions
Mask ROM version
f(STCK) ≤ 6 MHz
Limits
Min.
f(STCK) ≤ 4.4 MHz
4
2.7
2
5.5
4
5.5
2.7
5.5
f(STCK) ≤ 2.2 MHz
2.5
5.5
5.5
f(STCK) ≤ 4.4 MHz
2.7
VRAM
RAM back-up voltage
at RAM back-up mode
1.8
VSS
Supply voltage
VLC3
LCD power supply (Note 1)
One Time PROM version
VIH
VIH
“H” level input voltage
“H” level input voltage
P0, P1, P2, P3, P4, D0–D7, VDCE
XIN, XCIN
RESET
SCK, SIN, CNTR0, CNTR1, INT0, INT1
V
V
2
VDD
V
2.5
VDD
VDD
V
VDD
V
0.85VDD
VDD
V
0.8VDD
VDD
V
0.2VDD
V
0.3VDD
0.3VDD
V
V
0.15VDD
V
–20
mA
0.8VDD
0.7VDD
VIL
“L” level input voltage
P0, P1, P2, P3, P4, D0–D7, VDCE
0
VIL
“L” level input voltage
XIN, XCIN
0
VIL
VIL
“L” level input voltage
“L” level input voltage
RESET
0
0
IOH(peak)
“H” level peak output current
SCK, SIN, CNTR0, CNTR1, INT0, INT1
VDD = 5 V
P0, P1, P4, D0–D6
V
V
0
Mask ROM version
Unit
5.5
f(STCK) ≤ 2.2 MHz
Supply voltage
(when RC oscillation is used)
“H” level input voltage
“H” level input voltage
Max.
5.5
One Time PROM version f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
VDD
VIH
VIH
Typ.
SCK, SOUT
VDD = 3 V
–10
“H” level peak output current
D 7, C
VDD = 5 V
VDD = 3 V
–30
–15
mA
“H” level average output current
CNTR0, CNTR1
P0, P1, P4, D0–D6
VDD = 5 V
–10
mA
(Note 2)
SCK, SOUT
VDD = 3 V
–5
“H” level average output current
D 7, C
VDD = 5 V
–20
(Note 2)
CNTR0, CNTR1
VDD = 3 V
–10
IOL(peak)
“L” level peak output current
P0, P1, P4
VDD = 5 V
VDD = 3 V
24
12
mA
IOL(peak)
“L” level peak output current
mA
IOH(peak)
IOH(avg)
IOH(avg)
IOL(peak)
“L” level peak output current
D0–D9, C, SCK, SOUT,
VDD = 5 V
24
CNTR0, CNTR1
VDD = 3 V
12
P2, P3, RESET
VDD = 5 V
10
VDD = 3 V
4
mA
mA
IOL(avg)
“L” level average output current
P0, P1, P4
VDD = 5 V
VDD = 3 V
12
6
mA
IOL(avg)
(Note 2)
“L” level average output current
D0–D9, C, SCK, SOUT,
VDD = 5 V
15
mA
(Note 2)
CNTR0, CNTR1
VDD = 3 V
7
“L” level average output current
P2, P3, RESET
VDD = 5 V
5
VDD = 3 V
2
IOL(avg)
(Note 2)
ΣIOH(avg)
ΣIOL(avg)
“H” level total average current
P0, P1, D0–D6, SCK, SOUT
“L” level total average current
P4, D7, C, CNTR0, CNTR1
P0, P1, D0–D6, SCK, SOUT
P2, P3, P4, D7–D9, C, RESET, CNTR0, CNTR1
mA
–60
–60
mA
80
mA
80
Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3
At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3
2: The average output current is the average value during 100 ms.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-3
APPENDIX
3.1 Electrical characteristics
4524 Group
Table 3.1.3 Recommended operating conditions 2
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
f(XIN)
Parameter
Conditions
Oscillation frequency
Mask ROM
(with a ceramic resonator)
Through mode
Min.
Limits
Typ.
Max.
VDD = 4 to 5.5 V
6
VDD = 2.7 to 5.5 V
version
Frequency/2 mode VDD = 2.7 to 5.5 V
6
VDD = 2 to 5.5 V
4.4
Frequency/4, 8 mode VDD = 2 to 5.5 V
VDD = 4 to 5.5 V
One Time PROM Through mode
VDD = 2.7 to 5.5 V
version
6
6
4.4
2.2
VDD = 2.5 to 5.5 V
Frequency/2 mode VDD = 2.7 to 5.5 V
6
VDD = 2.5 to 5.5 V
4.4
Frequency/4, 8 mode VDD = 2.5 to 5.5 V
6
4.4
MHz
VDD = 4 to 5.5 V
4.8
MHz
VDD = 2.7 to 5.5 V
3.2
VDD = 2 to 5.5 V
1.6
VDD = 2.7 to 5.5 V
Oscillation frequency
MHz
4.4
2.2
VDD = 2 to 5.5 V
f(XIN)
Unit
(at RC oscillation) (Note)
f(XIN)
Oscillation frequency
Mask ROM
(with a ceramic resonator selected,
version
Through mode
external clock input)
Frequency/2 mode VDD = 2.7 to 5.5 V
VDD = 2 to 5.5 V
4.8
Frequency/4, 8 mode VDD = 2 to 5.5 V
3.2
One Time PROM Through mode
VDD = 4 to 5.5 V
4.8
4.8
version
VDD = 2.7 to 5.5 V
3.2
VDD = 2.5 to 5.5 V
1.6
Frequency/2 mode VDD = 2.7 to 5.5 V
VDD = 2.5 to 5.5 V
4.8
3.2
4.8
Frequency/4, 8 mode VDD = 2.5 to 5.5 V
f(CNTR) Timer external input frequency
f(XCIN)
Quartz-crystal oscillator
CNTR0, CNTR1
tw(CNTR) Timer external input period
CNTR0, CNTR1
f(SCK)
Oscillation frequency (sub-clock)
(“H” and “L” pulse width)
Serial I/O external input frequency
3/f(STCK)
kHz
50
f(STCK)/6 Hz
s
3/f(STCK)
f(STCK)/6 Hz
s
SCK
tw(SCK) Serial I/O external input frequency
(“H” and “L“ pulse width)
SCK
TPON
Power-on reset circuit
Mask ROM version
VDD = 0 → 2 V
100
valid supply voltage rising time
One Time PROM version
VDD = 0 → 2.5 V
100
µs
Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
<System clock (STCK) Operating condition map>
➀ When ceramic resonator is used.
➁ When RC oscillation is used.
➂ When external clock is used.
f(STCK)
[MHz]
f(STCK)
[MHz]
f(STCK)
[MHz]
6
4.8
4.4
4.4
3.2
Recommended
operating
condition
2.2
2
(2.5)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
2.7
4
5.5
Recommended
operating
condition
VDD
[V]
2.7
Recommended
operating
condition
1.6
5.5
VDD
[V]
2
(2.5)
2.7
4
5.5
VDD
[V]
3-4
APPENDIX
3.1 Electrical characteristics
4524 Group
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
VOH
Parameter
“H” level output voltage
Test conditions
IOH = –10 mA
IOH = –3 mA
4.1
VDD = 3 V
IOH = –5 mA
IOH = –1 mA
2.1
VDD = 5 V
IOH = –20 mA
3
IOH = –6 mA
IOH = –10 mA
4.1
2.1
IOH = –3 mA
2.4
VDD = 5 V
P0, P1, P4, D0–D6, SCK, SOUT
VOH
“H” level output voltage
D7, C, CNTR0, CNTR1
VDD = 3 V
VOL
“L” level output voltage
“L” level output voltage
“L” level output voltage
V
IOL = 6 mA
0.9
IOL = 2 mA
0.6
IOL = 15 mA
2
IOL = 5 mA
0.9
VDD = 3 V
IOL = 9 mA
IOL = 3 mA
1.4
0.9
VDD = 5 V
IOL = 5 mA
2
IOL = 1 mA
0.6
IOL = 2 mA
0.9
VDD = 3 V
“H” level input current
2.4
VDD = 3 V
VDD = 5 V
Unit
V
2
0.9
P2, P3, RESET
IIH
Max.
IOL = 12 mA
IOL = 4 mA
D0–D9, C, SCK, SOUT, CNTR0, CNTR1
VOL
Typ.
VDD = 5 V
P0, P1, P4
VOL
Limits
Min.
3
V
V
V
VI = VDD
1
µA
VI = 0 V P0, P1 No pull-up
–1
µA
P0, P1, P2, P3, P4, D0–D7, VDCE,
RESET, CNTR0, CNTR1, INT0, INT1
IIL
“L” level input current
P0, P1, P2, P3, P4, D0–D7, VDCE,
SCK, SIN, CNTR0, CNTR1, INT0, INT1
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-5
APPENDIX
3.1 Electrical characteristics
4524 Group
Table 3.1.5 Electrical characteristics 2
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
IDD
Parameter
Test conditions
VDD = 5 V
Supply current at active mode
(with a ceramic resonator) f(XIN) = 6 MHz
f(XCIN) = 32 kHz
Limits
Min.
f(STCK) = f(XIN)/8
Typ.
1.4
1.6
2
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
5.6
VDD = 5 V
1.1
2.2
f(XIN) = 4 MHz
f(STCK) = f(XIN)/4
1.2
2.4
f(XCIN) = 32 kHz
f(STCK) = f(XIN)/2
1.5
f(STCK) = f(XIN)
2
0.4
3
4
0.8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
0.5
1
0.6
1.2
f(STCK) = f(XIN)
0.8
1.6
110
120
f(STCK) = f(XIN)/8
at active mode
(with a quartz-crystal
VDD = 5 V
f(STCK) = f(XIN)/8
55
f(XIN) = stop
f(STCK) = f(XIN)/4
oscillator)
f(XCIN) = 32 kHz
f(STCK) = f(XIN)/2
60
65
70
140
VDD = 3 V
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
12
24
f(XIN) = stop
f(STCK) = f(XIN)/4
13
26
f(XCIN) = 32 kHz
f(STCK) = f(XIN)/2
14
f(STCK) = f(XIN)
28
30
VDD = 5 V
15
20
VDD = 3 V
5
at clock operation mode
f(XCIN) = 32 kHz
(POF instruction execution)
at RAM back-up mode
Ta = 25 °C
(POF2 instruction execution)
VDD = 5 V
0.1
VI = 0 V
P0, P1, RESET
VDD = 5 V
30
VDD = 3 V
50
60
120
VT+ – VT– Hysteresis
VDD = 5 V
0.2
SCK, SIN, CNTR0, CNTR1, INT0, INT1
VT+ – VT– Hysteresis RESET
VDD = 3 V
0.2
VDD = 5 V
1
VDD = 3 V
∆f(XIN)
mA
mA
mA
µA
130
60
µA
µA
15
1
µA
10
VDD = 3 V
Pull-up resistor value
Unit
4
2.8
f(XCIN) = 32 kHz
f(RING)
2.8
3.2
f(STCK) = f(XIN)
f(STCK) = f(XIN)/8
VDD = 3 V
f(XIN) = 4 MHz
RPU
Max.
On-chip oscillator clock frequency
VDD = 5 V
Frequency error
VDD = 3 V
VDD = 5 V ± 10 %, Ta = 25 °C
6
125
kΩ
250
V
V
0.4
1
0.5
2
1
3
MHz
1.8
±17
%
(with RC oscillation,
RCOM
RSEG
error of external R, C not included )
VDD = 5 V ± 10 %, Ta = 25 °C
(Note)
COM output impedance
VDD = 5 V
SEG output impedance
VDD = 3 V
VDD = 5 V
±17
VDD = 3 V
RVLC
Internal resistor for LCD power supply
1.5
2
7.5
1.5
7.5
2
10
kΩ
10
When dividing resistor 2r ✕ 3 selected
300
480
960
When dividing resistor 2r ✕ 2 selected
200
320
When dividing resistor r ✕ 3 selected
150
When dividing resistor r ✕ 2 selected
100
240
160
640
480
kΩ
kΩ
320
Note: When RC oscillation is used, use the external 33 pF capacitor (C).
Rev.2.00 Aug, 06 2004
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3-6
APPENDIX
3.1 Electrical characteristics
4524 Group
3.1.4 A/D converter recommended operating conditions
Table 3.1.6 A/D converter recommended operating conditions
(Comparator mode selected, Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
Supply voltage
VDD
Conditions
Ta = 25 °C
Ta = –20 to 85 °C
VIA
Analog input voltage
f(XIN)
Oscillation frequency
VDD = 2.7 to 5.5 V
Min.
Limits
Typ.
Max.
2.7
5.5
3
5.5
0
VDD
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
0.8
0.4
f(STCK) = f(XIN)/2
0.2
f(STCK) = f(XIN)
0.1
Unit
V
V
MHz
Table 3.1.7 A/D converter characteristics
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
–
–
Resolution
Linearity error
Ta = 25 °C, VDD = 2.7 V to 5.5 V
–
Differential non-linearity error
Ta = 25 °C, VDD = 2.7 V to 5.5 V
V0T
Zero transition voltage
VDD = 5.12 V
VFST
Full-scale transition voltage
IADD
A/D operating current
VDD = 5 V
(Note 1)
VDD = 3 V
A/D conversion time
f(XIN) = 6 MHz
Min.
Limits
Typ.
Unit
Max.
10
±2
bits
LSB
±0.9
LSB
20
12
5130
3075
0.9
0.3
248
124
62
31
8
±20
±15
32
16
8
4
mV
Ta = –20 °C to 85 ° C, VDD = 3 V to 5.5 V
Ta = –20 °C to 85 ° C, VDD = 3 V to 5.5 V
TCONV
10
VDD = 3.072 V
VDD = 5.12 V
0
0
5110
5120
VDD = 3.072 V
3063
3069
0.3
0.1
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
–
Comparator resolution
–
Comparator error (Note 2)
VDD = 5.12 V
–
Comparator comparison time
VDD = 3.072 V
f(XIN) = 6 MHz
6
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
mV
mA
µs
bits
mV
µs
Notes 1: When the A/D converter is used, IADD is added to IDD (supply current).
2: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison
voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref
Vref =
VDD
256
✕n
n = Value of register AD (n = 0 to 255)
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-7
APPENDIX
3.1 Electrical characteristics
4524 Group
3.1.5 Voltage drop detection circuit characteristics
Table 3.1.8 Voltage drop detection circuit characteristics
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Test conditions
Parameter
Min.
3.3
2.7
Ta = 25 °C
VRST
Detection voltage (Note 1)
IRST
Operation current
at power down
VDD = 5 V
VDD = 3 V
Detection time
(Note 2)
VDD → (VRST–0.1 V) (Note 3)
TRST
Limits
Typ.
3.5
50
30
0.2
Max.
3.7
4.2
100
60
1.2
Unit
V
µA
ms
Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
2: After the SVDE instruction is executed, the voltage drop detection circuit is valid at power down mode.
3: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST–0.1 V].
3.1.6 Basic timing diagram
Machine cycle
Parameter
Mi
Mi+1
Pin (signal) name
System clock
STCK
Port D output
D0–D9
Port D input
D0–D7
Ports P0, P1, P2, P3, P00–P03
P10–P13
P4 output
P20–P23
P30–P33
P40–P43
Ports P0, P1, P2, P3, P00–P03
P10–P13
P4 input
P20–P23
P30–P33
P40–P43
Interrupt input
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
INT0, INT1
3-8
APPENDIX
3.2 Typical characteristics
4524 Group
3.2 Typical characteristics
The data described below are characteristic examples for the 4524 Group.
Unless otherwise noted, the characteristics for Mask ROM version are shown here.
The data shown here are just characteristics examples and are not guaranteed.
For rated values, refer to “3.1 Electrical characteristics”.
Standard characteristics are different between Mask ROM version and One Time PROM version, due to the
difference in the manufacturing processes.
Even in the MCUs which have the same memory type, standard characteristics are different in each sample, too.
3.2.1 V DD–IDD characteristics
(1) High-speed mode (ceramic resonance): V DD–IDD
Measurement condition: f(X IN) = 6 MHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 °C
4
3.5
High-speed through mode
3
I DD [mA]
2.5
High-speed frequency/2 mode
2
High-speed frequency/4 mode
High-speed frequency/8 mode
1.5
1
0.5
0
2
2.5
3
3.5
VDD [V]
4
4.5
5
5.5
(2) High-speed mode (ceramic resonance): VDD–I DD
Measurement condition: f(X IN) = 4 MHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 °C
3
2.5
High-speed through mode
I DD [mA]
2
High-speed frequency/2 mode
1.5
High-speed frequency/4 mode
High-speed frequency/8 mode
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD [V]
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3-9
APPENDIX
3.2 Typical characteristics
4524 Group
(3) High-speed mode (ceramic resonance): VDD–I DD
Measurement condition: f(X IN) = 2 MHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 °C
2
1.8
High-speed through mode
I DD [mA]
1.6
1.4
High-speed frequency/2 mode
1.2
High-speed frequency/4 mode
High-speed frequency/8 mode
1
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
(4) High-speed mode (ceramic resonance): VDD–I DD
Measurement condition: f(X IN) = 1 MHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 °C
1.8
1.6
High-speed through mode
1.4
High-speed frequency/2 mode
High-speed frequency/4 mode
I DD [mA]
1.2
High-speed frequency/8 mode
1
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD [V]
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3-10
APPENDIX
3.2 Typical characteristics
4524 Group
(5) High-speed mode (ceramic resonance): V DD–IDD
Measurement condition: f(X IN) = 400 kHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 °C
1.2
1.1
1
High-speed through mode
0.9
High-speed frequency/2 mode
High-speed frequency/4 mode
0.8
I DD [mA]
0.7
High-speed frequency/8 mode
0.6
0.5
0.4
0.3
0.2
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD [V]
(6) High-speed mode (on-chip oscillator): V DD–IDD
Measurement condition: f(X IN) = stop f(X CIN) = stop, Ta = 25 °C
1.2
1.1
1
0.9
High-speed through mode
0.8
I DD [mA]
0.7
0.6
High-speed frequency/2 mode
0.5
0.4
High-speed frequency/4 mode
0.3
High-speed frequency/8 mode
0.2
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
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3-11
APPENDIX
3.2 Typical characteristics
4524 Group
(7) High-speed mode (RC oscillation): R–I DD
Measurement condition: f(X CIN) = stop, f(RING) = stop, V DD = 5.0 V, C = 33 pF, Ta = 25 °C
2.6
2.4
2.2
2
1.8
I DD [mA]
1.6
1.4
1.2
1
0.8
High-speed
High-speed
High-speed
High-speed
0.6
0.4
through mode
frequency/2 mode
frequency/4 mode
frequency/8 mode
0.2
0
0
2
4
6
8
10
12
14
16
18
20
Resistor R [kΩ]
(8) High-speed mode (RC oscillation): R–I DD
Measurement condition: f(X CIN) = stop, f(RING) = stop, V DD = 3.0 V, C = 33 pF, Ta = 25 °C
1.3
1.2
1.1
1
0.9
I DD [mA]
0.8
0.7
0.6
0.5
0.4
0.3
High-speed through mode
High-speed frequency/2 mode
High-speed frequency/4 mode
High-speed frequency/8 mode
0.2
0.1
0
0
2
4
6
8
10
12
14
16
18
20
Resistor R [kΩ]
Rev.2.00 Aug, 06 2004
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3-12
APPENDIX
3.2 Typical characteristics
4524 Group
(9) Low-speed mode (quartz-crystal oscillation): VDD–IDD
Measurement condition: f(X IN) = stop, f(X CIN) = 32 kHz, f(RING) = stop, Ta = 25 °C
50
45
40
Low-speed through mode
I DD [µA]
35
30
Low-speed frequency/2 mode
25
Low-speed frequency/4 mode
Low-speed frequency/8 mode
20
15
10
5
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
(10) Clock operating mode (POF instruction execution): V DD–I DD
Measurement condition: f(X IN) = stop, f(X CIN) = 32 kHz, f(RING) = stop, Ta = 25 °C
50
45
40
I DD [µA]
35
30
25
20
15
10
5
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
Rev.2.00 Aug, 06 2004
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3-13
APPENDIX
3.2 Typical characteristics
4524 Group
(11) RAM back-up mode (POF2 instruction execution): V DD–I DD
Measurement condition: f(X IN) = stop, f(X CIN) = stop, f(RING) = stop, Ta = 25 °C
100
90
80
70
60
I DD [nA]
50
40
30
20
10
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD [V]
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3-14
APPENDIX
3.2 Typical characteristics
4524 Group
3.2.2 Frequency characteristics
(1) On-chip oscillator frequency characteristics: V DD–f(RING)
4
3.5
f(RING) [MHz]
3
Ta = –30 °C
2.5
Ta = 25 °C
2
Ta = 95 °C
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
(2) On-chip oscillator frequency characteristics: Ta–f(RING)
3
2.5
f(RING) [MHz]
2
V DD = 5.0 V
1.5
1
V DD = 3.0 V
0.5
0
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Ta [°C]
Rev.2.00 Aug, 06 2004
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3-15
APPENDIX
3.2 Typical characteristics
4524 Group
(3) RC oscillation frequency characteristics: R-f(XIN)
Measurement condition: V DD = 5.0 V, C = 33pF, Ta = 25 °C
7
6
5
f(XIN) [MHz]
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Resistor R [kΩ]
(4) RC oscillation frequency characteristics (Ta-f(X IN))
Measurement condition: V DD = 5.0 V, C = 33pF
7
6
R = 3.3 kΩ
f(X IN)[MHz]
5
R = 4.7 kΩ
4
R = 6.8 kΩ
3
R = 9.1 kΩ
2
R = 15 kΩ
R = 20 kΩ
1
0
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Ta [°C]
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-16
APPENDIX
3.2 Typical characteristics
4524 Group
(5) RC oscillation frequency characteristics: R-f(X IN)
Measurement condition: V DD = 3.0 V, C = 33pF, Ta = 25 °C
7
6
5
f(XIN) [MHz]
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Resistor R [kΩ]
(6) RC oscillation frequency characteristics (Ta-f(X IN))
Measurement condition: V DD = 3.0 V, C = 33pF
7
6
R = 3.3 kΩ
f(X IN)[MHz]
5
4
R = 4.7 kΩ
3
R = 6.8 kΩ
R = 9.1 kΩ
2
R = 15 kΩ
R = 20 kΩ
1
0
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Ta [°C]
Rev.2.00 Aug, 06 2004
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3-17
APPENDIX
3.2 Typical characteristics
4524 Group
3.2.3 Port typical characteristics (V DD = 5.0 V)
(1) Ports P0, P1, P4, D0–D 6: V OH–I OH
Measurement condition: VDD = 5.0 V
-100
-90
-80
-70
I OH [mA]
-60
-50
Ta = –30 °C
Ta = 25 °C
Ta = 95 °C
-40
-30
-20
-10
0
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VOH [V]
(2) Ports D 7, C: V OH–I OH
Measurement condition: VDD = 5.0 V
-100
Ta = –30 °C
-90
Ta = 25 °C
-80
Ta = 95 °C
I OH [mA]
-70
-60
-50
-40
-30
-20
-10
0
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VOH [V]
Rev.2.00 Aug, 06 2004
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3-18
APPENDIX
3.2 Typical characteristics
4524 Group
(3) Ports P0, P1, P4: V OL–I OL
Measurement condition: V DD = 5.0 V
Ta = –30 °C
100
90
Ta = 25 °C
80
Ta = 95 °C
I OL [mA]
70
60
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOL [V]
(4) Ports D 0–D 9, C: V OL–I OL
Measurement condition: V DD = 5.0 V
Ta = –30 °C
100
90
Ta = 25 °C
80
Ta = 95 °C
70
I OL [mA]
60
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOL [V]
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-19
APPENDIX
3.2 Typical characteristics
4524 Group
(5) Ports P2, P3, RESET: VOL–I OL
Measurement condition: VDD = 5.0 V
100
90
80
70
60
Ta = –30 °C
I OL [mA]
50
Ta = 25 °C
40
Ta = 95 °C
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOL [V]
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-20
APPENDIX
3.2 Typical characteristics
4524 Group
3.2.4 Port typical characteristics (V DD = 3.0 V)
(1) Ports P0, P1, P4, D 0–D 6: V OH–I OH
Measurement condition: V DD = 3.0 V
-50
-45
-40
-35
I OH [mA]
-30
-25
-20
Ta = –30 °C
Ta = 25 °C
Ta = 95 °C
-15
-10
-5
0
3
2.5
2
1.5
1
0.5
0
VOH [V]
(2) Ports D 7, C: V OH–I OH
Measurement condition: V DD = 3.0 V
-50
-45
-40
Ta = –30 °C
-35
I OH [mA]
Ta = 25 °C
Ta = 95 °C
-30
-25
-20
-15
-10
-5
0
3
2.5
2
1.5
1
0.5
0
VOH [V]
Rev.2.00 Aug, 06 2004
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3-21
APPENDIX
3.2 Typical characteristics
4524 Group
(3) Ports P0, P1, P4: VOL-IOL
Measurement condition: VDD = 3.0 V
50
45
Ta = –30 °C
40
Ta = 25 °C
35
Ta = 95 °C
30
I OL [mA]
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
VOL [V]
(4) Ports D0 –D 9, C: V OL-I OL
Measurement condition: VDD = 3.0 V
50
45
Ta = –30 °C
40
Ta = 25 °C
I OL [mA]
35
Ta = 95 °C
30
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
VOL [V]
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-22
APPENDIX
3.2 Typical characteristics
4524 Group
(5) Ports P2, P3, RESET: V OL-I OL
Measurement condition: V DD = 3.0 V
50
45
40
35
30
I OL [mA]
25
Ta = –30 °C
Ta = 25 °C
20
Ta = 95 °C
15
10
5
0
0
0.5
1
1.5
2
2.5
3
VOL [V]
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-23
APPENDIX
3.2 Typical characteristics
4524 Group
3.2.5 Input threshold characteristics
(1) Ports P0–P4, D 0–D 7 , VDCE: VDD-VIH, V DD-VIL
Measurement condition: Ta = 25 °C
5
4.5
4
3.5
VIH/V IL [V]
3
VIH
VIL
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
(2) XIN: VDD-V IH, V DD-VIL
Measurement condition: Ta = 25 °C
5
4.5
4
3.5
VIH/V IL [V]
3
VIH
VIL
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
Rev.2.00 Aug, 06 2004
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3-24
APPENDIX
3.2 Typical characteristics
4524 Group
(3) X CIN: VDD-V IH, V DD-VIL
Measurement condition: Ta = 25 °C
5
4.5
4
3.5
VIH/V IL [V]
3
VIH
VIL
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD [V]
(4) RESET: V DD-VIH, V DD-VIL
Measurement condition: Ta = 25 °C
5
4.5
4
VIH
VIH/V IL [V]
3.5
3
VIL
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD [V]
Rev.2.00 Aug, 06 2004
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3-25
APPENDIX
3.2 Typical characteristics
4524 Group
(5) SCK , S IN, CNTR0, CNTR1, INT0, INT1: VDD-V IH, V DD-V IL
Measurement condition: Ta = 25 °C
5
4.5
4
3.5
VIH/V IL [V]
3
VIH
VIL
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
Rev.2.00 Aug, 06 2004
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3-26
APPENDIX
3.2 Typical characteristics
4524 Group
3.2.6 Pull-up resistor: V DD–RPU characteristics example
(1) Ports P0, P1, RESET: V DD-RPU
Measurement condition: V I = 0 V
300
275
250
225
R PU (kΩ)
200
175
150
125
100
75
Ta = 95 °C
50
Ta = 25 °C
Ta = –30 °C
25
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD (V)
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APPENDIX
3.2 Typical characteristics
4524 Group
3.2.7 Internal resistor for LCD power: Ta–R VLC
(1) V DD = 5.0 V: Ta-R VLC
600
550
2r ✕ 3
500
450
R VLC (kΩ)
400
350
300
r ✕ 3
250
200
150
100
50
0
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Ta [°C]
(2) VDD = 3.0 V: Ta-R VLC
600
550
2r ✕ 3
500
450
400
R VLC (kΩ)
350
300
r ✕ 3
250
200
150
100
50
0
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Ta [°C]
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APPENDIX
3.2 Typical characteristics
4524 Group
3.2.8 A/D converter typical characteristics
15
1LSB WIDTH
+1LSB
➀
0
➂
➃
➄
ERROR
0
1LSB WIDTH [mV]
ERROR [mV]
➁
-1LSB
-15
0
1
1022 1023
Fig. 3.2.1 A/D conversion characteristics data
Figure 3.2.1 shows the A/D accuracy measurement data.
(1) Non-linearity error ......................... This means a deviation from the ideal characteristics between V0 to
V1022 of actual A/D conversion characteristics. In Figure 3.2.1, it is
(➃–➀)/1LSB.
(2) Differential non-linearity error ..... This means a deviation from the ideal characteristics between the
input voltages V 0 to V 1022 necessary to change the output data to
“1.” In Figure 3.2.1, this is ➁/1LSB.
(3) Zero transition error ..................... This means a deviation from the ideal characteristics between the
input voltages 0 to VDD when the output data changes from “0” to “1.”
In Figure 3.2.1, this is the value of ➀.
(4) Full-scale transition error ............. This means a deviation from the ideal characteristics between the
input voltages 0 to V DD when the output data changes from “1022”
to “1023.” In Figure 3.2.1, this is the value of ➄.
(5) Absolute accuracy ........................ This means a deviation from the ideal characteristics between 0 to
VDD of actual A/D conversion characteristics. In Figure 3.2.1, this is
the value of ERROR in each of ➀, ➂, ➃ and ➄.
For the A/D converter characteristics, refer to the section 3.1 Electrical characteristics.
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APPENDIX
3.2 Typical characteristics
4524 Group
(1) V DD = 5.12 V
Measurement condition: f(X IN) = 4 MHz (high-speed through mode), Ta = 25 °C
ERROR/1LSB WIDTH [mV]
15
Error
10
5
1LSB Width
0
-5
-10
-15
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
416
432
448
464
480
496
512
672
688
704
720
736
752
768
928
944
960
976
992
1008
1024
STEP No.
ERROR/1LSB WIDTH [mV]
15
10
Error
5
1LSB Width
0
-5
-10
-15
256
272
288
304
320
336
352
368
384
400
STEP No.
ERROR/1LSB WIDTH [mV]
15
10
Error
5
0
1LSB Width
-5
-10
-15
512
528
544
560
576
592
608
624
640
656
STEP No.
ERROR/1LSB WIDTH [mV]
15
10
Error
5
1LSB Width
0
-5
-10
-15
768
784
800
816
832
848
864
880
896
912
STEP No.
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APPENDIX
3.2 Typical characteristics
4524 Group
(2) VDD = 3.072 V
Measurement condition: f(X IN) = 2 MHz (high-speed through mode), Ta = 25 °C
ERROR/1LSB WIDTH [mV]
9
6
Error
3
0
1LSB Width
-3
-6
-9
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
416
432
448
464
480
496
512
672
688
704
720
736
752
768
928
944
960
976
992
1008
1024
ERROR/1LSB WIDTH [mV]
STEP No.
9
6
Error
3
0
1LSB Width
-3
-6
-9
256
272
288
304
320
336
352
368
384
400
ERROR/1LSB WIDTH [mV]
STEP No.
9
6
Error
3
0
1LSB Width
-3
-6
-9
512
528
544
560
576
592
608
624
640
656
ERROR/1LSB WIDTH [mV]
STEP No.
9
6
Error
3
0
1LSB Width
-3
-6
-9
768
784
800
816
832
848
864
880
896
912
STEP No.
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APPENDIX
3.2 Typical characteristics
4524 Group
3.2.9 Analog input current characteristics example
(1) f(X IN) = 6 MHz, V DD = 5.0 V: V AIN–I AIN
Measurement condition: High-speed through mode, Ta = 25 °C
250
200
150
100
I AIN (nA)
50
0
-50
-100
-150
-200
-250
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V AIN (V)
(2) f(X IN ) = 4 MHz, V DD = 5.0 V: V AIN–IAIN
Measurement condition: High-speed through mode, Ta = 25 °C
150
120
90
60
I AIN (nA)
30
0
-30
-60
-90
-120
-150
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VAIN (V)
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APPENDIX
3.2 Typical characteristics
4524 Group
(3) f(X IN ) = 2 MHz, V DD = 5.0 V: V AIN–IAIN
Measurement condition: High-speed through mode, Ta = 25 °C
100
80
60
40
I AIN (nA)
20
0
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VAIN (V)
(4) f(X IN) = 1 MHz, V DD = 5.0 V: V AIN–I AIN
Measurement condition: High-speed through mode, Ta = 25 °C
50
40
30
20
I AIN (nA)
10
0
-10
-20
-30
-40
-50
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VAIN (V)
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APPENDIX
3.2 Typical characteristics
4524 Group
(5) f(X IN ) = 6 MHz, V DD = 3.0 V: V AIN–IAIN
Measurement condition: High-speed through mode, Ta = 25 °C
250
200
150
100
I AIN (nA)
50
0
-50
-100
-150
-200
-250
0
0.5
1
1.5
2
2.5
3
VAIN (V)
(6) f(X IN) = 4 MHz, V DD = 3.0 V: V AIN–I AIN
Measurement condition: High-speed through mode, Ta = 25 °C
150
120
90
60
I AIN (nA)
30
0
-30
-60
-90
-120
-150
0
0.5
1
1.5
2
2.5
3
V AIN (V)
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APPENDIX
3.2 Typical characteristics
4524 Group
(7) f(X IN ) = 2 MHz, V DD = 3.0 V: V AIN–IAIN
Measurement condition: High-speed through mode, Ta = 25 °C
100
80
60
40
I AIN (nA)
20
0
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
V AIN (V)
(8) f(X IN) = 1 MHz, V DD = 3.0 V: V AIN–I AIN
Measurement condition: High-speed through mode, Ta = 25 °C
50
40
30
20
I AIN (nA)
10
0
-10
-20
-30
-40
-50
0
0.5
1
1.5
2
2.5
3
V AIN (V)
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APPENDIX
3.2 Typical characteristics
4524 Group
3.2.10 A/D converter operation current (V DD–IA DD) characteristics
Measurement condition: Ta = 25 °C
200
180
160
IA DD [µA]
140
120
100
80
60
40
20
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD [V]
3.2.11 Voltage drop detection circuit characteristics
(1) Detection voltage (Mask ROM version): Ta–VRST
5
4.5
V RST [V]
4
3.5
3
2.5
2
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Ta [°C]
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APPENDIX
3.2 Typical characteristics
4524 Group
(2) Detection voltage (One Time PROM version): Ta–V RST
5
4.5
V RST [V]
4
3.5
3
2.5
2
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Ta [°C]
(3) Operation current: V DD–I RST
Measurement condition: Ta = 25 °C
100
90
80
I RST [µA]
70
60
50
40
30
20
10
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD [V]
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APPENDIX
4524 Group
3.3 List of precautions
3.3 List of precautions
3.3.1 Program counter
Make sure that the PC H does not specify after the last page of the built-in ROM.
3.3.2 Stack registers (SKS )
Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels.
However, one of stack registers is used respectively when using an interrupt service routine and when
executing a table reference instruction. Accordingly, be careful not to over the stack when performing these
operations together.
3.3.3 Notes on I/O port
(1) Note when ports P0, P1, P4 and D0–D 7 are used as an input port
In the following conditions, the pin state of port P0, P1, P4 or D0–D7 is transferred as input data to
register A when the corresponding input instruction is executed.
• Set bit i (i=0, 1, 2 or 3) of register FR0, FR1, FR2 or FR3 to “0” according to the port to be used.
• Set the output latch of the specified port to “1” with the corresponding output instruction.
If bit i of FR0, FR1, FR2 or FR3 is “0” and the output latch is set to “0,” “0” is output to specified
port.
If bit i of FR0, FR1, FR2 or FR3 is “1”, the output latch value is output to specified port.
(2) Note when ports P2 and P3 are used as an input port
In the following condition, the pin state of port P2 or P3 is transferred as input data to register A when
the IAP2 or IAP3 instruction is executed.
• Set the output latch of specified port P2i or P3i (i=0, 1, 2 or 3) to “1” with the OP2A or OP3A
instruction.
If the output latch is “0”, “0” is output to specified port P2 or P3.
(3) Noise and latch-up prevention
Connect an approximate 0.1 µF bypass capacitor directly to the VSS line and the V DD line with the
thickest possible wire at the shortest distance, and equalize its wiring in width and length.
The CNVSS pin is also used as the V PP pin (programming voltage = 12.5 V) at the One Time PROM
version.
Connect the CNVSS/VPP pin to V SS through an approximate 5 kΩ resistor which is connected to the
CNV SS/V PP pin at the shortest distance.
(4) Multifunction
• Be careful that the output of ports D8 and D9 can be used even when INT0 and INT1 pins are selected.
• Be careful that the input of ports D4–D6 can be used even when SIN, SOUT and SCK pins are selected.
• Be careful that the input/output of port D7 can be used even when input of CNTR0 pin is selected.
• Be careful that the input of port D 7 can be used even when output of CNTR0 pin is selected.
• Be careful that the “H” output of port C can be used even when output of CNTR1 pin is selected.
(5) Connection of unused pins
Table 3.3.1 shows the connections of unused pins.
(6) SD, RD, SZD instructions
When the SD and RD instructions are used, do not set “1010 2” or more to register Y.
When the SZD instructions is used, do not set “1000 2” or more to register Y.
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APPENDIX
4524 Group
3.3 List of precautions
(7) Port D 8/INT0 pin
When the power down mode is used by clearing the bit 3 of register I1 to “0” and setting the input
of INT0 pin to be disabled, be careful about the following note.
• When the input of INT0 pin is disabled (register I1 3 = “0”), clear bit 0 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(8) Port D 9/INT1 pin
When the power down mode is used by clearing the bit 3 of register I2 to “0” and setting the input
of INT1 pin to be disabled, be careful about the following note.
• When the input of INT1 pin is disabled (register I2 3 = “0”), clear bit 2 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
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APPENDIX
4524 Group
3.3 List of precautions
Table 3.3.1 Connections of unused pins
Connection
Pin
Usage condition
Connect to V SS. Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1)
XIN
Sub-clock input is selected for system clock (MR 0=1).
(Note 2)
Open.
XOUT
Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1)
RC oscillator is selected (CRCK instruction is executed)
External clock input is selected for main clock (CMCK instruction is executed). (Note 3)
Sub-clock input is selected for system clock (MR 0=1).
(Note 2)
Connect to V SS. Sub-clock is not used.
XCIN
Open.
XCOUT
Sub-clock is not used.
Open.
D0–D3
Connect to V SS. N-channel open-drain is selected for the output structure.
(Note 4)
Open.
D4/S IN
S IN pin is not selected.
Connect to V SS. N-channel open-drain is selected for the output structure.
Open.
D5/S OUT
Connect to V SS. N-channel open-drain is selected for the output structure.
Open.
D6/S CK
S CK pin is not selected.
Connect to V SS. N-channel open-drain is selected for the output structure.
Open.
D7/CNTR0
CNTR0 input is not selected for timer 1 count source.
Connect to V SS. N-channel open-drain is selected for the output structure.
Open.
D8/INT0
“0” is set to output latch.
Connect to V SS.
Open.
D9/INT1
“0” is set to output latch.
Connect to V SS.
Open.
C/CNTR1
CNTR1 input is not selected for timer 3 count source.
Open.
P00–P03
The key-on wakeup function is not selected.
(Note 4)
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 5)
The pull-up function is not selected.
(Note 4)
The key-on wakeup function is not selected.
(Note 4)
Open.
P10–P13
The key-on wakeup function is not selected.
(Note 4)
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 5)
The pull-up function is not selected.
(Note 4)
The key-on wakeup function is not selected.
(Note 4)
Open.
P20/A IN0–
Connect to Vss.
P23/AIN3
Open.
P30/A IN4–
Connect to Vss.
P33/AIN7
Open.
P40–P43
Connect to Vss. N-channel open-drain is selected for the output structure.
(Note 4)
COM0–COM3 Open.
Open.
VLC3/SEG0
SEG0 pin is selected.
Open.
VLC2/SEG1
SEG1 pin is selected.
Open.
VLC1/SEG2
SEG2 pin is selected.
SEG3–SEG 19 Open.
Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator)
is selected for main clock.
2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting “1” to bit 1 (MR1)
of clock control register MR, main clock is stopped.
3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input
for the main clock.
4: Be sure to select the output structure of ports D0–D3 and P40–P43 and the pull-up function and keyon wakeup function of P0 0–P0 3 and P1 0–P13 with every one port. Set the corresponding bits of
registers for each port.
5: Be sure to select the output structure of ports P0 0–P03 and P10–P1 3 with every two ports. If only
one of the two pins is used, leave another one open.
(Note when connecting unused pins to V SS or V DD)
● Connect the unused pins to V SS or V DD using the thickest wire at the shortest distance against noise.
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APPENDIX
4524 Group
3.3 List of precautions
3.3.4 Notes on interrupt
(1) Setting of INT0 interrupt valid waveform
Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction.
Depending on the input state of D 8/INT0 pin, the external interrupt request flag (EXF0) may be set
to “1” when the bit 2 of register I1 is changed.
(2) Setting of INT0 pin input control
Set a value to the bit 3 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction.
Depending on the input state of D 8/INT0 pin, the external interrupt request flag (EXF0) may be set
to “1” when the bit 3 of register I1 is changed.
(3) Setting of INT1 interrupt valid waveform
Set a value to the bit 2 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction.
Depending on the input state of D 9/INT1 pin, the external interrupt request flag (EXF1) may be set
to “1” when the bit 2 of register I2 is changed.
(4) Setting of INT1 pin input control
Set a value to the bit 3 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to
“0” after executing at least one instruction.
Depending on the input state of D 9/INT1 pin, the external interrupt request flag (EXF1) may be set
to “1” when the bit 3 of register I2 is changed.
(5) Multiple interrupts
Multiple interrupts cannot be used in the 4524 Group.
(6) Notes on interrupt processing
When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt
disable state). In order to enable the interrupt at the same time when system returns from the
interrupt, write EI and RTI instructions continuously.
(7) D 8/INT0 pin
When the external interrupt input pin INT0 is used, set the bit 3 of register I1 to “1”.
Even in this case, port D 8 output function is valid.
Also, the EXF0 flag is set to “1” when bit 3 of register I1 is set to “1” by input of a valid waveform
(valid waveform causing external 0 interrupt) even if it is used as an output port D 8.
(8) D 9/INT1 pin
When the external interrupt input pin INT1 is used, set the bit 3 of register I2 to “1”.
Even in this case, port D 9 output function is valid.
Also, the EXF1 flag is set to “1” when bit 3 of register I2 is set to “1” by input of a valid waveform
(valid waveform causing external 1 interrupt) even if it is used as an output port D 9.
(9) POF instruction, POF2 instruction
When the POF or POF2 instruction is executed continuously after the EPOF instruction, system
enters the power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction
and the POF or POF2 instruction continuously.
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APPENDIX
4524 Group
3.3 List of precautions
3.3.5 Notes on timer
(1) Prescaler
Stop counting and then execute the TABPS instruction to read from prescaler data.
Stop counting and then execute the TPSAB instruction to set prescaler data.
(2) Count source
Stop timer 1, 2, 3, 4 or LC counting to change its count source.
(3) Reading the count values
Stop timer 1, 2, 3 or 4 counting and then execute the TAB1, TAB2, TAB3 or TAB4 instruction to
read its data.
(4) Writing to the timer
Stop timer 1, 2, 3, 4 or LC counting and then execute the T1AB, T2AB, T3AB, T4AB or TLCA
instruction to write its data.
(5) Writing to reload register R1, reload register R3 and reload register R4H
When writing data to reload register R1 while timer 1 is operating respectively, avoid a timing when
timer 1 underflows.
When writing data to reload register R3 while timer 3 is operating respectively, avoid a timing when
timer 3 underflows.
When writing data to reload register R4H while timer 4 is operating respectively, avoid a timing when
timer 4 underflows.
(6) Timer 4
• Avoid a timing when timer 4 underflows to stop timer 4.
• When “H” interval extension function of the PWM signal is set to be “valid”, set “0116” or more to
reload register R4H.
(7) Timer 5
Stop timer 5 counting to change its count source.
(8) Timer input/output pin
• Set the port C output latch to “0” to output the PWM signal from C/CNTR1 pin.
(9) Watchdog timer
• The watchdog timer function is valid after system is released from reset. When not using the
watchdog timer function, stop the watchdog timer function and execute the DWDT instruction, the
WRST instruction continuously, and clear the WEF flag to “0”.
• The watchdog timer function is valid after system is returned from the power down state. When not
using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction
and the WRST instruction continuously every system is returned from the power down state.
• When the watchdog timer function and power down function are used at the same time, initialize
the flag WDF1 with the WRST instruction before system enters into the power down state.
(10) Pulse width input to CNTR0 pin, CNTR1 pin
Refer to section “3.1 Electrical characteristics” for rating value of pulse width input to CNTR0 pin,
CNTR1 pin.
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APPENDIX
3.3 List of precautions
4524 Group
3.3.6 Notes on A/D conversion
(1) Note when the A/D conversion starts again
When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous
input data is invalidated and the A/D conversion starts again.
(2) A/D converter-1
Each analog input pin is equipped with a capacitor which is used to compare the analog voltage.
Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/
discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce
the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins.
Figure 3.3.1 shows the analog input external circuit example-1.
When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit
in order to keep the voltage within the rated range as shown the Figure 3.3.2. In addition, test the
application products sufficiently.
Sensor
About 1kΩ
AIN
Sensor
AIN
Apply the voltage withiin the specifications
to an analog input pin.
Fig. 3.3.2 Analog input external circuit example-2
Fig. 3.3.1 Analog input external circuit example-1
(3) Notes for the use of A/D conversion 2
Do not change the operating mode of the A/D converter by bit 3 of register Q1 during A/D conversion
(A/D conversion mode and comparator mode).
(4) Notes for the use of A/D conversion 3
When the operating mode of the A/D converter is changed from the comparator mode to the A/D
conversion mode with bit 3 of register Q1 in a program, be careful about the following notes.
• Clear bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the
comparator mode to the A/D conversion mode (refer to Figure 3.3.3➀).
• The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D
converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a
value to bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag to “0”.
•
•
•
Clear bit 2 of register V2 to “0”.......➀
↓
Change of the operating mode of the A/D converter
from the comparator mode to the A/D conversion mode
↓
Clear the ADF flag to “0” with the SNZAD instruction
↓
Execute the NOP instruction for the case when a skip is
performed with the SNZAD instruction
•
•
•
Fig. 3.3.3 A/D converter operating mode program example
Rev.2.00 Aug, 06 2004
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3-43
APPENDIX
3.3 List of precautions
4524 Group
(5) A/D converter is used at the comparator mode
The analog input voltage is higher than the comparison voltage as a result of comparison, the
contents of ADF flag retains “0,” not set to “1.”
In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled.
Accordingly, consider the time until the comparator operation is completed, and examine the state
of ADF flag by software. The comparator operation is completed after 8 machine cycles.
(6) Analog input pins
When P20/AIN0–P23/AIN3, P3 0/AIN4–P33/AIN7 are set to pins for analog input, they cannot be used as
I/O ports P2 and P3.
(7) TALA instruction
When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is “0.”
(8) Recommended operating conditions when using A/D converter
The recommended operating conditions of supply voltage and system clock frequency when using A/
D converter are different from those when not using A/D converter.
Table 3.3.2 shows the recommended operating conditions when using A/D converter.
Table 3.3.2 Recommended operating conditions (when using A/D converter)
Parameter
Condition
System clock frequency V DD = 4.0 to 5.5 V (through mode)
(at ceramic resonance) V DD = 2.7 to 5.5 V (through mode)
(Note 2)
V DD = 2.7 to 5.5 V (Frequency/2 mode)
V DD = 2.7 to 5.5 V (Frequency/4 mode)
V DD = 2.7 to 5.5 V (Frequency/8 mode)
Limits
Unit
Min. Typ. Max.
0.1
6.0 MHz
0.1
4.4
0.1
3.0
0.1
0.1
1.5
0.7
System clock frequency V DD = 2.7 to 5.5 V (through mode)
0.1
4.4
(at RC oscillation)
V DD = 2.7 to 5.5 V (Frequency/2 mode)
0.1
(Note 2)
V DD = 2.7 to 5.5 V (Frequency/4 mode)
V DD = 2.7 to 5.5 V (Frequency/8 mode)
0.1
2.2
1.1
0.1
0.5
V DD = 4.0 to 5.5 V (through mode)
4.8
V DD = 2.7 to 5.5 V (through mode)
0.1
0.1
V DD = 2.7 to 5.5 V (Frequency/2 mode)
0.1
2.4
V DD = 2.7 to 5.5 V (Frequency/4 mode)
0.1
1.2
0.6
System clock frequency
(ceramic resonance
selected, at external
clock input)
MHz
MHz
3.2
0.1
V DD = 2.7 to 5.5 V (Frequency/8 mode)
Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set
the constants within the range of the frequency limits.
3.3.7 Notes on serial I/O
(1) Note when an external clock is used as a synchronous clock:
• An external clock is selected as the synchronous clock, the clock is not controlled internally.
• Serial transmit/receive is continued as long as an external clock is input. If an external clock is input
9 times or more and serial transmit/receive is continued, the receive data is transferred directly as
transmit data, so that be sure to control the clock externally.
Note also that the SIOF flag is set to “1” when a clock is counted 8 times.
• Be sure to set the initial input level on the external clock pin to “H” level.
• Refer to section “3.1 Electrical characteristics” when using serial I/O with an external clock.
Rev.2.00 Aug, 06 2004
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3-44
APPENDIX
3.3 List of precautions
4524 Group
3.3.8 Notes on LCD function
(1) Timer LC count source
Stop timer LC counting to change timer LC count source.
(2) Writing to timer LC
Stop timer LC counting and then execute the data write instruction (TLCA).
(3) VLC3/SEG0 pin
When the V LC3 pin function is selected, apply voltage of V LC3 < V DD to the pin externally.
(4) V LC2/SEG1 pin, VLC1/SEG 2 pin
• When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used;
Apply voltage of 0<V LC1<V LC2<V LC3 to these pins.
Short the V LC2 pin and V LC1 pin at 1/2 bias.
• When SEG 1 and SEG 2 pin function is selected;
Use the internal dividing resistor.
(5) LCD power circuit
Select the LCD power circuit suitable for LCD panel and evaluate the display state on the actual system.
3.3.9 Notes on reset
(1) Register initial value
The initial value of the following registers are undefined after system is released from reset. After
system is released from reset, set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
(2) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset
circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from
0 V to the minimum rating value of the recommended operating conditions must be set to 100 µs or
less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and V SS at the
shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the
minimum rating value of the recommended operating conditions.
3.3.10 Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage
of this product is set up lower than the minimum
value of the supply voltage of the recommended
operating conditions.
When the supply voltage of a microcomputer falls
below to the minimum value of recommended
operating conditions and re-goes up (ex. battery
exchange of an application product), depending on
the capacity value of the bypass capacitor added to
the power supply pin, the following case may cause
program failure (Figure 3.3.4);
• supply voltage does not fall below to V RST, and
• its voltage re-goes up with no reset.
In such a case, please design a system which supply
voltage is once reduced below to V RST and re-goes
up after that.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
VDD
Recommended
operatng condition
min.value
VRST
No reset
Program failure may occur.
→ Normal operation
VDD
Recommended
operatng condition
min.value
VRST
Reset
Fig. 3.3.4 V DD and VRST
3-45
APPENDIX
4524 Group
3.3 List of precautions
3.3.11 Notes on power down
(1) POF instruction, POF2 instruction
Execute the POF or POF2 instruction immediately after executing the EPOF instruction to enter the
power down state.
Note that system cannot enter the power down state when executing only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction
and the POF or POF2 instruction.
(2) Key-on wakeup function
After checking none of the return condition for ports (P0, P1, INT0 and INT1 specified with register
K0–K2) with valid key-on wakeup function is satisfied, execute the POF or POF2 instruction.
If at least one of return condition for ports with valid key-on wakeup function is satisfied, system
returns from the power downn state immediately after the POF or POF2 instruction is executed.
(3) Timer 5 interrupt request flag
When POF or POF2 instruction is executed while T5F is “1”, system returns from the power down
state immediately.
(4) Return from power down mode
After system returns from power down mode, set the undefined registers and flags.
The initial value of the following registers are undefined at power down. After system is returned from
power down mode, set initial values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
(5) Watchdog timer
• The watchdog timer function is valid after system is returned from the power down state. When not
using the watchdog timer function, stop the watchdog timer function with the DWDT instruction and
the WRST instruction continuously every system is returned from the power down.
• When the watchdog timer function and power down function are used at the same time, initialize
the flag WDF1 with the WRST instruction before system goes into the power down state.
(6) Port D 8/INT0 pin
When the power down mode is used by clearing the bit 3 of register I1 to “0” and setting the input
of INT0 pin to be disabled, be careful about the following note.
• When the input of INT0 pin is disabled (register I1 3 = “0”), clear bit 0 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(7) Port D 9/INT1 pin
When the power down mode is used by clearing the bit 3 of register I2 to “0” and setting the input
of INT1 pin to be disabled, be careful about the following note.
• When the input of INT1 pin is disabled (register I2 3 = “0”), clear bit 2 of register K2 to “0” to
invalidate the key-on wakeup before system goes into the power down mode.
(8) External clock
When the external clock signal is used as the main clock (f(X IN)), note that the power down mode
(POF or POF2 instruction) cannot be used.
Rev.2.00 Aug, 06 2004
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3-46
APPENDIX
4524 Group
3.3 List of precautions
3.3.12 Notes on oscillation circuit
(1) Clock control
Execute the CMCK or the CRCK instruction to select the main clock (f(X IN)) in the initial setting
routine of program (executing it in address 0 in page 0 is recommended).
The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation
circuit corresponding to the first executed one of these two instructions is valid. Another oscillation
circuits and the on-chip oscillator stop.
(2) On-chip oscillator
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation
temperature range.
Be careful that margin of frequencies when designing application products.
Also, the oscillation stabilize wait time after system is released from reset is generated by the onchip oscillator clock. When considering the oscillation stabilize wait time after system is released
from reset, be careful that the margin of frequencies of the on-chip oscillator clock.
(3) External clock
When the external clock signal is used as the main clock (f(X IN)), note that the power down mode
(POF or POF2 instructions) cannot be used.
(4) Value of a part connected to an oscillator
Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and
the board. Accordingly, consult the oscillator manufacturer for values of each part connected the
oscillator.
3.3.13 Electric characteristic differences between Mask ROM and One Time PROM version MCU
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation
between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing
processes.
When manufacturing an application system with the One time PROM version and then switching to use of
the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM
version.
3.3.14 Note on Power Source Voltage
When the power source voltage value of a microcomputer is less than the value which is indicated as the
recommended operating conditions, the microcomputer does not operate normally and may perform unstable
operation.
In a system where the power source voltage drops slowly when the power source voltage drops or the
power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended
operating conditions and design a system not to cause errors to the system by this unstable operation.
Rev.2.00 Aug, 06 2004
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3-47
APPENDIX
3.4 Notes on noise
4524 Group
3.4 Notes on noise
Countermeasures against noise are described below.
The following countermeasures are effective against
noise in theory, however, it is necessary not only to
take measures as follows but to evaluate before actual
use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function
as an antenna which feeds noise into the
microcomputer.
The shorter the total wiring length (by mm unit), the
less the possibility of noise insertion into a
microcomputer.
(1) Package
Select the smallest possible package to make
the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package,
for example QFP and not DIP, makes the
total wiring length short to reduce influence
of noise.
(2) Wiring for RESET input pin
Make the length of wiring which is connected
to the RESET input pin as short as possible.
Especially, connect a capacitor across the
RESET input pin and the V SS pin with the
shortest possible wiring.
● Reason
In order to reset a microcomputer correctly,
1 machine cycle or more of the width of a
pulse input into the RESET pin is required.
If noise having a shorter pulse width than
this is input to the RESET input pin, the
reset is released before the internal state
of the microcomputer is completely initialized.
This may cause a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
DIP
Reset
circuit
SDIP
SOP
VSS
RESET
VSS
QFP
O.K.
Fig. 3.4.2 Wiring for the RESET input pin
Fig. 3.4.1 Selection of packages
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3-48
APPENDIX
3.4 Notes on noise
4524 Group
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected
to clock I/O pins as short as possible.
• Make the length of wiring across the
grounding lead of a capacitor which is
connected to an oscillator and the V SS pin
of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation
from other V SS patterns.
Noise
(4) Wiring to CNVSS pin
Connect the CNV SS pin to the V SS pin with
the shortest possible wiring.
● Reason
The operation mode of a microcomputer is
influenced by a potential at the CNVSS pin.
If a potential difference is caused by the
noise between pins CNV SS and V SS , the
operation mode may become unstable. This
may cause a microcomputer malfunction or
a program runaway.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
CNVSS
VSS
VSS
O.K.
Fig. 3.4.3 Wiring for clock I/O pins
● Reason
If noise enters clock I/O pins, clock
waveforms may be deformed. This may
cause a program failure or program runaway.
Also, if a potential difference is caused by
the noise between the V SS level of a
microcomputer and the V SS level of an
oscillator, the correct clock will not be input
in the microcomputer.
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
CNVSS
N.G.
O.K.
Fig. 3.4.4 Wiring for CNV SS pin
3-49
APPENDIX
3.4 Notes on noise
4524 Group
(5) Wiring to VPP pin of built-in PROM version
In the built-in PROM version of the 4524 Group,
the CNV SS pin is also used as the built-in
PROM power supply input pin V PP .
● When the V PP pin is also used as the
CNV SS pin
Connect an approximately 5 kΩ resistor to
the VPP pin the shortest possible in series
and also to the VSS pin. When not
connecting the resistor, make the length of
wiring between the V PP pin and the V SS
pin the shortest possible (refer to Figure
3.4.5)
3.4.2 Connection of bypass capacitor across VSS
line and V DD line
Connect an approximately 0.1 µF bypass capacitor
across the V SS line and the V DD line as follows:
• Connect a bypass capacitor across the V SS pin
and the V DD pin at equal length.
• Connect a bypass capacitor across the V SS pin
and the VDD pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal
lines for V SS line and V DD line.
• Connect the power source wiring via a bypass
capacitor to the V SS pin and the V DD pin.
AA
AA
AA
AA
AA
VDD
Note: Even when a circuit which included an
approximately 5 kΩ resistor is used in the
Mask ROM version, the microcomputer
operates correctly.
● Reason
The V PP pin of the built-in PROM version
is the power source input pin for the builtin PROM. When programming in the builtin PROM, the impedance of the VPP pin is
low to allow the electric current for writing
flow into the PROM. Because of this, noise
can enter easily. If noise enters the V PP
pin, abnormal instruction codes or data are
read from the built-in PROM, which may
cause a program runaway.
VSS
N.G.
AA
AA
AA
AA
AA
VDD
VSS
O.K.
Fig. 3.4.6 Bypass capacitor across the V SS line
and the V DD line
When the VPP pin is also used as the CNVSS pin
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.5 Wiring for the V PP pin of the built-in
PROM version
Rev.2.00 Aug, 06 2004
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3-50
APPENDIX
3.4 Notes on noise
4524 Group
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor
to an analog signal line which is connected to an
analog input pin in series. Besides, connect the
resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across
the V SS pin and the analog input pin. Besides,
connect the capacitor to the V SS pin as close as
possible. Also, connect the capacitor across the
analog input pin and the V SS pin at equal length.
●
Reason
Signals which is input in an analog input pin
(such as an A/D converter/comparator input
pin) are usually output signals from sensor.
The sensor which detects a change of event
is installed far from the printed circuit board
with a microcomputer, the wiring to an analog
input pin is longer necessarily. This long wiring
functions as an antenna which feeds noise
into the microcomputer, which causes noise
to an analog input pin.
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates
clocks for a microcomputer operation from being
affected by other signals.
(1) Keeping oscillator away from large current
signal lines
Install a microcomputer (and especially an
oscillator) as far as possible from signal lines
where a current larger than the tolerance of
current value flows.
● Reason
In the system using a microcomputer, there
are signal lines for controlling motors, LEDs,
and thermal heads or others. When a large
current flows through those signal lines,
strong noise occurs because of mutual
inductance.
Microcomputer
Mutual inductance
M
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.8 Wiring for a large current signal line
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a
capacitor
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-51
APPENDIX
3.4 Notes on noise
4524 Group
(2) Installing oscillator away from signal lines
where potential levels change frequently
Install an oscillator and a connecting pattern
of an oscillator away from signal lines where
potential levels change frequently. Also, do
not cross such signal lines over the clock lines
or the signal lines which are sensitive to noise.
● Reason
Signal lines where potential levels change
frequently (such as the CNTR pin signal
line) may affect other lines at signal rising
edge or falling edge. If such lines cross
over a clock line, clock waveforms may be
deformed, which causes a microcomputer
failure or a program runaway.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.9 Wiring to a signal line where potential
levels change frequently
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print
a VSS pattern on the underside (soldering side)
of the position (on the component side) where
an oscillator is mounted.
Connect the VSS pattern to the microcomputer
V SS pin with the shortest possible wiring.
Besides, separate this VSS pattern from other
VSS patterns.
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as
follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port
in series.
<Software>
• As for an input port, read data several times by
a program for checking whether input levels are
equal or not.
• As for an output port or an I/O port, since the
output data may reverse because of noise, rewrite
data to its output latch at fixed periods.
• Rewrite data to pull-up control registers at fixed
periods.
3.4.6 Providing of watchdog timer function by
software
If a microcomputer runs away because of noise or
others, it can be detected by a software watchdog
timer and the microcomputer can be reset to normal
operation. This is equal to or more effective than
program runaway detection by a hardware watchdog
timer. The following shows an example of a watchdog
timer provided by software.
In the following example, to reset a microcomputer
to normal operation, the main routine detects errors
of the interrupt processing routine and the interrupt
processing routine detects errors of the main routine.
This example assumes that interrupt processing is
repeated multiple times in a single main routine
processing.
An example of VSS patterns on the
underside of a printed circuit board
AAAAAAA
AAA
AAAAAA
AAA
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 V SS pattern on the underside of an
oscillator
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3-52
APPENDIX
3.4 Notes on noise
4524 Group
<The main routine>
• Assigns a single word of RAM to a software
watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the
main routine. The initial value N should satisfy
the following condition:
N+1≥
(Counts of interrupt processing executed in
each main routine)
As the main routine execution cycle may change
because of an interrupt processing or others, the
initial value N should have a margin.
• Watches the operation of the interrupt processing
routine by comparing the SWDT contents with
counts of interrupt processing after the initial value
N has been set.
• Detects that the interrupt processing routine has
failed and determines to branch to the program
initialization routine for recovery processing in the
following case:
If the SWDT contents do not change after interrupt
processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each
interrupt processing.
• Determines that the main routine operates normally
when the SWDT contents are reset to the initial
value N at almost fixed cycles (at the fixed interrupt
processing count).
• Detects that the main routine has failed and
determines to branch to the program initialization
routine for recovery processing in the following
case:
If the SWDT contents are not initialized to the
initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
EI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
≤0
>0
RTI
Return
Main routine
errors
Fig. 3.4.11 Watchdog timer by software
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
3-53
APPENDIX
3.5 Package outline
4524 Group
3.5 Package outline
64P6N-A
Plastic 64pin 14✕14mm body QFP
EIAJ Package Code
QFP64-P-1414-0.80
Weight(g)
1.11
Lead Material
Alloy 42
MD
e
JEDEC Code
–
HD
64
b2
ME
D
49
1
I2
48
Recommended Mount Pad
HE
E
Symbol
33
16
A
32
L1
c
A2
17
b
y
Rev.2.00 Aug, 06 2004
REJ09B0107-0200Z
x
M
A1
F
e
L
Detail F
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
–
–
2.8
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
13.8
14.0
14.2
0.8
–
–
16.5
16.8
17.1
16.5
16.8
17.1
0.4
0.6
0.8
1.4
–
–
–
–
0.2
0.1
–
–
0°
10°
–
0.5
–
–
–
–
1.3
14.6
–
–
–
–
14.6
3-54
RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
4524 Group
Publication Data :
Rev.1.00 Dec 19, 2003
Rev.2.00 Aug 06, 2004
Published by :
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
4524 Group
User's Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan