M66281FP
5120 × 8-Bit × 2 Line Memory
REJ03F0254-0200
Rev.2.00
Sep 14, 2007
Description
The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and
adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits × 2.
Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the
compensation of data of multiple lines.
Features
•
•
•
•
•
•
•
•
•
•
Memory configuration:
5120 words × 8 bits × 2 (dynamic memory)
High speed cycle:
25 ns (Min)
High speed access:
18 ns (Max)
Output hold:
3 ns (Min)
Reading and writing operations can be completely carried out independently and asynchronously
Variable length delay bit
Input/output:
TTL direct connection allowable
Output:
3 states
Q00 to Q07:
1 line delay
Q10 to Q17:
2 line delay
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs
D0 to D7
Data outputs
Q0 to Q7
31 30 29 28 27 23 22 21
Input buffer
VCC
9 10 11 12 13 16 17 18
Output buffer
(
Memory array
5120 words × 8 bits × 2
Memory only for 1 line delay data
Memory only for 2 line delay data
)
Read
enable input
Read control circuit
Write
clock input
6
Read address counter
WCK 34
Write address counter
WRESB 35
Write
reset input
45 46 47 2 3 4 5
42 REB
Write control circuit
WEB 36
Write
enable input
Data outputs
Q10 to Q17
41 RRESB
Read
reset input
40 RCK
Read
clock input
8
7 GND
VCC 19
20 GND
VCC 32
33 GND
VCC 44
43 GND
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 1 of 15
M66281FP
26 NC
25 NC
28 D3
27 D4
30 D1
29 D2
32 VCC
31 D0
34 WCK
33 GND
39
24 NC
40
23 D5
41
22 D6
42
21 D7
43
20 GND
M66281FP
14
13
12
5
4
3
2
NC
Q03
Q04
Q05
Q06
Q07
GND
VCC
Q10
Q11
Q12
Q13
Q14
NC
11
15 NC
9
16 Q15
48
10
17 Q16
47
8
46
7
19 VCC
18 Q17
6
45
44
1
NC
RCK
RRESB
REB
GND
VCC
Q00
Q01
Q02
NC
36 WEB
35 WRESB
38 NC
37 NC
Pin Arrangement
(Top view)
Outline: PRQP0048JA-A (48P6S-A)
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 2 of 15
NC: No connection
M66281FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Supply voltage
Symbol
VCC
Input voltage
Output voltage
VI
VO
Power dissipation
Storage temperature
Pd
Tstg
Note:
*
Ratings
−0.3 to +4.6
Unit
V
−0.3 to VCC + 0.3
−0.3 to VCC + 0.3
V
V
540
−55 to 150
mW
°C
Conditions
Value based on the GND pin
*
Ta = 0 to 63°C. Ta > 63°C are derated at −9 mW / °C
Recommended Operating Conditions
Min
Typ
Max
Unit
Supply voltage
Supply voltage
Item
VCC
GND
Symbol
2.7
3.15
0
3.6
V
V
Operating temperature
Topr
0
70
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Min
Typ
Max
Unit
High-level input voltage
Low-level input voltage
Item
VIH
VIL
Symbol
2.0
0.8
V
V
High-level output voltage
Low-level output voltage
VOH
VOL
VCC − 0.4
0.4
V
V
IOH = −4 mA
IOL = 4 mA
High-level input current
IIH
1.0
µA
VI = VCC
Low-level input current
IIL
−1.0
µA
VI = GND
Off-state high-level output current
Off-state low-level output current
IOZH
IOZL
5.0
−5.0
µA
µA
VO = VCC
VO = GND
Average supply current during
operation
ICC
150
mA
Input capacitance
CI
10
pF
VI = VCC, GND, Output open
tWCK, tRCK = 25 ns
f = 1 MHz
Off-time output capacitance
CO
15
pF
f = 1 MHz
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 3 of 15
Test Conditions
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
M66281FP
Function
When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are written into memory only for 1 line
delay data in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is
the case, the write address counter of memory only for 1 line delay data is incremented simultaneously.
When WEB is set to "H", the writing operation is inhibited and the write address counter of memory only for 1 line
delay data stops.
When write reset input WRESB is set to "L", the write address counter of memory only for 1 line delay data is
initialized.
When read enable input REB is set to "L", the contents of memory only for 1 line delay data are output to data outputs
Q00 to Q07 and the contents of memory only for 2 line delay data are output to Q10 to Q17 in synchronization with a
rising edge of read clock input RCK to perform reading operation.
When this is the case, the read address counters of memory only for 1 line delay data and memory only for 2 line delay
data are incremented simultaneously.
In addition, data of Q00 to Q07 is written into memory only for 2 line delay data in synchronization with a rising edge
of RCK. When this is the case, the write address counter of memory only for 2 line delay data is then incremented.
When REB is set to "H", operation for reading data from memory only for 1 line delay and from memory only for 2 line
delay data is inhibited and the read address counter of each memory stops.
Outputs Q00 to Q07 and Q10 to Q17 are placed in a high impedance state. In addition, the write address counter of
memory only for 2 line delay data then stops.
When read reset input RRESB is set to "L", the read address counters of memory only for 1 line delay data as well as
the write address counter and read address counter of memory only for 2 line delay data are then initialized.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 4 of 15
M66281FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Symbol
Access time
tAC
Min
Typ
Max
18
Unit
ns
Output hold time
Output enable time
tOH
tOEN
3
3
18
ns
ns
Output disable time
tODIS
3
18
ns
Timing Requirements
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Min
Typ
Max
Unit
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Item
tWCK
tWCKH
Symbol
25
11
ns
ns
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKL
tRCK
11
25
ns
ns
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
tRCKH
tRCKL
11
11
ns
ns
Input data setup time for WCK
Input data hold time for WCK
tDS
tDH
7
3
ns
ns
Reset setup time for WCK/RCK
Reset hold time for WCK/RCK
tRESS
tRESH
7
3
ns
ns
Reset non-selection setup time for WCK/RCK
Reset non-selection hold time for WCK/RCK
tNRESS
tNRESH
7
3
ns
ns
WEB setup time for WCK
WEB hold time for WCK
tWES
tWEH
7
3
ns
ns
WEB non-selection setup time for WCK
WEB non-selection hold time for WCK
tNWES
tNWEH
7
3
ns
ns
REB setup time for RCK
REB hold time for RCK
tRES
tREH
7
3
ns
ns
REB non-selection setup time for RCK
REB non-selection hold time for RCK
tNRES
tNREH
7
3
ns
ns
Input pulse up/down time
Data hold time*
tr, tf
tH
20
20
ns
ms
Notes: Perform reset operation after turning on power supply.
* For 1 line access, the following conditions must be satisfied:
WEB high-level period ≤ 20 ms − 5120 • tWCK − WRESB low-level period
REB high-level period ≤ 20 ms − 5120 • tRCK − RRESB low-level period
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 5 of 15
M66281FP
Switching Characteristics Measurement Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3 V
Input pulse up/down time: 3 ns
Judging voltage Input:
1.3 V
Output: 1.3 V (However, tODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is
judged with 90% of the output amplitude)
Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item
SW1
SW2
tODIS (LZ)
tODIS (HZ)
Close
Open
Open
Close
tOEN (ZL)
tOEN (ZH)
Close
Open
Open
Close
tODIS and tOEN Measurement Condition
3V
RCK
1.3 V
1.3 V
GND
3V
REB
GND
tODIS (HZ)
tOEN (ZH)
VOH
90%
1.3 V
Qn
tODIS (LZ)
Qn
1.3 V
10%
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 6 of 15
tOEN (ZL)
VOL
M66281FP
Operation Timing
Write Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle
n + 4 cycle
WCK
tWCKH tWCKL tWEH tNWES
tWCK
tNWEH tWES
WEB
tDS tDH
Dn
(n)
(n + 1)
(n + 2)
(n + 4)
(n + 3)
WRESB = "H"
Write Reset Cycle
n − 1 cycle
n cycle
tWCK
tNRESH tRESS
Reset cycle
0 cycle
1 cycle
2 cycle
WCK
tRESH tNRESS
WRESB
tDS tDH
Dn
(n − 1)
(n)
(0)
(1)
(2)
WEB = "L"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 7 of 15
M66281FP
Matters that Needs Attention when WCK Stops
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
tWCK
tNWES
WEB
Dn
tDS tDH
tDS tDH
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 8 of 15
M66281FP
Read Cycle
n cycle
n + 1 cycle
n + 2 cycle
tRCK
tRCKH tRCKL
tREH tNRES
Disable cycle
n + 3 cycle
n + 4 cycle
RCK
tNREH
tRES
tAC
REB
tODIS
Q0n
(Q1n)
(n)
(n + 1)
tOEN
HIGH-Z
(n + 2)
(n + 3)
(n + 4)
tOH
RRESB = "H"
Read Reset Cycle
n − 1 cycle
n cycle
tRCK
tNRESH tRESS
Reset cycle
0 cycle
1 cycle
2 cycle
RCK
tRESH tNRESS
RRESB
tAC
Q0n
(Q1n)
(n − 1)
(n)
(0)
(0)
(0)
(1)
tOH
REB = "L"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 9 of 15
(2)
M66281FP
Notes on Reading of Written Data in Read Disable
When writing operation is performed at n cycle and n + 1 cycle on the writing side in the read disable period after n − 1
cycle on the reading side, output at n cycle and n + 1 cycle after read enable is invalid. For output at n + 2 cycle and
after, however, data written in the read disable period is to be output.
n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle n + 4 cycle n + 5 cycle n + 6 cycle n + 7 cycle
WCK
tDS tDH
(n − 1)
Dn
(n)
n − 1 cycle
(n + 1)
(n + 2)
Disable cycle
(n + 3)
(n + 4)
n cycle
(n + 5)
(n + 6)
(n + 7)
n + 1 cycle n + 2 cycle
RCK
REB
tAC
Q0n
(Q1n)
tODIS
(n − 1)
tOEN
HIGH-Z
Invalid
Invalid
(n + 2)
WEB = "L"
WRESB = "H"
RRESB = "H"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 10 of 15
M66281FP
Variable Length Delay Bit
1 Line (5120 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK
before read cycle to easily make 1 line delay.
0 cycle
1 cycle
2 cycle
5118 cycle 5119 cycle
5120 cycle 5121 cycle 5122 cycle
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRESB
RRESB
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
(5117)
(5118)
(5119)
(0')
(2')
(3')
(1)
(2)
(3)
tOH
tAC
5120 cycle
(1')
Q0n
(Q1n)
(0)
WEB, REB = "L"
n-bit Delay Bit
(Reset at cycles according to the delay length)
0 cycle
1 cycle
n − 2 cycle n − 1 cycle
2 cycle
n cycle
(0')
n + 1 cycle n + 2 cycle n + 3 cycle
(1')
(2')
(3')
WCK
RCK
tRESS tRESH
tRESS tRESH
WRESB
RRESB
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
m cycle
Q0n
(Q1n)
(n − 3)
(n − 2)
(n − 1)
tAC
(0')
(1')
(2')
(3')
(1)
(2)
(3)
tOH
(0)
WEB, REB = "L"
m≥3
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 11 of 15
M66281FP
n-bit Delay 2
(Slides input timings of WRESB and RRESB at cycles according to the delay length)
0 cycle
1 cycle
n − 2 cycle n − 1 cycle
2 cycle
n + 1 cycle n + 2 cycle n + 3 cycle
n cycle
WCK
RCK
tRESS tRESH
WRESB
tRESS tRESH
RRESB
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
(n − 2)
(n − 1)
(n)
Q0n
(Q1n)
(n + 2)
(n + 3)
(1)
(2)
(3)
tOH
tAC
m cycle
(n + 1)
(0)
WEB, REB = "L"
m≥3
n-bit Delay 3
(Slides address by disabling REB in the period according to the delay length)
0 cycle
1 cycle
n − 1 cycle
2 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tNREH tRES
REB
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
m cycle
Q0n
(Q1n)
(n − 2)
(n − 1)
(n)
tAC
(n + 1)
(n + 2)
(n + 3)
(1)
(2)
(3)
tOH
HIGH-Z
Invalid
WEB = "L"
m≥3
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 12 of 15
M66281FP
Reading Shortest n-cycle Write Data "n"
(Reading side n − 2 cycle ends after the end of writing side n + 1 cycle)
When the reading side n − 2 cycle ends before the end of the writing side n + 1 cycle, output Qn of n cycle is made
invalid. In the following diagram, end of reading side n − 2 cycle and end of writing side n + 1 cycle overlap each other.
This example can read n cycle data in the shortest time. When this is the case, reading operation at n − 1 cycle is
invalid.
n + 1 cycle
n cycle
n + 2 cycle
n + 3 cycle
WCK
(n)
Dn
(n +1)
n − 2 cycle
(n + 2)
n − 1 cycle
(n + 3)
n cycle
RCK
Q0n
(Q1n)
Invalid
(n)
Reading Longest n-cycle Write Data "n": 1 Line Delay
(When writing side n-cycle <2> starts, reading side n cycle <1> then starts)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle
<2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n − 1) <1>*
(n) <1>*
n cycle <0>*
(0) <2>*
0 cycle <1>*
(n − 1) <2>*
(n) <2>*
n cycle <1>*
RCK
Q0n
(Q1n)
(n − 1) <0>*
(n) <0>*
Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 13 of 15
(0) <1>*
(n − 1) <1>*
(n) <1>*
M66281FP
Application Example
Sub Scan Resolution Compensation Circuit with Laplacian Filter
D0 Q00
to
to
D7 Q07
B
(n + 1) line
image data
Adder
N + K {2N − (A + B) }
N
n line image data
M66281
×2
Subtractor
2N − (A + B)
1 line
delay
A
(n − 1) line
image data
2 line
delay
Sub scan direction
×K
Adder
A+B
Q10
to
Q17
Compensated
image data
Main scan direction
A
(n − 1) line
N
n line
B
(n + 1) line
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 14 of 15
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
K: Laplacian coefficient
M66281FP
Package Dimensions
JEITA Package Code
P-QFP48-7x10-0.65
RENESAS Code
PRQP0048JA-A
Previous Code
48P6S-A
MASS[Typ.]
0.3g
HD
*2
D
25
38
39
E
*1
HE
24
ZE
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
48
15
Reference
Symbol
Index mark
1
14
D
E
A2
HD
HE
A
A1
bp
c
c
ZD
e
y
*3
bp
x
A1
A
A2
F
L
Detail F
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 15 of 15
e
x
y
ZD
ZE
L
Dimension in Millimeters
Min
9.8
6.8
Nom Max
10.0 10.2
7.0 7.2
1.85
11.7 12.0 12.3
8.7 9.0 9.3
2.15
0
0.1 0.2
0.2 0.25 0.35
0.13 0.15 0.2
0°
10°
0.65
0.13
0.10
0.775
0.575
0.3 0.5 0.7
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Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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