MAX3625B Evaluation Kit Evaluates: MAX3625B

19-5172; Rev 0; 2/10
EVALUATION KIT AVAILABLE
MAX3625B Evaluation Kit
The MAX3625B evaluation kit (EV kit) is an assembled
demonstration board that provides convenient evaluation of the MAX3625B low-jitter, precision clock generator. The EV kit includes an on-board 25MHz crystal to
allow immediate testing.
The EV kit includes switches to allow easy selection of
different modes of operation. The reference input and
clock outputs use SMA connectors and are AC-coupled
to simplify connection to test equipment.
Features
S AC-Coupled I/Os for Ease of Testing
S Fully Assembled and Tested
S +3.3V Power-Supply Operation
S On-Board 25MHz Crystal
Ordering Information
PART
TYPE
MAX3625BEVKIT+
EV Kit
+Denotes lead(Pb)-free and RoHS compliant.
Component List
DESIGNATION
C1, C3, C4, C5,
C7, C8,
C11–C16, C18,
C19
QTY
DESCRIPTION
DESIGNATION
QTY
R5, R6
0
Not installed
DESCRIPTION
R7–R10, R14,
R15, R16
7
49.9I Q1% resistors (0402)
14
0.1FF Q10% ceramic capacitors
(0402)
R11
1
10.5I Q1% resistor (0402)
C2
1
10FF Q10% ceramic capacitor
(0603)
SW1, SW2,
SW3, SW11
4
SP3T switches
C6, C17, C20
3
0.01FF Q10% ceramic capacitors
(0402)
5
SPDT switches
C9
1
33pF Q10% ceramic capacitor
(0402)
SW6, SW8,
SW9, SW12,
SW13
TP6, TP7
2
Test points
C10
1
27pF Q10% ceramic capacitor
(0402)
U1
1
J1, J3, J5
0
Not installed
Low-jitter, precision clock generator (24 TSSOP-EP*)
Maxim MAX3625BEUG+
Microsemi
J2, J48
2
Test points
J4
1
2-pin header, 0.1in centers
Y1
1
25MHz crystal
NDK EXS00A-AT00429
J13–J16, J18,
J19, J36
7
SMA connectors
—
1
Shunt
L1
1
2.7FH inductor
1
PCB: MAX3625B EVALUATION
BOARD+, REV A
R1–R4, R12,
R13
6
150I Q5% resistors (0402)
—
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Component Supplier
SUPPLIER
NDK America
PHONE
815-544-7900
WEBSITE
www.ndk.com/en
Note: Indicate that you are using the MAX3625B when contacting this component supplier.
1
Evaluates: MAX3625B
General Description
Evaluates: MAX3625B
MAX3625B Evaluation Kit
Quick Start
To evaluate the MAX3625B, configure the EV kit as follows:
1) D
etermine which output is going to be evaluated and
remove the 49.9I termination resistors located near
the connectors. Then connect that output to the test
equipment using SMA cables.
2) C
onnect a +3.3V power supply to J48 (VCC) and J2
(GND). Set the current limit to 200mA.
3) If the on-board crystal is used (IN_SEL set HIGH), the
PLL divider should be set to divide by 25 (FB_SEL
set LOW) to achieve the standard output rates shown
in Table 3.
4) U
se Table 3 to set the output divider switches to
achieve the output frequency desired.
5) E
nable the output under test by setting the related
output-enable switch (Qx_OE) HIGH.
Table 1. Adjustment and Control Descriptions (see Quick Start first)
COMPONENT
NAME
FUNCTION
J4
INDUCTOR
SHUNT
SW1
SELB1
SW1 and SW2 set the output divider for the QB outputs. See Table 3 for more information.
SW2
SELB0
SW1 and SW2 set the output divider for the QB outputs. See Table 3 for more information.
SW3
SELA1
SW3 and SW11 set the output divider for the QA outputs. See Table 3 for more information.
SW6
BYPASS
Set LOW to bypass the PLL. Set HIGH to engage the PLL. Note that when the PLL is
bypassed the output dividers are automatically set to divide by 1.
SW8
FB_SEL
Sets the PLL divider. See Table 2 for more information.
SW9
QA_OE
Set HIGH to enable LVPECL output QA. Set LOW to force a logic zero at QA.
SW11
SELA0
SW3 and SW11 set the output divider for the QA outputs. See Table 3 for more information.
SW12
QB_OE
Set HIGH to enable the QB LVPECL outputs. Set LOW to force a logic zero at the QB outputs. See Table 3 for more information.
SW13
IN_SEL
Set HIGH to select the crystal as the frequency source. Set LOW to select the REF_IN as
the frequency source.
J4 shunts the power-supply inductor. Normal operation is J4 shunted.
Table 2. PLL Divider Settings
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Table 3. Output Divider Settings
FB_SEL INPUT
PLL DIVIDER
HIGH
÷24
LOW
÷25
INPUT
SELA1/
SELB1
SELA0/
SELB0
NA/NB
DIVIDER
OUTPUT
FREQUENCY
(MHz)
M = 25 AND
XTAL = 25MHz
LOW
HIGH
÷2
312.5
HIGH
LOW
÷4
156.25
HIGH
HIGH
÷5
125
LOW
LOW
÷10
62.5
QB0
J16
R10
49.9Ω
1%
QB0
J15
R9
49.9Ω
1%
QB1
J14
R8
49.9Ω
1%
C16
0.1µF
C15
0.1µF
C18
0.1µF
J13
C17
0.01µF
VCC
R7
49.9Ω
1%
VCC
BYPASS
SELB0
SELB1
R3
150Ω
C19
0.1µF
QA
J18
C20
0.01µF
TP1
2
3
MR
1
SELB0 BYPASS
22
OB0
23
SELB1 VCCO_B
24
R4
150Ω
C14
0.1µF
C13
0.1µF
5
QA
QB1
20
R15
49.9Ω
1%
C11
0.1µF
R13
150Ω
4
VCCO_A
OB0
21
X_IN
16
C12
0.1µF
R12
150Ω
7
J19
QA
QB_OE
8
SELB1
SW1
11
VCC
C7
0.1µF
REF_IN
VCC
C1
0.1µF
12
SELA0
SELA1
13
C9
33pF
C10
27pF
J36
GND
14
FB_SEL
10
VCCA
X_OUT
15
QA_OE
9
QB_OE QA_OE FB_SEL
R16
49.9Ω
1%
6
QA
17
IN_SEL REF_IN
18
MAX3625B
QB1
19
IN_SEL
R1
150Ω
R2
150Ω
R14
49.9Ω
1%
C8
0.1µF
R6
OPEN
SELB0
J1
SW2
VCC
ALT GND
J5
ALT GND
J3
ALT GND
C2
R11
10µF 10.5Ω
1%
SELA0
SELA1
Y1
R5
OPEN
J2
GND
J48
+3.3V
SELA1
C4
0.1µF
VCC
J4
SW3
C3
0.1µF
TP7
L1
2.7µH
VCC
SELA0
BYPASS
IN_SEL
FB_SEL
QA_OE
QB_OE
C5
0.1µF
TP6
SW11
SW6
SW13
SW8
SW9
SW12
VCC
VCC
VCC
VCC
VCC
VCC
C6
0.01µF
VCC
Evaluates: MAX3625B
QB1
MAX3625B Evaluation Kit
Figure 1. MAX3625B EV Kit Schematic
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Evaluates: MAX3625B
MAX3625B Evaluation Kit
Figure 2. MAX3625B EV Kit Assembly Drawing—Top Side
4 _
MAX3625B Evaluation Kit
Evaluates: MAX3625B
Figure 3. MAX3625B EV Kit Layout—Component Side
5
Evaluates: MAX3625B
MAX3625B Evaluation Kit
Figure 4. MAX3625B EV Kit Layout—Ground Plane
6 _
MAX3625B Evaluation Kit
Evaluates: MAX3625B
Figure 5. MAX3625B EV Kit Layout—Power Plane
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Evaluates: MAX3625B
MAX3625B Evaluation Kit
Figure 6. MAX3625B EV Kit Layout—Solder Side
8 _
MAX3625B Evaluation Kit
Evaluates: MAX3625B
Figure 7. MAX3625B EV Kit Assembly Drawing—Bottom Side
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