SuperLite™ 3.3V, 2.7Gbps DUAL 2X2 CROSSPOINT SWITCH Micrel SuperLite™ SY55859L SY55859L FINAL FEATURES ■ Pin-for-pin, plug-in compatible to the MAX3840 ■ Supply voltage operation: +3.3V ±10% ■ Low jitter: • 2ps rms random jitter • 5ps pk-pk deterministic jitter ■ Power saving output disable feature ■ 15ps channel-to-channel skew ■ Fast CML outputs: <100ps tr /tf ■ Available in a small (5mm x 5mm) 32-pin EPAD-MLF package SuperLite™ DESCRIPTION The SY55859L is a dual CML 2x2 crosspoint switch optimized for high-speed data and/or clock applications (up to 2.7Gbps or 2.7GHz) where low jitter and skew are critical. This device is pin-for-pin, plug-in compatible to the MAX3840. Each 2x2 of the SY55859L routes any input to any output, and thus can distribute or multiplex a clock or data stream. The I/O architecture is fully differential and CML compatible. Both inputs and outputs are optimized for 50Ω transmission lines. The inputs (DA 0-1 and DB 0-1) are internally terminated with 50Ω, thus eliminating external termination, and the outputs (QA0-1 and QB0-1) include 50Ω source termination. Furthermore, a power-saving output enable feature is provided which powers-down unused outputs. The SY5859L operates from a +3.3V ±10% supply, and is guaranteed over the industrial (–40°C to +85°C) temperature range. It is available in a 32-pin (5mm x 5mm) MLF package. For applications that require either lower voltage operation or a more flexible input interface (for applications such as AC–coupled LVPECL inputs), consider the SY55858U. APPLICATIONS ■ SONET/SDH optical transport ■ High-speed backplane redundancy ■ Add-drop multiplexers CROSS REFERENCE TABLE Micrel Semiconductor Maxim SY55859LMI MAX3840EGJ TYPICAL APPLICATIONS CIRCUIT TYPICAL PERFORMANCE Data CDR Laser Driver Clock Output Swing (60mV/div.) Limiting Amplifier SY55859L Data Limiting Amplifier CDR Clock Laser Driver TIME (50ps/div.) 2.7Gbps, 223 – 1 PRBS SuperLite is a trademarks of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. Rev.: B 1 Amendment: /0 Issue Date: March 2003 SuperLite™ SY55859L Micrel ENA1 /DA1 DA1 ENA0 SELA0 /DA0 DA0 SELA1 PACKAGE/ORDERING INFORMATION 1 2 3 4 5 6 7 8 32 3130 29 28 27 26 25 24 23 22 32-pin 21 20 MLF 19 18 17 9 10 11 12 13 14 15 16 GND VCC QA0 /QA0 VCC QA1 /QA1 VCC Part Number Package Type Operating Range Package Marking SY55859LMI H32-1 Industrial SY55859LMI SY55859LMITR* H32-1 Industrial SY55859LMI *Tape and Reel GND VCC /QB0 QB0 VCC /QB1 QB1 VCC ENB1 DB1 /DB1 ENB0 SELB0 DB0 /DB0 SELB1 Ordering Information PIN DESCRIPTION Pin Number Pin Name Pin Function 1 ENB1 2 DB1 CML Input. Channel B1 true input. 3 /DB1 CML Input. Channel B1 complement input. 4 ENB0 TTL Input. Channel B0 Output Enable. Setting this pin inactive low powers down QB0 and /QB. Do not leave floating. 5 SELB0 TTL Input. Channel B0 output select. Please refer to Table 2. Do not leave floating. 6 DB0 CML Input. Channel B0 true input. 7 /DB0 CML Input. Channel B0 complement input. 8 SELB1 9, 24 GND Supply ground. Most negative supply voltage. 10, 13, 16, 17, 20, 23 VCC Positive supply. 11 /QB0 CML Output. Channel B0 complement output. 12 QB0 CML Output. Channel B0 true output. 14 /QB1 CML Output. Channel B1 complement output. 15 QB1 CML Output. Channel B1 true output. 18 /QA1 CML Output. Channel A1 complement output. 19 QA1 CML Output. Channel A1 true output. 21 /QA0 CML Output. Channel A0 complement output. 22 QA0 CML Output. Channel A0 true output. 25 SELA1 26 DA0 CML Input. Channel A0 true input. 27 /DA0 CML Input. Channel A0 complement input. 28 SELA0 TTL Input. Channel A0 output select. Please refer to Table 1. Do not leave floating. 29 ENA0 TTL Input. Channel A0 output enable. Setting this pin inactive low powers down QA0 and /QA0. Do not leave floating. 30 DA1 CML Input. Channel A1 true input. 31 /DA1 CML Input. Channel A1 complement input. 32 ENA1 TTL Input. Channel A1 output enable. Setting this pin inactive low powers down QA1 and /QA1. Do not leave floating. EP Exposed Pad TTL Input. Channel B1 Output Enable. Setting this pin inactive low powers down QB1 and /QB1. Do not leave floating. TTL Input. Channel B1 output select. Please refer to Table 2. Do not leave floating. TTL Input. Channel A1 output select. Please refer to Table 1. Do not leave floating. Ground. This must be soldered to circuit board ground for proper electrical and thermal operation. 2 SuperLite™ SY55859L Micrel Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VCC) .................................. –0.5V to +6.0V CML Input Voltage (VIN) .............................. –0.5V to +6.0V TTL Control Input Voltage (VIN) ........... –0.5V to VCC +0.5V CML Output Voltage (VOUT) ......... VCC –1.0V to VCC +0.5V CML Output Current (IOUT) ........................................ 22mA Lead Temperature (soldering, 10sec.) .................... +300°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage (VCC) .................................. +3.0V to +3.6V Ambient Temperature (TA) ......................... –40°C to +85°C Junction Temperature (TJ) ........................................ 160°C Package Thermal Resistance MLF (θJA) still-air .............................................................. 28°C/W 500lfpm ............................................................ 20°C/W MLF (θJC) .............................................................. 4°C/W Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. DC ELECTRICAL CHARACTERISTICS(1) TA = –40°C to +85°C Symbol Parameter VCC Power Supply Voltage ICC Power Supply Current Note 1. Condition Min Typ Max Units 3.0 3.3 3.6 V 160 190 mA No Load, Over Supply Voltage; All Outputs Enabled Specification for packaged product only. CML DC ELECTRICAL CHARACTERISTICS(1) VCC = 3.0V to 3.6V; GND = 0V; TA = –40°C to +85°C(Note 2) Symbol Parameter Condition Min Typ Max Units VOUT CML Differential Output Swing RL = 50Ω to VCC, Figure 3 640 800 1000 mVp-p ROUT Differential Output Impedance Figure 2 85 100 115 Ω VOCM CML Output Common Mode Voltage RL = 50Ω to VCC, Figure 3 VIS CML Input Voltage Range Figure 4 VCC–0.8 VCC+0.4 V VDIFF CML Differential Input Voltage Swing Figure 5 300 1600 mVp-p CML Single-ended Input Impedance Figure 1 42.5 57.5 Ω VCC–0.2 50 V Note 1. Specification for packaged product only. Note 2. The device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in a socket such that transverse airflow of ≥500lfpm is maintained. TTL CONTROL ELECTRICAL CHARACTERISTICS(1) VCC = 3.0V to 3.6V; GND = 0V; TA = –40°C to +85°C(Note 2) Symbol Parameter VIH TTL Input HIGH Voltage VIL TTL Input LOW Voltage IIH TTL Input HIGH Current IIL TTL Input LOW Current Condition Min Typ Max 2.0 Units V 0.8 V –10 +10 µA –10 +10 µA Note 1. Specification for packaged product only. Note 2. The device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in a socket such that transverse airflow of ≥500lfpm is maintained. 3 SuperLite™ SY55859L Micrel AC ELECTRICAL CHARACTERISTICS(1) VCC = 3.0V to 3.6V; GND = 0V; TA = –40°C to +85°C(Note 2) Symbol Parameter fMAX Maximum NRZ Data Rate 2.7 Gbps fMAX Maximum Clock Rate 2.7 GHz tPD Propagation Delay from Input-to-Output 275 ps RJ Random Jitter Note 3 2 ps(rms) DJ Deterministic Jitter Note 4 5 20 ps(pk-pk) tSKDIFF CML Output Differential Skew Any Differential Pair – Duty Cycle Distortion 7 25 ps tSKEW CML Output Channel-to-Channel Note 5, Any Two Outputs 15 40 ps tr,tf CML Output Rise/Fall Times (20% to 80%) 80 135 ps Note 1. Note 2. Note 3. Note 4. Note 5. Condition Min Typ Max Specification for packaged product only. AC characteristics are guaranteed by design and characterization. Tested using environment of Figure 6, 50Ω equivalent load. Measured with 100mVp-p noise (f ≤ 2MHz) on the power supply. Deterministic jitter (DJ) is the arithmetic sum of pattern-dependent jitter and pulse width distortion. This represents the skew on a QA and QB output with their inputs receiving the same signal. 4 Units SuperLite™ SY55859L Micrel TYPICAL OPERATING CHARACTERISTICS VCC D Invalid VIS(max) 50Ω 1.2mA D, /D Inputs Valid VIS(min) 50Ω Invalid /D Figure 4. Input Range 1.2mA SY55859L Figure 1. Input Structure D vcc VDIFF 2 50Ω 50Ω Q /D /Q Figure 5a. Input Levels 16mA |D – /D| SY55859L VDIFF Figure 2. Output Structure Q Figure 5b. Input Levels VOUT 2 VOCM /Q 0V Q 50Ω Figure 3a. Output Levels 100Ω /Q 50Ω |Q — /Q| VOUT SY55859L Figure 6. Output Interface Figure 3b. Output Levels 5 SuperLite™ SY55859L Micrel TYPICAL OPERATING CHARACTERISTICS Channel-to-Channel Skew Histogram Supply Current vs. Temperature 500 SUPPLY CURRENT (mA) 180 400 300 200 100 0 -30 -20 -10 0 10 SKEW (ps) 20 160 140 4 Outputs Enabled 120 3 Outputs Enabled 100 2 Outputs Enabled 80 1 Output Enabled 60 40 No Outputs Enabled 20 0 -40 -20 0 20 40 60 TEMPERATURE (°C) 30 6 80 SuperLite™ SY55859L Micrel FUNCTIONAL DESCRIPTION SY55859L is a dual cross point with excellent pin-to-pin and part-to-part skew matching. As shown in table 1, based on the logic value at TTL input SELA0, output QA0 replicates either input DA0 or DA1. TTL input SELA1 selects whether output QA1 replicates input DA0 or DA1. As shown in table 2, TTL inputs SELB0 and SELB1 perform similarly for outputs QB0 and QB1 respectively, choosing between inputs DB0 or DB1. If the two control inputs are tied together, SY55859L behaves as a redundant distribution device. Depending on the state of the combined control inputs, QA0 and QA1 will both replicate either DA0 or DA1. If the two control inputs are made the logical complement of each other, the SY55859L functions as a crosspoint, either sending DA0 to QA0 and DA1 to QA1, or sending DA0 to QA1 and DA1 to QA0. The same applies to channel B. SY85859L’s CML outputs are source terminated to 50Ω individually, 100Ω differentially. The CML inputs are parallel terminated, also to 50Ω. This improves signal integrity. With all terminations on chip, high-speed interfacing is greatly simplified, eliminating the need for external termination passive components. Figures 1 and 2 show the input and output structures. SELA0 SELA1 QA0 QA1 Function 0 0 DA0 DA0 Fanout Buffer 0 1 DA0 DA1 Dual Buffer 1 0 DA1 DA0 Dual Buffer 1 1 DA1 DA1 Fanout Buffer CTL CTL Same Same Redundant Distribution CTL /CTL Opposite Opposite Crosspoint Table 1. Input to Output Connectivity, Crosspoint A SELB0 SELB1 QB0 QB1 Function 0 0 DA0 DA0 Fanout Buffer 0 1 DA0 DA1 Dual Buffer 1 0 DA1 DA0 Dual Buffer 1 1 DA1 DA1 Fanout Buffer CTL CTL Same Same Redundant Distribution CTL /CTL Opposite Opposite Crosspoint Table 2. Input to Output Connectivity, Crosspoint B 7 SuperLite™ SY55859L Micrel FUNCTIONAL BLOCK DIAGRAM DA0 0 /DA0 QA0 A0 CML 1 /QA0 SELA0 0 DA1 QA1 A1 CML 1 /QA1 /DA1 SELA1 DB0 0 /DB0 QB0 B0 CML 1 /QB0 SELB0 0 DB1 QB1 B1 1 CML /QB1 /DB1 SELB1 8 SuperLite™ SY55859L Micrel APPLICATIONS INFORMATION The delay from a logic transition on an enable input to the corresponding effect on the CML output is not defined in the tables of this data sheet. This delay is 3ns typical, and 10ns maximum. Please note that, for cases where highly capacitive lines are being driven, the RC effects of the line may make this delay longer. The delay from a logic transition on a select input to the corresponding CML output is also not defined in the tables. It is 300psec typical, 500psec maximum. For best performance, use good high frequency layout techniques, filter VCC supplies, and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the SY55859L data inputs and outputs. The eight TTL compliant inputs to SY55859L are ENA0, ENA1, ENB0 ENB1, SELA0, SELA1, SELB0 and SELB1. These high impedance inputs do not default to a stable logic state when left unconnected. Therefore, these TTL compliant inputs cannot be left floating. Connect these inputs to a valid control signal, or hardwire to VCC or GND. The four enable TTL inputs, when driven low, disable the corresponding output stage. This reduces power consumption. Disabled output stages do not go into a high impedance state. Rather, each pin of a disabled output stage pair goes high through its respective 50Ω source termination. RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY55854U 2x2 CML Crosspoint www.micrel.com/product-info/products/sy55854u.shtml SY55858U Dual 2x2 CML Crosspoint www.micrel.com/product-info/products/sy55858u.shtml 9 SuperLite™ SY55859L Micrel 32 LEAD Micro LEADFRAME™ (MLF-32) Rev. 01 MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 10