HD74LV2GT53A 2–channel Analog Multiplexer / Demultiplexer REJ03D0144–0200Z (Previous ADE-205-697A (Z)) Rev.2.00 Oct.17.2003 Description The HD74LV2GT53A has 2–channel analog multiplexer / demultiplexer in an 8 pin package. Applications include signal gating, chopping, modulation, or demodulation (modem), and signal multiplexing for analog to digital and digital to analog conversion systems. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Control input is TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range : –40 to +85°C • Control inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • Control inputs have hysteresis voltage for the slow transition. • Ordering Information Part Name Package Type HD74LV2GT53AUSE SSOP-8 pin Rev.2.00, Oct.17.2003, page 1 of 1 Package Code Package Abbreviation Taping Abbreviation (Quantity) TTP-8DBV US E (3,000 pcs/reel) HD74LV2GT53A Outline and Article Indication • HD74LV2GT53A Index band Lot No. Y M W T 5 3 Y : Year code (the last digit of year) M : Month code W : Week code SSOP–8 Marking Function Table Control inputs INH A On channel H X None L H Y1 L L Y0 H : High level L : Low level X : Immaterial Rev.2.00, Oct.17.2003, page 2 of 9 HD74LV2GT53A Pin Arrangement COM 1 INH 2 O GND 3 O GND 4 C C 8 VCC I 7 Y0 I 6 Y1 5 A (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Symbol Ratings Unit VCC –0.5 to 7.0 V VI –0.5 to 7.0 V Test Conditions VO –0.5 to VCC + 0.5 V Output : H or L Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±50 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg –65 to 150 °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.2.00, Oct.17.2003, page 3 of 9 HD74LV2GT53A Recommended Operating Conditions Item Symbol Min Supply voltage range VCC 3.0 5.5 V Input voltage range VI 0 5.5 V Input / output voltage range VI/O 0 VCC V ns / V Input transition rise or fall rate ∆t / ∆v Operating free-air temperature Ta Max 0 100 0 20 –40 85 Unit Conditions VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V °C Note: Unused or floating control inputs must be held high or low. Electrical Characteristics Ta = 25°C Ta = –40 to 85°C Item Symbol VCC (V) Min Typ Max Min Typ Max Unit Test Conditions Input voltage VIH 3.0 to 3.6 — — — 1.5 — — 4.5 to 5.5 — — — 2.0 — — 3.0 to 3.6 — — — — — 0.6 0.8 VIL Hysteresis voltage VH 4.5 to 5.5 — — — — — 3.3 — — — — 0.10 — — V Control input only V + – VT – VT Ω VIN = VCC or GND VC = VIH IT = 2 mA Ω VIN = VCC to GND VC = VIH IT = 2 mA Ω VIN = VCC to GND VINH = VIL IT = 2 mA 5.0 — — — On-state switch RON resistance 3.0 — 50 150 — — 190 4.5 — 40 75 — — 100 Peak on resistance RON (P) 3.0 — 90 180 — — 225 4.5 — 50 100 — — 125 Difference of on-state resistance between switches ∆RON 3.0 — 10 20 — — 30 4.5 — 7 15 — — 20 Off-state switch Is (OFF) leakage current 5.5 — — ±0.1 — — ±1.0 µA VIN = VCC, VOUT = GND or VIN = GND, VO = VCC, VINH = VIH On-state switch Is (ON) leakage current 5.5 — — ±0.1 — — ±1.0 µA VIN = VCC or GND VINH = VIL Input current IIN 0 to 5.5 — — ±0.1 — — ±1.0 µA VIN = 5.5 V or GND Quiescent supply current ICC 5.5 — — — — 10 ∆ICC 5.5 — — — — — 1.5 mA VIN = 3.4 V CIC — — 3.5 — — — — pF Switch terminal CIN / OUT — capacitance — 6.0 — — — — pF Feed through capacitance — 0.5 — — — — pF Control input capacitance CIN–OUT — Rev.2.00, Oct.17.2003, page 4 of 9 — 0.15 — µA VIN = VCC or GND HD74LV2GT53A Switching Characteristics • VCC = 3.3 ± 0.3 V Ta = 25°C Test Ta = –40 to 85°C FROM Item Symbol Min Typ Max Min Max Unit Conditions (Input) Propagation delay time tPLH tPHL — 2.0 6.0 — 10.0 ns — 4.0 9.0 — 12.0 Enable time tZH tZL — 5.0 12.0 — 15.0 — 7.0 20.0 — 25.0 tHZ tLZ — 7.0 12.0 — 15.0 — 10.0 20.0 — 25.0 Disable time CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 15 pF (Output) COM or Yn or Yn COM INH COM or Yn INH COM or Yn FROM TO CL = 50 pF ns TO CL = 50 pF • VCC = 5.0 ± 0.5 V Ta = 25°C Test Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Conditions (Input) Propagation delay time tPLH tPHL — 1.5 4.0 — 7.0 ns — 3.0 6.0 — 8.0 Enable time tZH tZL — 4.0 8.0 — 10.0 — 5.0 14.0 — 18.0 tHZ tLZ — 5.0 8.0 — 10.0 — 8.0 14.0 — 18.0 Disable time CL = 15 pF CL = 50 pF ns CL = 15 pF COM or Yn or Yn COM INH COM or Yn INH COM or Yn CL = 50 pF ns CL = 15 pF (Output) CL = 50 pF Operating Characteristics • CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 5.0 8.0 — pF f = 10 MHz Rev.2.00, Oct.17.2003, page 5 of 9 — HD74LV2GT53A Test Circuit • R ON VCC VINH =VIL VCC VIN =VCC (ON) VOUT R ON = GND 2.0 mA + V VIN–OUT 2 × 10 -3 (Ω) – VIN–OUT • I S (off), I S (on) VCC VCC VINH =VIL VINH =VIH VCC A VIN =VCC or GND VCC (OFF) GND Rev.2.00, Oct.17.2003, page 6 of 9 A VOUT =GND or VCC VIN =VCC or GND (ON) GND VOUT OPEN HD74LV2GT53A tr VI 90% 90% Vref Vref VIN • t PLH ,t PHL tf 10% 10% t PHL t PLH VCC VOUT VINH =VIL 50% GND VOH 50% VOL VCC VIN CL= 15 or 50 pF GND INPUTS VCC (V) VOUT (ON) VI Vref tr / tf 3.3±0.3 2.5 V ≤ 3.0 ns 50% 5.0±0.5 3 V ≤ 3.0 ns 1.5 V Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω. 2. The output are measured one at a time with one transition per measurement. • t ZH ,t ZL / t HZ ,t LZ VC 10% VINH S1 VIN R L= 1kΩ VCC VOUT GND Item t ZH t ZL t HZ t LZ tf tr VCC S1 VCC GND VCC GND CL=15 or 50 pF S2 R L= 1kΩ 90% Vref t ZH waveform–A VI 90% Vref 10% VOH –0.3 V 50% VOH GND VOUT t ZL waveform–B t LZ 50% VCC VOL +0.3 V S2 GND VCC VCC (V) GND VCC 3.3±0.3 2.5 V ≤ 3.0 ns 50% 5.0±0.5 3 V ≤ 3.0 ns 1.5 V INPUTS VI tr / tf Vref Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00, Oct.17.2003, page 7 of 9 GND t HZ VOL HD74LV2GT53A • C IN/OUT , C IN–OUT CIN–OUT VINH = VIH VCC VCC (OFF) CIN/OUT Rev.2.00, Oct.17.2003, page 8 of 9 GND CIN/OUT HD74LV2GT53A Package Dimensions 2.0 ± 0.2 1.5 ± 0.2 + 0.1 (0.17) 8 − 0.2 − 0.05 Package Code JEDEC JEITA Mass (reference value) Rev.2.00, Oct.17.2003, page 9 of 9 + 0.1 0.13 − 0.05 0 − 0.1 0.7 ± 0.1 (0.4) 2.3 ± 0.1 (0.5) (0.5) (0.5) 3.1 ± 0.3 (0.4) Unit: mm TTP–8DBV 0.010 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 1.0