REJ03F0260-0100
Rev. 1.00
Jan. 10. 2008
R8A66153FP
PROGRAMMABLE BUFFERED I/O EXPANDER
DESCRIPTION
The R8A66153FP is a programmable I/O expander using a high-voltage CMOS process.
And has three sets of 8-bit I/O ports, two sets of 8-bit high voltage output ports, and one 4-bit input port.
FEATURES
● Output pattern can be written in input mode
● 8-bit X 2 high voltage output ports with IOL=24mA
● CMOS level schmitt trigger input
● Vcc=4.5~5.5V, Ta=-40~85oC
APPLICATION
● I/O port expansion for MCU.
PIN CONFIGRATION (TOP VIEW)
Output port F
33
34
35
36
37
38
39
40
41
42
43
44
45
46
32
50
31
51
30
52
29
53
28
54
27
55
26
R8A66153FP
56
57
25
24
16
15
14
13
12
PA1
PA0
VCC
RD
WR
CS
RESET
GND
A2
A1
A0
D0
D1
D2
D3
D4
11
17
10
18
64
9
19
63
8
20
62
7
21
61
6
22
60
5
23
59
4
58
1
Bi-directional
port A
49
3
Bi-directional
port B
PE7
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA7
PA6
PA5
PA4
PA3
PA2
2
Output port E
47
48
PE6
PE5
PE4
PE3
PE2
PE1
PE0
VCC
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Output port E
Bi-directional
port A
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REJ03F0260-0100 Rev.1.00 Jan.10.2008
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Port address
input
Data bus
GND
PG3
PG2
PG1
PG0
PC3
PC2
PC1
PC0
PC4
PC5
PC6
PC7
D7
D6
D5
Input port G
Bi-directional
port C
Data bus
R8A66153FP
BLOCK DIAGRAM
8
PA7
PA6
Port A
(8 bit)
PA5
PA4
PA3
PA2
PA1
PA0
4
RD
Port C
PC7
PC6
WR
(Upper 4bit)
PC5
PC4
Port C
PC3
PC2
(Lower 4bit)
PC1
PC0
A2
A1
Read/Write
control
circuit
4
A0
RESET
PB7
8
PB6
Port B
CS
(8 bit)
PB5
PB4
PB3
PB2
PB1
PB0
D7
D6
D5
D4
D3
PE7
8
Data bus
buffer
PE6
Port E
D2
D1
Ｄ0
(8 bit)
PE5
PE4
PE3
PE2
PE1
PE0
PF7
8
PF6
Vcc
Vcc
Port F
PF5
(8 bit)
PF4
PF3
PF2
PF1
PF0
GND
GND
GND
4
Port G
(4 bit）
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REJ03F0260-0100 Rev.1.00 Jan.10.2008
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PG3
PG2
PG1
PG0
R8A66153FP
FUNCTIONAL DESCRIPTION
The R8A66153FP is a general purpose programmable I/O expander with three 8-bit I/O ports (portA,B,C)
and two 8-bit high voltage output ports (portE,F) and one 4-bit input port (portG).
I/O ports can be set INPUT for OUTPUT by a command.
The portC can be divided into two 4-bit ports, and if it is set to output, bit set/reset operation is available.
The portE and port F is the high voltage N-channel open drain output. (Vo=24V, IOL=24mA)
The port G is a 4-bit input port with CMOS level schimitt trigger input.
When RESET="H", output port E and F turn to disable state and other I/O ports turn to input mode.
FUNCTION
RD (read input)
If the input is "L", the port input data or port latch data appear at the data bus.
WR (write input)
By the positive edge of WR input, data bus data is written into the control register or into the port latch.
A2, A1, A0 (Port selection input)
Select the port or the control register. (see table 1)
RESET (reset input)
If the input is "H", all I/O and output port turn to high impedance state.
(Port A,B,C : input mode, Port E,F : "Z")
CS (chip select input)
"L" enables to communicate with MCU. When "H", data bus keeps high impedance state and ignored the
command from MCU. The port condition and the data of the port latch are not changed even if CS="H".
Read/Write control circuit
According to the data from the MCU, set the port condition and transmit the data between port and data
bus.
Data bus buffer
This is the bi-directional bus buffer. When WR="L" data bas data is written into the register of R8A66153,
and when RD="L" port data or port latch data is appears.
Port A and Port B
Port A and Port B are 8-bit bi-directional port with output latch. By the command from MCU, set these port
as an input or an output.
The output circuit of these ports are CMOS 3-state output and input buffer is CMOS schmitt trigger input.
When port is set to output, data bus data is written into the port latch by the positive edge of /WR and is
output to the terminal.
When RD="L" in the state of output mode, port terminal data(=output data) is appears to the data bus.
When RD="L" in the state of input mode, port terminal data(=input data) is appears to the data bus.
In the state of input mode, data bus data is written into the port latch by the positive edge of WR.
Port latch data is not determined when power ON.
Port C
Basic function of port C is the same as the port A and port B. The difference between port A/B and port C
is that port C can be used as the two 4-bit ports. And when is set to output, bit set/reset function is
available by a bit.
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REJ03F0260-0100 Rev.1.00 Jan.10.2008
Page 3 of 9
R8A66153FP
Port E and Port F
Port E and Port F are 8-bit high voltage output ports with Vo=24V/IOL=24mA. Output transistor is N-ch
open drain transistor.
When this port is selected, data bus data is written into the port latch by the positive edge of WR.
And if is set to output enable, port latch
Port G
Port G is a input port with CMOS schmitt trigger. When this port is selected and RD="L", input data is
appears to the data bus.
Table 1. Function Table
A2
A1
A0
CS
RD
WR
FUNCTION
0
0
0
0
0
1
Data bus
Port A
0
0
1
0
0
1
Data bus
Port B
0
1
0
0
0
1
Data bus
Port C
0
1
1
0
0
1
1
0
0
0
0
1
Data bus
Data bus
Port G
Port E latch data
1
0
1
0
0
1
Data bus
Port F latch data
0
0
0
0
1
Port A
Data bus
0
0
1
0
1
Port B
Data bus
0
1
1
0
0
0
0
0
1
1
Port C
Data bus
Port E
Data bus
1
0
1
0
1
Port F
Data bus
1
1
1
0
1
Control register
Data bus
×
×
×
1
×
×
Data bus is in high impedance state
note: "0" means "L" level and "1" means "H" level.
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REJ03F0260-0100 Rev.1.00 Jan.10.2008
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R8A66153FP
CONTROL WORD
When (A0, A1, A2)=(1,1,1), data bus data is recognized as the control word.
This control word is to set the port condition and the bit set/reset function of port C. (see Fig.1 and Fig.2)
"1" when mode set control word
don't care
Port E enable/disable set
Port F enable/disable set
"0" : Enable
"1" : Disable
Port A input/output set
Port B input/output set
Port C input/output set (Upper 4-bit)
Port C input/output set (Lower 4-bit)
D7
D6
D5
D4
D3
D2
D1
"0" : Output
"1" : Input
D0
Fig.1 Control word to set port conditions
"0" when port C bit set/reset function
don't care
Bit select (see below)
Bit select
D3
D2
D1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Set/reset
D7
D6
D5
D4
D3
D2
D1
D0
Fig.2 Control word for bit set/reset function of port C
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REJ03F0260-0100 Rev.1.00 Jan.10.2008
Page 5 of 9
"0" : Reset ("L")
"1" : Set ("H")
R8A66153FP
ABSOLUTE MAXIMUM RATINGS (Ta=-40~+85oC, unless otherwise noted)
Symbol
Parameter
Conditions
Ratings
Unit
V
V
V
V
mW
o
C
-0.3 to +7
Vcc
Supply voltage
VI
Input voltage
VO
Output voltage
Pd
Power dissipation
Tstg
Storage temperature
-0.3 to Vcc+0.3
-0.3 to Vcc+0.3
except port E, F
-0.3 to +28
Port E,F
o
500
-65 to 150
Ta=85 C
RECOMMENDED OPERATING CONDITIONS (Ta=-40~+85oC, unless otherwise noted)
Symbol
Parameter
Conditions
Min.
Limits
Typ.
Supply voltage
VO
"H" output voltage
IOL
"L" output current
Topr
Operating temperature
Port E,F
Unit
IOH < 250uA
0
24
V
V
VOL < 0.6V
0
24
mA
-40
85
4.5
Vcc
Max.
5
5.5
o
C
ELECTRICAL CHARACTERISTICS (Vcc=4.5~5.5V, Ta=-40~+85oC, unless otherwise noted)
Symbol
Parameter
Port A,B,C,G
0.35Vcc 0.78Vcc
V
Port A,B,C,G
0.2Vcc
0.55Vcc
V
Control pin (note),
Data bus
Positive going
VT-
Negative going
threshold voltage
VOH
"H" output voltage
Data bus,
0.7Vcc
IOH=-2.5mA
IO=2.5mA
Vcc-2
0.45
VOL
"L" output voltage
Port A,B,C
VOL
"L" output voltage
Port E,F
IOL=24mA
0.6
IOH
II
"H" output leak current
Port E,F
VO=24V
250
Input leak current
VO=0 to Vcc
±10
IOZ
OFF-state output current
VO=0 to Vcc
±10
ICCS
CI
Static supply current with no output load.
All ports "H" output
2
Input pin capacitance
f=1MHz
CI/O
I/O pin capacitance
Other pins 0V
10
20
note : Control pins are RD, WR, RESET, CS, A2, A1 and A0 pin.
.
Unit
V
V
"H" input voltage
"L" input voltage
threshold voltage
Limits
Min.
Max.
0.3Vcc
VIH
VIL
VT+
Test conditions
REJ03F0260-0100 Rev.1.00 Jan.10.2008
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V
V
V
uA
uA
uA
mA
pF
pF
R8A66153FP
TIMING REQUIREMENTS (Vcc=4.5~5.5V, Ta=-40~+85oC, unless otherwise noted)
Symbol
Parameter
Limits
Test conditions
Min.
tsu(A-R)=0ns
160
tsu(A-R)>40ns
120
Max.
Unit
tw(R)
Read pulse width
tsu(PE-R)
Peripheral setup time before read
0
ns
th(R-PE)
Peripheral hold time after read
0
ns
tsu(A-R)
Address setup time before read
0
ns
th(R-A)
Address hold time after read
0
ns
tw(W)
Write pulse width
120
ns
tsu(DQ-W)
Data setup time before write
40
ns
th(W-DQ)
Data hold time after write
0
ns
tsu(A-W)
Address setup time before write
0
th(W-A)
Address hold time after write
0
ns
ns
ns
SWITCHING CHARACTERISTICS (Vcc=4.5~5.5V, Ta=-40~+85oC, unless otherwise noted)
Symbol
tpZH(R-DQ)
tpZL(R-DQ)
tpHZ(R-DQ)
tpLZ(R-DQ)
Parameter
Read access time
Limits
Test conditions
tsu(A-R)=0ns
Min.
120
CL=150pF (note)
tsu(A-R)>40ns
Read to data floating time
Max.
85
CL=150pF (note)
3
85
tpHL(W-PE)
Write to output
Port A,B,C
CL=150pF (note)
200
tpLH(W-PE)
delay time
Port E,F
CL=150pF, RL=200ohm (note)
250
Input measuring
point
Vcc
Unit
ns
ns
ns
Output measuring
point
RL=2k ohm (data bus)
200 ohm (portE,F)
Input
(1)
P.G.
S1
Output
DUT
50ohm
（2 ）
CL
S2
Symbol
(2) CL includes stray capacitance and probe
capacitance.
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REJ03F0260-0100 Rev.1.00 Jan.10.2008
Page 7 of 9
S2
Open
Closed
Open
Data bus
Open
Closed
Data bus
Closed
Open
tpLH(W-PE)
Port E,F
tpZH(R-DQ)
tpZL(R-DQ)
tpLZ(R-DQ)
（1 ） Pulse Generator (P.G.)
tr=6ns, tf=6ns, Zo=50ohm
S1
Open
Port A,B,C
tpHZ(R-DQ)
2k ohm
Output pin
tpHL(W-PE)
R8A66153FP
TIMING DIAGRAM
Read operation
tw(R)
RD
tsu(A-R)
th(R-A)
CS, A0 ~ A2
tsu(PE-R)
th(R-PE)
PORT INPUT
tpZL(R-DQ),
tpZH(R-DQ)
tpLZ(R-DQ), tpHZ(R-DQ)
D0~D7
Write operation
tw(W)
WR
tsu(A-W)
th(W-A)
CS, A0 ~ A2
tsu(DQ-W)
th(W-DQ)
D0~D7
tpLH(W-PE), tpHL(W-PE)
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REJ03F0260-0100 Rev.1.00 Jan.10.2008
Page 8 of 9
R8A66153FP
PACKAGE OUTLINE
Package
64pin LQFP
RENESAS Code
PLQP0064KD-A
Previous Code
64P6X-B
All trademarks and registered trademarks are the property of their respective owners.
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REJ03F0260-0100 Rev.1.00 Jan.10.2008
Page 9 of 9