RENESAS M61520FP

M61520FP
6ch Electronic Volume with Tone Control
REJ03F0057-0100Z
Rev.1.0
Sep.19.2003
Features
Function names
Features
Volume
Six independent high-performance independent volumes on-chip (0 to 87 dB in 1 dB steps, -∞)
Input selector
REC output
L/R ch: 6 inputs with muting and attenuation
Two-channel record output (one channel includes a mute switch)
Gain control
Bass boost
Input gain control for FL, FR, C, SL, SR, and SW channels (0/3.6 dB)
Record-input gain control (+1/+3/+4.6/+6.6 dB)
Output gain control for SL, SR and C channels (0/+6 dB)
Output gain control for the SW channel (+6/+10 dB)
Output gain control for FL and FR channels (0/+2/+6.5/+10.5 dB) *1
Microphone-mix gain control (0/-2/+6.5/+10.5 dB) *1
On-chip bass-boost circuits for the FL and FR channels
Balanced output
Internal balanced outputs for the ADC
Note: 1 The microphone mix gain is coupled with output gain control for the FL and FR channels.
Application
Mini-component systems, TVs, etc.
Recommended Operating Conditions
Analog power-supply voltage range: 8.0 V to 10.0 V
Digital power-supply voltage range: 3.0 V to 5.5 V
Rev.1.0, Sep.19.2003, page 1 of 15
M61520FP
System Block Diagram
1
2
3
4
5
6
0/-2/-6.5/-10.5dB
Coupled
ATT
Gain
ATT
+
-4.4/-9.4/
-8/-13/
-11.6/-16.6dB
-1
+
ref
-
DSP
1
2
3
4
5
6
-
+
DAC
-
0/+3.6dB
ADC
Gain
+1/+3/
+4.6/+6.6dB
MIC IN
REC OUT
-
Gain
-
+
Bass Boost
Master VOL.
+
Gain
ref
0/+2/+6.5/+10.5dB
ATT
-4.4/-9.4/
-8/-13/
-11.6/-16.6dB
Master VOL.
Gain
Gain
0/+3.6dB
Master VOL.
Gain
Gain
0/+3.6dB
0/+6dB
ref
MCU I/F
C
Master VOL.
Gain
Gain
0/+3.6dB
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
LATCH
CLOCK
DATA
Rev.1.0, Sep.19.2003, page 2 of 15
SR
0/+6dB
ref
+
SL
0/+6dB
ref
-
FR
Master VOL.
Gain
Gain
-1
FL
0/+2/+6.5/+10.5dB
0/+3.6dB
Gain
+1/+3/
+4.6/+6.6dB
Bass Boost
Gain
-
-
+
REC OUT
Master VOL.
+
0/+3.6dB
ref
+6/+10dB
SW
M61520FP
NC
RIN6
RIN5
RIN4
RIN3
RIN2
RIN1
AV CC
NC
LI N6
LI N5
LI N4
LI N3
LI N2
LI N1
NC
Block Diagram with Pin Connections
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
60k
MI CIN
1
LRECIN
2
SRIN 10
SL IN 11
CIN 12
SWIN 13
DGND 14
60k
60k
60k
60k
60k
60k
60k
64 LRECOUT1
Input selector
63 LRECOUT2
+
-
+
+
-
+
+1/+3/
+4.6/+6.6dB
62 RRECOUT1
61 RRECOUT2
60k
ATT
-1
+1/+3/
+4.6/+6.6dB
-4.4/-9.4/
-8/-13/
-11.6/-16.6dB
C/SW block REF
-4.4/-9.4/
-8/-13/
-11.6/-16.6dB
59 REFOUTEX1
58 REFIN
REF.
ATT
0/+3.6dB
+
-
FR
60k
L/R/FL/FR block REF
Coupled
0/+3.6dB
Internal power
supply
+
-
60k
0/+3.6dB
0/+2/+6.5/
+10.5dB
0/+3.6dB
SL
60k
53 FROUT
Bass
Boost
0/+3.6dB
52 FRBB2
C
60k
55 IVD D
54 AGND
SR
60k
57 REFOUT
56 IVSS
FL
60k
60 REFOUTEX2
SL/SR block REF
ATT
0/-2/-6.5/-10.5dB
-1
FRIN 8
9
60k
60k
ADL+OUT 6
FLIN
60k
+
-
ADR+OUT 4
ADL-OUT 7
60k
Input selector
RRECIN 3
ADR-OUT 5
60k
60k
0/+3.6dB
51 FRBB1
SW
FR
50 FRVOLIN
DATA 15
MCU
CLOCK 16
49 FRBUF
I/F
0/+2/+6.5/
+10.5dB
LA TCH 17
48 FRREF
Bass
Boost
PORT1 18
47 BBREFOUT
46 FLOUT
PORT2 19
FL
PORT3 20
PORT4 21
SR
SL
C
SW
45 FLBB2
44 FLBB1
PORT5 22
43 FLVOLIN
PORT6 23
42 FLBUF
DVDD 24
+6/+10dB
0/+6dB
0/+6dB
0/+6dB
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SWREF
SWBUF
SWVOLIN
SWOUT
CREF
CBUF
CVOLIN
COUT
SLREF
SLBUF
SLVOLIN
SLOUT
SRREF
SRBUF
SRVOLIN
SROUT
Rev.1.0, Sep.19.2003, page 3 of 15
41 FLREF
M61520FP
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Unit
Max. power-supply voltage
AVCC
10.5
V
DVDD
6.5
V
Internal power dissipation
Ambient operating temperature
Pd
Topr
1.4
-20 to +75
W
°C
Storage temperature
Tstg
-40 to +125
°C
Conditions
Thermal derating curve
Internal power dissipation pd [W]
2.0
1.5
1.4
1.0
0.7
0.5
0
0
25
50
75
100
125
150
Ambient temperature Ta [°C]
Recommended Operating Condition
Limits
Item
Symbol
Min.
Typ.
Max.
Unit
Condition
Power-supply voltage
AVCC
8.0
9.0
10.0
V
Input voltage (L level)
DVDD
VIL
3.0
0.0
5.0

5.5
0.8
V
V
Pins 15, 16, and 17
Input voltage (H level)
VIH
2.0

VDD
V
Pins 15, 16, and 17
Electrical characteristics
Unless otherwise noted, Ta = 25°C, AVCC = 9.0 V, DVDD = 5.0 V, f = 1 kHz, and bass boosting is switched off.
(1) Power-supply characteristics
Limits
Item
Symbol
Min.
Typ.
Max.
Unit
Condition
Analog power-supply circuit
current
AICC

20
40
mA
Current on pin 73 when AVCC = 5 V,
with no signal
Digital power-supply circuit
current
Dldd

0.8
1.5
mA
Current on pin 24 when DVDD = 5 V,
with no signal
Rev.1.0, Sep.19.2003, page 4 of 15
M61520FP
(2) Input/output characteristics
Limits
Item
Symbol
Min.
Typ.
Max.
Unit
Condition
Input impedance
Rin
30
60
90
KΩ
66pin, 74pin
Input-selector max. input voltage
Vin
1.8
2.2

Vrms
66pin, 74pin
FL, FR OUT max. output voltage
Vom
1.8
2.2

Vrms
REC OUT max. output voltage
Vomrec
1.8
2.2

Vrms
Input on pins 8 and 9, output on pins 46
and 53, RL = 10 kΩ, THD = 1%, bass
boost = on, fin = 80 Hz
Input on pins 2 and 3, output on pins 62
and 64, RL = 10 kΩ, THD = 1%, fin = 1
kHz
C, SL, SR, SW max. output
voltage
Vomvol
1.8
2.2

Vrms
Bypass gain 1
Gv1

-8.0

dB
Bypass gain 2
Max. attenuation
Gv2
ATT

-87
0
-92


dB
dB
Gain from pins 8 to 53 and pins 9 to 46.
Vo = 1 Vrms, on pins 40 and 36, JIS-A
filter
ADOUT output noise voltage
Vadno

4.0
12.0
µVrms
RECOUT output noise voltage
Vrecno

7.0
15.0
µVrms
JIS-A filter, when no signal is present, RG
= 10 kΩ, on pins 4 and 6, “normal
function” settings
JIS-A filter, when no signal is present, RG
= 10 kΩ, on pins 62 and 64, “normal
function” settings
FL, FROUT output noise voltage
C, SL, SRVOLOUT output noise
voltage
Vono1
Vvolno1


7.0
6.0
15.0
12.0
µVrms
µVrms
SW VOLOUT output noise
voltage
FL, FROUT output noise voltage
Vvolwno1 
12.0
24.0
µVrms
Vono2

5.0
10.0
µVrms
C, SL, SRVOLOUT output noise
voltage
SW VOLOUT output noise
voltage
Vvolno2

4.0
8.0
µVrms
Vvolwno2 
8.0
16.0
µVrms
Distortion on FL, FROUT
THD

0.01
0.05
%
Distortion on REC OUT
THDrec

0.01
0.05
%
Distortion on C, SL, SR,
SWVOLOUT
Crosstalk between channels
THDvol

0.01
0.05
%
CT

-70
-55
dB
CTrec

-70
-55
dB
Normal function settings:
•
•
•
•
•
Input attenuator: -8 dB
REC input gain amp: +1 dB
FL, FR, C, SL, SR, SW input gain amp: 0 dB
SL, SR, C output gain amp: 0 dB
SW output gain amp: +6 dB
Rev.1.0, Sep.19.2003, page 5 of 15
Input on pins 10 and 11, output on pins
36 and 40. RL = 10 kΩ, THD = 1%, fin =
1 kHz, gain = 6 dB
Gain from pins 4 to 74 and pins 6 to 66.
JIS-A filter, when no signal is
present, Rg = 10 kΩ, volume
setting: 0 dB, “normal
function” settings
JIS-A filter, when no signal is
present, Rg = 10 kΩ, volume
setting: -∞ dB, “normal
function” setting
46, 53pin
40, 36pin
28pin
46, 53pin
40, 36pin
28pin
On pins 46 and 53, BW = 400 to 30 kHz,
Vo = 300 mVrms, RL = 30 kΩ
On pins 62 and 64, BW = 400 to 30 kHz,
Vo = 300 mVrms, RL = 51 kΩ
On pins 40 and 36, BW = 400 to 30 kHz,
Vo = 300 mVrms, RL = 30 kΩ
Vo = 0.5 Vrms, RL = 10 kΩ, JIS-A, Rg =
10 kΩ, between pins 46 and 53
Vo = 0.5 Vrms, RL = 30 kΩ, JIS-A, Rg =
10 kΩ, between pins 62 and 64
M61520FP
Specification of Control Data
Data is fetched on rising edges of SCK; after 16 bits have been fetched, they are internally latched on the rising edge of
REQ.
DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
SCK
REQ
(All data for the ten formats must be initialized each time the power is turned on.)
D0 D1 D2 D3 D4
A
B
0
0
0
0
0
0
D5
0
1
D6
D7
D8
(1)
Input selector
(6)
(7)
MIC MIX/FL/FR Gain SL/SR/C Gain
(15)
(16)
(8)
SW
Gain
D9
D10
D11
(2)
(3)
Input ATT
REC inGain
(9)
(10)
1
0
0
0
D
1
0
0
1
0
0
E
1
0
1
0
0
0
0
F
1
0
1
1
0
0
0
(11)
(12)
Lch
volume
Rch
volume
(18)
1
0
0
0
0
0
H
1
1
0
1
0
0
0
D15
(13)
(14)
PORT5
PORT6
(19)
(19)
Bass Boost
1
D14
(5)
FL/FR inGain SL/SR/C/SW inGain
PORT1 PORT2 PORT3 PORT4
ALL MUTE MIC MUTE REC2 MUTE
G
D13
(4)
(17)
C
D12
Chip address
1
(19)
Cch
volume
(19)
volume
SLch
(19)
SRch
volume
(19)
SWch
volume
Initial internal state of the IC (state just after power is turned on):
(1) Input selector :
(2) Input ATT :
(3) Record-input gain amp :
(4) FL/FRch input gain amp :
(5) SL/SR/C/SWch input gain amp :
(6) MIC mixing gain,
FL/FR output gain amp :
(7) SL/SR/Cch output gain amp :
(8) SWch output gain amp :
MUTE
-8dB
+1dB
0dB
0dB
0dB
0dB
+6dB
(9) OUTPUTPORT1 :
(10) OUTPUTPORT2 :
(11) OUTPUTPORT3 :
(12) OUTPUTPORT4 :
(13) OUTPUTPORT5 :
(14) OUTPUTPORT6 :
(15) Mute all :
(16) MIC MUTE :
(17) REC2 MUTE :
PORT1OFF
PORT2OFF
PORT3OFF
PORT4OFF
PORT5OFF
PORT6OFF
No muting
MUTE
THRU
(18) Bass boost:
(19) LchVOL :
(20) RchVOL :
(21) CchVOL :
(22) SLchVOL :
(23) SRchVOL :
(24) SWchVOL :
No boost
-∞dB
-∞dB
-∞dB
-∞dB
-∞dB
-∞dB
Note: Do not input values other than those specified above. Operation is not guaranteed with other values.
Rev.1.0, Sep.19.2003, page 6 of 15
1
M61520FP
Setting just after power
is turned on
♦
(1) Input selector setting
INPUT SEL.
♦
D4A
D5A
(7) SL/SR/C ch output gain amp setting
(15) Mute-all setting
D6A
ALL MUTE
1
0
0
0
2
0
0
1
3
0
1
0
SL/SR/C GAIN AMP D6B
♦
0
1
0
1
1
(8) SW ch output gain amp setting
(16) Microphone mute setting
1
0
0
SW GAIN AMP
MIC MUTE
6
1
0
1
MUTE
1
1
1
♦
-8dB
D7B
+6dB
0
+10dB
1
(9) Output port 1 setting
D7A
D8A
0
D9A
0
0
-13 dB
0
0
1
-4.4 dB
0
1
0
-9.4 dB
0
1
1
-11.6 dB
1
0
0
-16.6 dB
1
0
1
PORT1
♦
REC IN GAIN
D10A
0
0
+3 dB
0
1
+4.6 dB
1
0
+6.6 dB
1
1
0
PORT1 ON
1
D12A
0
+3.6 dB
1
0
PORT2 ON
1
PORT3
♦
D10B
PORT3 OFF
0
PORT3 ON
1
PORT4
♦
D11B
PORT4 OFF
0
PORT4 ON
1
(13) Output port 5 setting
SL/SR/C/SW IN GAIN
PORT5
♦
D13A
0 dB
0
+3.6 dB
1
D12B
PORT5 OFF
0
PORT5 ON
1
(14) Output port 6 setting
PORT6
♦
(6) MIC mixing gain, FL/FR ch output gain setting
MIC MIX GAIN
♦
FL/FR GAIN AMP
D4B
D5B
0 dB
0 dB
0
0
-2 dB
+2 dB
0
1
-6.5 dB
+6.5 dB
1
0
-10.5 dB
+10.5 dB
1
1
Rev.1.0, Sep.19.2003, page 7 of 15
THRU
MUTE
BASS BOOST
D9B
PORT2 OFF
(11) Output port 3 setting
(5) SL/SR/C/SW ch input gain amp setting
♦
REC2 MUTE
♦
(18) Bass-boost setting
(12) Output port 4 setting
0 dB
MUTE
D8B
PORT1 OFF
PORT2
♦
(4) FL/FR ch input gain amp setting
FL/FR IN GAIN
♦
(10) Output port 2 setting
D11A
+1 dB
THRU
(17) RECOUT2 mute setting
(3) REC input gain amp setting
♦
No MUTE
ALL MUTE
4
INPUT ATT
♦
♦
5
(2) Input ATT setting
♦
0
+6dB
D13B
PORT6 OFF
0
PORT6 ON
1
♦
No Boost
Boost ON
M61520FP
(19) Volume setting
(FLch, FRch, SLch, SRch, SWch)
ATT
D7C~H
D8C~H
D9C~H
Setting just after power
is turned on
♦
ATT
D10C~H D11C~H D12C~H D13C~H
D7C~H
D8C~H
D9C~H
D10C~H D11C~H D12C~H D13C~H
±0dB
0
0
0
0
0
0
0
-45.0dB
1
0
1
1
0
1
0
-1.0dB
1
0
0
0
0
0
0
-46.0dB
0
1
1
1
0
1
0
-2.0dB
0
1
0
0
0
0
0
-47.0dB
1
1
1
1
0
1
0
-3.0dB
1
1
0
0
0
0
0
-48.0dB
0
0
0
0
1
1
0
-4.0dB
0
0
1
0
0
0
0
-49.0dB
1
0
0
0
1
1
0
-5.0dB
1
0
1
0
0
0
0
-50.0dB
0
1
0
0
1
1
0
-6.0dB
0
1
1
0
0
0
0
-51.0dB
1
1
0
0
1
1
0
-7.0dB
1
1
1
0
0
0
0
-52.0dB
0
0
1
0
1
1
0
-8.0dB
0
0
0
1
0
0
0
-53.0dB
1
0
1
0
1
1
0
-9.0dB
1
0
0
1
0
0
0
-54.0dB
0
1
1
0
1
1
0
-10.0dB
0
1
0
1
0
0
0
-55.0dB
1
1
1
0
1
1
0
-11.0dB
1
1
0
1
0
0
0
-56.0dB
0
0
0
1
1
1
0
-12.0dB
0
0
1
1
0
0
0
-57.0dB
1
0
0
1
1
1
0
-13.0dB
1
0
1
1
0
0
0
-58.0dB
0
1
0
1
1
1
0
-14.0dB
0
1
1
1
0
0
0
-59.0dB
1
1
0
1
1
1
0
-15.0dB
1
1
1
1
0
0
0
-60.0dB
0
0
1
1
1
1
0
-16.0dB
0
0
0
0
1
0
0
-61.0dB
1
0
1
1
1
1
0
-17.0dB
1
0
0
0
1
0
0
-62.0dB
0
1
1
1
1
1
0
-18.0dB
0
1
0
0
1
0
0
-63.0dB
1
1
1
1
1
1
0
-19.0dB
1
1
0
0
1
0
0
-64.0dB
0
0
0
0
0
0
1
-20.0dB
0
0
1
0
1
0
0
-65.0dB
1
0
0
0
0
0
1
-21.0dB
1
0
1
0
1
0
0
-66.0dB
0
1
0
0
0
0
1
-22.0dB
0
1
1
0
1
0
0
-67.0dB
1
1
0
0
0
0
1
-23.0dB
1
1
1
0
1
0
0
-68.0dB
0
0
1
0
0
0
1
-24.0dB
0
0
0
1
1
0
0
-69.0dB
1
0
1
0
0
0
1
-25.0dB
1
0
0
1
1
0
0
-70.0dB
0
1
1
0
0
0
1
-26.0dB
0
1
0
1
1
0
0
-71.0dB
1
1
1
0
0
0
1
-27.0dB
1
1
0
1
1
0
0
-72.0dB
0
0
0
1
0
0
1
-28.0dB
0
0
1
1
1
0
0
-73.0dB
1
0
0
1
0
0
1
-29.0dB
1
0
1
1
1
0
0
-74.0dB
0
1
0
1
0
0
1
-30.0dB
0
1
1
1
1
0
0
-75.0dB
1
1
0
1
0
0
1
-31.0dB
1
1
1
1
1
0
0
-76.0dB
0
0
1
1
0
0
1
-32.0dB
0
0
0
0
0
1
0
-77.0dB
1
0
1
1
0
0
1
-33.0dB
1
0
0
0
0
1
0
-78.0dB
0
1
1
1
0
0
1
-34.0dB
0
1
0
0
0
1
0
-79.0dB
1
1
1
1
0
0
1
-35.0dB
1
1
0
0
0
1
0
-80.0dB
0
0
0
0
1
0
1
-36.0dB
0
0
1
0
0
1
0
-81.0dB
1
0
0
0
1
0
1
-37.0dB
1
0
1
0
0
1
0
-82.0dB
0
1
0
0
1
0
1
-38.0dB
0
1
1
0
0
1
0
-83.0dB
1
1
0
0
1
0
1
-39.0dB
1
1
1
0
0
1
0
-84.0dB
0
0
1
0
1
0
1
-40.0dB
0
0
0
1
0
1
0
-85.0dB
1
0
1
0
1
0
1
-41.0dB
1
0
0
1
0
1
0
-86.0dB
0
1
1
0
1
0
1
-42.0dB
0
1
0
1
0
1
0
-87.0dB
1
1
1
0
1
0
1
-43.0dB
1
1
0
1
0
1
0
-∞dB
1
1
1
1
1
1
1
-44.0dB
0
0
1
1
0
1
0
♦
Note: Do not input values other than those specified above. Operation is not guaranteed with other values.
Rev.1.0, Sep.19.2003, page 8 of 15
M61520FP
Control-Data Timing
t1, t2
VDD=5V
2.2V
DATA
0.8V
t6
t7
t1
t4
t2
2.2V
SCK
0.8V
t5
t10
t3
t9
t8
2.2V
REQ
0.8V
t1
t2
Name
Symbol
Min.
Typ.
Max.
Unit
Time for signal to rise
Time for signal to fall
t1
t2




0.3
0.3
µs
µs
SCK clock width
SCK high pulse width
t3
t4
1
0.4




µs
µs
SCK low pulse width
DATA setup time
t5
t6
0.4
0.4




µs
µs
DATA hold time
REQ rise hold time
t7
t8
0.4
0.8




µs
µs
REQ high pulse width
SCK setup time
t9
t10
0.4
0.4




µs
µs
Rev.1.0, Sep.19.2003, page 9 of 15
M61520FP
Functional description
(1) Input selector, input attenuator
The IC incorporates a selector for either of two six-input channels and a mute switch. An input level for the selected
input is chosen from among -4.4, -8, -9.4, -11.6, -13, and -16.6 dB.
60k
1
2
3
4
5
60k
60k
-4.4/-9.4/
-8/-13/
-11.6/-16.6dB
60k
60k
+
60k
-
ATT
+
Balanced output for the ADC
(positive phase)
-
6
+
Balanced output for the ADC
(inverse phase)
(2) REC block
The REC signal is mixed with the MIC signal and then output. The gain of the signal for mixing with the MIC
signal is selected from among +1 dB, +3, +4.6, +6.6 dB. The REC OUT2 side includes a mute switch.
0dB
From MIC
REC OUT1
REC input
+
60k
-
-
REC OUT2
+
MUTE
SW
+1/+3/+4.6/+6.6dB
Rev.1.0, Sep.19.2003, page 10 of 15
M61520FP
(3) Microphone mixing
In the microphone-input circuit, the input signal is passed through an op-amp buffer to prevent crosstalk between
FL and FR and then mixed with FL and FR. The level of the mixed signal changes in accordance with the variable
gain of the output gain amplifier (see the table below). A mute switch is incorporated to improve noise
characteristics when microphone mixing is not in use.
to REC OUT
60k
Microphone input
MUTE SW
0/-2/-6.5/-10.5dB
+
-
-
ATT
Lch/Rch OUT
+
Main signals
FL,FR
The relation between the output gain and mixing gain
FL/FR output gain
Mixing gain
0
0
+2dB
+6.5dB
-2dB
-6.5dB
+10.5dB
-10.5dB
(4) Master volume (FL ch, FR ch, C ch, SL ch, SR ch, SW ch)
This IC incorporates six independently controlled electronic volumes, each of which has low-distortion and lownoise characteristics.
Volume: attenuation of 0 dB to –87 dB, settable in 1-dB steps.
FL/FRch
VOL IN
+
-
VOL OUT
Volume: 0 dB to -87 dB in 1-dB steps, 0/+2/+6.5/+10.5dB
SL/SR/Cch
SWch
VOL IN
VOL IN
+
Volume: 0 dB to -87 dB in 1-dB steps, -
Rev.1.0, Sep.19.2003, page 11 of 15
+
-
VOL OUT
Volume: 0 dB to -87 dB in 1-dB steps, -
0/+6dB
+6/+10dB
VOL OUT
M61520FP
(5) Equivalent Circuit for the Bass-Boost Circuit
Q=4 (G=10dB)
Input
Output
+
-
SEL
G0
0dB
Switching-noise
reduction circuit
f0
Positive-feedback second-order high-pass filter circuit for the bass-boost module
R1
C1
VIN
C2
VOUT
+K
R2
Amplitude characteristics of the second-order high-pass filter
Q
G0
1
2
4
5
10
0 to 1dB
6dB
10dB
13dB
20dB
The transfer function is described by the following expressions:
ωo2 =
Ks2
VOUT
=
VIN
s2 + s
1
1
1
1
+
+ (1-K)
+
R2C2
R1C1
R1R2C1C2
R2C1
In the above figure, when R1 = 1.2 kΩ, R2 = 470 kΩ, and C1 = C2 = 0.1 µF (K = +1),
Rev.1.0, Sep.19.2003, page 12 of 15
1
Q=
The bass-boost module includes the above positive-feedback second-order high-pass filter.
Fo = 70 Hz (f0 = ωo/2π), Q = 10.
1
R1R2C1C2
R1C1
+
R2C2
R1C2
+ (1-K)
R2C1
R2C2
R1C1
M61520FP
Gain Level Diagram
<I NPUT SELECTOR>
SELECTOR
INPUT
ATT
TOTAL GAIN
AD OUT
-4.4/-9.4/
-8/-13/
-11.6/-16.6dB
Input D range
2.2Vrms(9V Vcc)
<REC BLOCK>
MIC INPUT
-1
-4.4/-8/-9.4/-11.6/-13/-16.6dB
MIC BUF
MIC MIXING (0dB)
TOTAL GAIN
+
REC INPUT
Input D range
2.2Vrms (9V Vcc)
<FL,FR BUF>
REC OUT
REC MIXING
(+1/+3/+4.6/+6.6dB)
Output D range
2.2Vrms(9V Vcc)
INPUT GAIN
(0/+3.6dB)
FL,FR IN
+1/+3/+4.6/+6.6dB (Mixed)
FL,FR BUF OUT
+
Input D range
1.8Vrms (9V Vcc)
Output D range
1.8Vrms (9V Vcc)
MIC MIXI NG
(0/-2/-6.5/-10.5dB)
MIC BUF
Coupled
<FL,FR Vol>
OUTPUT GAIN
(0/+2/+6.5/+10.5dB)
FL,FR VOL IN
FL,FR OUT
Bass Boost
Input D range
1.8Vrms (9V Vcc)
<C to SW BUF>
Output D range
2.2Vrms (9V Vcc)
C to SW IN
Input D range
1.8Vrms (9V Vcc)
INPUT GAIN
(0/+3.6dB)
C to SW BUFOUT
TOTAL GAIN
Output D range
0dB or 3.6dB
1.8Vrms (9V Vcc)
<C,SL,SR Vo l>
C,SL,SR VOL IN
Input D range
C,SL,SR OUT
OUTPUT GAIN
(0/+6dB)
1.8Vrms (9V Vcc)
<SW Vol>
1.8Vrms (9V Vcc)
0dB or 6dB
Output D range
2.2Vrms (9V Vcc)
SW VOL IN
Input D range
SW OUT
OUTPUT GAIN
(+6/+10dB)
Output D range
2.2Vrms (9V Vcc)
Caution: Do not input a signal which exceeds the power-supply voltage level.
Rev.1.0, Sep.19.2003, page 13 of 15
TOTAL GAIN
TOTAL GAIN
6dB or 10dB
M61520FP
1
LRECIN
2
RRECIN
3
ADR+OUT
4
ADR-OUT
ADL +OUT
60k
60k
60k
60k
FRIN
11
CIN
SWIN
66
60k
60k
60k
60k
60k
65
60k
+
-
+
+
-
+
60k
ATT
-1
+1/+3
+4.6/+6.6dB
-4.4/-9.4
-8/-13
-11.6/-16.6dB
C/SW block REF
-4.4/-9.4/
-8/-13/
-11.6/-16.6dB
-1
+
-
L/R/FL/FR block REF
Coupled
60k
47µ
REFOUTEX1
47µ
57
0.01µ
REFOUTEX1
100µ
Analog GND
Rch OUT
52
470k
0.1µ
0/+3.6dB
51
SW
1.2k
0.1µ
FR
15
50
10µ
MCU
MCU
0.01µ
0.01µ
+
220µ
53
Bass
Boost
C
14
REFOUTEX2
0.01µ
+
47µ
54
0/+2/
+6.5/+10.5dB
SL
13
60
55
SR
Digital GND
RRECOUT2
Internal power
supply
+
-
0/+3.6dB
0/+3.6dB
61
100µ
FL
60k
RRECOUT1
56
60k
0/+3.6dB
62
58
0/+3.6dB
60k
LRECOUT2
59
REF.
FR
12
63
SL/SR block REF
ATT
60k
LRECOUT1
ATT
0/+3.6dB
60k
64
+
SLIN
67
+1/+3
+4.6/+6.6dB
8
10
68
Input selector
60 k
7
SRIN
69
+
-
6
9
70
60k
Input selector
5
FLIN
71
60k
0/-2/-6.5/-10.5dB
ADL -OUT
LI N1
72
+
60k
MICIN
73
LI N2
RIN1
74
LI N3
RIN2
75
LI N4
RIN3
76
LI N5
RIN4
77
LI N6
RIN5
78
+
79
AnalogVCC
9.0V
+
80
RIN6
Application Example
16
+
49
I/F
0/+2/
+6.5/+10.5dB
17
48
FRVOLREF
Bass
Boost
47
PORT1
18
PORT2
19
PORT3
20
PORT4
21
PORT5
22
43
PORT6
23
42
BBREFOUT
46
FL
Lch OUT
45
470k
0.1µ
44
SR
SL
C
SW
1.2k
0.1µ
10µ
+6/
+10dB
24
0/
+6dB
0/
+6dB
0/
+6dB
+
41
FLVOLREF
Digital VDD
Rev.1.0, Sep.19.2003, page 14 of 15
33
34
+
10µ
35
36
37
38
10
39
40
SROU T
32
SRVOLREF
+
10µ
31
SLOUT
30
SLVOLREF
29
COUT
+
10µ
28
27
CVOLREF
26
SWOUT
SWVOLREF
25
y
e
b
40
x
41
24
65
64
25
HD
D
JEDEC Code
—
1
80
EIAJ Package Code
QFP80-P-1420-0.80
E
M
F
Weight(g)
1.58
A
Detail F
Lead Material
Alloy 42
L1
c
L
b2
I2
MD
ME
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
Dimension in Millimeters
Min
Nom
Max
3.05
—
—
0.1
0.2
0
2.8
—
—
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.8
—
—
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
—
—
—
—
0.2
—
—
0.1
—
0˚
10˚
—
—
0.5
1.3
—
—
14.6
—
—
—
—
20.6
Recommended Mount Pad
Symbol
I2
MD
Plastic 80pin 14✕20mm body QFP
e
b2
MMP
A2
Rev.1.0, Sep.19.2003, page 15 of 15
A1
ME
80P6N-A
M61520FP
Package Dimensions
HE
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
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