Preliminary M61545AFP Serial Data Control Dual Electronic Volume REJ03F0162-0200 Rev.2.0 Dec 21, 2005 Description The M61545AFP is a dual channel electronic volume controlled with 2-wire serial data. The built-in reference and power regulator circuitries allow operation of an electronic volume with less external parts. M61545AFP is able to cater for large supply voltage range of 4.5 to 15.0V. Features • Electronic volume • • • • • • 0 to –95dB/ 1-dB step, –∞dB 2-ch independent controllable electronic volume Low distortion THD = 0.002% typ. Vno = 5.0μVrms typ. (ATT = –∞, JIS-A network) Supply voltage range Single power supply: Vcc = 4.5 to 15V (regulated) Supply to both digital & analog circuitries Serial data interface 2-wire type Package 8 pin SOP/ 8 pin DIP Process 0.5μ BIC-DMOS Reference circuit Built-in Recommended Operating Condition • Supply voltage range: Vcc = 4.5 to 15.0V VIN1 1 VOUT1 2 GND 3 DATA 4 Outline 8P2S-A(FP) Rev.2.0 Dec 21, 2005 page 1 of 11 M61545AFP Pin Configuration 8 VIN2 7 VOUT2 6 VCC 5 CLOCK M61545AFP Preliminary IC Internal Block Diagram VIN2 VOUT2 8 Vol VCC 7 CLOCK 6 5 + - R2 Vol AMP2 + - Logic Control Vregulated Vol AMP1 Vol REF AMP + R1 1 2 VIN1 VOUT1 3 4 GND DATA Pin Description Pin Symbol Function 1 2 VIN1 VOUT1 1-ch input pin 1-ch output pin 3 4 GND DATA Ground pin Control data input pin. Inputs data in synchronization with clock 5 6 CLOCK VCC Clock input pin for transferring serial data Power supply pin. Stabilize the pin with decoupling capacitor 7 8 VOUT2 VIN2 2-ch output pin 2-ch input pin Absolute Maximum Ratings Parameter Supply voltage Symbol Vcc, Vdd Power dissipation Operating temperature Pd Topr Ratings 16.0 *1 385 –40 to +85 Units V mW °C Storage temperature Tstg –55 to +125 °C Note: *1. These are the allowable values up to Ta = 31°C mounting on 30% wiring density glass epoxy board. Derate by 7.14mW/°C above that temperature. Rev.2.0 Dec 21, 2005 page 2 of 11 M61545AFP Preliminary Electrical Characteristics (Vcc = 14.0V, Ta = 25°C, unless stated otherwise) Parameter Symbol Min Limits Typ Max Unit — 8 –90 10 –80 mA dB Test Conditions Circuit current Maximum attenuation ICC ATT Attenuation error Maximum input voltage ΔATT VIM –2.0 — 0 5.4 2.0 — dB Vrms ATT = 0dB THD = 1%, ATT = –6dB Maximum output voltage VOM VNO1 3.8 — 4.2 1.5 — 5.0 Vrms µVrms THD = 1%, ATT = 0dB ATT = 0dB, Rg = 0, JIS-A Total harmonic distortion VNO2 THD — — 7.0 0.002 12.0 0.009 µVrms % ATT = –∞, Rg = 0, JIS-A F = 1kHz, Vo = 0.5Vrms, ATT = 0dB Channel separation CS — –80 –70 dB Output noise voltage ATT = –∞ F = 1kHz, JIS-A, ATT = 0dB Electrical Characteristics (Vcc = 10.0V, Ta = 25°C, unless stated otherwise) Limits Typ NA Max 10 Unit — –2.0 –90 0 –80 2.0 dB dB VIM VOM — 2.4 4.0 2.9 — — Vrms Vrms THD = 1%, ATT = –6dB THD = 1%, ATT = 0dB Output noise voltage VNO1 VNO2 — — 1.5 6.0 5.0 12.0 µVrms µVrms ATT = 0dB, Rg = 0, JIS-A ATT = –∞, Rg = 0, JIS-A Total harmonic distortion Channel separation THD CS — — 0.002 –80 0.009 –70 % dB Parameter Symbol Circuit current ICC Maximum attenuation Attenuation error ATT ΔATT Maximum input voltage Maximum output voltage Min Test Conditions mA ATT = –∞ ATT = 0dB F = 1kHz, Vo = 0.5Vrms, ATT = 0dB F = 1kHz, JIS-A, ATT = 0dB Electrical Characteristics (Vcc = 7.0V, Ta = 25°C, unless stated otherwise) Limits Parameter Symbol Min Typ NA Max 10 Unit Test Conditions Circuit current ICC Maximum attenuation Attenuation error ATT ΔATT — –2.0 –90 0 –80 2.0 dB dB Maximum input voltage Maximum output voltage VIM VOM — 1.3 2.9 1.8 — — Vrms Vrms THD = 1%, ATT = –6dB THD = 1%, ATT = 0dB Output noise voltage VNO1 VNO2 — — 1.5 5.0 5.0 12.0 µVrms µVrms ATT = 0dB, Rg = 0, JIS-A ATT = –∞, Rg = 0, JIS-A Total harmonic distortion Channel separation THD CS — — 0.002 –80 0.009 –70 % dB Rev.2.0 Dec 21, 2005 page 3 of 11 mA ATT = –∞ ATT = 0dB F = 1kHz, Vo = 0.5Vrms, ATT = 0dB F = 1kHz, JIS-A, ATT = 0dB M61545AFP Preliminary Electrical Characteristics (Vcc = 5.0V, Ta = 25°C, unless stated otherwise) Parameter Symbol Min Limits Typ Max Unit — NA –90 10 –80 mA dB Test Conditions Circuit current Maximum attenuation ICC ATT Attenuation error Maximum input voltage ΔATT VIM –2.0 — 0 2.0 2.0 — dB Vrms ATT = 0dB THD = 1%, ATT = –6dB Maximum output voltage VOM VNO1 0.5 — 1.1 1.5 — 5.0 Vrms µVrms THD = 1%, ATT = 0dB ATT = 0dB, Rg = 0, JIS-A Total harmonic distortion VNO2 THD — — 5.0 0.01 12.0 0.05 µVrms % ATT = –∞, Rg = 0, JIS-A F = 1kHz, Vo = 0.1Vrms, ATT = 0dB Channel separation CS — –80 –70 dB Output noise voltage ATT = –∞ F = 1kHz, JIS-A, ATT = 0dB DC Characteristics of Digital Block Limits Parameter Symbol Typ — Max 0.6 Unit Test Conditions “L” level input voltage VIL Min 0 “H” level input voltage “L” level input current VIH IIL 2.2 –10 — — — 10 V µA VI = 0, “H” level input current IIH — — 10 µA VI = 5V, V Data, clock pin Data, clock pin AC Characteristics of Digital Block Parameter Symbol Min Limits Typ Max CLOCK cycle time CLOCK pulse width (“H” level) tcr tWHC 4 1.6 — — — — CLOCK pulse width (“L” level) CLOCK rise time tWLC tr 1.6 — — — — 0.4 CLOCK fall time DATA setup time tf tSD — 0.8 — — 0.4 — DATA hold time tHD 0.8 — — Clock and Data Timings (Recommended Conditions) tcr 75% CLOCK 25% tf tr tWHC DATA tWLC 75% tSD Rev.2.0 Dec 21, 2005 page 4 of 11 tHD Unit µsec M61545AFP Preliminary Relationship Between Data, Clock DATA Latch signal is “H”. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 CLOCK D0 DATA signal is read at rising edge of CLOCK. Latch signal is read at falling edge of CLOCK. Data Format for “H” & “L” DATA DATA = “L” DATA =”H” CLOCK For initialization, 2 blocks of identical 18-bit data need to be sent. The 2 blocks of data would set the operation condition for M61545AFP. This shown in figure below, DATA CLOCK 1 st Block of Data time 2nd Block of Data 0.2sec There should be a delay of 0.2 second before the first block of Clock and Data appear. The interval between the 1st Block of data and the 2nd Block should be 0.2 second as well. This sequence is to ensure proper operation of M61545AFP due to the wide dynamic voltage range, which M61545AFP is made to cater for. This format of initialization needs to be done once only during every powering up of M61545AFP. It recommends to use external mute switch together because it might generate the shock noise during this initial setup timing. Rev.2.0 Dec 21, 2005 page 5 of 11 M61545AFP Preliminary Initialization Examples Example 1: Setting supply of 9.0 to 12.0 V, and attenuation of – 20dB (please refer to page 7 for data format) /CLOCK /DATA 2.0m 2.8m st 1 Block data Delay of 0.2 second Data format is A14BH Rev.2.0 Dec 21, 2005 page 6 of 11 time (s) 3.6m nd 2 Block data 4.4m M61545AFP Preliminary Example 2: Setting supply of 4.5V to 6.0V, and attenuation of –90dB (please refer to data format below) /CLOCK /DATA 2.7m time (s) 3.4m 1st Block data 4.2m 2nd Block data Delay of 0.2 second Data format is D5A3H Data Input Format D0 D1 D2 D3 D4 D5 D6 D7 D8 Left Channel D10 D11 Right Channel DC Switch Supply Voltage (V) D14 D15 12.0 to15.0 9.0 to 12.0 1 1 1 0 6.0 to 9.0 4.5 to 6.0 0 0 1 0 Rev.2.0 Dec 21, 2005 page 7 of 11 D9 D12 D13 D14 D15 DC Switch D16 D17 1 1 M61545AFP Preliminary Volume Code D0 D1 D2 D3 D4 D5 D6 ← Left Channel D7 L D8 L D9 L D10 L D11 L D12 L D13 L ← Right Channel 0 –1 –2 L L L L L L L L L L L H H L –3 –4 L L L L L L L L L H H L H L –5 –6 L L L L L L L L H H L H H L –7 –8 L L L L L L L H H L H L H L –9 –10 L L L L L L H H L L L H H L –11 –12 L L L L L L H H L H H L H L –13 –14 L L L L L L H H H H L H H L –15 –16 L L L L L H H L H L H L H L –17 –18 L L L L H H L L L L L H H L –19 –20 L L L L H H L L L H H L H L –21 –22 L L L L H H L L H H L H H L –23 –24 L L L L H H L H H L H L H L –25 –26 L L L L H H H H L L L H H L –27 –28 L L L L H H H H L H H L H L –29 –30 L L L L H H H H H H L H H L –31 –32 L L L H H L H L H L H L H L –33 –34 L L H H L L L L L L L H H L –35 –36 L L H H L L L L L H H L H L –37 –38 L L H H L L L L H H L H H L –39 –40 L L H H L L L H H L H L H L –41 –42 L L H H L L H H L L L H H L –43 –44 L L H H L L H H L H H L H L –45 –46 L L H H L L H H H H L H H L –47 –48 L L H H L H H L H L H L H L –49 L H H L L L H ATT Rev.2.0 Dec 21, 2005 page 8 of 11 M61545AFP Preliminary D0 D1 D2 D3 D4 D5 D6 ← Left Channel D8 H D9 H D10 L D11 L D12 H D13 L ← Right Channel –50 D7 L –51 –52 L L H H H H L L L H H L H L –53 –54 L L H H H H L L H H L H H L –55 –56 L L H H H H L H H L H L H L –57 –58 L L H H H H H H L L L H H L –59 –60 L L H H H H H H L H H L H L –61 –62 L L H H H H H H H H L H H L –63 –64 L H H L H L H L H L H L H L –65 –66 H H L L L L L L L L L H H L –67 –68 H H L L L L L L L H H L H L –69 –70 H H L L L L L L H H L H H L –71 –72 H H L L L L L H H L H L H L –73 –74 H H L L L L H H L L L H H L –75 –76 H H L L L L H H L H H L H L –77 –78 H H L L L L H H H H L H H L –79 –80 H H L L L H H L H L H L H L –81 –82 H H L L H H L L L L L H H L –83 –84 H H L L H H L L L H H L H L –85 –86 H H L L H H L L H H L H H L –87 –88 H H L L H H L H H L H L H L –89 –90 H H L L H H H H L L L H H L –91 –92 H H L L H H H H L H H L H L –93 –94 H H L L H H H H H H L H H L –95 –∞ H H L H H H H H H H H H H H ATT Rev.2.0 Dec 21, 2005 page 9 of 11 M61545AFP Preliminary Application Example 2.2µF 100µF + + VIN2 VOUT2 8 Vol R2 VCC 7 CLOCK 6 5 + Vol AMP2 + - Vregulated Logic Control Vol AMP1 Vol R1 REF AMP + 1 2 VIN1 + 2.2µF VOUT1 3 4 GND DATA Units: Resistance: Ω Capacitance: F Rev.2.0 Dec 21, 2005 page 10 of 11 M61545AFP Preliminary Package Dimensions Unit: mm 4.85 4.4 5.25 Max 5 8 1 0.75 Max *0.22 ± 0.05 0.20 ± 0.04 2.03 Max 4 0.25 6.50 +– 0.15 1.05 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0° – 8° 0.25 0.60 +– 0.18 0.15 0.12 M *Dimension including the plating thickness Base material dimension Rev.2.0 Dec 21, 2005 page 11 of 11 Package Code JEDEC JEITA Mass (reference value) FP-8D — Conforms 0.10 g Sales Strategic Planning Div. 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