M61532FP 8ch Electronic Volume with 9 Input Selector REJ03F0041-0100Z Rev.1.0 Sep.19.2003 Feature FUNCTION FEATURE Electric Volume 8channel independent Electric Volume with High Voltage Transistor. (0~-99.0dB/0.5dBstep,-∞dB) Twin Input Selector Front L/R channel has twin 9 Input Selector.(Main & Sub) Multi Channel Input Selector Input Gain Control Every channel has 2 Input Selector and Input Gain Control Input Gain Control (0/+6/+12/+18dB) REC Output Output Gain Control 2 Lines REC Output (Both L and R channels) Output Gain Control (0/+6/+12/+18dB) Output for ADC Input ATT Built-in Single-end output (for ADC) Input ATT (for ADC:0/-6/-12/-18dB) Application Receiver,AV Amp,Mini Stereo etc. Recommended Operating Condition Supply Voltage Range AVCC=7.0V(typ) , AVEE=-7.0V(typ) , DVDD=2.7~5.5V Multi FRin REC OUTL Multi FLin 1 AVEE AVCC DVDD DGND DATA LATCH SUB OUTL CLOCK System Block Diagram MCU I/F 2 Output Gain Control 3 Lout 4 Lch 5 Output Gain Control 6 Rout 7 8 Multi SBLin Output Gain Control SBLout 9 Multi SBRin 1 2 SBRout 3 Multi Cin 4 Rch Output Gain Control Input ATT (for ADC) Output Gain Control Cout ADOUTL 5 Input ATT (for ADC) 6 7 8 Output Gain Control Multi SLin Output Gain Control SRout ADOUTR 9 Multi SRin SLout SUB OUTR REC OUTR Multi SWin Output Gain Control SWRout GND Rev.1.0, Sep.19.2003, page 1 of 14 M61532FP SLOUT SLVIN SLSELOUT CSELOUT CVIN COUT SWOUT SWVIN SWSELOUT SBRSELOUT SBRVIN SBROUT SBLOUT SBLVIN SBLSELOUT GND Block Diagram and Pin Configuration (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SROUT 41 24 AVEE SRVIN 42 23 GND SRSELOUT 43 22 AVCC LSELOUT 44 21 DVDD LVIN 45 20 CLOCK LOUT 46 19 LATCH ROUT 47 18 DATA RVIN 48 17 DGND RSELOUT 49 16 MCU I/F SBRIN2 SR 58 7 AROUT GND 59 6 ALOUT SUBOUTR 60 5 REC R2 SUBOUTL 61 4 REC L2 REC R1 62 3 GND REC L1 63 2 INL1 GND 64 1 INR1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 INL2 8 RIN1 INR2 57 GND INL3 LIN1 INR3 9 RIN2 INL4 10 LIN2 SWIN1 INR4 CIN1 INL5 11 SWIN2 INR5 SLIN1 INL6 12 CIN2 INR6 SRIN1 INL7 13 SLIN2 INR7 SBLIN1 INL8 14 SRIN2 INR8 SBRIN1 INL9 15 SBLIN2 INR9 GND 56 SBL 55 SBR 54 SW 53 C 52 SL 51 L 50 R Rev.1.0, Sep.19.2003, page 2 of 14 M61532FP Pin Description PIN No. Name Function 2,80,78,76,74,72,70,68,66, 1,79,77,75,73,71,69,67,65 3,8,23,25,50,59,64 63,4,62,5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 60 61 INL1,2,3,4,5,6,7,8,9 INR1,2,3,4,5,6,7,8,9 GND1,2,3,4,5,6,7, REC L1/L2/R1/R2 ALOUT AROUT RIN2 LIN2 SWIN2 CIN2 SLIN2 SRIN2 SBLIN2 SBRIN2 DGND DATA LATCH CLOCK DVDD AVCC AVEE SBLSELOUT SBLVIN SBLOUT SBROUT SBRVIN SBRSELOUT SWSELOUT SWVIN SWOUT COUT CVIN CSELOUT SLSELOUT SLVIN SLOUT SROUT SRVIN SRSELOUT LSELOUT LVIN LOUT ROUT RVIN RSELOUT SBRIN1 SBLIN1 SRIN1 SLIN1 CIN1 SWIN1 LIN1 RIN1 SUBOUTR SUBOUTL Input pin of L channel (Input Selector) Input pin of R channel (Input Selector) Analog Ground Output pin of REC L/R Output pin of L channel for ADC(Single ended) Output pin of R channel for ADC(Single ended) Input pin of R channel Input pin of L channel Input pin of SW channel Input pin of C channel Input pin of SL channel Input pin of SR channel Input pin of SBL channel Input pin of SBR channel Ground of internal logic circuit Input pin of Control Data Input pin of Control Trigger Input pin of Control Clock Power supply to internal logic circuit Positive power supply to internal analog circuit Negative power supply to internal analog circuit Output pin of SBL channel volume input selector Input pin of SBL channel volume Output pin of SBL channel Output pin of SBR channel Input pin of SBR channel volume Output pin of SBR channel volume input selector Output pin of SW channel volume input selector Input pin of SW channel volume Output pin of SW channel Output pin of C channel Input pin of C channel volume Output pin of C channel volume input selector Output pin of SL channel volume input selector Input pin of SL channel volume Output pin of SL channel Output pin of SR channel Input pin of SR channel volume Output pin of SR channel volume input selector Output pin of L channel volume input selector Input pin of L channel volume Output pin of L channel Output pin of R channel Input pin of R channel volume Output pin of R channel volume input selector Input pin of SBR channel Input pin of SBL channel Input pin of SR channel Input pin of SL channel Input pin of C channel Input pin of SW channel Input pin of L channel Input pin of R channel Sub Output pin of R channel Sub Output pin of L channel Rev.1.0, Sep.19.2003, page 3 of 14 M61532FP Absolute Maximum Ratings Symbol Parameter Condition Ratings Unit Supply voltage Power supply AVCC-AVEE ±8.0 V DVDD-GND 6.0 Pd Kθ Power dissipation Thermal derating Ta≤25°C Ta>25°C 1250 12.5 mW mW/°C Topr Tstg Operating temperature Storage temperature -20~+55 -40~+125 °C °C THERMAL DERATINGS (MAXIMUM RATING) POWER DISSIPATION pd (W) 1.5 1.0 0.5 0 55 0 Rev.1.0, Sep.19.2003, page 4 of 14 25 50 75 100 125 150 AMBIENT TEMPERATURE Ta ( C) M61532FP Recommended Operating Conditions (Ta=25°C, unless otherwise noted) Parameter Symbol Analog supply voltage (Positive) Analog supply voltage (Negative) Digital supply voltage Logic “H” level input voltage Logic “L” level input voltage Condition MIN TYP MAX Unit AVCC 4.5 7.0 7.5 V AVEE -7.5 -7.0 -4.5 V DVDD 2.7 3.3 5.5 V VIH DGND reference DVDD x 0.7 DVDD V VIL DGND reference DGND DVDD x 0.2 V Note:VEE≤DGND≤VDD≤VCC Relationship Between Data and Clock LATCH SIGNAL H DATA L D0 D1 D21 D22 D23 H CLOCK L H LATCH L DATA signal is read at the rising edge of CLOCK. Serial data (D0 – D23) is loaded at the rising edge of the LATCH signal. Rev.1.0, Sep.19.2003, page 5 of 14 D0 M61532FP Clock and Data Timings tSC tcr 75% CLOCK 25% 25% tr tf tWHC tWLC 75% DATA 25% tr tf tSD tHD tWHC tr tf tSL LATCH 75% 25% Timing Definition of Digital Block Limits Symbol Parameter Min typ Max Unit tcr tWHC Clock cycle time Clock pulse width (“H” level) 4 1.6 µsec tWLC tr Clock pulse width (“L” level) Rising time of clock,data and latch 1.6 0.4 tf tSD Falling time of clock,data and latch Data setup time 0.8 0.4 tHD tSL Data hold time Latch setup time 0.8 1 tWHL tSC Latch pulse width Clock setup time 1.6 4 Rev.1.0, Sep.19.2003, page 6 of 14 D2a D1b D1c D1c D1c D0c Rev.1.0, Sep.19.2003, page 7 of 14 D0c D0c D2c D2c D2c D2b Input Selector (Main) D1a D0b D0a D4b D4a D4c D4c D4c SBLch Volume D3c SLch Volume D3c Cch Volume D3c FLch Volume D3b D3a D6a D5c D5c D5c D5b D6c D6c D6c D6b Input Selector (Sub) D5a D7c D7c D7c D7b D7a D9a D8c D8c D8c D8b D9c D9c D9c D9b Input ATT D8a D10c D10c D10c D12b Multi Input Selector D12a D12c D12c D12c SBRch Volume D11c SRch Volume D11c SWch Volume D11c FRch Volume D11b REC Output 2 REC Output 1 D10b D11a D10a D13c D13c D13c D13b Multi Input Mute D13a D14c D14c D14c D14b FL/FR VOL Control D14a D16a D15c D15c D15c D15b 0 D16c 0 D16c 0 D16c 0 D16b Input Gain Control D15a D18a 0 D17c 0 D17c 0 D17c 0 D17b 0 D18c 0 D18c 0 D18c 0 D18b Output Gain Control D17a 0 D19c 0 D19c 0 D19c 0 D19b All ch Output Mute D19a 0 D20c 0 D20c 0 D20c 0 D20b 0 D20a 1 D21 0 D21 0 D21 0 D21 0 D21 0 D22 1 D22 1 D22 0 D22 0 D22 0 D23 1 D23 0 D23 1 D23 0 D23 M61532FP Data Control Specification Initialize all data of the 5 formats when Digital Power supply (DVDD) turn on. M61532FP Setting Code (1) Input Selector Main Setting Sub ALL OFF IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 D0a D4a 0 0 0 0 0 0 0 0 1 1 D1a D5a 0 0 0 0 1 1 1 1 0 0 (2) Input ATT Setting 0dB -6dB -12dB -18dB D8a 0 0 1 1 D9a 0 1 0 1 (3) REC Output REC Output Setting OFF ON REC1 REC2 D10a D11a 0 0 1 1 D2a D6a 0 0 1 1 0 0 1 1 0 0 D3a D7a 0 1 0 1 0 1 0 1 0 1 (4) Multi Input Setting Multi In1 Multi In2 D12a 0 1 (5) Multi Input Mute (Except For FL/FR) Setting D13a Mute OFF 0 depend on (4) Multi Input Mute ON 1 (6) FL/FR VOL Input Setting Bypass Multi Input D14a 0 1 (7) Input Gain Control Setting 0dB +6dB +12dB +18dB D15a D16a 0 0 0 1 1 0 1 1 (8) Output Gain Control Setting 0dB +6dB +12dB +18dB D17a D18a 0 0 0 1 1 0 1 1 (9) All Ch Output Mute Setting Mute off Mute on D19a 0 1 It's initial setting when power is turned on. Rev.1.0, Sep.19.2003, page 8 of 14 M61532FP (9)6 channel Volume ATT - - - FLch FRch Cch SWch SLch SRch SBLch SBRch 0.0 dB 0.5 dB 1.0 dB 1.5 dB 2.0 dB 2.5 dB 3.0 dB 3.5 dB 4.0 dB 4.5 dB 5.0 dB 5.5 dB 6.0 dB • • 50.0 dB 50.5 dB 51.0 dB 51.5 dB 52.0 dB • • 95.0 dB 95.5 dB 96.0 dB 96.5 dB 97.0 dB 97.5 dB 98.0 dB 98.5 dB 99.0 dB ∞ dB D0b D8b D0c D8c D0d D8d D0e D8e 0 0 0 0 0 0 0 0 0 0 0 0 0 D1b D9b D1c D9c D1d D9d D1e D9e 0 0 0 0 0 0 0 0 0 0 0 0 0 D2b D10b D2c D10c D2d D10d D2e D10e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 D3b D11b D3c D11c D3d D11d D3e D11e 0 0 0 0 0 0 0 0 0 0 0 0 0 • • 0 0 0 0 0 • • 1 1 0 0 0 0 0 0 0 1 D4b D12b D4c D12c D4d D12d D4e D12e 0 0 0 0 0 0 0 0 1 1 1 1 1 D5b D13b D5c D13c D5d D13d D5e D13e 0 0 0 0 1 1 1 1 0 0 0 0 1 D6b D14b D6c D14c D6d D14d D6e D14e 0 0 1 1 0 0 1 1 0 0 1 1 0 D7b D15b D7c D15c D7d D15d D7e D15e 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 It's initial setting when power is turned on. Rev.1.0, Sep.19.2003, page 9 of 14 M61532FP Electrical Characteristics Unless otherwise noted, Ta=25°C,AVCC=7V,AVEE=-7V,DVDD=3.3V,f=1kHz, Volume=0dB, Input Selector=IN1,Input ATT=0dB,Input Gain Control=0dB,Output Gain Control=0dB, L/R Volume Input=Bypass,Multi Input Selector=Multi IN1 setting (1) Power supply characteristics Limits Parameter Symbol Test condition min typ max Unit Analog positive power circuit current AIcc With AVCC=7V and AVEE=-7V Pin22 pin current, when no signal is provided 50 70 mA Analog negative power Circuit current AIee -70 -50 mA Digital power circuit current Dldd With AVCC=7V and AVEE=-7V Pin24 pin current, when no signal is provided With DVDD=3.3V, Pin21 pin current, when no signal is provided 3 6 mA (2) Input/Output characteristics (OVER ALL) Limits Parameter Input resistance Symbol Rin Maximum output voltage VOM Pass gain Gv Distortion THD1 THD2 Channels balance CBAL Output noise voltage Vono (VOL =-∞dB) Vono (VOL=0dB) Vonodac (dac out) Rev.1.0, Sep.19.2003, page 10 of 14 Test Condition 65-80pin when each selector chooses a terminal concerned (1,2,51,5253,54,55,56) pin input, (47,46,29,28,41,40,35,34) pin output, THD=1%, RL=10kΩ Output Gain Control =+12dB setting (1,2,51,5253,54,55,56) pin input, (47,46,29,28,41,40,35,34) pin output, Vi=0.3Vrms,FLAT (1,2,51,5253,54,55,56) pin input, (47,46,29,28,41,40,35,34) pin output, BW:400Hz~30kHz f=1kHz , Vo=0.3Vrms , RL=10kΩ (1,2,51,5253,54,55,56) pin input, (47,46,29,28,41,40,35,34) pin output, BW:400Hz~30kHz f=1kHz , Vo=2Vrms , RL=10kΩ (1,2)pin input,(47,46)pin output, Vi=0.3Vrms , JIS-A JIS-A , (1,2,51,5253,54,55,56) pin: Output Gain Rg=0Ω, Control=0dB (47,46,29,28,41,40,35,34) pin Output Gain output, Control=+12dB Volume=-∞dB setting JIS-A , (1,2)pin : Output Gain Rg=0Ω, Control=0dB (47,46)pin output, Output Gain Volume=0dB setting Control=+12dB JIS-A , (1,2)pin:Rg=0Ω (5.4)pin output min 35 typ 47 max 65 Unit kΩ 3.6 4.2 Vrms -2.0 0 2.0 dB 0.00 5 0.05 % 0.03 0.1 % -0.5 0 0.5 dB 1.5 6 µVrms 9 20 µVrms 2.5 8 µVrms 12 25 µVrms 3 9 µVrms M61532FP Limits Parameter Symbol Test Condition min typ max Unit Input/Multi selector channel separation CS1 <Input selector> -90 -70 dB -90 -70 dB -90 -70 dB -90 -70 dB (47,46)pin output, Vo=1Vrms , Rg=0Ω, RL=10kΩ, JIS-A CS2 <Multi channel selector> (47,46,29,28,41,40,35,34) pin output, Vo=1Vrms , Rg=0Ω, RL=10kΩ, JIS-A, FL/FR VOL Input=Multi input Cross talk between channels CT1 (L/R) (1,2) pin input, (47,46) pin output, CT2 (Multi Input) (51,52,10,53,54,55,56,57,58) pin input, Vo=1Vrms , Rg=0Ω, RL=10kΩ, JIS-A (29,28,41,40,35,34,47,46) pin output, Vo=1Vrms , Rg=0Ω, RL=10kΩ, JIS-A, L/R VOL Input=Multi input (3) 8 channel Volume characteristics Limits Parameter Symbol Test condition min typ max Unit Maximum attenuation ATTmax (47,46,29,28,41,40,35,34) pin output, -100 -95 dB Volume gain Between channels Dvol -0.5 0 +0.5 dB Vi=2Vrms,JIS-A,VOL=-∞ Rev.1.0, Sep.19.2003, page 11 of 14 (47,46,29,28,41,40,35,34) pin output, Volume=0dB setting Rev.1.0, Sep.19.2003, page 12 of 14 77 75 73 71 69 67 65 47k 47k 47k 47k 47k 47k 47k 47k Input Selector (Main) 60 Input ATT 0/-6/-12/-18dB 7 Input ATT 0/-6/-12/-18dB 6 DVDD AVCC AVEE -7V DGND +5.0V +7V 34 30 36 64 62 5 47k 47k Input Selector (Main) Input Selector (Sub) 63 47k 79 47k 47k 47k 47k 47k 47k 47k 47k 4 47k 1 66 78 76 74 72 70 68 80 47k 61 47k INR1 INR2 INR3 INR4 INR5 INR6 INR7 INR8 INR9 INL1 INL2 INL3 INL4 INL5 INL6 INL7 INL8 INL9 2 Input Selector (Sub) SBRIN1 SBRIN2 SBLIN1 SBLIN2 56 SWIN1 SWIN2 16 51 15 52 11 55 12 14 53 13 54 9 58 10 57 CIN1 CIN2 SRIN1 SRIN2 SLIN1 SLIN2 RIN1 RIN2 LIN1 LIN2 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k Input Gain Control 0/+6/+12/+18dB Input Gain Control 0/+6/+12/+18dB Input Gain Control 0/+6/+12/+18dB Input Gain Control 0/+6/+12/+18dB Input Gain Control 0/+6/+12/+18dB Input Gain Control 0/+6/+12/+18dB Input Gain Control 0/+6/+12/+18dB Input Gain Control 0/+6/+12/+18dB 31 26 32 37 43 38 49 44 0~-99dB,mute SWch VOL 0~-99dB,mute 0~-99dB,mute Cch VOL 0~-99dB,mute SRch VOL SLch VOL 0~-99dB,mute 0~-99dB,mute Rch VOL 0~-99dB,mute Lch VOL 0~-99dB,mute SBRch VOL 30 SBLch VOL 27 33 36 42 39 48 45 46 LOUT ROUT SLOUT SROUT COUT SWOUT SBLOUT SBROUT Output Gain Control 29 Output Gain Control 28 Output Gain Control 34 Output Gain Control 35 Output Gain Control 41 Output Gain Control 40 Output Gain Control 47 Output Gain Control M61532FP Internal Block Diagram M61532FP 36 34 33 32 31 30 4.7u + 29 28 27 26 GND 4.7u + SBLSELOUT 4.7u SBLVIN + SWVIN 35 SBLOUT SBROUT 4.7u CVIN SLVIN 39 4.7u + 4.7u SBRVIN 37 + 4.7u SWSELOUT SBRSELOUT 38 4.7u 40 SLOUT COUT CSELOUT 4.7u SLSELOUT 4.7u SLOUT SLOUT SWOUT SLOUT Application Example 25 4.7u 100u 22 21 SL C SW SBR SBL 15 SR L 51 14 52 13 53 12 SBRIN1 R 50 GND 2.2u 16 49 RSELOUT DATA 17 + 4.7u RVIN 48 ROUT LATCH 47 4.7u 2.2u SBLIN1 2.2u SRIN1 2.2u 11 54 SLIN1 2.2u 10 55 CIN1 2.2u 9 56 SWIN1 GND AVCC 0.1u DVDD CLOCK 18 46 MCU I/F + 100u 19 LVIN 45 4.7u LOUT + 20 4.7u + AVEE 23 44 LSELOUT 43 SRSELOUT 42 +SRVIN 4.7u 0.1u 24 41 SROUT M C U 100u + DGND + + + + + + + + 2.2u SBRIN2 2.2u SBLIN2 2.2u SRIN2 2.2u SLIN2 2.2u CIN2 2.2u SWIN2 2.2u LIN2 2.2u RIN2 2.2u 57 8 58 7 LIN1 2.2u RIN1 GND 4.7u AROUT 4.7u 4.7u REC R2 5 60 4.7u 4 62 3 63 2 4.7u 61 SUBOUTL ALOUT 6 59 GND 4.7u SUBOUTR REC L2 4.7u REC R1 4.7u REC L1 GND 2.2u INL1 2.2u 1 64 Rev.1.0, Sep.19.2003, page 13 of 14 2.2u 79 80 2.2u 2.2u INL2 2.2u 78 INR2 2.2u 77 INL3 2.2u 76 INR3 2.2u 75 INL4 2.2u 74 INR4 2.2u 73 INL5 2.2u 72 INR5 2.2u 71 INL6 2.2u 70 INR6 2.2u 69 INL7 2.2u 68 INR7 67 INL8 2.2u INR9 2.2u 66 INR8 65 INL9 GND 0.1u INR1 y e b 40 x 41 24 65 64 25 HD D JEDEC Code — 1 80 EIAJ Package Code QFP80-P-1420-0.80 E M F Weight(g) 1.58 A Detail F Lead Material Alloy 42 L1 c L b2 I2 MD ME A A1 A2 b c D E e HD HE L L1 x y Dimension in Millimeters Min Nom Max — — 3.05 0.1 0.2 0 2.8 — — 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 — — 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 — — — — 0.2 0.1 — — 0˚ 10˚ — 0.5 — — 1.3 — — 14.6 — — — — 20.6 Recommended Mount Pad Symbol I2 MD Plastic 80pin 14✕20mm body QFP e b2 MMP A2 Rev.1.0, Sep.19.2003, page 14 of 14 A1 ME 80P6N-A M61532FP Package Dimensions HE Sales Strategic Planning Div. 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