SPLC501C - NewHaven Display

SPLC501C
132 x 65 Dot Matrix LCD Driver
MAR. 15, 2004
Version 1.8
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY
CO. is believed to be accurate and reliable.
However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order.
No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product
may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPLC501C
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 4
2. FEATURES.................................................................................................................................................................................................. 4
3. BLOCK DIAGRAM ...................................................................................................................................................................................... 5
4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 6
4.1.
POWER SUPPLY PINS ......................................................................................................................................................................... 6
4.2.
LCD POWER SUPPLY CIRCUIT TERMINALS ........................................................................................................................................... 6
4.3.
SYSTEM BUS CONNECTION TERMINALS................................................................................................................................................ 7
4.4.
LIQUID CRYSTAL DRIVE TERMINALS ...................................................................................................................................................... 9
4.5.
TEST TERMINALS ................................................................................................................................................................................ 9
5. FUNCTIONAL DESCRIPTIONS................................................................................................................................................................ 10
5.1.
THE MPU INTERFACE ........................................................................................................................................................................ 10
5.2.
THE CHIP SELECT ..............................................................................................................................................................................11
5.3.
ACCESSING THE DISPLAY DATA RAM AND THE INTERNAL REGISTERS ...................................................................................................11
5.4.
THE BUSY FLAG .................................................................................................................................................................................11
5.5.
DISPLAY DATA RAM .......................................................................................................................................................................... 12
5.6.
THE DISPLAY DATA LATCH CIRCUIT .................................................................................................................................................... 13
5.7.
THE OSCILLATOR CIRCUIT ................................................................................................................................................................. 13
5.8.
THE COMMON OUTPUT STATUS SELECT............................................................................................................................................. 13
5.9.
DISPLAY TIMING GENERATOR CIRCUIT ............................................................................................................................................... 13
5.10. THE LIQUID CRYSTAL DRIVER CIRCUITS .............................................................................................................................................
14
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5.11. THE POWER SUPPLY CIRCUITS ..........................................................................................................................................................
15
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5.12. HIGH POWER MODE ..........................................................................................................................................................................
19
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5.13. THE INTERNAL POWER SsUPPLY SHUTDOWN COMMAND SEQUENCE ..................................................................................................... 19
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5.14. REFERENCE CIRCUIT
npEXAMPLES ....................................................................................................................................................... 20
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5.15. THE RESET CIRCUIT
6. COMMANDS ............................................................................................................................................................................................. 23
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6.1.
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DISPLAY ON/OFF .............................................................................................................................................................................
24
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6.2.
s .................................................................................................................................................................. 24
DISPLAY START LINE SU
ET
6.3.
PAGE ADDRESS SR
ET .......................................................................................................................................................................... 24
6.8.
ADC SELECT (SEGMENT DRIVER DIRECTION SELECT) ....................................................................................................................... 26
6.9.
DISPLAY NORMAL/REVERSE .............................................................................................................................................................. 26
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A
-G SET ..................................................................................................................................................................... 25
6.4. COLUMN ADDRESS
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6.5. STATUSVREAD ................................................................................................................................................................................... 25
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6.6. DW
ISPLAY DATA WRITE ........................................................................................................................................................................ 26
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6.7.
r N DISPLAY DATA READ .......................................................................................................................................................................... 26
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6.10. DISPLAY ALL POINTS ON/OFF........................................................................................................................................................... 27
6.11. LCD BIAS SET .................................................................................................................................................................................. 27
6.12. READ/MODIFY/WRITE........................................................................................................................................................................ 27
6.13. END................................................................................................................................................................................................. 28
6.14. RESET ............................................................................................................................................................................................ 29
6.15. COMMON OUTPUT MODE SELECT ...................................................................................................................................................... 29
6.16. POWER CONTROLLER SET ................................................................................................................................................................ 29
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Version: 1.8
SPLC501C
6.17. V5 VOLTAGE REGULATOR INTERNAL RESISTOR RATIO SET .................................................................................................................. 30
6.18. THE ELECTRONIC VOLUME (DOUBLE BYTE COMMAND)....................................................................................................................... 30
6.19. STATIC INDICATOR (DOUBLE BYTE COMMAND).................................................................................................................................... 31
6.20. PAGE BLINKING (DOUBLE BYTE COMMAND)........................................................................................................................................ 31
6.21. SET DRIVING MODE (DOUBLE BYTE COMMAND) ................................................................................................................................. 32
6.22. POWER SAVE (COMPOUND COMMAND) .............................................................................................................................................. 33
6.23. NOP ................................................................................................................................................................................................ 34
6.24. TEST ............................................................................................................................................................................................... 34
6.25. TABLE 13 TABLE OF SPLC501C COMMANDS ..................................................................................................................................... 35
7. COMMAND DESCRIPTION ...................................................................................................................................................................... 37
7.1.
INSTRUCTION SETUP: REFERENCE (REFERENCE) ............................................................................................................................... 37
7.2.
PRECAUTIONS ON TURNING OFF THE POWER .................................................................................................................................. 38
8. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 40
8.1.
ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................................... 40
8.2.
DC CHARACTERISTICS ...................................................................................................................................................................... 41
8.3.
DISPLAY PATTERN OFF ..................................................................................................................................................................... 42
8.4.
DISPLAY PATTERN CHECKER.............................................................................................................................................................. 42
8.5.
DISPLAY PATTERN CHECKER.............................................................................................................................................................. 42
8.6.
TIMING CHARACTERISTICS................................................................................................................................................................. 43
8.7.
THE MPU INTERFACE (REFERENCE EXAMPLES) ................................................................................................................................. 50
8.8.
CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) ....................................................................................................... 51
8.9.
CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) ..................................................................................................... 52
8.10. VLCD VOLTAGE (VOLTAGE BETWEEN VDD TO V5) RELATIONSHIP OF V5 VOLTAGE REGULATOR INTERNAL RESISTOR RATIO REGISTER AND
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ELECTRONIC VOLUME CONTROL REGISTER
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9. PACKAGE/PAD LOCATIONS ...................................................................................................................................................................
53
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9.1.
PAD ASSIGNMENT AND LOCATIONS
.................................................................................................................................................... 53
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9.2.
ORDERING INFORMATION
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10. DISCLAIMER.............................................................................................................................................................................................
54
11. REVISION HISTORY ................................................................................................................................................................................. 55
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© Sunplus Technology Co., Ltd.
Proprietary & Confidential
3
MAR. 15, 2004
Version: 1.8
SPLC501C
132 x 65 DOT MATRIX LCD DRIVER
1. GENERAL DESCRIPTION
The SPLC501C, a single-chip dot matrix liquid crystal display
These chips not designed for resistance to light or Resistance
drivers, is specially designed to connect directly with a
microprocessor bus.
to radiation.
The 8-bit parallel or serial display data sent
High-speed 8-bit MPU interface (capability to be connected
from the microprocessor is stored in the internal display data RAM.
directly to the both the 80 X 86 series MPUs and the 68000
It generates a liquid crystal drive signal independent of the
series MPUs)/Serial interface are supported.
microprocessor.
Since the SPLC501C contains a 65 X 132 bits
Wide range of operating temperatures.
of display data RAM, a 1-to-1 correspondence between the liquid
CMOS process
crystal panel pixels and the internal RAM bits, it is able to enable
CR oscillator circuit equipped internally
displays with a high degree of flexibility.
The SPLC501C contains
(External clock can also be input).
65 common output circuits, 132 segment output circuits and
Abundant command functions
therefore, a single chip can drive a 65 X 132 dot display (capable
Display data Read/Write, display ON/OFF, Normal/Reverse
of displaying 8 columns X 4 rows of a 16 X 16 dot kanji font). In
display mode, page address set, display start line set, column
addition, the capacity of the display can also be extended through
address set, status read, display all points ON/OFF, LCD bias
the use of master/slave structures between chips.
set, electronic volume, read/modify/write, segment driver
The chips can
save a great amount of power because no external operating
direction select, power saver, static indicator, common output
status select, V5 voltage regulation internal resistor ratio set.
clock is required for the display data RAM to read and write
operations.
Low-power liquid crystal display power supply circuit equipped
Since each chip is equipped internally with a
low-power liquid crystal driver power supply, resistors for liquid
internally.
crystal driver power voltage adjustment and a display clock CR
Booster circuit (with Boost ratios of Double/Triple/Quad, where
oscillator circuit, the SPLC501C can be used for creating the
the step-up voltage reference power supply can be input
lowest power display system with the fewest components for high
externally).
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performance portable devices.
2. FEATURES
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High-accuracy voltage adjustment circuit
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(Thermal gradient -0.05%/℃ or external input).
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V5 voltage regulator resistors equipped internally,
V4 - 1 voltage divider resistors equipped internally, electronic
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Direct display of RAM data
Su through the display data RAM.
volume function equipped internally, voltage follower.
Driving Mode register provided for different size panel loading.
‘1’: Non-illuminated.
RAM capacity.
65 X 132 = 8580 bits.
Extremely low power consumption.
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‘0’: Illuminated.
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Low operating power when the built-in power supply is used
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Display driver circuits. AR
-G outputs and 132 segment outputs.
SPLC501C: 65 common
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Static drive circuit
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(1 system,
W with variable flashing speed.)
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Duty
Bias
SEG Dr
SPLC501C
1/65
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
1/9, 1/7
132
Power supply
Operable on the low 2.4 voltage
Logic power supply VDD - VSS = 2.4V to 5.5V
Boost reference voltage: VDD - VSS2 = 2.4V to 6.0V
Liquid crystal drive power supply: VDD - V5 = 4.5V to 12V
COM Dr
VREG Temperature Gradient
Shipping Forms
65
-0.05%/℃
Bare Chip with Gold Bump
4
MAR. 15, 2004
Version: 1.8
SPLC501C
COMS
COM63
COM0
SEG0
SEG131
3. BLOCK DIAGRAM
VDD
V1
V2
V3
V4
V5
COMS
VSS
COM
Drivers
SEG Drivers
COM output
status select
circuit
Display timing generation
circuit
Display data RAM
132 X 65
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Bus holder
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Command
decoder
Proprietary & Confidential
Status
5
D2
D3
D4
D5
D6(SCL)
D7(SI)
RESET
PS
WR (RWP)
A0P
CS2
CS1
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RD (EP)
HA
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CLS
MPU interface
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DOF
MS
Column address circuit
Oscillator
circuit
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FRS
FR
CL
D0
HPM
REF
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D1
VSS2
VR
VRS
IRS
Line address circuit
Power
supply
circuit
I/O buffer
Page address circuit
Display data
latch circuit
CAP1P
CAP1N
CAP2P
CAP2N
CAP3N
VOUT
MAR. 15, 2004
Version: 1.8
SPLC501C
4. SIGNAL DESCRIPTIONS
4.1. Power Supply PINs
Mnemonic
PIN No.
Type
Description
VDD
12
P
VDD Shared with MPU power supply terminal VCC
VSS
11
P
0V terminal connected to the system GND.
VSS2
4
P
A reference power supply for the step-up voltage circuit for the liquid crystal drive
VRS
1
P
The external-input VREG power supply for the LCD power supply voltage regulator.
These can
only be enabled for the models with the VREG external input option.
10
V1, V2,
P
A multi-level power supply for the liquid crystal drive.
The voltage applied is determined by the
V3, V4,
liquid crystal cell, and is changed through the use of a resistive voltage divided or through
V5
changing the impedance using an op. amp.
Voltage levels are determined based on VDD, and
must maintain the relative magnitudes shown below.
VDD (= V0) ≧V1≧V2≧V3≧V4≧V5
Master operation: When the power supply turns ON, the internal power supply circuits generate
the V1 to V4 voltages shown below. The voltage settings are selected by the LCD bias command.
SPLC501C
V1
1/9．V5 1/7．V5
V2
2/9．V5 2/7．V5
V3
7/9．V5 5/7．V5
V4
8/9．V5 6/7．V5
P: Power Supply
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4.2. LCD Power Supply Circuit Terminals
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Mnemonic
CAP1P
CAP1N
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PIN No.
Type
2
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2
Description
DC/DC voltage converter. A capacitor is connected between this terminal and the CAP1N
terminal.
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DC/DC voltage converter. A capacitor is connected between this terminal and the CAP1P
yterminal.
CAP2P
2
CAP2N
2
CAP3N
N
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OUT
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FVoR
HA
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nl DC/DC
voltage converter. A capacitor is connected between this terminal and the CAP2N
terminal.
DC/DC voltage converter. A capacitor is connected between this terminal and the CAP2P
terminal.
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DC/DC voltage converter. A capacitor is connected between this terminal and the CAP1P
terminal.
3
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DC/DC voltage converter. A capacitor is connected between this terminal and VSS.
2
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Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive
voltage divider.
used (IRS = ‘L’).
These are only enabled when the V5 voltage regulator internal resistors are not
These cannot be used when the V5 voltage regulator internal resistors are
used (IRS = ‘H’).
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MAR. 15, 2004
Version: 1.8
SPLC501C
4.3. System Bus Connection Terminals
Mnemonic
DB7 - 0
PIN No.
Type
Description
8
I/O
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus.
(SI) (SCL)
When the serial interface is selected (PS = ‘L’), DB7 serves as the serial data input terminal (SI)
and DB6 serves as the serial clock input terminal (SCL).
high impedance.
A0P
1
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At the same time, DB5 - 0 are set to
When the chip select is inactive, DB0 to DB7 are set to high impedance.
This is connected to the least significant bit of the normal MPU address bus, and it determines
whether the data bits are data or a command.
A0P = ‘H’: Indicates DB7 - 0 is display data.
A0P = ‘L’: Indicates DB7 - 0 is control data.
RESET
1
I
When RESET is set to ‘L’, the settings are initialized.
The RESET signal level performs the reset operation.
CS1
2
I
1
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This is the chip select signal.
CS2
When CS1 = ‘L’ and CS2 = ‘H’, the chip select becomes active,
and data/command I/O is enabled.
RD (EP)
When connected to an 8080 MPU, this is LOW active.
This pin is connected to the RD signal of
the 8080 MPU, and the SPLC501C data bus is in an output status when this signal is ‘L’.
When connected to a 6800 Series MPU, this is HIGH active.
This is the 68000 Series MPU
enable clock input terminal.
1
WR (RWP)
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When connected to an 8080 MPU, this is LOW active.
This terminal connects to the 8080 MPU
WR signal. The signals on the data bus are latched at the rising edge of the WR signal.
When connected to a 6800 Series MPU:
This is the read/write control signal input terminal.
When RWP = ‘H’: Read.
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When
tiaRWP = ‘L’: Write.
C86
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d is the MPU interface switch terminal.
iThis
nf C86 = ‘H’: 6800 Series MPU interface.
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C86 = ‘L’: 8080 MPU interface.
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This is the parallel data input/serial data input switch terminal.
PS = ‘H’: Parallel data input.
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PS
Data/Command
Data
Read/Write
Serial Clock
'H'
A0P
DB0 to DB7
RD , WR
Write only
SCL (DB6)
'L'
A0P
SI(DB7)
When PS = ‘L’, DB0 to DB5 are high impedance.
(EP) and WR (RWP) are fixed to either ‘H’ or ‘L’.
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CLS
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DB0 to DB5 may be ‘H’, ‘L’ or Open.
RD
With serial data input, RAM display data
reading is not supported.
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Terminal to select whether to enable or disable the display clock internal oscillator circuit.
CLS = ‘H’: Internal oscillator circuit is enabled.
CLS = ‘L’: Internal oscillator circuit is disabled (requires external input).
When CLS = ‘L’, input the display clock through the CL terminal.
FR
1
I/O
This is the liquid crystal alternating current signal I/O terminal.
MS = ‘H’: Output
MS = ‘L’: Input
When the SPLC501C chip is used in master/slave mode, the various FR terminals must be
connected.
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Version: 1.8
SPLC501C
Mnemonic
PIN No.
Type
1
I
MS
Description
This terminal selects the master/slave operation for the SPLC501C chips. Master operation
outputs the timing signals that are required for the LCD display, while slave operation inputs the
timing signals required for the liquid crystal display, synchronizing the liquid crystal display
system.
MS = ‘H’: Master operation
MS = ‘L’: Slave operation
The following is true depending on the MS and CLS status:
Supply Circuit
'H'
Enabled
'L'
Disabled
'H'
'L'
CLS
'H'
'L'
CL
1
I/O
Power
Oscillator
Circuit
MS
CL
FR
FRS
DOF
Enabled
Output
Output
Output
Output
Enabled
Input
Output
Output
Output
Disabled
Disabled
Input
Input
Output
Input
Disabled
Disabled
Input
Input
Output
Input
This is the display clock input terminal
The following is true depending on the MS and CLS status.
MS
CLS
CL
'H'
'H'
Output
'L'
Input
'H'
Input
'L'
Input
'L'
When the SPLC501C chips are used in master/slave mode, the various CL terminals must be
connected.
1
DOF
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iathe liquid crystal display blanking control terminal.
This tis
I/O
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d = ‘H’: Output
iMS
nf MS = ‘L’: Input
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C
When the SPLC501C chip is used in master/slave mode, the various DOF terminals must be
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FRS
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1
IRS
1
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connected.
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yindicator display is ON when in master operation mode, and is used in conjunction with the FR
nl terminal.
This terminal selects the resistors for the V5 voltage level adjustment.
IRS = ‘L’: Do not use the internal resistors.
The V5 voltage level is regulated by an external resistive voltage divider attached to the VR
V
HA
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IRS = ‘H’: Use the internal resistors.
EN
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HPM
This is the output terminal for the static drive. This terminal is only enabled when the static
terminal. This pin is enabled only when the master operation mode is selected. It is fixed to either
‘H’ or ‘L’ when the slave operation mode is selected.
1
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This is the power control terminal for the power supply circuit for liquid crystal drive.
HPM = ‘H’: Normal mode.
HPM = ‘L’: High power mode.
This pin is enabled only when the master operation mode is selected.
It is fixed to either ‘H’ or
‘L’ when the slave operation mode is selected.
REF
1
I
This is the reference source select terminal for the power supply circuit for liquid crystal drive.
REF = “H”; external reference source from VRS terminal.
REF = “L”; internal reference source from SPLC501C terminal.
This pin is enable only when the master operation mode is selected.
It is fixed to either “H” or
“L” when the slave operation mode is selected.
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MAR. 15, 2004
Version: 1.8
SPLC501C
4.4. Liquid Crystal Drive terminals
Mnemonic
PIN No.
Type
Description
SEG131 - 0
132
O
These are the liquid crystal segment drive outputs. Through a combination of the contents of the
display RAM and with the FR signal, a single level is selected from VDD, V2, V3, and V5.
COM63 - 0
64
O
RAM DATA
FR
H
H
Output Voltage
Normal Display
Reverse Display
H
VDD
V2
L
V5
V3
L
H
V2
VDD
L
L
V3
V5
Power save
-
VDD
These are the liquid crystal common drive outputs.
Part No.
COM
SPLC501C
COM63 - 0
Through a combination of the contents of the scan data and with the FR signal, a single level is
selected from VDD, V1, V4, and V5.
Scan Data
FR
Output Voltage
H
H
V5
H
L
VDD
L
H
V1
L
L
V4
Power Save
-
VDD
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COMS
2
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A1R
-G 2
EN
V
TEST5, TEST6
HA
W
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Both terminals output the same signal.
When in master/slave mode, the same signal is
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TEST3, TEST4
These are the COM output terminals for the indicator.
output by both master and slave.
PIN No.Us
TEST
e
Leave these pins open if they are not used.
4.5. Test Terminals
Mnemonic
ia
nt
2
O
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Type
Description
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This is terminal for IC chip testing only.
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These are terminals for IC chip testing only.
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These are terminals for IC chip testing only.
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Proprietary & Confidential
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MAR. 15, 2004
Version: 1.8
SPLC501C
5. FUNCTIONAL DESCRIPTIONS
5.1. The MPU Interface
5.1.1. Selecting the interface type
For SPLC501C, data transfers are accomplished through an 8-bit
to select either parallel data input or serial data input as shown in
bi-directional data bus (DB7 - 0) or through a serial data input (SI).
Table 1.
By selecting the PS terminal polarity to the ‘H’ or ‘L’, it is possible
Table 1
PS
CS1
CS2
A0P
RD
WR
C86
DB7
DB6
DB5 - 0
H: Parallel Input
CS1
CS2
A0P
RD
WR
C86
DB7
DB6
DB5 - 0
L: Serial Input
CS1
CS2
A0P
-
-
-
SI
SCL
(HiZ)
‘-‘ indicates fixed to either ‘H’ or to ‘L’
5.1.2. The parallel interface
When the parallel interface is selected (PS = ‘H’), it is possible to
MPU (as shown in Table 2) by selecting the C86 terminal to either
connect directly to either an 8080-system MPU or a 6800 Series
‘H’ or ‘L’.
Table 2
C86
CS1
CS2
A0P
RD
WR
DB7 - 0
H: 6800 Series MPU Bus
CS1
CS2
A0P
EP
RWP
DB7 - 0
L: 8080 MPU Bus
CS1
CS2
A0P
RD
WR
DB7 - 0
Data bus signals are recognized by a combination
al of A0P, RD (EP), WR (RWP) signals, shown in Table 3.
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Table 3
6800
s Series
Shared
A0P
1
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WRP
RD
WR
1
0
1
1
0
0
1O
0
8080 Series
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Function
Read the display data
1
0
Write the display data
0
1
Read Status
1
0
Write control data (command)
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5.1.3. The serial interface
N
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When the serialAinterface
is selected (PS = ‘L’) and when the chip
H
is in active W
state ( CS1= ‘L’ and CS2 = ‘H’), the serial data input (SI)
E
and the
r Nserial clock input (SCL) can be received. The serial data
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F
is read from the serial data input pin at the rising edge of the serial
The A0P input determines whether the serial data input is display
clocks DB7, DB6 through DB0 in order.
clock after the chip is active.
data or command data; when A0P = ‘H’, the data is display data,
and when A0P = ‘L’, the data is command data.
The A0P input is
read and used for detecting every 8th rising edge of the serial
The data is converted to
8-bit parallel data at the rising edge of the eighth serial clock.
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MAR. 15, 2004
Version: 1.8
SPLC501C
CS1
CS2
SI
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
8
9
10
11
12
13
14
SCL
1
2
3
4
5
6
7
A0P
Figure 1: serial interface signal chart.
Note1: When the chip is not active, the shift registers and counter are reset to their initial states.
Note2: Reading is not acceptable in serial interface mode.
Note3: Caution is required on the SCL signal when it comes to line-end reflections and external noise. SUNPLUS recommends that operation should be
rechecked on the actual equipment.
5.2. The Chip Select
Writing
The SPLC501C have two chip-select-terminals: CS1 and CS2.
MPU
WR
The MPU interface or the serial interface is enabled only when
Internal Timing
DATA
CS1 = ‘L’ and CS2 = ‘H’.
N
N+1
N
N+1
MPU
t
en
RD
DATA
C
5.3. Accessing the Display Data
s RAM and the Internal
INternal Timing
lu
S speed is ensured since the MPU is
Data transferring at a high
N
n
n+1
Read Signal
Column Address
Preset N
Bus Holder
N
required to satisfy the cycle time (tCYC) requirement alone in
accessing the SPLC501C.
N
Address Preset
p
un
Registers
N+3
WR
l
When the serial interface is selected, the shift
ia register and the
id
N+2
Reading
impedance state, and the A0P, RD , and WR inputs are inactive.
f
on
N+3
Write Signal
When the chip select is inactive, DB7 - 0 enter into a high
counter are reset.
N+2
Latch
BUS Holder
Address Set
#n
ly
Increment N+1
n
Dummy
Read
N+2
n+1
Data Read
#n
n+2
Data Read
#n+1
n may not be considered.
Wait time
O
e data is sent from MPU.
Also, in SPLC501C chips, each stime
U
Figure2
A
type of pipeline process between
Y LSIs is performed through the
R
A internal data bus.
bus holder attached to the
G
N-
5.4. The Busy Flag
For example, when
When the busy flag is ‘1’, it indicates that the SPLC501C is
the MPU writes data
E to the display data RAM, once the data is
V
stored in the bus
HA holder, it is written to the display data RAM
before the W
next data write cycle. Moreover, when the MPU reads
NE data RAM, the first data read cycle (dummy) stores the
the display
r
Fo
read data in the bus holder, and then the data is read from the bus
holder to the system bus at the next data read cycle.
running internal processes.
At this moment, no command aside
from a status read will be received.
The busy flag is outputted to
DB7 pin with the read instruction.
If the cycle time (tCYC) is
remained, it is not necessary to check for this flag before each
command.
There is a
This makes vast improvements in MPU processing
capabilities possible.
certain restriction in the read sequence of the display data RAM.
Note that data of the specified address is not generated by the
read instruction issued immediately after the address setup. This
data is generated in data read of the second time.
Thus, a
dummy read is required whenever the addresses setup or write
cycle operation is conducted.
This relationship is shown in
Figure 2.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
11
MAR. 15, 2004
Version: 1.8
SPLC501C
5.5. Display Data RAM
5.5.1. Display data RAM
relationship between the display data RAM column address and
The display data RAM is a RAM that stores the dot data for the
display.
It has a 65 (8 page x 8 bit +1) x 132-bit structure.
the segment output.
It is
possible to access the desired bit by specifying the page address
and the column address.
Because of this, the constraints on the IC
layout when the LCD module is assembled can be minimized.
Because, as is shown in Figure 3, the
Table 4
DB7 - 0 display data from the MPU corresponds to the liquid
SEG Output
crystal display common direction, there are few constraints at the
SEG0
SEG131
time of display data transfer when multiple SPLC501C chips are
ADC ‘0’
0 (H) Æ
Column Address Æ83(H)
used.
(DB0) ‘1’
83(H) Å
Column Address Å 0(H)
Therefore, display structures can be created easily and
with a high degree of freedom.
5.5.4.
The line address circuit, as shown in Figure 4, specifies the line
COM0
COM1
COM2
COM3
address relating to the COM output when the contents of the
display data RAM are displayed.
COM4
can be specified.
when the common output mode is reversed.
Figure 3
address.
If the line addresses are changed dynamically using
the display start line address set command, screen scrolling, page
side is performed through the I/O buffer, which is an independent
swapping, …etc. can be performed.
ti
asynchronously during liquid crystal display,
en it will not cause
D3
Page Address
D2
D1
D0
fid
adverse effects on the display (such as
onflickering).
C
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
l
p
5.5.2. The page addressncircuit
Su
As shown in Figure 4, page address of the display data RAM is
specified through the Page Address Set Command.
The page
ly
n
address must be specified again when
O changing pages to perform
e
access. Page address 8 (DB3,sDB2, DB1, DB0 = 1, 0, 0, 0) is
U
Y
the page for the RAM region
used
only by the indicators, and only
AR
display data DB0 is used.
G
NE
V
5.5.3. The column
addresses
HA
W
E in Figure 4, the display data RAM column address is
As is shown
rN
o
specified
by the Column Address Set command. The specified
F
column address is incremented (+1) with each display data
This allows the MPU display data to be
accessed continuously.
Moreover, the increment of column
addresses stops with 83H.
depends
on
Because the column address
the page address, it is necessary to re-specify both
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
83
82
81
80
7F
7E
7D
7C
Furthermore, as is shown in Table 4, the ADC command (segment
driver direction select command) can be used to reverse the
When the
common output
mode is normal
COM
Output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
CMOS
Page 8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
example, from page 0 column 83H to page 1 column 00H.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
00
01
02
03
04
05
06
07
the page address and the column address when moving, for
Data
0
Consequently, even if the display data RAM
al is accessed
Column
Address
operation from signal reading for the liquid crystal driver.
read/write command.
The display area is
a 65-line area for the SPLC501C from the display start line
Moreover, reading from and writing to the display RAM in the MPU
us
This is the COM0 output when the common
output mode is normal and the COM63 output for SPLC501C
Liquid crystal display
1
Display data RAM
Using the display start line
address set command, which is normally the top line of the display
D0
D0
ADC
0
0
0
0
0
Regardless of the display
start line address, the
SPLC501A access 65th line
LCD
Out
1
0
0
0
1
7C
7D
7E
7F
80
81
82
83
1
0
0
1
0
07
06
05
04
03
02
01
00
1
0
1
0
0
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
0
1
0
0
0
D0
D1
D2
D3
D4
The line address circuit
Figure 4
12
MAR. 15, 2004
Version: 1.8
SPLC501C
5.6. The Display Data Latch Circuit
The display data latch circuit temporarily stores the display data
Table 5
that is output to the liquid crystal driver circuit from the display
data RAM.
COM Scan Direction
Status
Because the display normal/reverse status, display
SPLC501C
ON/OFF status, and display all points ON/OFF commands control
Normal
COM0ÆCOM63
only the data within the latch, they do not change the data within
Reverse
COM63ÆCOM0
the display data RAM itself.
5.9. Display Timing Generator Circuit
5.7. The Oscillator Circuit
This is a CR-type oscillator that produces the display clock.
The display timing generator circuit generates the timing signal to
The
the line address circuit and the display data latch circuit using the
oscillator circuit is only enabled when MS = ‘H’ and CLS = ‘H’.
display clock. The display data is latched into the display data
When CLS = ‘L’, the oscillation stops, and the display clock is
latch circuit synchronized with the display clock, and is output to
input through the CL terminal.
the data driver output terminal.
Reading to the display data liquid
crystal driver circuits is completely independent of accesses to the
5.8. The Common Output Status Select
display data RAM by the MPU.
Consequently, even if the display
In the SPLC501C chips, the COM output scan direction can be
data RAM is accessed asynchronously during liquid crystal display,
selected by the common output status select command (See Table
there is absolutely no adverse effect (such as flickering) on the
5.).
Consequently, the constraints in IC layout at the time of LCD
display.
module assembly can be minimized.
Moreover, the display timing generator circuit generates
the common timing and the liquid crystal alternating current signal
(FR) from the display clock. It generates a drive-wave form using
a 2-frame alternating current drive method, as is shown in Figure 5,
for the liquid crystal drive circuit.
Two-frame alternating current drive-wave form
l (SPLC501C)
tia
64
65
1
2
3
CL
us
4
n
de
fi
n
Co
5
6
60
61
62
63
64
65
1
2
3
4
5
6
l
np
FR
Su
VDD
COM0
V1
y
Y
AR
-G
e
Us
O
nl
V4
V5
VDD
EN
V1
V
HA
EW
COM1
V4
N
r RAM
Fo
V5
DATA
VDD
V2
SEGn
V3
V5
Figure 5
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Proprietary & Confidential
13
MAR. 15, 2004
Version: 1.8
SPLC501C
When multiple SPLC501C chips are used, the slave chips must be
Operating Mode
supplied the display timing signals (FR, CL, DOF ) from the
Slave (MS = ‘L’):
master chip(s).
The internal oscillator circuit is
Table 6 shows the status of the FR, CL, and
DOF signals.
FR
CL
DOF
Input
Input
Input
Input
Input
Input
enabled (CLS = ‘H’)
The internal oscillator circuit is
disabled (CLS = ‘L’)
Table 6
Operating Mode
FR
CL
DOF
5.10. The Liquid Crystal Driver Circuits
Master (MS = ‘H’):
The internal oscillator circuit is
Output
Output
Output
Output
Input
Output
These are a 197-channel (SPLC501C) that generates four voltage
levels for driving the liquid crystal. The combination of the display
enabled (CLS = ‘H’)
The internal oscillator circuit is
data, the COM scan signals, and the FR signal produces the liquid
disabled (CLS = ‘L’)
crystal drive voltage output.
Figure 6 shows examples of the
SEG and COM output waveform.
VDD
VSS
FR
COM0
COM1
VDD
V1
V2
COM2
COM0
COM3
V3
V4
V5
COM4
VDD
V1
V2
COM5
COM6
COM1
V3
V4
V5
COM7
VDD
V1
V2
COM8
COM9
fid
COM11
COM12
s
COM13
COM14
n
Su
COM15
l
ia
COM10
u
pl
n
Co
t
en
COM2
V3
V4
V5
VDD
V1
V2
SEG0
V3
V4
V5
VDD
V1
V2
SEG1
Y
AR
-G
e
Us
n
VDD
V1
V2
SEG2
V3
V4
V5
V5
V4
V3
EN
V
HA
W
E
O
V3
V4
V5
ly
V2
V1
V∞
-V1
-V2
COM0-SEG0
rN
-V3
-V4
-V5
Fo
V5
V4
V3
V2
V1
V∞
-V1
-V2
COM0-SEG1
-V3
-V4
-V5
Figure 6
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
14
MAR. 15, 2004
Version: 1.8
SPLC501C
5.11. The Power Supply Circuits
The power supply circuits are low-power consumption power
Table 7 The Control Details of Each Bit of the Power Control
supply circuits that generate the voltage levels for the liquid crystal
drivers.
Set Command
They comprise Booster circuits, voltage regulator circuits,
and voltage follower circuits.
operation.
The power supply circuits can turn the Booster circuits,
DB2 Booster circuit control bit
the voltage regulator circuits, and the voltage follower circuits ON
DB1 Voltage regulator circuit
or OFF independently through the use of the Power Control Set
command.
Status
Item
They are only enabled in master
(V regulator circuit) control bit
Consequently, it is possible to make an external
DB0 Voltage follower circuit
power supply and the internal power supply function in parallel.
(V/F circuit) control bit
Table 7 shows the Power Control Set Command 3-bit data control
'1'
'0'
ON
OFF
ON
OFF
ON
OFF
functions, and Table 8 shows reference combinations.
Table 8 Reference Combinations
Use Settings
Step-up
V regulator
V/F
External
Step-up Voltage
circuit
circuit
circuit
voltage input
SystemTerminal
1
O
O
O
VSS2
Used
1
1
X
O
O
VOUT, VSS2
Open
0
0
1
X
X
O
V5, VSS2
Open
0
0
0
X
X
X
V1 to V5
Open
DB0
DB1
DB0
1
1
0
Only the V/F circuit is used
Only the external power supply is used
Only the internal power supply is used
Only the V regulator circuit and
the
V/F circuit are used
Note1: The ‘step-up system terminals’ refer CAP1P, CAP1N, CAP2P, CAP2N, and CAP3N.
Note2: While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use.
5.11.1. The step-up voltage circuits
l
ia
t
en
Using the step-up voltage circuits equipped
id within the SPLC501C
nf
Triple step-up: Connect capacitor C1 between CAP1P and CAP1N,
o step-up, a Triple step-up,
chips, it is possible to product a Quad
between CAP2P and CAP2N and between VSS2
C
and a Double step-up of the VDD
us- VSS2 voltage levels.
l
np
Su
and VOUT, and short between CAP3N and VOUT
to produce a voltage level in the negative direction
at the VOUT terminal that is 3 times the voltage
Quad step-up: Connect capacitor C1 between CAP1P and CAP1N,
difference between VDD and VSS2.
between CAP2P and CAP2N,
between CAP1P
y
nl VSS2 and VOUT, to
and CAP3N, and between
O
e
produce a voltage
Us level in the negative direction at
Y that is 4 times the voltage level
the VOUT terminal
AR
between
-GVDD and VSS2.
N
VE
A
H
EW
Double step-up: Connect capacitor C1 between CAP1P and
CAP1N, and between VSS2 and VOUT, leave
CAP2P open, and short between CAP2N,
CAP3N and VOUT to produce a voltage in the
negative direction at the VOUT terminal that is
twice the voltage between VDD and VSS2.
rN
Fo
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
15
MAR. 15, 2004
Version: 1.8
SPLC501C
The step-up voltage relationships are shown in Figure 7.
C1
VSS2
+
VOUT
C1
CAP2N
+
VOUT
C1
CAP2P
4 x step-up voltage circuit
CAP1P
+
CAP1N
+
VSS2
+
VOUT
CAP3N
C1
CAP1P
+
CAP1N
CAP2N
CAP2N
CAP2P
OPEN CAP2P
3 x step-up voltage circuit
SPLC501C
CAP1N
C1
SPLC501C
CAP1P
VSS2
+
CAP3N
SPLC501C
CAP3N
C1
+
C1
C1
C1
2 x step-up voltage circuit
VDD = 0V
VDD = 0V
VDD = 0V
VSS2 = -3V
VSS2 = -3V
VSS2 = -5V
VOUT = 3 x VSS2 = -9V
VOUT=2 x VSS2 = -10V
VOUT = 4 x VSS2 = -12V
4 x step-up voltage relationships
3 x step-up voltage relationships
2 x step-up voltage relationships
Figure 7
Note: The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rate.
l
ia
5.11.2. The voltage regulator circuitent
fid
The step-up voltage generated at VOUT
on outputs the liquid crystal
 Rb 
V5 = 1 +
 • VEN
 Ra 
C
driver voltage V5 through the voltage
us regulator circuit. Because
l
pinternal high-accuracy fixed voltage
the SPLC501C chips have an
un
S
power supply with a 64-level electronic volume function and
α 
 Rb  
= 1 +
 • VREG
 • 1 −
 Ra   162 
[Q V
EN
= (1 − α 162) • VREG]
Equation A-1
internal resistors for the V5 voltage regulator, systems can be
VDD
ly
n high-accuracy voltage
constructed without having to include
regulator circuit components.
O
VEN (constant voltage supply + electronic volume)
Moreover,
in the SPLC501C, two
se
U
Internal Ra
types of thermal gradients have
Y been prepared as VREG options: (1)
V5
R
approximately -0.05%/℃Aand (2) external input (supplied to the
VRS terminal).
H
-G
N
E
AV
Internal Rb
5.11.2.1.EWWhen the V5 voltage regulator internal
rN
Fo
resistors are used
Through the use of the V5 voltage regulator internal resistors and
Figure 8
the electronic volume function, the liquid crystal power supply
voltage, V5, can be controlled by commands alone (without adding
VREG is the IC-internal fixed voltage supply, and its voltage at TA =
any external resistors), making it possible to adjust the liquid
25℃ is as shown in Table 9.
crystal display brightness.
The V5 voltage can be calculated
using equation A-1 over the range where | V5 | < | VOUT |.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
16
MAR. 15, 2004
Version: 1.8
SPLC501C
5.11.2.2. When an external resistance is used
Table 9
Thermal
Equipment Type
Units
Gradient
(1) Internal Power Supply
VREG
-0.05
[%/℃]
-2.224
[V]
-
-
VRS
[V]
(2) External Input
(i.e., The V5 Voltage Regulator Internal
Units
Resistors are not used) (1)
The liquid crystal power supply voltage V5 can also be set without
using the V5 voltage regulator internal resistors (IRS terminal = ‘L’)
by adding resistors Ra’ and Rb’ between VDD and VR, and
between VR and V5, respectively.
α is set to 1 level of 64 possible levels by the electronic volume
function depending on the data set in the 6-bit electronic volume
register.
When this is done, the use of
the electronic volume function makes it possible to adjust the
brightness of the liquid crystal display by controlling the liquid
Table 10 shows the value for depending on the
crystal power supply voltage V5 through commands.
electronic volume register settings.
In the
range where | V5 | < | VOUT |, the V5 voltage can be calculated
using equation B-1 based on the external resistance, Ra’ and Rb’.
Table 10
DB5
DB4
DB3
DB2
DB1
DB0
α
0
0
0
0
0
0
63
0
0
0
0
0
1
62
0
0
0
0
1
0
61
:
:
:
:
:
:
:
1
1
1
1
0
1
2
1
1
1
1
1
0
1
1
1
1
1
1
1
0
 Rb' 
V5 = 1 +
 • VEN
 Ra' 
α 
 Rb'  
= 1 +
 • VREG
 • 1 −
 Ra'   162 
[Q V
EN
= (1 − α 162) • VREG]
Equation B-1
VDD
VEN (fixed voltage power supply + electronic volume)
External
resistor Ra'
V5
Rb/Ra is the V5 voltage regulator internal resistor ratio, and can be
set to 8 different levels through the V5 voltage regulator internal
resistor ratio set command.
External
resistor Rb'
The (1 + Rb/Ra) ratio
l assumes the
ia
values shown in Table 11 depending on thent3-bit data settings in
de
i register.
the V5 voltage regulator internal resistornfratio
us
Co
Figure 9
V5 voltage regulator internal resistance
ratio register value and (1
pl
Setup example: When selecting TA = 25℃ and V5 = -7.0V for an
+ Rb/Ra) ratio (ReferenceSvalue)
SPLC501C model where the temperature gradient = -0.05%/℃.
un
When the central value of the electron volume register is (DB5,
y
nl
Table 11
DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0), then α = 31 and
O
e SPLC501C
s
U Type by Thermal Gradient
Equipment
Y
AR
[Units: %/℃]
-G
Register
DB2 DB1 DB0EN
V
0
0 HA0
0
E0 W 1
N
0 or 1
0
F
(1) -0.05
(2) VREG External Input
3.16
1.5
3.70
2.0
4.24
2.5
VREG = -2.1V.
According to equation B-1:
 Rb' 
V5 = 1+
 • VEN
 Ra' 
α 
 Rb'  
− 7.0V = 1+
 • 1− 162  • ( −2.1)
Ra'


 
Equation B-2
0
1
1
4.78
3.0
1
0
0
5.32
3.5
Moreover, when the value of the current running through Ra’ and
1
0
1
5.86
4.0
Rb’ is set to 5µA,
1
1
0
6.40
4.5
1
1
1
6.80
5.0
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Proprietary & Confidential
Ra' + Rb' = 1.4MΩ
17
Equation B-3
MAR. 15, 2004
Version: 1.8
SPLC501C
5.11.2.3. When external resistors are used
Consequently, by equations B-2 and B-3,
(i.e.
Rb'
Ra'
The
V5
Voltage
Regulator
Internal
Resistors Are Not Used). (2)
= 3.12
When the external resistor described above are used, adding a
variable resistor makes it possible to perform fine adjustments on
Ra' = 340kΩ
Ra’ and Rb’, to set the liquid crystal drive voltage V5.
Rb' = 1060kΩ
In this case,
the use of the electronic volume function makes it possible to
At this time, the V5 voltage variable range and notch width, based
control the liquid crystal power supply voltage V5 by commands to
on the electron volume function, is as given in Table 12.
adjust the liquid crystal display brightness.
In the range where |
V5 | < | VOUT | the V5 voltage can be calculated by equation C-1
Table 12
below based on the R1 and R2 (variable resistor) and R3 settings,
V5
Variable
Range
Min.
Typ.
Max.
-8.6
-7.0
-5.3
(63 levels)
Notch width
[V]
(central value) (0 level)
-
52
where R2 can be subjected to fine adjustments (△R2).
Units
-
[mV]
 R3 + R2 - ∆R2 
V5 = 1 +
 • VEN
R1 + ∆R2 

α 
 R3 + R2 + ∆R2  
= 1 +
 • 1 − 162  • (VREG)
R1 + ∆R2  


[Q V
EN
= (1 − α 162) • VREG]
Equation C-1
l
VDD
ia
fid
t
en
VEN (fixed voltage power supply + electronic volume)
n
External
Co R1
resistor
us
Ra'
l
np
Su
V5
External
y
resistor
nl R2
Y
AR
-G
e
Us
O
∆ R2
VR
Rb'
N
VE
HA
W
E
rN
Fo
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
External
resistor R3
Figure 10
18
MAR. 15, 2004
Version: 1.8
SPLC501C
Setup example: When selecting TA = 25℃ and V5 = -5.0V to -9.0V
5.11.3. The liquid crystal voltage generator circuit
(using R2) for an SPLC501C model where the temperature
The V5 voltage is produced by a resistive voltage divider within the
gradient = -0.05%/℃.
IC, and can be produced at the V1, V2, V3, and V4 voltage levels
required for liquid crystal driving.
Moreover, when the voltage
When the central value for the electronic volume register is set at
follower changes the impedance, it provides V1, V2, V3 and V4 to
(DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0),
the liquid crystal drive circuit. 1/9 bias or 1/7 bias for SPLC501C
can be selected.
α = 31
V REG = -2.1V
5.12. High Power Mode
so, according to equation C-1, when △R2 = 0Ω , in order to make
The power supply circuit equipped in the SPLC501C chips has
V5 = -9.0V,
very low power consumption (normal mode: HPM = ‘H’). However,
for LCDs or panels with large loads, this low-power power supply
may cause display quality to degrade. When this occurs, setting
 R3 + R2   31 
− 9.0V = 1+
 • 1−  • (-2.1)
R1   162 

Equation C-2
the HPM terminal to ‘L’ (high power mode) can improve the
quality of the display. We recommend that the display be checked
When △R2 = R2, in order to make V = -5.0V,
on actual equipment to determine whether or not to use this mode.
Moreover, if the improvement to the display is inadequate even
R3  
31 

− 5.0V = 1+
 • 1−
 • (-2.1)
 R1 + R2   162 
after high power mode has been set, it is necessary to add a liquid
Equation C-3
crystal drive power supply externally.
Moreover, when the current flowing VDD and V5 is set to 5µA,
R1 + R2 + R3 = 1.4MΩ
5.13. The Internal Power Supply Shutdown Command
Sequence
Equation C-4
The sequence shown in Figure 11 is recommended for shutting
down the internal power supply.
With this, according to equation C-2, C-3 and C-4,
l
tia
power saver mode and then turn the power supply OFF.
n
R1 = 264kΩ
e
fid
n
R2 = 211kΩ
R3 = 925kΩ
us
Co
First place the power supply in
Sequence
l
Details
Command address
(Command, status)
D7 D6 D5 D4 D3 D2 D1 D0
Step1
Display OFF
1
0 1
0
1
1 1
0
S variable range and notch width based
At this time, the V5 voltage
Step2
Display all points ON
1
0 1
0
0
1 0
1
on the electron volume function is as shown in Table 13.
END
p
un
Table 13
e
Us
O
y
nl
Power saver
commands
(compound)
Internal power supply OFF
Figure 11
Y Typ.
Max.
Units
AR
Variable
-8.6-G
-7.0
-5.3
[V]
N
Range
(63 E
levels) (central value)
(0 level)
V
A Notch width H
53
[mV]
W
E
Note1: When
the V voltage regulator internal resistors or the electronic
N function is used, it is necessary to at least set the voltage
r volume
Fo regulator circuit and the voltage follower circuit to an operating mode
V5
Min.
5
using the power control set commands.
Moreover, it is necessary
to provide a voltage from VOUT when the Booster circuit is OFF.
Note2: The VR terminal is enabled only when the V5 voltage regulator
internal resistors are not used (i.e. the IRS terminal = ‘L’). When
the V5 voltage regulator internal resistors are used (i.e. when the
IRS terminal = ‘H’), the VR terminal is left open.
Note3: Because the input impedance of the VR terminal is high, it is
necessary to take into consideration short leads, shield cables, etc.
to handle noise.
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MAR. 15, 2004
Version: 1.8
SPLC501C
5.14. Reference Circuit Examples
Figure 12 shows reference circuit examples.
5.14.1.1. When using all of the step-up circuit, voltage regulating circuit and V/F circuit
A. When the voltage regulator internal resistor is used.
Example where VSS2 = VSS, with 4x step-up
B. When the voltage regulator internal resistor is not used.
Example where VSS2 = VSS, with 4x step-up
VDD
VDD
IRS
IRS
MS
REF
REF
C1
CAP3-
CAP2+
C1
CAP2V5
C2
s
luC2
np
Su
e
Us
VR
R1
VDD
C2
V2
C2
V3
C2
V4
O
V5
C2
id
nf
C2
Y
AR
-G
al
ti
C2
CAP2-
R3
VDD
V1 en
Co
CAP2+
R2
VDD
C2
CAP1-
C1
VR
VDD
CAP1+
C1
SPLC501C
CAP1-
CAP3-
C1
VSS
CAP1+
C1
VOUT
ly
C2
n V5
SPLC501C
VOUT
C1
VSS
VSS2
VSS2
C1
MS
V1
V2
V3
V4
V5
Figure 12
N
r
Fo
H
W
E
N
E
AV
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MAR. 15, 2004
Version: 1.8
SPLC501C
5.14.1.2. When the voltage regulator circuit and V/F circuit alone are used
A. When the V5 voltage regulator internal resistor is not used.
B. When the voltage regulator internal resistor is used.
VDD
VDD
IRS
MS
IRS
REF
REF
VSS2
VSS2
VOUT
VOUT
CAP3N
External
power
supply
CAP1P
VSS
CAP1N
External
power
supply
CAP2P
VDD
R3
V5
R2
VR
R1
C2
C2
C2
C2
CAP1N
CAP2N
V5
VDD
VR
VDD
C2
CAP1P
CAP2P
SPLC501C
CAP2N
CAP3N
SPLC501C
VSS
MS
VDD
V1
C2
V2
C2
V3
C2
V4
C2
V5
al
C2
ti
n
de
V1
V2
V3
V4
V5
fi
s
n
Su
u
pl
n
Co
Figure 13
y
Y
AR
-G
e
Us
O
nl
N
r
Fo
H
W
E
N
E
AV
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21
MAR. 15, 2004
Version: 1.8
SPLC501C
C. When the V/F circuit alone are used.
D. When the built-in power is not used.
VDD
VDD
REF
IRS
REF
MS
VSS2
VOUT
CAP3N
CAP1P
CAP1P
CAP1N
CAP1N
CAP2P
CAP2P
CAP2N
V5
VDD
VR
C2
C2
CAP2N
VDD
V1
V1
us
External
power
supply
l
ia
V4 fid
C2
t
en
V2
V3
V4
n
Co
l
np
VR
VDD
V3
C2
V5
VDD
V2
C2
VOUT
CAP3N
SPLC501C
VSS
VSS
SPLC501C
VSS2
External
power
supply
MS
IRS
V5
V5
Su
Figure 14
y
Y
AR
-G
e
Us
O
nl
N
r
Fo
H
W
E
N
E
AV
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Version: 1.8
SPLC501C
5.15. The Reset Circuit
is ‘L.’.
While
When the RESET input comes to the ‘L’ level, these LSIs return
supply short-circuits to VDD when RESET
to the default state.
RESET is ‘L,’ the oscillator and the display timing generator stop,
Their default states are as follows:
and the CL, FR, FRS and DOF terminals are fixed to ‘H’.
The
1).
Display OFF
terminals DB7 - 0 are not affected.
2).
Normal display
from the SEG and COM output terminals.
3).
ADC select: Normal (ADC command DB0 = ‘L’)
internal resistor is connected between VDD and V5.
4).
Power control register: (DB2, DB1, DB0) = (0, 0, 0)
internal liquid crystal power supply circuit is not used on other
5).
Serial interface internal register data clear
models of SPLC501C, it is necessary that RESET is ‘L’ when the
6).
LCD power supply bias rate:
external liquid crystal power supply is turned on.
SPLC501C...............................................1/9 bias
7).
9).
It means that an
When the
While RESET
is ‘L,’ the oscillator works, but the display timing generator stops,
All-indicator lamps-on OFF (All-indicator lamps ON/OFF
and the CL, FR, FRS and DOF terminals are fixed to ‘H’.
command DB0 = ‘L’)
8).
The VDD level is output
The
terminals DB7 - 0 are not affected.
Power saving clear
V5 voltage regulator internal resistors, Ra and Rb, are
connected.
6. COMMANDS
10). Output conditions of SEG and COM terminals
The SPLC501C chips identify the data bus signals by a
SEG: VDD, COM: VDD
11). Read modify write OFF
combination of A0P, RD (EP), WR (RWP) signals.
Command
12). Static indicator OFF
interpretation and execution do not depend on the external clock,
but rather is performed through internal timing only, and thus the
Static indicator register: (DB1, DB2) = (0, 0)
13). Display start line set to first line
processing is fast enough that normally a busy check is not
14). Column address set to Address 0
required.
15). Page address set to Page 0
l
ia
t
en
16). Common output status normal
In the 8080 MPU interface, commands are launched by inputting a
low pulse to the RD terminal for reading, and inputting a low
17). V5 voltage regulator internal resistor
fidratio set mode clear
on clear
18). Electronic volume register set C
mode
s
Electronic volume register:lu
(DB5, DB4, DB3, DB2, DB1, DB0)
p
n
= (1, 0. 0, 0, 0, 0)
Su
interface, the interface is placed in a read mode when a ‘H’ signal
20). Driving mode register: (DB7, DB6)=(0,
ly 0)
launched by inputting a high pulse to the EP terminal (See ‘10.
pulse to the WR terminal for writing.
is input to the RWP terminal.
O
It is placed in a write mode when a
‘L’ signal is input to the RWP terminal.
19). Test mode clear
n
In the 6800 Series MPU
Then, the command is
Timing Characteristics’ regarding the timing).
e
On the other hand, when the reset
Us command is used, only above
Y
default settings from 11 toR19 are executed. When the power is
A
turned on, the IC internal
-G state becomes unstable, and it is
N
necessary to initialize
VE it using the RESET terminal. After the
A
initialization, H
W each input terminal should be controlled normally.
E
Moreover,
r N when the control signal from the MPU is in the high
impedance,
an over-current may flow to the IC. After applying a
Fo
Consequently, the
6800 Series MPU interface is different from the 80x86 Series MPU
interface in that in the explanation of commands and the display
commands the status read and display data read RD (EP)
becomes ‘1(H)’.
In the explanations below, the commands are
explained using the 8080 Series MPU interface as the example.
When the serial interface is selected, the data is inputted in the
sequence starting from DB7.
current, it is necessary to take proper measures to prevent the
input terminal from getting into the high impedance state.
If the
internal liquid crystal power supply circuit is not used on
SPLC501C, it is necessary that RESET is ‘H’ when the external
liquid crystal power supply is turned on.
This IC has the function
to discharge V5 when RESET is ‘L,’ and the external power
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MAR. 15, 2004
Version: 1.8
SPLC501C
<Explanation of Commands>
6.1. Display ON/OFF
This command turns the display ON and OFF.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
1
0
1
0
1
1
1
DB0
Setting
1
Display ON
0
Display OFF
When the display OFF command is executed and when in the display all points ON mode, power saver mode is entered.
See the section
on the power saver for details.
6.2. Display Start Line Set
This command is used to specify the display start line address of the display data RAM shown in Figure 4.
For further details, see the
explanation of this function in ‘The Line Address Circuit’.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Line Address
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
↓
l
2
↓
1
1
1
1
1
0
62
1
1
1
1
1
1
63
tia
id
nf
6.3. Page Address Set
en
o
This command specifies the pageCaddress corresponding to the
Changing the page address does not accompany a change in the
low address when the MPU accesses
the display data RAM (see
pl
status display.
Figure 4).
Description (page 12) for the detail.
us
Specifying
n
the
Su page
address and column address
See the page address circuit in the Function
enables to access a desired bit of the display data RAM.
EP
RWP
A0P
RD
WR
0
1
0 Y
AR
-G
y
O
nl
eDB7
Us
1
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Page Address
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
EN
V
HA
EW
↓
N
or
F
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24
2
↓
0
1
1
1
7
1
0
0
0
8
MAR. 15, 2004
Version: 1.8
SPLC501C
6.4. Column Address Set
This command specifies the column address of the display data
making it possible for the MPU to continuously read from/write to
RAM shown in Figure 4.
the display data.
The column address is split into two
The column address increment is topped at
sections (the higher 4 bits and the lower 4 bits) when it is set
83H.
(fundamentally, set continuously). Each time the display data RAM
See the function explanation in ‘The Column Address Circuit’ for
This does not change the page address continuously.
is accessed, the column address automatically incremented (+1),
details.
EP RWP
A0P RD
High bits →
0
Column
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
0
0
1
A7
A6
A5
A4
0
0
0
0
0
0
0
0
0
0
A3
A2
A1
A0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
Low bits →
DB0 A7 A6 A5 A4 A3 A2 A1 A0
↓
Address
2
↓
1
0
0
0
0
0
0
0
130
1
0
0
0
0
0
1
1
131
6.5. Status Read
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
BUSY
ADC
ON/OFF
RESET
0
0
0
0
BUSY
When BUSY = ‘1’, it indicates that either processing is occurring internally or a reset condition is in process.
While the
chip does not accept commands until BUSY = ‘0’, if the cycle time can be satisfied, there is no need to check for BUSY
condition.
ADC
l
tia
n between the column address and the segment driver.
This shows the relationship
de
i
0: Reverse (column address
131-nÙSEG n)
nf
o
C address nÙSEG n)
1: Normal (column
us
(The ADC command
switches the polarity.)
pl
ON/OFF
un
S indicates the display ON/OFF state.
ON/OFF:
0: Display ON
y
nl
O
(This display ON/OFF
se command switches the polarity.)
U
This indicates
Y that the chip is in the process of initialization either because of a
AR
command.
-G
N
0:
Operating
state
E
AV
1: Display OFF
RESET
H
EW
RESET signal or because of a reset
1: Reset in progress
rN
Fo
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MAR. 15, 2004
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SPLC501C
6.6. Display Data Write
This command writes 8-bit data to the specified display data RAM
address.
by one after the write, the MPU can write the display data.
Since the column address is automatically incremented
EP
RWP
A0P
RD
WR
1
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write data
6.7. Display Data Read
This command reads 8-bit data from the specified display data
after the column address being set.
RAM address.
in “Display Data RAM” for the explanation of accessing the internal
Since the column address is automatically
incremented by one after the read, the CPU can continuously read
registers.
multiple-word data.
data becomes unavailable.
One dummy read is required immediately
EP
RWP
A0P
RD
WR
1
0
1
DB7
DB6
DB5
See the function explanation
When the serial interface is used, reading the display
DB4
DB3
DB2
DB1
DB0
Read Data
6.8. ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence between the
12) for the detail.
display RAM data column address and the segment driver output.
accompanying the reading or writing the display data is done
Thus, sequence of the segment driver output pins may be
according to the column address indicated in Figure 4.
reversed by the command.
Increment of the column address (by ‘1’)
See the column address circuit (page
EP
RWP
A0P
RD
WR
DB7
0
1
0
1
id
f
on
us
DB6
l
tia
n
e 0
DB5
DB4
DB3
DB2
DB1
DB0
Setting
1
0
0
0
0
0
Normal
1
Reverse
C
pl
6.9. Display Normal/Reverse
un
S
This command can reverse the lit and unlit display without
done, the display data RAM contents are maintained.
overwriting the contents of the displaylydata RAM. When this is
EP
A0P
RD
0
1
H
EW
RWP
se
WR U
Y
AR
-G 0
EN
O
n
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
0
1
1
0
AV
1
Setting
RAM Data ‘H’
LCD ON voltage (normal
RAM Data ‘L’
LCD ON voltage (reverse)
rN
Fo
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SPLC501C
6.10. Display All Points ON/OFF
This command makes it possible to force all display points ON
command
regardless of the content of the display data RAM. The contents of
command.
the display data RAM are maintained when this is done.
takes
priority
over
the
display
normal/reverse
This
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
1
0
1
0
0
1
0
When the display is in an OFF mode, executing the display all
DB0
Setting
0
Normal display mode
1
Display all points ON
For more details, see the Power Save Section.
points ON command will place the display in power save mode.
6.11. LCD Bias Set
This command selects the voltage bias ratio for the liquid crystal display.
EP
RWP
Select Status
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SPLC501C
0
1
0
1
0
1
0
0
0
1
0
1/9 bias
1
1/7 bias
6.12. Read/Modify/Write
Once
command is inputted, the column address returns to the address
this command has been inputted, the display data read command
at when the read/modify/write command was entered. This
does not change the column address, but onlyl the display data
function makes it possible to reduce the load on the MPU when
This command is used paired with the ‘END’ command.
tia
write command increment (+1) the column naddress.
This mode
e
fid
remains until the END command is ninputted.
When the END
o
EP
RWP C
s
lu
A0P
pWR
DB7
DB6
RD
n
u
S
0
1
0
1
1
there is repeating data changes in a specified display region, such
as when there is a blanking cursor.
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
Note: Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
y
command cannot be used.
Y
AR
-G
e
Us
O
nl
However, the column address set
N
r
Fo
H
W
E
N
E
AV
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SPLC501C
6.12.1. The sequence for cursor display
Page address set
Column address set
Read/modify/write
Dummy read
Data read
Data process
Data write
No
Change complete?
Yes
End
l
ia
id
nf
6.13. END
us
t
en
Figure 15
Co
This command releases the read
pl / modify / write mode, and returns the column address to the address at when the mode was entered.
n
Su RWP
EP
A0P
0
RD
WR
1
0
Y
AR
-G
e
Us
EN
Column
AV address
H
EW
rN
Fo
O
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
0
1
1
1
0
y
nl
Return
N
N+1
N+2
N+3
Read/modify/write mode set
N+m
N
End
Figure 16
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MAR. 15, 2004
Version: 1.8
SPLC501C
6.14. RESET
This command initializes the display start line, the column address,
mode are released.
the page address, the common output mode, the V5 voltage
See the function explanation in “Reset” for details.
There is no impact on the display data RAM.
regulator internal resistor ratio, the electronic volume, and the
operation is performed after the reset command is entered.
The reset
static indicator are reset, and the read/modify/write mode and test
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
1
0
0
0
1
0
The initialization must be done through applying a reset signal to the RESET terminal when the power supply is applied.
6.15. Common Output Mode Select
This command can select the scan direction of the COM output
Output Mode Select Circuit”.
terminal. For details, see the function explanation in “Common
EP
RWP
Select Status
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
0
0
0
*
*
*
SPLC501C
1
Normal
COM0
--> COM63
Reverse
COM63
--> COM0
Note: *Disabled bit
6.16. Power Controller Set
This command sets the power supply circuit functions.
A0P
0
EP
RWP
RD
WR
DB7
0
d
0nfi
o
C
1
us
l
tia
DB6
n
e
See the function explanation in “The Power Supply Circuit” for more details.
DB5
DB4
DB3
1
0
1
0
l
np
DB1
DB0
0
Booster circuit: OFF
Booster circuit: ON
Voltage regulator circuit :OFF
1
y
nl
O
Note: Display off command masks the power control circuits
e
Us
Y
AR
-G
N
VE
A
H
W
E
rN
Fo
29
Selected Mode
1
0
Su
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Proprietary & Confidential
DB2
Voltage regulator circuit: ON
0
Voltage follower circuit: OFF
1
Voltage follower circuit: ON
MAR. 15, 2004
Version: 1.8
SPLC501C
6.17. V5 Voltage Regulator Internal Resistor Ratio Set
This command sets the V5 voltage regulator internal resistor ratio.
For details, see the function explanation in “The Power Supply
Circuits”.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Setting
0
1
0
0
0
1
0
0
0
0
0
Small
0
0
1
0
1
0
↓
↓
1
1
0
1
1
1
Large
6.18. The Electronic Volume (Double Byte Command)
6.18.1. The electronic volume mode set
This command makes it possible to adjust the brightness of the
When this command is input, the electronic volume register set
liquid crystal display by controlling the liquid crystal drive voltage
command becomes enabled.
V5 through the output from the voltage regulator circuits of the
has been set, no other command except for the electronic volume
internal liquid crystal power supply.
register command can be used.
This command is a two bytes
Once the electronic volume mode
Once the electronic volume
command used as a pair with the electronic volume mode set
register set command has been used to set data into the register,
command and the electronic volume register set command, and
the electronic volume mode is released.
both commands must be issued one after the other.
EP
RWP
A0P
RD
WR
DB7
0
1
0
1
l
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
tia
n
e
6.18.2. Electronic volume registeridset
nf
o of data to the electronic
By using this command to set sixCbits
electronic volume mode is released after the electronic volume
s
volume register, the liquid crystal
lu driving voltage, V5, assumes one
p
n
of the 64 voltage levels.u When this command is input, the
S
A0P
EP
RWP
RD
WR
0
1
0
0
1
0Y
0
1
0
0
H
EW
ly
DB7
e
Us
AR
G 0
N
O
n
DB6
DB5
register has been set.
DB4
DB3
DB2
DB1
DB0
| V5|
Small
*
*
0
0
0
0
0
1
*
*
0
0
0
0
1
0
*
*
0
0
0
0
1
1
↓
↓
E
A1V
0
*
*
1
1
1
1
1
0
1
0
*
*
1
1
1
1
1
1
Large
N bit
Note: r*Inactive
Fo
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MAR. 15, 2004
Version: 1.8
SPLC501C
6.18.3. The electronic volume register set sequence
electrodes is connected to the FR terminal, and the other is
connected to the FRS terminal.
Electronic volume mode set
A different pattern is
recommended for the static indicator electrodes than for the
dynamic drive electrodes.
If the pattern is too close, it can result
in deterioration of the liquid crystal and of the electrodes.
Electronic volume register set
The
static indicator ON command is a double byte command paired
Electronic volume mode clear
No
with the static indicator register set command, and thus one must
execute one after the other.
Changes complete?
The static indicator OFF command
is a single byte command.
Yes
6.19.1. Static indicator ON/OFF
Figure 17
When the static indicator ON command is entered, the static
6.19. Static Indicator (Double Byte Command)
indicator register set command is enabled.
This command controls the static drive system indicator display.
indicator ON command is entered, no other command aside from
The static indicator display is controlled by this command only,
the static indicator register set command can be used.
and is independent from other display control commands.
mode is cleared when data is set in the register by the static
This
Once the static
indicator register set command.
is used when one of the static indicator liquid crystal drive
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Static Indicator
0
1
0
1
0
1
0
1
1
0
0
OFF
1
ON
6.19.2. Static indicator register set
This
l
ia
t
en
This command sets two bits of data into fthe
id static indicator register, and is used to set the static indicator into a blinking mode.
EP
RWP
A0P
RD
WR
0
1
0
Note: *Disabled bit
n
s
Co
DB7pluDB6 DB5 DB4 DB3 DB2 DB1 DB0
n
Su*
*
*
*
*
*
*
*e
Us
O
*
*
*
*
0
0
OFF
*
*
*
*
0
1
ON (blinking at approximately 0.5 second intervals)
*
*
*
1
0
ON (blinking at approximately one second intervals)
*
*
*
1
1
ON (constantly on)
y
nl *
*
Y
AR
-G(Double Byte Command)
6.20. Page Blinking
N
VE blinking mode set
6.20.1. The page
A
H
W EP
RWP
E
N
r
A0P
WR
DB7
DB6
RD
Fo
0
1
0
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Proprietary & Confidential
Static Indicator
1
0
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
31
MAR. 15, 2004
Version: 1.8
SPLC501C
6.20.2. Page blinking register set
Set either bit to '1' will set corresponding PAGE0 - PAGE7 to blink.
EP
RWP
A0P
RD
WR
0
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Blinking Page
1
0
0
0
0
0
0
0
PAGE 7 blink
0
1
0
0
0
0
0
0
PAGE 6 blink
0
0
1
0
0
0
0
0
PAGE 5 blink
0
0
0
1
PAGE 0 blink
↓
0
0
0
0
6.20.3. Page blinking indicator register set sequence
6.21. Set Driving Mode (Double Byte Command)
This
command
makes
it
possible
to
reduce
the
power
consumption by instruction command for using different liquid
Page Blinking mode set
crystal panel. User can select the appropriate mode for their liquid
crystal panel and display pattern. The driving capability sequence
Blinking Page set
is
and
so
as
the
current
consumption.
(Page Blinking mode clear)
No
Mode1>Mode2>Mode3>Mode4,
Changes complete?
Yes
Figure 18
6.21.1. The driving mode set
EP
RWP
A0P
RD
WR
0
1
us
0
l
ia
t
en
fidDB7
n
Co
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
0
1
0
1
l
np
u
S register set
6.21.2. Mode selection
EP
RWP
A0P
RD
WR
0
1
0
Y
AR
-G
y
DB7O
e
Us 1
N
E
AV
nl
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Driving Duty Selection
1
0
0
0
0
0
0
Mode 1
0
0
0
0
0
0
0
0
Mode 2
0
1
0
0
0
0
0
0
Mode 3
1
0
0
0
0
0
0
0
Mode 4
H
Note1: DB5 W
- DB0 6 bits must fill 0.
E
Note2: Mode2
N (DB7, DB6)=(0,0) is default.
r Driving
Note3:
capability Mode1>Mode2>Mode3>Mode4.
o
F
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MAR. 15, 2004
Version: 1.8
SPLC501C
6.22. Power Save (Compound Command)
When the display all points ON is performed while the display is in
When the static indicator is ON, the standby mode is entered.
the OFF mode, the power saver mode is entered and therefore, it
the sleep mode and standby mode, the display data is saved as is
In
reduces a great amount of power.
The power saver mode has
the operating mode that was in effect before the power saver
two different modes: the sleep mode and the standby mode.
mode was initiated, and the MPU is still able to access the display
When the static indicator is OFF, the sleep mode is entered.
data RAM.
Static indicator OFF
Refer to figure 19 for power save off sequence.
Static indicator ON
Power saver (compound command)
Sleep mode
Standby mode
Power save OFF (compound command)
Display all points OFF command
Static indicator ON
(2 bytes command)
Power save OFF
(Display all points OFF command)
Sleep mode cancel
Standby mode cancel
Figure 19
6.22.1. Sleep mode
This stops all operations in the LCD display system, and as long
When a reset command is performed while in standby mode, the
as there are no accesses from the MPU, the consumption
current
al
system enters sleep mode.
ti
is reduced to a value close to the staticen
current. The internal
id
modes during sleep mode are as follows:
nf
o
1). The oscillator circuit and thes C
LCD power supply circuit are
lu
p
halted.
un
2). All liquid crystal driveScircuits are halted, and the segment in
Note1: When an external power supply is used, it is recommended that the
functions of the external power supply circuit should be stopped
when the power saver mode is started.
resistive voltage dividers, it is recommended that a circuit be added
in order to cut the electrical current flowing through the resistive
common drive outputs output a VDD level.
6.22.2. Standby mode
Y
e
Us
O
For example, when the
various levels of liquid crystal drive voltage are provided by external
ly
voltage divider circuit when the power saver mode is in effect.
n
terminal DOF .
This terminal enters a ‘L’ state when the power
The duty LCD display system
R operations are halted and only the
saver mode is launched.
G indicator continues to operate, providing
static drive system for -the
to stop the function of an external power supply circuit.
A
N
the minimum required
VE consumption current for the static drive.
A
The internal H
modes
W
mode. NE
or LCD power
1).FThe
Using the output of DOF , it is possible
Note2: When the master is turned on, the oscillator circuit is operable
immediately after the power on.
are in the following states during standby
supply circuits are halted.
The
SPLC501C chips have a liquid crystal display blanking control
The oscillator
circuit continues to operate.
2). The duty drive system liquid crystal drive circuits are halted
and the segment and common driver outputs a VDD level.
The static drive system does not operate.
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MAR. 15, 2004
Version: 1.8
SPLC501C
6.23. NOP
Non-Operation Command
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
1
0
0
0
1
1
6.24. TEST
This is a command for IC chip testing.
Please do not use it. If
applying a ‘L’ signal to the RESET input by the reset command
the test command is used by accident, it can be cleared by
A0P
EP
RWP
RD
WR
DB7
DB6
or by using a NOP.
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
1
1
*
*
*
*
0
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
0
1
0
1
0
0
Note: The SPLC501C chips maintain their operating modes until some conditions occurred to change them.
Consequently, excessive external noise, etc.,
can change the internal modes of the SPLC501C chip. Thus, in the packaging and system design, it is necessary to suppress the noise or take
measurement to prevent the noise from influencing the chip.
Moreover, it is recommended that the operating modes be refreshed periodically to
prevent the effects.
l
ia
fid
us
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np
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N
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Fo
H
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AV
© Sunplus Technology Co., Ltd.
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MAR. 15, 2004
Version: 1.8
SPLC501C
6.25. Table 13 Table of SPLC501C Commands
Command Code
Command
A0P
RD
WR
0
1
0
1). Display ON/OFF
1
0
1
0
2). Display start line set
0
1
0
0
1
3). Page address set
0
1
0
1
0
1
1
4). Column address set
0
1
0
0
0
0
1
1
0
1
0
5). Status read
0
0
1
6). Display data write
1
1
0
7). Display data read
1
0
1
8). ADC select
0
1
0
0
0
1
1
0
LCD display ON/OFF
1
0: OFF, 1: ON
Sets the display RAM display start line
Display start address
0
0
address
Sets the display RAM page address
Page address
upper bit
Column address set
Function
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Most significant
Sets the most significant 4 bits of the
column address
display RAM column address.
Least significant
Set the least significant 4 bits of the
display RAM column address.
column address
lower bit
Status
0
0
0
0
Write data
Writes to the display RAM
Read data
1
0
1
0
0
Reads the status data
Reads from the display RAM
0
0
0
Sets the display RAM address SEG
1
output correspondence
0: normal, 1:reverse
9). Display normal/reverse
0
1
0
1
0
1
0
0
1
1
0
Sets the LCD display normal/ reverse
1
0: normal, 1:reverse
10). Display
0
1
0
1
0
1
0
0
1
0
0
Display all points
1
0: normal display
all
points
ON/OFF
l
ia
nt
11). LCD bias set
12). Read/modify/write
e
fid1
0
n
Co
n
Su
s
lu 0
1
p
0
0
1: all points ON
1
1
0
1
1
0
1
0
0
0
0
0
1
0
0
Sets the LCD driver voltage bias ratio
1
SPLC501C……….0:1/9, 1:1/7
0
Column address increment
At write: +1
At read: 0
0
1
1
1
0
1
1
1
0
Clear read/modify/write
e0
1
0
1
1
1
0
0
0
1
0
Internal reset
0
1
0
1
1
0
0
0
*
*
*
Select COM output scan direction
13). End
ly 1
14). Reset
s
15). Common output mode U
Y
select
AR
G
EN
V
16). Power control
set
HA
W
N5Evoltage regulator
17).r V
o
F internal resistor ratio
0
O
n
1
0: normal direction,
1: reverse direction
0
1
0
0
0
1
0
1
Operating mode
Select internal power supply operating
mode
0
1
0
0
0
1
0
0
Resistor ratio
Select internal resistor ratio (Rb/Ra)
mode
set
18). Electronic volume
0
1
0
0
1
0
1
0
0
0
0
0
0
mode set
Electronic volume
1
Set the V5 output voltage electronic
volume register
*
*
Electronic volume value
register set
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MAR. 15, 2004
Version: 1.8
SPLC501C
Command Code
Command
A0P
RD
WR
0
1
0
19). Static indicator
Function
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
1
1
0
ON/OFF
0
0: OFF, 1: ON
1
Static indicator
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
P7
P6
P5
P4
P3
P2
P1
P0
*
*
*
*
*
*
Mode
Set the flashing mode
Register set
20). Page Blink
Page selection
P7 - 0: 1 - blinking page
0 - no blinking, normal display
21). Driving Mode Set
Mode selection
0
1
0
1
1
0
1
0
0
1
0
Set the driving mode register
0
1
0
D1
D0
0
0
0
0
0
0
Driving capability (D1, D0):
(1,1)>(0,0)>(0,1)>(1,0)
22). Power saver
Display OFF and display all points ON
compound command
23). NOP
0
1
0
1
1
1
0
0
0
24). Test
0
1
0
1
1
1
1
*
*
1
1
0
1
0
1
1
1
Command for non-operation
*
*
Command for IC test.
0
0
this command
Do not use
l
ia
fid
us
t
en
n
Co
l
np
Su
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Y
AR
-G
e
Us
O
nl
N
r
Fo
H
W
E
N
E
AV
© Sunplus Technology Co., Ltd.
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MAR. 15, 2004
Version: 1.8
SPLC501C
7. COMMAND DESCRIPTION
7.1. Instruction Setup: Reference (Reference)
7.1.1. Initialization
2). When the built-in power is not being used immediately after
Note: When the power is applied, LCD driving non-selective potentials V2
turning on the power:
and V3 (SEG pin) and V1 and V4 (COM pin) are output through the
LCD driving output pins SEG and COM. When electric charge is
remaining in the smoothing capacitor connecting between the LCD
Turn ON the VDD-VSS power keeping the
RESET pin = "L".
driving voltage output pins (V5 - 1) and the VDD pin, the picture on the
display may become totally dark instantaneously when the power is
turned on.
To avoid occurrence of such a failure, we recommend
When the power is stabilized
the following flow when turning on the power.
Release the reset state. (RESET pin = "H")
1). When the built-in power is being used immediately after turning
on the power:
Initialized state (Default) *1
Arrange to start the power saver
within 5ms after releasing the
reset state. Execute the
procedures from turning on the
power to setting the power
control in 5ms.
Power saver START (multiple commands) *8
Turn ON the VDD-VSS power keeping the
RESET pin = "L".
Function setup by command input(User setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4
When the power is stabilized
Release the reset state. (RESET pin = "H")
Function setup by command input(User setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
Initialized state (Default) *1
Arrange to execute all the
procedures from releasing the
reset state through setting the
power control within 5ms.
Execute the procedures from
turning on the power to setting
the power control in 5ms.
Function setup by command input(User setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4
Function setup by command input(User setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
us
Power saver OFF *8
Function setup by command input(User setup)
(16) Power control setting *7
l
tia
id
nf
en
Arrange to start power control
setting within 5ms after turning
OFF the power saver.
This concludes the initialization
Co
l
np
Figure 21
Function setup by command input(User setup)
(16) Power control setting *7
Su
Note1: The target time of 5ms varied depending on the panel characteristics
This concludes the initialization
Figure 20
and the capacitance of the smoothing capacitor.
y
nl
O
e
s
Note1: The target time of 5ms varied
Udepending on the panel characteristics
and the capacitance ofYthe smoothing apacitor. Therefore, we
AR an operation check using the actual
suggest users to conduct
G
equipment.
EN sections or paragraphs listed below.
Note2: Refer to respective
V
HAof functions; Reset circuit
*1:Description
W
*2:Command
description; LCD bias setting
NE
*3:Command
description; ADC selection
r
o
F*4:Command
description; Common output state selection
equipment.
Note2: Refer to respective sections or paragraphs listed below.
*1:Description of functions; Resetting circuit
*2:Command description; LCD bias setting
*3:Command description; ADC selection
*4:Command description; Common output state selection
*5:Description of functions; Power circuit & Command description;
Setting the built-in resistance radio for regulation of the V5 voltage
*6:Description of functions; Power circuit & Command description;
Electronic volume control
*5:Description of functions; Power circuit & Command description;
*7:Description of functions; Power circuit & Command description;
Setting the built-in resistance radio for regulation of the V5 voltage
Power control setting
*6:Description of functions; Power circuit & Command description;
*8:The power saver ON state can either be in sleep state or stand-by
Electronic volume control
state.
*7:Description of functions; Power circuit & Command description;
Command description; Power saver START (multiple
commands)
Power control setting.
© Sunplus Technology Co., Ltd.
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Therefore, we
suggest users to conduct an operation check using the actual
37
MAR. 15, 2004
Version: 1.8
SPLC501C
7.1.2. Data display
End of initialization
Function setup by command input (User setup)
(2) Display start line set *9
(3) Page address set *10
(4) Column address set *11
Function setup by command input (User setup)
(6) Display data write *12
Notes: Reference items
*9: Command Description; Display start line set
*10: Command Description; Page address set
*11:Command Description; Column address set
*12: Command Description; Display data write
*13: Command Description; Display ON/OFF
Avoid displaying all the data at the data display
start(when the display is ON) in white.
Function setup by command input (User setup)
(1) Display ON/OFF *13
End of data display
Figure 22
7.1.3. Power OFF *14
Optional status
Set the time (tL) from reset active to
turning off the VDD - VSS Power ( VDD VSS = 2.4 V) longer than the time (tH)
when the potential of V5 - 1 becomes below
the threshold voltage (approximately 1V)
of the LCD panel. For tH, refer to the
<Reference Data> of this event. When tH
is too long, insert a resistor between V5
and VDD to reduct it.
Function setup by command input (User setup)
(20) Power save *15
Reset active( RESET pin = "L")
al
i
VDD - VSS power
nt OFF
id
f
on
s
Note: Reference items
n
Su
u
pl
e
C
Figure 23
7.2. Precautions ON Turning OFF The Power
*14:The logic circuit of this IC’s power supply VDD - VSS controls the
driver of the LCD power supply VDD - V5.
y
nl
7.2.1. Power save (the LCD powers (VDD - V5) are off.)
→ Reset input → Power (VDD - VSS) OFF
Therefore, if the power
supply VDD - VSS is cut off when the LCD power supply VDD - V5
O
e
s
uncontrolled voltage.
When
U turning off the power, observe the
following basic procedures:Y
AR
• After turning off the
G internal power supply, make sure that the
has
potential V
N become below the threshold voltage of the LCD
Eturn
panel, and then
off this IC’s power supply (VDD - VSS).
V
A
Refer toH “6. Description of Function, Power Circuit” for more
information.
EW
N
*15: rAfter inputting the power save command, be sure to reset the function
Fousing the RESET terminal until the power supply VDD - VSS is
has still any residual voltage, the driver (COM. SEG) may output any
1). Observe tL > tH.
2). When tL < tH, an irregular display may occur.
Set tL on the MPU according to the software.
5 - 1
turned off.
tH is determined
according to the external capacity C2 (smoothing capacity of
V5 - 1) and the driver’s discharging capacity.
Refer to “ 7. Command Description, (20) Power Save”
for more information.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
38
MAR. 15, 2004
Version: 1.8
SPLC501C
Power
save Reset Power off
tL
VDD
1.8 V
RESET
VDD
SEG
Since the power (VDD-VSS)
is cut off, the output comes
not to be fixed.
VDD
COM
V1
V2
V3
V4
V5
About 1V: Below Vth of the LCD Panel
tH
Figure 24
l
ia
fid
us
t
en
n
Co
l
np
Su
y
Y
AR
-G
e
Us
O
nl
N
r
Fo
H
W
E
N
E
AV
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
39
MAR. 15, 2004
Version: 1.8
SPLC501C
8. ELECTRICAL SPECIFICATIONS
8.1. Absolute Maximum Ratings
(Unless otherwise noted, VSS = 0V)
Parameter
Symbol
Conditions
Unit
VDD
-0.3 to + 7.0
V
Power Supply Voltage
Power supply voltage (2)
-7.0 to +0.3
(VDD standard)
With Triple step-up
VSS2
-4.0 to +0.3
Power supply voltage (3) (VDD standard)
V5, VOUT
-12.0 to +0.3
V
Power supply voltage (4) (VDD standard)
V1, V2, V3, V4
V5 to +0.3
V
Input voltage
VIN
-0.3 to VDD +0.3
V
Output voltage
VO
-0.3 to VDD +0.3
V
TOPR
-40 to +85
℃
TSTR
-55 to +125
℃
With Quad step-up
-3.0 to +0.3
Operating temperature
Storage temperature
V
Bare chip
VDD
VDD
GND
VSS
VDD
VSS2,V1 to V4
V5 , VOUT
l
System (MPU) side
ia
SPLC501C chip side
t
n
de
fi
Notes and Cautions:
us
n
Co
Figure 25
l
np
u
and VOUT
S are relative to the VDD = 0V reference.
1. The VSS2, V1 to V5
2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD≧V1≧V2≧V3≧V4≧V5.
3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation
y
nl
the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but
e
Us
O
may have a negative impact on the LSI reliability as well.
Y
AR
-G
N
r
Fo
H
W
E
N
E
AV
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
40
MAR. 15, 2004
Version: 1.8
SPLC501C
8.2. DC Characteristics
(Unless otherwise specified, VSS = 0V, VDD = 3.0V±10%, TA = 25℃)
Item
Symbol
Operating
Possible Operating
Voltage (1)
Voltage (1A)
Rating
Condition
VDD
Possible Operating
Units
Applicable
PIN
Min.
Typ.
Max.
2.8
-
3.0
V
VDD*1
3.0
-
5.5
V
VDD*1
Voltage (1B)
Operating
Recommended
Voltage (2)
Voltage
Possible Operating
VSS2
(Relative to VDD)
-3.3
-
-2.7
V
VSS2
VSS2
(Relative to VDD)
-6.0
-
-1.8
V
VSS2
V5
(Relative to VDD)
-10
-
-4.5
V
V5*2
-12
-
-4.5
V
V5*2
Voltage
Operating
Possible Operating
Voltage (3)
Voltage (3A)
Possible Operating
Voltage (3B)
Possible Operating
V1, V2
(Relative to VDD)
0.4 x V5
-
VDD
V
V1, V2
V3, V4
(Relative to VDD)
V5
-
0.6 x V5
V
V3, V4
Voltage
Possible Operating
Voltage
High-level Input Voltage
VIHC
0.8 x VDD
-
VDD
V
*3
Low-level Input Voltage
VILC
VSS
-
0.2 x VDD
V
*3
High-level Input Voltage
VOHC
IOH = -0.5mA
0.8 x VDD
-
VDD
V
*4
Low-level Input Voltage
VOLC
IOL = 0.5mA
VSS
-
0.2 x VDD
V
*4
VIN = VDD or VSS
-1.0
-
1.0
µA
*5
-3.0
-
3.0
µA
*6
e
fid ILO
Output leakage current
Liquid Crystal Driver ON
Resistance
s
n
Static Consumption Current
Su
u
pl
n
Co
I5Q
Input Terminal Capacitance
Oscillator
Internal Oscillator
Frequency
External Input
Internal Power
Y
AR
-G
e
Us
EN
V
Supply Setup-up
output
HA
W
voltage
Circuit
NE regulator Circuit
r Voltage
Fo
RON
TA = 25℃
V5 = -12V
-
2.0
3.5
KΩ
SEGn
(Relative To VDD)
V5 = -8.0V
-
3.2
5.4
KΩ
COMn*7
-
0.01
5.0
µA
VSS, VSS2
V5 = -12V (Relative to VDD)
-
0.01
15
µA
V5
TA = 25℃ f = 1.0MHz
ISSQ
Output Leakage Current
Input Voltage
al
ILInti
Input leakage current
Operating Voltage
Voltage Follower Circuit
Operating Voltage
Base Voltage
O
ly CIN
-
5.0
8.0
pF
fOSC
TA = 25℃
18
22
26
KHz
*8
fCL
SPLC501C
18
22
26
KHz
CL
n
VSS2
With Triple (Relative to VDD)
-4.0
-
-2.4
V
VSS2
VSS2
With Quad (Relative to VDD)
-3.0
-
-2.4
V
VSS2
VOUT
(Relative to VDD)
-12
-
-
V
VOUT
VOUT
(Relative to VDD)
-12
-
-6.0
V
VOUT
V5
(Relative to VDD)
-12
-
-4.5
V
V5 *9
-2.28
-2.22
-2.16
V
*10
VREG0
TA = 25℃
-0.05%/℃
(Relative to VDD)
*Possible operating voltage (1A) is applied for possible operating voltage (3A)
*Possible operating voltage (1B) is applied for possible operating voltage (3B)
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Version: 1.8
SPLC501C
Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF.
Current consumed by total ICs when an external power supply is used.
8.3. Display Pattern OFF
(TA = 25℃)
Item
Symbol
SPLC501C
Rating
Condition
IDD(1)
Min.
Typ.
Max.
VDD = 5.0V, V5 - VDD = -11V
-
4.6
12.6
VDD = 3.0V, V5 - VDD = -11V
-
2.9
5.8
Units
Notes
µA
*11
8.4. Display Pattern Checker
(TA = 25℃)
Item
Symbol
SPLC501C
Rating
Condition
IDD(1)
Min.
Typ.
Max.
VDD = 5.0V, V5 - VDD = -11V
-
8.2
15
VDD = 3.0V, V5 - VDD = -11V
-
5.0
7.5
Units
Notes
µA
*11
Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON
8.5. Display Pattern Checker
(TA = 25℃)
Item
Symbol
Rating
Condition
Min.
Typ.
Max.
VDD = 5.0V,
tia Double step-up Normal Mode
-
130
220
voltage. d V5 - VDD = -9.0V
-
140
280
-
200
270
-
250
320
l
SPLC501C
i
nf
VDDo =
C
s
luvoltage.
IDD(2)
p
un
en
3.0V,
Quad
High-Power Mode
step-up Normal Mode
V5 - VDD = -9.0V
High-Power Mode
Units
Notes
µA
*12
Units
Notes
S
Item
Sleep Mode SPLC501C
Y
AR
-G
EN
V
HA
SPLC501C
EW *8
N
or
F
e
Us
O
ly
Symbol
Condition
IDDS1
-
n
Rating
Min.
Typ.
Max.
-
0.01
5.0
Item
When the internal oscillator circuit is used
µA
fCL
fFR
fOSC
fOSC
4
4x65
fCL
When the internal oscillator circuit is not used
External input (fCL)
260
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is
being accessed.
*2 The operating voltage range for the VDD system and the V5 system is applied when the external power supply is being used.
*3 The A0P, DB0 to DB5, DB6 (SCL), DB7 (SI), RD (EP), WR (RWP), CS1 , CS2, CLS, CL, FR, MS, C86, PS, DOF , RES , IRS, and HPM terminals.
*4 The DB0 to DB7, FR, FRS, DOF , and CL terminals.
*5 The A0P, RD (EP), WR (RWP), CS1 , CS2, CLS, MS, C86, PS, RES , IRS, and HPM terminals.
*6 Applies when the DB0 to DB5, DB6 (SCL), DB7 (SI), CL, FR, and DOF terminals are in a high impedance state.
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MAR. 15, 2004
Version: 1.8
SPLC501C
*7 These are the resistance values for when a 0.1V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1,
V2, V3, and V4). These are specified for the operating voltage (3) range.
RON = 0.1V/ △I (Where △I is the current that flows when 0.1V is applied while the power supply is ON.)
*8 The relationship between the oscillator frequency and the frame rate frequency.
*9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
*10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the SPLC501C, the temperature range can come in three types as
VREG options: (1) approximately –0.05%/C, and (2) external input.
*11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
The SPLC501C is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no
access from the MPU.
*12 It is the value on a model having the VREG option temperature gradient is –0.05%/C when the V5 voltage regulator internal resistor is used.
8.6. Timing Characteristics
8.6.1. System bus read/write characteristics 1 (For the 8080 Series MPU)
A0P
tAH8
tAW8
CS1
(CS2="1")
tCYC8
tCCLR, tCCLW
WR, RD
tCCHR , tCCHW
tDS8
DB7 - 0
(Write)
tDS8
l
ia
fid
us
DB7 - 0
(Read)
t
en
n
Co
tOH8
tACC8
l
np
Su
y
Item
e
Us
Y
AR
-G
Address hold time
N
E
Address setupVtime
A
H
SystemW
cycle time
E
N L pulse width ( WR )
Control
or
FControl
L pulse width ( RD )
O
nl
(VDD = 4.5V to 5.5V, TA = 25℃)
Signal
Symbol
Condition
Rating
Min.
Max.
Units
tAH8
0
-
ns
tAW8
0
-
ns
A0P
tCYC8
166
-
ns
WR
A0P
tCCLW
30
-
ns
RD
tCCLR
70
-
ns
WR
tCCHW
30
-
ns
tCCHR
30
-
ns
Data setup time
tDS8
30
-
ns
Address hold time
tDH8
10
-
ns
-
70
ns
5.0
50
ns
Control H pulse width ( WR )
Control H pulse width ( RD )
RD access time
Output disable time
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
RD
DB7 - 0
tACC8
tOH8
43
CL = 100pF
MAR. 15, 2004
Version: 1.8
SPLC501C
(VDD = 2.7V to 4.5V, TA = 25℃)
Item
Signal
Address hold time
Symbol
A0P
Address setup time
System cycle time
A0P
Condition
Rating
Min.
Max.
Units
tAH8
0
-
ns
tAW8
0
-
ns
tCYC8
300
-
ns
-
ns
Control L pulse width ( WR )
WR
tCCLW
60
Control L pulse width ( RD )
RD
tCCLR
120
-
ns
-
ns
Control H pulse width ( WR )
WR
tCCHW
60
Control H pulse width ( RD )
RD
tCCHR
60
-
ns
Data setup time
tDS8
40
-
ns
Address hold time
tDH8
15
-
ns
-
140
ns
10
100
ns
DB7 - 0
RD access time
tACC8
tOH8
Output disable time
CL = 100pF
(VDD = 2.4V to 2.7V, TA = 25℃)
Item
Signal
Address hold time
Symbol
Control L pulse width ( WR )
Control H pulse width ( RD )
Data setup time
s
lu
Address hold time
id
f
on
RD access time
Output disable time
Units
0
-
ns
0
-
ns
A0P
tCYC8
1000
-
ns
WR
tCCLW
120
-
ns
RD
tCCLR
240
-
ns
tCCHW
120
-
ns
RD
tCCHR
120
-
ns
tDS8
80
-
ns
tDH8
30
-
ns
-
280
ns
10
200
ns
C
p
un
Max.
tAH8
i
t
en
Min.
l
aWR
Control L pulse width ( RD )
Control H pulse width ( WR )
Rating
tAW8
A0P
Address setup time
System cycle time
Condition
DB7 - 0
S
tACC8
tOH8
CL = 100pF
Note1: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf)≦(tCYC8 - tCCLW - tCCHW) for (tr
e
Us
O
y
nl
+ tf)≦(tCYC8 - tCCLR - tCCHR) are specified.
Note2: All timing is specified using 20% and 80% of VDD as the reference.
Y
AR
-G
Note3: tCCLW and tCCLR are specified as the overlap between CS1 being 'L' ( CS2 = 'H') and WR and RD being at the 'L' level.
N
r
Fo
H
W
E
N
E
AV
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
44
MAR. 15, 2004
Version: 1.8
SPLC501C
8.6.2. System bus read/write characteristics 2 (6800 series MPU)
A0P
RWP
tAW6
tAH6
CS1
(CS2="1")
tCYC6
tEWHR, tEWHW
EP
tEWLR , tEWLW
tDS6
tDH6
DB7 - 0
(Write)
tOH6
tACC6
DB7 - 0
(Read)
(VDD = 4.5V to 5.5V, TA = 25℃)
Item
Signal
Address hold time
id
nf
System cycle time
Data setup time
us
Co
l
np
Data hold time
Su
Access time
l
ia
Address setup time
Output disable time
Enable H pulse time
Y
AR
-G
A0P
A0P
DB7 - 0
y
Read
nl
O
eWrite
Us
Enable L pulse time
t
en
Read
Write
EP
EP
Symbol
Condition
Rating
Min.
Max.
Units
tAH6
0
-
ns
tAW6
0
-
ns
tCYC6
166
-
ns
tDS6
30
-
ns
10
-
ns
tACC6
-
70
ns
tOH6
10
50
ns
tDH6
CL = 100pF
tEWHR
70
-
ns
tEWHW
30
-
ns
tEWLR
30
-
ns
tEWLW
30
-
ns
EN
V
HA
W
E
rN
Fo
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
45
MAR. 15, 2004
Version: 1.8
SPLC501C
(VDD = 2.7V to 4.5V, TA = 25℃)
Item
Signal
Address hold time
Symbol
A0P
Address setup time
System cycle time
A0P
Condition
Rating
Min.
Max.
Units
tAH6
0
-
ns
tAW6
0
-
ns
tCYC6
300
-
ns
Data setup time
tDS6
40
-
ns
Data hold time
tDH6
15
-
ns
tACC6
-
140
ns
tOH6
10
100
ns
DB7 - 0
Access time
Output disable time
Read
Enable H pulse time
EP
Write
Read
Enable L pulse time
EP
Write
CL = 100pF
tEWHR
120
-
ns
tEWHW
60
-
ns
tEWLR
60
-
ns
tEWLW
60
-
ns
(VDD = 2.4V to 2.7V, TA = 25℃)
Item
Signal
Address hold time
Symbol
A0P
Address setup time
System cycle time
A0P
Condition
Rating
Units
Min.
Max.
tAH6
0
-
ns
tAW6
0
-
ns
tCYC6
1000
-
ns
Data setup time
tDS6
80
-
ns
Data hold time
tDH6
30
-
ns
tACC6
-
280
ns
tOH6
10
120
ns
Access time
ia
Output disable time
Enable H pulse time
s
Enable L pulse time
l
DB7 - 0
n
Su
u
pl
id
Read
nf
o
C
Write
t
en
Read
Write
EP
EP
CL = 100pF
tEWHR
240
-
ns
tEWHW
120
-
ns
tEWLR
120
-
ns
tEWLW
120
-
ns
Note1: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf)≦(tCYC6 - tEWLW - tEWHW) for
y
(tr + tf)≦(tCYC6 - tEWLR - tEWHR) are specified.
O
nl
Note2: All timing is specified using 20% and 80% of VDD as the reference.
e
Us
Note3: tEWLW and tEWLR are specified as the overlap between CS1 being 'L' (CS2 = 'H') and EP.
Y
AR
-G
N
r
Fo
H
W
E
N
E
AV
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
46
MAR. 15, 2004
Version: 1.8
SPLC501C
8.6.3. The serial interface
tCSS
tCSH
CS1
(CS2="1")
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tF
tR
tSDS
tSDH
SI
(VDD = 4.5V to 5.5V, TA = 25℃)
Item
Signal
Serial Clock Period
SCL 'H' pulse width
id
f
on
SCL 'L' pulse width
Address setup time
Address hold time
us
l
tia
n
e SCL
C
l
np
A0P
Su
Data setup time
SI
Data hold time
y
CS-SCL time
Y
AR
-G
e
Us
N
VE
HA Item
W
E
O
nl
CS
Symbol
Condition
tSCYC
Max.
-
200
-
ns
tSHW
-
75
-
ns
tSLW
-
75
-
ns
tSAS
-
50
-
ns
tSAH
-
100
-
ns
tSDS
-
50
-
ns
tSDH
-
50
-
ns
tCSS
-
100
-
ns
tCSH
-
100
-
ns
(VDD = 2.7V to 4.5V, TA = 25℃)
Condition
tSCYC
tSHW
SCL 'L' pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
Units
Min.
Symbol
N Clock Period
Serial
or
FSCL
'H' pulse width
Rating
Signal
SCL
A0P
SI
CS
Rating
Units
Min.
Max.
-
250
-
ns
-
100
-
ns
tSLW
-
100
-
ns
tSAS
-
150
-
ns
tSAH
-
150
-
ns
tSDS
-
100
-
ns
tSDH
-
100
-
ns
tCSS
-
150
-
ns
tCSH
-
150
-
ns
47
MAR. 15, 2004
Version: 1.8
SPLC501C
(VDD = 2.4V to 2.7V, TA = 25℃)
Item
Signal
Symbol
Condition
tSCYC
tSHW
SCL 'L' pulse width
Address setup time
Serial Clock Period
SCL
SCL 'H' pulse width
A0P
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
CS
Rating
Units
Min.
Max.
-
400
-
ns
-
150
-
ns
tSLW
-
150
-
ns
tSAS
-
250
-
ns
tSAH
-
250
-
ns
tSDS
-
150
-
ns
tSDH
-
150
-
ns
tCSS
-
250
-
ns
tCSH
-
250
-
ns
Note1: The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
Note2: All timing is specified using 20% and 80% of VDD as the standard.
8.6.4. Display control output timing
CL
(OUT)
tDFR
FR
l
ia
t
en
Item
us
id
Signal
nf
o
C
l
np
FR delay time
FR
(VDD = 4.5V to 5.5V, TA = 25℃)
Symbol
Condition
tDFR
CL = 50pF
Rating
Min.
Typ.
Max.
-
10
40
Units
ns
Su
(VDD = 2.7V to 4.5V, TA = 25℃)
ly
Item
Y
AR
-G
FR delay time
e
Us
n
OSignal
Symbol
Condition
FR
tDFR
CL = 50pF
Rating
Min.
Typ.
Max.
-
20
80
N
E
AV
H
Item
EW
rN
o delay time
FFR
Units
ns
(VDD = 2.4V to 2.7V, TA = 25℃)
Signal
Symbol
Condition
FR
tDFR
CL = 50pF
Rating
Min.
Typ.
Max.
-
50
200
Units
ns
Note1: Valid only when the master mode is selected.
Note2: All timing is based on 20% and 80% of VDD.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
48
MAR. 15, 2004
Version: 1.8
SPLC501C
8.6.5. Reset timing
tRW
RESET
tR
Internal
status
During reset
Reset complete
(VDD = 4.5V to 5.5V, TA = 25℃)
Item
Signal
Symbol
RES
tRW
Reset time
Condition
tR
Reset 'L' pulse width
-
Rating
Min.
Units
Typ.
Max.
-
-
0.5
µs
0.5
-
-
µs
(VDD = 2.7V to 4.5V, TA = 25℃)
Item
Signal
Symbol
Reset time
Condition
tR
Reset 'L' pulse width
RES
l
-
tRW
Rating
Units
Min.
Typ.
Max.
-
-
1.0
µs
1.0
-
-
µs
tia
id
nf
Item
s
lu
en
Co
Signal
np
Su
Reset time
Reset 'L' pulse width
(VDD = 2.4V to 2.7V, TA = 25℃)
Symbol
Condition
tR
RES
-
t
Rating
Units
Min.
Typ.
Max.
-
-
1.5
µs
1.5
-
-
µs
y
nl
Note: All timing is specified with 20% and 80% of VDD as the standard.
Y
AR
-G
e
Us
O
N
r
Fo
H
W
E
N
E
AV
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
49
MAR. 15, 2004
Version: 1.8
SPLC501C
8.7. The MPU Interface (Reference Examples)
The SPLC501C can be connected to either 80 X 86 Series MPUs
The display area can be enlarged by using multiple SPLC501C
or to 68000 Series MPUs.
chips.
Moreover, The serial interface is
possible to operate the SPLC501C chips with fewer signal lines.
When this is done, the chip select signal can be used to
select the individual ICs to access.
8.7.1. 8080 series MPUs
VDD
VDD
A0P
A0P
MPU
A7 - 1
IORQ
CS1
CS2
Decoder
DB7 - 0
RD
WR
DB7 - 0
RD
WR
RESET
RESET
GND
RESET
C86
SPLC501C
VCC
PS
VSS
VSS
Figure 26
8.7.2. 6800 series MPUs
l
ia
id
nf
Co
pl
VDD
A0P
A15 - 1
VMA
MPU
y
Y
AR
-G
H
EW
O
nl
GND
C86
A0P
CS1
CS2
Decoder
e
Us DB7 - 0
N
E
AV
VDD
DB7 - 0
EP
RWP
RESET
E
R/W
RESET
SPLC501C
n
Su
VCC
us
t
en
PS
VSS
RESET
rN
Fo
VSS
Figure 27
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
50
MAR. 15, 2004
Version: 1.8
SPLC501C
8.7.3. Using the serial interface
VDD
VCC
VDD
A0P
A0P
CS1
CS2
MPU
Decoder
Port 1
Port 2
RESET
SPLC501C
A7 - 1
SI
SCL
RESET
GND
VDD or
VSS
C86
PS
VSS
RESET
VSS
Figure 28
8.8. Connections Between LCD Drivers (Reference Example)
The liquid crystal display area can be enlarged with ease through the use of multiple SPLC501C chips.
Use a same equipment type.
8.8.1. SPLC501C (Master)<->SPLC501C (Slave)
s
lu
l
ia
VDD
id
nf
o
CMS
t
en
MS
SPLC501C
Master
Y
AR
-G
e
Us
N
VE
y
O
nl
FR
FR
CL
CL
DOF
DOF
Output
SPLC501C
Slave
np
Su
Input
HA
W
E
rN
Fo
VSS
Figure 29
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
51
MAR. 15, 2004
Version: 1.8
SPLC501C
8.9. Connections Between LCD Drivers (Reference Examples)
The liquid crystal display area can be enlarged with ease through the use of multiple SPLC501C chips. Use a same equipment type, in the
composition of these chips.
8.9.1. Single-chip structure
132 x 65 Dots
COM
SEG
COM
SPLC501C Master
Figure 30
8.10. VLCD Voltage (Voltage between VDD to V5) relationship of V5 Voltage Regulator Internal Resistor Ratio
Register and Electronic Volume Control Register
l
ia
id
14.000
f
on
us
t
en
000
001
C
010
l
np
12.000
011
Su
100
10.000
101
y
8.000
6.000
Y
AR
-G
e
Us
O
nl
110
111
N
4.000
H
EW
E
AV
The V5 voltage
regulator internal
resistance ratio
2.000
rN
registers
Fo
(D2, D1, D0)
64
61
58
55
52
49
46
43
40
37
34
31
28
25
22
19
16
13
10
7
4
1
0.000
Note: Use External VOUT Power Supply.
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
52
MAR. 15, 2004
Version: 1.8
SPLC501C
9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment and Locations
Please contact Sunplus sales representatives for more information.
9.2. Ordering Information
Product Number
Package Type
SPLC501C-NnnV-C
Chip form with Gold Bump
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
l
ia
fid
us
t
en
n
Co
l
np
Su
y
Y
AR
-G
e
Us
O
nl
N
r
Fo
H
W
E
N
E
AV
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
53
MAR. 15, 2004
Version: 1.8
SPLC501C
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only.
SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement.
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
prices at any time without notice.
FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF
SUNPLUS reserves the right to halt production or alter the specifications and
Accordingly, the reader is cautioned to verify that the data sheets and other information in this
publication are current before placing orders.
Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits
illustrated in this document are for reference purposes only.
l
ia
fid
us
t
en
n
Co
l
np
Su
y
Y
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-G
e
Us
O
nl
N
r
Fo
H
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E
N
E
AV
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
54
MAR. 15, 2004
Version: 1.8
SPLC501C
11. REVISION HISTORY
Date
Revision #
MAR. 15, 2004
1.8
APR. 22, 2003
Description
1.7
APR. 08, 2003
1.6
Page
1. Correct VDD/VLCD range in “8.2 DC Characteristics”
41
2. Remove “Recommended Voltage” from Operating voltage (1) in “8.2 DC Characteristics”
41
1. Correct command 19 in “6.25 Table 13 Table of SPLC501C Commands”
36
2. Remove “9. PACKAGE/PAD LOCATIONS”
52
1. Correct table 9 VREG value: -2.1 to -2.224
17
2. Correct table 11 Equipment Type by Thermal Gradient [Units: %/℃] value
17
JAN. 29, 2003
1.5
Correct type error
4
NOV. 15, 2002
1.4
Correct “Note4: Gold Bump Height 17µm “ to 18µm
53
NOV. 07, 2002
1.3
Delete “ 8.5 Display Pattern Checker / Standby Mode SPLC501C ”
42
APR. 04, 2002
1.2
1. Add REF pin in “3. BLOCK DIAGRAM”
5
2. Add REF pin description at “4.3 System Bus Connection Terminal”
8
3. Add REF pin connection in 5.14.1.1 and 5.14.1.2
NOV. 06, 2001
1.1
n
Su
JUL, 30, 2001
1. Modify Boost reference voltage: VDD - VSS2 = 2.4V to -6.0V to 2.4V to 6.0V
4
2. Modify Liquid crystal drive power supply: VDD - V5 = -4.5V to -12V to 4.5V to 12V
4
3. Add “Driving Mode register provided for different size panel loading” in the “2. FEATURES”
4
4. Modify Mnemonic: COM64 - 0 to COM63 - 0, PIN No.: 64 to 64
9
5. Add “20.) Driving mode register: (DB7, DB6)=(0, 0)” in the “5.15 The Reset Circuit”
23
6. Add Note1 and Note2 in the “6.21.2 Mode selection register set”
32
7. Add “Drivingl capability (D1, D0): (1,1)>(0,0)>(0,1)>(1,0)” in the “6.25 Table 13 Table of
36
ia
SPLC501C
nt Commands”
e
8. Addfi“d8.10 VLCD Voltage (Voltage between VDD to V5) relationship of V5 Voltage
on
Internal Resistor Ratio Register and Electronic Volume Control Register”
CRegulator
us
pl
9. Modify “75µm(Min.)” to “60µm(Min.)” in the “9.1 PAD Assignment”
53
53
1. Delete “PRELIMINARY”
y
2. Change
nl title
4
O
e Add REF pin description in “4.3.System Bus Connection Terminals”
s3.
JUN. 12, 2001
52
10. Add Note4 in the “9.1 PAD Assignment”
1.0
Y
AR
-G0.1
20 - 22
U
EN
4. Modify base voltage
9
41
Original
V
HA
W
E
rN
Fo
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
55
MAR. 15, 2004
Version: 1.8

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