8. SED1565 Series (Rev. 1.2) SED1565 Series Contents GENERAL DESCRIPTION ................................................................................................................................... 8-1 FEATURES ........................................................................................................................................................... 8-1 BLOCK DIAGRAM ................................................................................................................................................ 8-3 PIN DIMENSIONS ................................................................................................................................................ 8-4 PIN DESCRIPTIONS .......................................................................................................................................... 8-20 DESCRIPTION OF FUNCTIONS ....................................................................................................................... 8-24 COMMANDS ...................................................................................................................................................... 8-48 COMMAND DESCRIPTION ............................................................................................................................... 8-57 ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 8-63 DC CHARACTERISTICS .................................................................................................................................... 8-64 TIMING CHARACTERISTICS ............................................................................................................................ 8-72 THE MPU INTERFACE (REFERENCE EXAMPLES) ........................................................................................ 8-80 CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) .......................................................... 8-81 CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) ....................................................... 8-82 A SAMPLE TCP PIN ASSIGNMENT .................................................................................................................. 8-83 EXTERNAL VIEW OF TCP PINS ....................................................................................................................... 8-84 SED1565 Series NOTICE .............................................................................................................................................................. 8-85 –i– GENERAL DESCRIPTION The SED1565 Series is a series of single-chip dot matrix liquid crystal display drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crystal drive signal independent of the microprocessor. Because the chips in the SED1565 Series contain 65 × 132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The SED1565 Series chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65 × 132 dot display (capable of displaying 8 columns × 4 rows of a 16 × 16 dot kanji font). The SED1567 Series chips contain 33 common output circuits and 132 segment output circuits, so that a single chip can drive 33 × 132 dot display (capable of displaying 8 columns × 2 rows of 16 × 16 dot kanji fonts). Thanks to the built-in 55 common output circuits and 132 segment output circuits, the SED1568*** is capable of displaying 55 × 132 dots (11 columns × 4 lines using 11 × 12 dots Kanji font) with a single chip. The SED1569 Series chips contain 53 common output circuits and 132 segment output circuits, so that a single chip can drive 53 × 132 dot display (capable of displaying 11 columns × 4 rows of 11 × 12 dot kanji fonts). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a lowpower liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock CR oscillator circuit, the SED1565 Series chips can be used to create the lowest power display system with the fewest components for highperformance portable devices. FEATURES • Direct display of RAM data through the display data RAM. RAM bit data: “1” Non-illuminated “0” Illuminated (during normal display) • RAM capacity 65 × 132 = 8580 bits • Display driver circuits SED1565***: 65 common output and 132 segment outputs SED1566***: 49 common output and 132 segment outputs SED1567***: 33 common outputs and 132 segment outputs SED1568***: 55 common outputs and 132 segment outputs SED1569***: 53 common outputs and 132 segment outputs • High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs) /Serial interfaces are supported. • Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. • Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.) • Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of Double/Triple/ Quad, where the step-up voltage reference power supply can be input externally) High-accuracy voltage adjustment circuit (Thermal gradient –0.05%/°C or –0.2%/°C or external input) V5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. • CR oscillator circuit equipped internally (external clock can also be input) • Extremely low power consumption Operating power when the built-in power supply is used (an example) SED1565D0B 81 µA (VDD – VSS = VDD – VSS2 = /SED1565DBB 3.0 V, Quad voltage, V5 – VDD = – 11.0 V) SED1566D0B 43 µA (VDD – VSS = VDD – VSS2 = /SED1566DBB 3.0 V, Triple voltage, V5 – VDD = – 8.0 V) SED1567D0B 29 µA (VDD – VSS = VDD – VSS2 = /SED1567DBB 3.0 V, Triple voltage, V5 – VDD = – 8.0 V) SED1568D0B/SED1568DBB /SED1569D0B/SED1569DBB 46µA (VDD – VSS = VDD – VSS2 = 3.0 V, Triple voltage, V5 – VDD = – 8.0 V) Conditions: When all displays are in white and the normal mode is selected (see page 60 *12 for details of the conditions). • Power supply Operable on the low 1.8 voltage Logic power supply VDD – VSS = 1.8 V to –5.5 V Boost reference voltage: V DD – V SS2 = 1.8 V to –6.0 V Liquid crystal drive power supply: VDD – V5 = –4.5 V to –16.0 V • Wide range of operating temperatures: –40 to 85°C • CMOS process • Shipping forms include bare chip and TCP. • These chips not designed for resistance to light or resistance to radiation. EPSON 8–1 SED1565 Series SED1565 Series SED1565 Series Series Specifications Product Duty Name SED1565D0B 1/65 /SED1565DBB SED1565T0* 1/65 1/65 SED1565D1B 1/65 * SED1565T1* 1/65 SED1565D2B * SED1565T2* 1/65 SED1566D0B 1/49 /SED1566DBB SED1566T0* 1/49 1/49 SED1566D1B 1/49 * SED1566T1* 1/49 SED1566D2B * SED1566T2* 1/49 SED1567D0B 1/33 /SED1567DBB SED1567T0* 1/33 1/33 SED1567D1B 1/33 * SED1567T1* 1/33 SED1567D2B * SED1567T2* 1/33 SED1568D0B 1/55 /SED1568DBB SED1569D0B 1/53 /SED1569DBB * SED1569T0* 1/53 * : Under development 8–2 Bias SED Dr COM Dr VREG Temperature Gradient Shipping Forms 1/9, 1/7 132 65 –0.05%/°C Bare Chip 1/9, 1/7 1/9, 1/7 1/9, 1/7 1/9, 1/7 1/9, 1/7 132 132 132 132 132 65 65 65 65 65 –0.05%/°C –0.2%/°C –0.2%/°C External Input External Input TCP Bare Chip TCP Bare Chip TCP 1/8, 1/6 132 49 –0.05%/°C Bare Chip 1/8, 1/6 1/8, 1/6 1/8, 1/6 1/8, 1/6 1/8, 1/6 132 132 132 132 132 49 49 49 49 49 –0.05%/°C –0.2%/°C –0.2%/°C External Input External Input TCP Bare Chip TCP Bare Chip TCP 1/6, 1/5 132 33 –0.05%/°C Bare Chip 1/6, 1/5 1/6, 1/5 1/6, 1/5 1/6, 1/5 1/6, 1/5 132 132 132 132 132 33 33 33 33 33 –0.05%/°C –0.2%/°C –0.2%/°C External Input External Input TCP Bare Chip TCP Bare Chip TCP 1/8, 1/6 132 55 –0.05%/°C Bare Chip 1/8, 1/6 132 53 –0.05%/°C Bare Chip 1/8, 1/6 132 53 –0.05%/°C TCP EPSON SED1565 Series BLOCK DIAGRAM COMS • • • • • • • • • • COM63 COM0 • • • • • • • • • • • • • • • • • • • • • • • • • SEG131 SEG0 Example: SED1565*** VSS V2 V3 SEG Drivers COMS VDD V1 COM Drivers V4 V5 COM output status select circuit CAP1+ Display data latch circuit VSS2 VR Display timing generation circuit Power supply circuit Line address circuit VOUT Page address circuit CAP2+ CAP2– CAP3+ I/O buffer CAP1– Display data RAM 132 x 65 VRS IRS HPM FRS FR CL DOF M/S Oscillator circuit Column address circuit Command decoder Status SED1565 Series Bus holder CLS EPSON D0 D1 D2 D3 D4 D5 D6 (SCL) D7 (SI) RES P/S WR (R/W) RD (E) A0 CS2 CS1 MPU interface 8–3 SED1565 Series PIN DIMENSIONS 99 1 100 309 Die No. (0, 0) D1565D0B SED1565 Series 275 134 135 8–4 274 Chip Size Bump Pitch Bump Size 10.82 mm × 2.81 mm 71 µm (Min.) PAD No. 1~24 PAD No. 25~82 PAD No. 83~99 PAD No. 100 PAD No. 101~133 PAD No. 134 PAD No. 135 PAD No. 136~273 PAD No. 274 PAD No. 275 PAD No. 276~308 PAD No. 309 Bump Height 17 µm (Typ.) Chip Thickness 625 µm EPSON 85 µm × 64 µm × 85 µm × 85 µm × 85 µm × 85 µm × 73 µm × 47 µm × 73 µm × 85 µm × 85 µm × 85 µm × 85 µm 85 µm 85 µm 73 µm 47 µm 73 µm 85 µm 85 µm 85 µm 73 µm 47 µm 73 µm SED1565 Series SED1565*** Pad Center Coordinates PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 VSS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 VSS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 VSS 31 VSS 32 VSS 33 VSS2 34 VSS2 35 VSS2 36 VSS2 37 (NC) 38 VOUT 39 VOUT 40 CAP3– X Y 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 1246 PAD No. PIN Name X Y 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR VDD VDD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 1246 EPSON PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS VSS C86 P/S VDD HPM VSS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 X Y –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 8–5 SED1565 Series Units: µm SED1565 Series Units: µm PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 8–6 PIN Name COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X Y –5252 –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X Y –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 –1246 EPSON PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 X Y –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 –1246 SED1565 Series Units: µm PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) COM32 COM33 COM34 COM35 COM36 X Y 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS (NC) X Y 5252 –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 SED1565 Series PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 EPSON 8–7 SED1565 Series SED1566*** Pad Center Coordinates Units: µm PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 VSS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 VSS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 VSS 31 VSS 32 VSS 33 VSS2 34 VSS2 35 VSS2 36 VSS2 37 (NC) 38 VOUT 39 VOUT 40 CAP3– 8–8 X Y 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 1246 PAD No. PIN Name X Y 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR VDD VDD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 1246 EPSON PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS VSS C86 P/S VDD HPM VSS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) (NC) (NC) COM23 (NC) COM22 (NC) COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 X Y –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 SED1565 Series Units: µm PIN Name COM7 COM6 COM5 COM4 COM3 COM2 COM1 (NC) COM0 (NC) COMS (NC) (NC) (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X Y –5252 –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X Y –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 –1246 EPSON PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 X Y –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 –1246 SED1565 Series PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 8–9 SED1565 Series Units: µm PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 8–10 PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) (NC) (NC) COM24 (NC) COM25 X Y 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name (NC) COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 (NC) COM47 (NC) COMS (NC) (NC) (NC) X Y 5252 –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 EPSON SED1565 Series SED1567*** Pad Center Coordinates PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 VSS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 VSS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 VSS 31 VSS 32 VSS 33 VSS2 34 VSS2 35 VSS2 36 VSS2 37 (NC) 38 VOUT 39 VOUT 40 CAP3– X Y 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 1246 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR VDD VDD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 X Y 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 1246 EPSON PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS VSS C86 P/S VDD HPM VSS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) COM15 COM15 COM14 COM14 COM13 COM13 COM12 COM12 COM11 COM11 COM10 COM10 COM9 COM9 COM8 COM8 COM7 COM7 COM6 COM6 X Y –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 8–11 SED1565 Series Units: µm SED1565 Series Units: µm PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 8–12 PIN Name COM5 COM5 COM4 COM4 COM3 COM3 COM2 COM2 COM1 COM1 COM0 COM0 COMS (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X Y –5252 –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X Y –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 –1246 EPSON PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 X Y –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 –1246 SED1565 Series Units: µm PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) COM16 COM16 COM17 COM17 COM18 X Y 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name COM18 COM19 COM19 COM20 COM20 COM21 COM21 COM22 COM22 COM23 COM23 COM24 COM24 COM25 COM25 COM26 COM26 COM27 COM27 COM28 COM28 COM29 COM29 COM30 COM30 COM31 COM31 COMS (NC) X Y 5252 –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 SED1565 Series PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 EPSON 8–13 SED1565 Series SED1568*** Pad Center Coordinates Units: µm PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 VSS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 VSS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 VSS 31 VSS 32 VSS 33 VSS2 34 VSS2 35 VSS2 36 VSS2 37 (NC) 38 VOUT 39 VOUT 40 CAP3– 8–14 X Y 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 1246 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR VDD VDD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 X Y 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 1246 EPSON PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS VSS C86 P/S VDD HPM VSS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) (NC) COM26 (NC) COM25 COM25 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 X Y –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 SED1565 Series Units: µm PIN Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 (NC) COM0 (NC) COMS (NC) (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X Y –5252 –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X Y –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 –1246 EPSON PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 X Y –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 –1246 SED1565 Series PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 8–15 SED1565 Series Units: µm PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 8–16 PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) (NC) COM27 (NC) COM28 (NC) X Y 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM48 COM50 COM51 COM52 COM53 (NC) COMS (NC) (NC) X Y 5252 –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 EPSON SED1565 Series SED1569*** Pad Center Coordinates PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 VSS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 VSS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 VSS 31 VSS 32 VSS 33 VSS2 34 VSS2 35 VSS2 36 VSS2 37 (NC) 38 VOUT 39 VOUT 40 CAP3– X Y 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 1246 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR VDD VDD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 X Y 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 1246 EPSON PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS VSS C86 P/S VDD HPM VSS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) (NC) COM25 (NC) COM24 (NC) COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 X Y –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 8–17 SED1565 Series Units: µm SED1565 Series Units: µm PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 8–18 PIN Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 (NC) COM0 (NC) COMS (NC) (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X Y –5252 –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X Y –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 –1246 EPSON PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 X Y –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 –1246 SED1565 Series Units: µm PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) (NC) COM26 (NC) COM27 (NC) X Y 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 (NC) COM51 (NC) COMS (NC) (NC) X Y 5252 –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 SED1565 Series PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 EPSON 8–19 SED1565 Series PIN DESCRIPTIONS Power Supply Pins Pin Name VDD VSS VSS2 VRS V1, V2, V3, V4, V5 I/O Power Supply Power Supply Power Supply Power Supply Power Supply No. of Pins 13 Function Shared with the MPU power supply terminal VCC. This is a 0V terminal connected to the system GND. 9 This is the reference power supply for the step-up voltage circuit for the liquid crystal drive. This is the externally-input VREG power supply for the LCD power supply voltage regulator. These are only enabled for the models with the VREG external input option. This is a multi-level power supply for the liquid crystal drive. The voltage applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. 4 2 10 VDD (= V0) ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 Master operation: When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. V1 V2 V3 V4 SED1565*** 1/9•V5 1/7•V5 2/9•V5 2/7•V5 7/9•V5 5/7•V5 8/9•V5 6/7•V5 SED1566*** 1/8•V5 1/6•V5 2/8•V5 2/6•V5 6/8•V5 4/6•V5 7/8•V5 5/6•V5 SED1567*** 1/6•V5 1/5•V5 2/6•V5 2/5•V5 4/6•V5 3/5•V5 5/6•V5 4/5•V5 SED1568*** 1/8•V5 1/6•V5 2/8•V5 2/6•V5 6/8•V5 4/6•V5 7/8•V5 5/6•V5 SED1569*** 1/8•V5 1/6•V5 2/8•V5 2/6•V5 6/8•V5 4/6•V5 7/6•V5 5/6•V5 LCD Power Supply Circuit Terminals Pin Name I/O Function CAP1+ O CAP1– O CAP2+ O CAP2– O CAP3– O VOUT O VR I DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. These are only enabled when the V5 voltage regulator internal resistors are not used (IRS = “L”). These cannot be used when the V5 voltage regulator internal resistors are used (IRS = “H”). 8–20 EPSON No. of Pins 2 2 2 2 2 2 2 SED1565 Series System Bus Connection Terminals I/O Function D7 to D0 I/O This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = “L”), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = “H”: Indicates that D0 to D7 are display data. A0 = “L”: Indicates that D0 to D7 are control data. When RES is set to “L,” the settings are initialized. The reset operation is performed by the RES signal level. This is the chip select signal. When CS1 = “L” and CS2 = “H,” then the chip select becomes active, and data/command I/O is enabled. • When connected to an 8080 MPU, this is active LOW. This pin is connected to the RD signal of the 8080 MPU, and the SED1565 series data bus is in an output status when this signal is “L”. • When connected to a 6800 Series MPU, this is active HIGH. This is the 68000 Series MPU enable clock input terminal. • When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. • When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = “H”: Read. When R/W = “L”: Write. This is the MPU interface switch terminal. C86 = “H”: 6800 Series MPU interface. C86 = “L”: 8080 MPU interface. This is the parallel data input/serial data input switch terminal. P/S = “H”: Parallel data input. P/S = “L”: Serial data input. The following applies depending on the P/S status: (SI) (SCL) A0 I RES I CS1 CS2 RD (E) I I WR (R/W) I C86 I P/S I P/S “H” “L” No. of Pins 8 1 1 2 1 1 1 1 SED1565 Series Pin Name Data/Command Data Read/Write Serial Clock A0 D0 to D7 RD, WR A0 SI (D7) Write only SCL (D6) When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L” or Open. RD (E) and WR (P/W) are fixed to either “H” or “L”. With serial data input, RAM display data reading is not supported. EPSON 8–21 SED1565 Series Pin Name I/O Function CLS I M/S I Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = “H”: Internal oscillator circuit is enabled CLS = “L”: Internal oscillator circuit is disabled (requires external input) When CLS = “L”, input the display clock through the CL terminal. This terminal selects the master/slave operation for the SED1565 Series chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. M/S = “H”: Master operation M/S = “L”: Slave operation The following is true depending on the M/S and CLS status: M/S CLS Oscillator Circuit “H” “L” CL I/O “L” I/O DOF I/O FRS O IRS I HPM I 8–22 Enabled Disabled Disabled Disabled CL FR FRS DOF Output Input Input Input Output Output Input Input Output Output Output Output Output Output Input Input This is the display clock input terminal The following is true depending on the M/S and CLS status. M/S “H” FR “H” “L” “H” “L” Power Supply Circuit Enabled Enabled Disabled Disabled CLS “H” “L” “H” “L” No. of Pins 1 1 1 CL Output Input Input Input When the SED1565 Series chips are used in master/slave mode, the various CL terminals must be connected. This is the liquid crystal alternating current signal I/O terminal. M/S = “H”: Output M/S = “L”: Input When the SED1565 Series chip is used in master/slave mode, the various FR terminals must be connected. This is the liquid crystal display blanking control terminal. M/S = “H”: Output M/S = “L”: Input When the SED1565 Series chip is used in master/slave mode, the various DOF terminals must be connected. This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON when in master operation mode, and is used in conjunction with the FR terminal. This terminal selects the resistors for the V5 voltage level adjustment. IRS = “H”: Use the internal resistors IRS = “L”: Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal. This pin is enabled only when the master operation mode is selected. It is fixed to either “H” or “L” when the slave operation mode is selected. This is the power control terminal for the power supply circuit for liquid crystal drive. HPM = “H”: Normal mode HPM = “L”: High power mode This pin is enabled only when the master operation mode is selected. It is fixed to either “H” or “L” when the slave operation mode is selected. EPSON 1 1 1 1 1 SED1565 Series Liquid Crystal Drive Terminals Pin Name I/O Function SEG0 to SEG131 O These are the liquid crystal segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from VDD, V2, V3, and V5. COM0 to COMn O RAM DATA FR H H L L Power save H L H L — No. of Pins 132 Output Voltage Normal Display Reverse Display VDD V2 V5 V3 V2 VDD V3 V5 VDD These are the liquid crystal common drive outputs. Part No. SED1565*** SED1566*** SED1567*** SED1568*** SED1569*** COM COM 0 ~ COM 63 COM 0 ~ COM 47 COM 0 ~ COM 31 COM 0 ~ COM 53 COM 0 ~ COM 51 Part No. SED1565*** SED1566*** SED1567*** SED1568*** SED1569*** 64 48 32 54 52 Through a combination of the contents of the scan data and with the FR signal, a single level is selected from VDD, V1, V4, and V5. COMS O FR H L H L — Output Voltage V5 VDD V1 V4 VDD These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used. When in master/slave mode, the same signal is output by both master and slave. 2 Test Terminals Pin Name I/O TEST0 to 4 TEST7 to 9 TEST5, 6 I/O I Function These are terminals for IC chip testing. They are set to OPEN. These are terminals for IC chip testing. They are set to VDD. No. of Pins 12 2 Total: 288 pins for the SED1565***. 272 pins for the SED1566***. 256 pins for the SED1567***. EPSON 8–23 SED1565 Series Scan Data H H L L Power Save SED1565 Series DESCRIPTION OF FUNCTIONS through a serial data input (SI). Through selecting the P/ S terminal polarity to the “H” or “L” it is possible to select either parallel data input or serial data input as shown in Table 1. The MPU Interface Selecting the Interface Type With the SED1565 Series chips, data transfers are done through an 8-bit bi-directional data bus (D7 to D0) or P/S H: Parallel Input L: Serial Input CS1 CS1 CS1 CS2 CS2 CS2 Table 1 A0 RD A0 RD A0 — The Parallel Interface When the parallel interface has been selected (P/S = “H”), then it is possible to connect directly to either an P/S H: 6800 Series MPU Bus L: 8080 MPU Bus WR C86 D7 D6 D5~D0 WR C86 D7 D6 D5~D0 — — SI SCL (HZ) “—” indicates fixed to either “H” or to “L” 8080-system MPU or a 6800 Series MPU (as shown in Table 2) by selecting the C86 terminal to either “H” or to “L”. Table 2 CS1 CS2 CS1 CS2 CS1 CS2 A0 A0 A0 RD E RD WR R/W WR D7~D0 D7~D0 D7~D0 Moreover, data bus signals are recognized by a combination of A0, RD (E), WR (R/W) signals, as shown in Table 3. Shared A0 1 1 0 0 8–24 6800 Series R/W 1 0 1 0 Table 3 8080 Series RD WR 0 1 1 0 0 1 1 0 EPSON Function Reads the display data Writes the display data Status read Write control data (command) SED1565 Series the eighth serial clock for the processing. The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = “H”, the data is display data, and when A0 = “L” then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart. The Serial Interface When the serial interface has been selected (P/S = “L”) then when the chip is in active state (CS1 = “L” and CS2 = “H”) the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of CS1 CS2 SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 1 2 3 4 5 6 7 8 9 10 D5 D4 D3 D2 13 14 SCL 11 12 A0 Figure 1 The Chip Select The SED1565 Series chips have two chip select terminals: CS1 and CS2. The MPU interface or the serial interface is enabled only when CS1 = “L” and CS2 = “H”. When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, RD, and WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset. Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the SED1565 Series. Wait time may not be considered. And, in the SED1565 Series chips, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is conducted. This relationship is shown in Figure 2. EPSON 8–25 SED1565 Series * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. SED1565 Series read instruction. If the cycle time (tCYC) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. The Busy Flag When the busy flag is “1” it indicates that the SED1565 Series chip is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the Internal Timing MPU Writing WR DATA N N+1 N+2 N+3 Latch N+1 N BUS Holder N+2 N+3 Write Signal Reading MPU WR RD Internal Timing DATA N N n Address Preset Read Signal Column Address Preset N Bus Holder Increment N+1 N Address Set #n n Dummy Read Figure 2 8–26 n+1 EPSON N+2 n+1 Data Read #n n+2 Data Read #n+1 SED1565 Series Display Data RAM Display Data RAM The display data RAM is a RAM that stores the dot data for the display. It has a 65 (8 page x 8 bit +1) x 132 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display data transfer when multiple SED1565 series chips are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). D0 0 1 1 1 0 COM0 D1 1 0 0 0 0 COM1 D2 0 0 0 0 0 COM2 D3 0 1 1 1 0 COM3 D4 1 0 0 0 0 COM4 — — Liquid crystal display Display data RAM Figure 3 The Column Addresses As is shown in Figure 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrementation of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. Table 4 SEG SEG 131 Output SEG0 ADC “0” 0 (H) → Column Address → 83 (H) (D0) “1” 83 (H) ← Column Address ← 0 (H) The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output for SED1565 Series, COM47 output for SED1566 Series and COM31 output for the SED1567 Series when the common output mode is reversed. The display area is a 65 line area for the SED1565 Series, a 49 line are for the SED1566 and a 33 line area for the SED1567 Series from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. EPSON 8–27 SED1565 Series The Page Address Circuit As shown in Figure 6-4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page for the RAM region used only by the indicators, and only display data D0 is used. SED1565 Series 1 0 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 83 82 81 80 7F 7E 7D 7C 00 01 02 03 04 05 06 07 0 Page 2 Figure 4 8–28 EPSON 54 lines 0 Start 32 lines 0 Page 1 48 lines 1 52 lines 0 63 lines 0 0 0 Page 0 1 0 D0 D0 ADC Column Address 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 11H 12H 13H 14H 15H 16H 17H 18H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH LCD Out 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 7C 7D 7E 7F 80 81 82 83 0 When the Line common output Address mode is normal Data 07 06 05 04 03 02 01 00 Page Address D2 D1 D0 SEG127 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 D3 COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS Regardless of the display start line address, the SED1565 Series accesses 65th line, the SED1566 Series accesses 49th line and the SED1567 Series accesses 33th line and the SED1568 Series accesses 55th line, the SED1569 Series accesses 53 lines. SED1565 Series The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/ OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S = “H” and CLS = “H”. When CLS = “L” the oscillation stops, and the display clock is input through the CL terminal. Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Two-frame alternating current drive wave form (SED1565***) 64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 CL FR VDD V1 COM0 V4 V5 VDD V1 COM1 RAM DATA VDD V2 SEGn V3 V5 Figure 5 EPSON 8–29 SED1565 Series V4 V5 SED1565 Series When multiple SED1565 Series chips are used, the slave chips must be supplied the display timing signals (FR, CL, DOF) from the master chip[s]. Table 5 shows the status of the FR, CL, and DOF signals. Master (M/S = “H”) Slave (M/S = “L”) Table 5 Operating Mode The internal oscillator circuit is enabled (CLS = “H”) The internal oscillator circuit is disabled (CLS = “L”) The internal oscillator circuit is enabled (CLS = “H”) The internal oscillator circuit is disabled (CLS = “L”) FR Output Output Input Input CL Output Input Input Input DOF Output Output Input Input The Common Output Status Select Circuit In the SED1565 Series chips, the COM output scan direction can be selected by the common output status select command. (See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized. Table 6 COM Scan Direction SED1565*** SED1566*** SED1567*** SED1568*** SED1569*** Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51 Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0 Status The Liquid Crystal Driver Circuits These are a 197-channel (SED1565 Series), a 181channel (SED1566 Series) multiplexers 165-channel (SED1567 Series) and a 185-channel (SED1569 Series) that generate four voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows examples of the SEG and COM output wave form. 8–30 EPSON SED1565 Series COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 FR VDD VSS COM0 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 COM1 COM2 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 SEG0 SEG1 SEG2 COM0–SEG0 V5 V4 V3 V2 V1 V∞ –V1 –V2 –V3 –V4 –V5 COM0–SEG1 V5 V4 V3 V2 V1 V∞ –V1 –V2 –V3 –V4 –V5 SED1565 Series COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Figure 6 EPSON 8–31 SED1565 Series The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON of OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations. Table 7 The Control Details of Each Bit of the Power Control Set Command Status Item “1” “0” D2 Booster circuit control bit ON OFF D1 Voltage regulator circuit (V regulator circuit) control bit ON OFF D0 Voltage follower circuit (V/F circuit) control bit ON OFF Table 8 Reference Combinations Use Settings Step-up V V/F D2 D1 D0 circuit regulator circuit circuit Step-up External voltage voltage system input terminal VSS2 Used Only the internal power supply is 1 1 1 O O O used 2 Only the V regulator circuit and 0 1 1 X O O VOUT, VSS2 Open the V/F circuit are used 3 Only the V/F circuit is used 0 0 1 X X O V5, VSS2 Open 4 Only the external power supply is 0 0 0 X X X V1 to V5 Open used * The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–. * While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. 1 The Step-up Voltage Circuits Using the step-up voltage circuits equipped within the SED1565 Series chips it is possible to product a Quad step-up, a Triple step-up, and a Double step-up of the VDD – VSS2 voltage levels. Quad step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, and between VSS2 and VOUT, to produce a voltage level in the negative direction at the V OUT terminal that is 4 times the voltage level between VDD and VSS2. Triple step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2– and between V SS2 and VOUT , and short between CAP3– and V OUT to produce a voltage level in the negative direction at the VOUT terminal that is 3 times the voltage difference between VDD and VSS2. 8–32 Double step-up: Connect capacitor C1 between CAP1+ and CAP1–, and between VSS2 and V OUT , leave CAP2+ open, and short between CAP2–, CAP3– and V OUT to produce a voltage in the negative direction at the VOUT terminal that is twice the voltage between VDD and VSS2. The step-up voltage relationships are shown in Figure 7. EPSON SED1565 Series VSS2 + VSS2 + C1 C1 VOUT CAP1– CAP1+ + C1 CAP1– CAP2– C1 CAP3– CAP1+ + C1 CAP1– CAP2– CAP2– CAP2+ OPEN CAP2+ SED1565 Series CAP1+ CAP3– VOUT SED1565 Series + C1 VOUT SED1565 Series CAP3– C1 VSS2 + C1 C1 + CAP2+ 4 x step-up voltage circuit + 3 x step-up voltage circuit VDD = 0V VDD = 0V VSS2 = –3V VSS2 = –3V 2 x step-up voltage circuit VDD = 0V VSS2 = –5V VOUT = 3 x VSS2 = –9V VOUT = 2 x VSS2 = –10V VOUT = 4 x VSS2 = –12V 4x step-up voltage relationships 3x step-up voltage relationships 2x step-up voltage relationships Figure 7 * The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value. The step-up voltage generated at V OUT outputs the liquid crystal driver voltage V5 through the voltage regulator circuit. Because the SED1565 Series chips have an internal high-accuracy fixed voltage power supply with a 64level electronic volume function and internal resistors for the V5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. Moreover, in the SED1565 Series, three types of thermal gradients have been prepared as V REG options: (1) approximately -0.05%/°C (2) approximately -0.2%/°C, and (3) external input (supplied to the VRS terminal). (A) When the V5 Voltage Regulator Internal Resistors Are Used Through the use of the V5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V 5 voltage can be calculated using equation A-1 over the range where | V5 | < | VOUT |. EPSON 8–33 SED1565 Series The Voltage Regulator Circuit SED1565 Series Rb V5 = 1 + ⋅ VEV Ra α Rb = 1+ ⋅ 1– ⋅ VREG Ra 162 [Q V = (1 − α 162) ⋅ V ] EV (Equation A-1) REG ∴ VDD VEV (constant voltage supply + electronic volume) Internal Ra + V5 – Internal Rb Figure 8 VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9. Equipment Type (1) Internal Power Supply (2) Internal Power Supply (3) External Input Table 9 Thermal Gradient –0.05 –0.2 — α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for α depending on the electronic volume register settings. Table 10 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 8–34 Units [%/°C ] [%/°C ] — VREG –2.1 –4.9 VRS Units [V] [V] [V] Rb/Ra is the V5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V 5 voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V5 voltage regulator internal resistor ratio register. α 63 62 61 . . . 2 1 0 EPSON SED1565 Series V5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Table 11 SED1565*** SED1566*** Register Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ] D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input (1) –0.05 (2) –0.2 (3) VREG External Input 0 0 0 3.0 1.3 1.5 3.0 1.3 1.5 0 0 1 3.5 1.5 2.0 3.5 1.5 2.0 0 1 0 4.0 1.8 2.5 4.0 1.8 2.5 0 1 1 4.5 2.0 3.0 4.5 2.0 3.0 1 0 0 5.0 2.3 3.5 5.0 2.3 3.5 1 0 1 5.5 2.5 4.0 5.4 2.5 4.0 1 1 0 6.0 2.8 4.5 5.9 2.8 4.5 1 1 1 6.4 3.0 5.0 6.4 3.0 5.0 SED1567*** SED1568***/SED1569*** Register Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ] D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input –0.05 0 0 0 3.0 1.3 1.5 3 0 0 1 3.5 1.5 2.0 3.5 0 1 0 4.0 1.8 2.5 4 0 1 1 4.5 2.0 3.0 4.5 1 0 0 5.0 2.3 3.5 5 1 0 1 5.4 2.5 4.0 5.4 1 1 0 5.9 2.8 4.5 5.9 1 1 1 6.4 3.0 5.0 6.4 SED1565 Series Figs. 9, 10, 11 (for SED1565 Series), 12, 13, 14 (for SED1566 Series) and Figs. 15, 16, 17 show V5 voltage measured by values of the internal resistance ratio resistor for V5 voltage adjustment and electric volume resister for each temperature grade model, when Ta = 25 °C. EPSON 8–35 SED1565 Series –16 SED1565D0B/SED1565DBB –15 –14 111 V5 [v] –13 –12 110 –11 101 –10 100 –9 011 –8 010 –7 001 –6 000 –5 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 9: SED1565D0B/SED1565DBB (1) For Models Where the Thermal Gradient = -0.05%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. SED1565D1B –16 –15 111 –14 110 –13 101 –12 100 –11 011 –10 V5 [v] –9 010 –8 001 –7 000 –6 –5 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 10: SED1565D1B (2) For Models Where the Thermal Gradient = -0.2%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. 8–36 EPSON SED1565 Series SED1565D2B –16 111 –15 –14 110 –13 101 –12 –11 100 –10 011 V5 [v] –9 –8 010 –7 001 –6 –5 000 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 11: SED1565D2B (3) For models with External Input The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. –16 SED1566D0B/SED1566DBB –14 111 –13 110 –12 101 –11 100 –10 011 V5 [v] –9 010 –8 001 –7 000 –6 –5 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –4 –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 12: SED1566D0B/SED1566DBB (1) For Models Where the Thermal Gradient = -0.05%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. EPSON 8–37 SED1565 Series –15 SED1565 Series SED1566D1B –16 111 –15 –14 110 –13 101 –12 100 –11 011 –10 010 V5 [v] –9 –8 001 –7 000 –6 –5 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 13: SED1566D1B (2) For Models Where the Thermal Gradient = -0.2%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. SED1566D2B –16 111 –15 110 –14 –13 101 –12 100 –11 –10 011 V5 [v] –9 –8 010 –7 001 –6 000 –5 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 14: SED1566D2B (3) For models with External Input The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. 8–38 EPSON SED1565 Series –16 SED1567D0B/SED1567DBB –15 –14 111 –13 110 –12 101 –11 100 –10 011 V5 [v] –9 010 –8 001 –7 000 –6 –5 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –4 –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 15: SED1567D0B/SED1567DBB (1) For Models Where the Thermal Gradient = -0.05%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. SED1567D1B –16 111 –15 110 –14 101 –13 –12 100 011 V5 [v] –10 –9 010 –8 001 –7 000 –6 –5 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 16: SED1567D1B (2) For Models Where the Thermal Gradient = -0.2%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. EPSON 8–39 SED1565 Series –11 SED1565 Series SED1567D2B –16 111 –15 110 –14 –13 101 –12 –11 100 –10 011 V5 [v] –9 –8 010 –7 001 –6 –5 000 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 17: SED1567D2B (3) For models with External Input The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. –16 SED1568D0B/SED1568DBB 111 –15 110 –14 –13 101 –12 –11 100 –10 011 V5 [v] –9 –8 010 –7 001 –6 –5 000 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 18: SED1568D0B/SED1568DBB (1) For Models Where the Thermal Gradient = –0.05%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. 8–40 EPSON SED1565 Series –16 SED1569D0B/SED1569DBB 111 –15 110 –14 –13 101 –12 –11 100 –10 011 V5 [v] –9 –8 010 –7 001 –6 –5 000 –4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) –3 –2 –1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 19: SED1569D0B/SED1569DBB (Temperature Gradient = –0.05%/°C Model The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. Setup example: When selecting Ta = 25°C and V5 = 7 V for an SED1567 model on which Temperature gradient = –0.05%/°C. Using Figure 15 and the equation A-1, the following setup is enabled. At this time, the variable range and the notch width of the V5 voltage is, as shown Table 13, as dependent on the electronic volume. Table 12 For V5 voltage regulator Electronic Volume Register D5 D4 D3 D2 D1 D0 — — — 0 1 0 1 V5 Variable Range Notch width 0 0 1 0 Min –8.4 (63 levels) SED1565 Series Contents 1 Table 13 Typ Max –6.8 (central value) –5.1 (0 level) 51 EPSON Units [V] [mV] 8–41 SED1565 Series (B) When an External Resistance is Used (i.e., The V5 Voltage Regulator Internal Resistors Are Not Used) (1) The liquid crystal power supply voltage V5 can also be set without using the V5 voltage regulator internal resistors (IRS terminal = “L”) by adding resistors Ra’ and Rb’ between VDD and VR, and between VR and V5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V5 through commands. In the range where | V5 | < | VOUT |, the V5 voltage can be calculated using equation B-1 based on the external resistances Ra’ and Rb’. Rb' ⋅ VEV V5 = 1 + Ra' α Rb' = 1+ ⋅ 1– ⋅ VREG Ra' 162 [Q V = (1 − α 162) ⋅ V ] EV ( Equation B-1) REG ∴ VDD VEV (fixed voltage power supply + electronic volume) External resistor Ra' + V5 – External resistor Rb' Figure 20 Setup example: When selecting Ta = 25°C and V5 = – 7 V for an SED1567 Series model where the temperature gradient = –0.05%/°C. When the central value of the electron volume register is (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and VREG = –2.1 V so, according to equation B-1, α Rb' V5 = 1 + ⋅ 1− ⋅ VREG Ra' 162 31 Rb' −11V = 1 + ⋅ 1− ⋅ ( −2.1) (Equation B-2) Ra' 162 Consequently, by equations B-2 and B-3, Rb' = 3.12 Ra' Ra' = 340 kΩ Rb' = 1060 kΩ At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14. Moreover, when the value of the current running through Ra’ and Rb’ is set to 5 µA, (Equation B-3) Ra' + Rb' = 1.4 MΩ V5 Variable Range Notch width 8–42 Min –8.6 (63 levels) Table 14 Typ Max –7.0 (central value) –5.3 (0 level) 52 EPSON Units [V] [mV] SED1565 Series the electronic volume function makes it possible to control the liquid crystal power supply voltage V5 by commands to adjust the liquid crystal display brightness. In the range where | V5 | < | VOUT | the V5 voltage can be calculated by equation C-1 below based on the R1 and R2 (variable resistor) and R3 settings, where R2 can be subjected to fine adjustments (∆ R2). (C) When External Resistors are Used (i.e. The V5 Voltage Regulator Internal Resistors Are Not Used). (2) When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra’ and Rb’, to set the liquid crystal drive voltage V5. In this case, the use of R + R2 − ∆R2 V5 = 1 + 3 ⋅ VEV R1 + ∆R2 R + R2 − ∆R2 α = 1 + 3 ⋅ 1– ⋅ VREG R1 + ∆R2 162 [Q V = (1 − α 162) ⋅ V ] EV (Equation C-1) REG ∴ VDD VEV (fixed voltage supply + electronic volume) Ra' External resistor R1 + V5 ∆R2 External resistor R2 – VR Rb' External resistor R3 Figure 21 α = 31 VREG = −2.1V so, according to equation C-1, when ∆ R2 = 0 Ω, in order to make V5 = –9 V, When ∆ R2 = R2, in order to make V = –5 V, R3 31 −5V = 1 + ⋅ 1 − 162 ⋅ ( −2.1) R 1 + R2 (Equation C-3) Moreover, when the current flowing VDD and V5 is set to 5 µA, R1 + R2 + R3 = 1.4 MΩ (Equation C-4) With this, according to equation C-2, C-3 and C-4, R1 = 264 kΩ R + R2 31 −9V = 1 + 3 ⋅ 1− ⋅ ( −2.1) R1 162 R2 = 211kΩ R3 = 925kΩ (Equation C-2) At this time, the V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15. V5 Variable Range Notch width Min –8.7 (63 levels) Table 15 Typ Max –7.0 (central value) –5.3 (0 level) 53 EPSON Units [V] [mV] 8–43 SED1565 Series Setup example: When selecting Ta = 25°C and V5 = – 5 to –9 V (using R2) for an SED1567 model where the temperature gradient = –0.05%/°C. When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), SED1565 Series * When the V5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF. * The VR terminal is enabled only when the V5 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”). When the V 5 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the VR terminal is left open. * Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables, etc. to handle noise. High Power Mode The power supply circuit equipped in the SED1565 Series chips has very low power consumption (normal mode: HPM = “H”). However, for LCDs or panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to “L” (high power mode) can improve the quality of the display. We recommend that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally. The Internal Power Supply Shutdown Command Sequence The Liquid Crystal Voltage Generator Circuit The V 5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3 and V 4 to the liquid crystal drive circuit. 1/9 bias or 1/7 bias for SED1565 Series, 1/8 bias or 1/6 bias for SED1566 Series and 1/6 bias or 1/5 bias for the SED1567 Series can be selected. Sequence Details (Command, status) The sequence shown in Figure 22 is recommended for shutting down the internal power supply, first placing the power supply in power saver mode and then turning the power supply OFF. Command address D7 D6 D5 D4 D3 D2 D1 D0 Step1 Display OFF 1 0 1 0 1 1 1 0 Step2 Display all points ON 1 0 1 0 0 1 0 1 End Internal power supply OFF Figure 22 8–44 EPSON Power saver commands (compound) SED1565 Series Reference Circuit Examples Figure 22 shows reference circuit examples. ➀ When used all of the step-up circuit, voltage regulating circuit and V/F circuit (1) When the voltage regulator internal resistor is used. (Example where VSS2 = VSS, with 4x step-up) (2) When the voltage regulator internal resistor is not used. (Example where VSS2 = VSS, with 4x step-up) VDD C1 VDD VDD C2 C2 C2 C2 C2 C1 VSS C1 C1 C1 R3 R2 VDD VDD C2 V2 V3 V4 C2 V4 V5 C2 V5 (2) When the V5 voltage regulator internal resistor is used. VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR R1 VDD C2 C2 C2 VDD M/S IRS VSS External power supply SED1565 Series VDD V2 V3 IRS R3 R2 V1 C2 VDD External power supply R1 C2 V1 ➁ When the voltage regulator circuit and V/F circuit alone are used (1) When the V5 voltage regulator internal resistor is not used. VSS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR M/S VDD VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR VDD C2 V1 C2 V2 M/S V1 V2 V3 C2 V3 C2 V4 C2 V4 C2 V5 C2 V5 EPSON SED1565 Series C1 C1 VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR IRS SED1565 Series C1 VSS M/S SED1565 Series IRS SED1565 Series VDD 8–45 SED1565 Series ➂ When the V/F circuit alone is used ➃ When the built-in power is not used VSS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR VSS External power supply VDD VDD C2 IRS M/S VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR SED1565 Series IRS VDD VDD V1 V1 C2 V2 C2 V3 C2 V4 C2 V5 VDD External power supply V2 V3 V4 V5 5 When the built-in power circuit is used to drive a liquid crystal panel heavily loaded with AC or DC, it is recommended to connect an external resistor to stabilize potentials of V1, V2, V3 and V4 which are output from the built-in voltage follower. Examples of shared reference settings When V5 can vary between –8 and 12 V Item Set value Units C1 C2 1.0 to 4.7 0.01 to 1.0 µF µF VDD, V0 R4 C2 V1 V2 V3 SED1565 Series R4 M/S SED1565 Series VDD V4 R4 R4 V5 Reference set value R4: 100KΩ ~ 1MΩ It is recommended to set an optimum resistance value R4 taking the liquid crystal display and the drive waveform. Figure 23 * 1 Because the VR terminal input impedance is high, use short leads and shielded lines. * 2 C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Example of the Process by which to Determine the Settings: • Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside. • Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value. • Next turn all the power supplies ON and determine C1. 8–46 EPSON SED1565 Series When the RES input comes to the “L” level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = “L”) 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate: SED1565*** ............................................... 1/9 bias SED1566***, 1568***, 1569*** ....... 1/8 bias SED1567*** ............................................... 1/6 bias 7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = “L”) 8. Power saving clear 9. V5 voltage regulator internal resistors Ra and Rb separation (In case of SED1565D BB , SED1566D BB , SED1567DBB, SED1568DBB and SED1569DBB, internal resistors are connected while RES is “L.”) 10. Output conditions of SEG and COM terminals SEG : V2/V3, COM : V1/V4 (In case of SED1565D BB , SED1566D BB , SED1567DBB, SED1568DBB and SED1569DBB, both the SEG terminal and the COM terminal output the VDA level while RES is “L.” In case of other models, the SEG terminal outputs V2 and the COM terminal outputs V1 while RES is “L.”) 11. Read modify write OFF 12. Static indicator OFF Static indicator register : (D1, D2) = (0, 0) 13. Display start line set to first line 14. Column address set to Address 0 15. Page address set to Page 0 16. Common output status normal 17. V5 voltage regulator internal resistor ratio set mode clear 18. Electronic volume register set mode clear Electronic volume register : (D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0, 0) 19. Test mode clear On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high impedance, an overcurrent may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on SED1565DBB, SED1566DBB, SED1567DBB, SED1568DBB and SED1569DBB, it is necessary that RES is “H” when the external liquid crystal power supply is turned on. This IC has the function to discharge V5 when RES is “L,” and the external power supply short-circuits to VDD when RES is “L.” While RES is “L,” the oscillator and the display timing generator stop, and the CL, FR, FRS and DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected. The VDD level is output from the SEG and COM output terminals. This means that an internal resistor is connected between VDD and V5. When the internal liquid crystal power supply circuit is not used on other models of SED1565 series, it is necessary that RE is “L” when the external liquid crystal power supply is turned on. While RES is “L,” the oscillator works but the display timing generator stops, and the CL, FR, FRS and DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected. EPSON SED1565 Series The Reset Circuit 8–47 SED1565 Series COMMANDS The SED1565 Series chips identify the data bus signals by a combination of A0, RD (E), WR (R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H” signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/ W terminal and then the command is launched by inputting a high pulse to the E terminal. (See “10. Timing Characteristics” regarding the timing.) Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. <Explanation of Commands> Display ON/OFF This command turns the display ON and OFF. A0 0 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 0 1 1 1 1 0 Setting Display ON Display OFF When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details. Display Start Line Set This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in “The Line Address Circuit”. A0 0 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 ↓ 1 1 1 1 1 0 1 1 1 1 1 1 Line address 0 1 2 ↓ 62 63 Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display. See the page address circuit in the Function Description (page 1–20) for the detail. A0 0 8–48 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 ↓ 0 1 1 1 1 0 0 0 EPSON Page address 0 1 2 ↓ 7 8 SED1565 Series Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the function explanation in “The Column Address Circuit,” for details. A0 High bits → 0 Low bits → E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 A7 1 0 0 0 0 1 A7 A6 A5 A4 0 0 A3 A2 A1 A0 0 0 1 1 A6 0 0 0 A5 0 0 0 0 0 0 0 A4 0 0 0 A3 0 0 0 ↓ 0 0 0 0 A2 0 0 0 0 0 Column A0 address 0 0 1 1 0 2 ↓ 1 0 130 1 1 131 A1 0 0 1 Status Read E R/W RD WR 0 1 BUSY ADC ON/OFF RESET D7 BUSY D6 ADC D5 D4 D3 D2 D1 D0 ON/OFF RESET 0 0 0 0 When BUSY = 1, it indicates that either processing is occurring internally or a reset condition is in process. While the chip does not accept commands until BUSY = 0, if the cycle time can be satisfied, there is no need to check for BUSY conditions. This shows the relationship between the column address and the segment driver. 0: Reverse (column address 131-n ↔ SEG n) 1: Normal (column address n ↔ SEG n) (The ADC command switches the polarity.) ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.) This indicates that the chip is in the process of initialization either because of a RES signal or because of a reset command. 0: Operating state 1: Reset in progress Display Data Write This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by “1” after the write, the MPU can write the display data. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 Write data Display Data Read This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 Read Data EPSON 8–49 SED1565 Series A0 0 SED1565 Series ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (page 1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 0 0 0 1 Setting Normal Reverse Display Normal/Reverse This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 1 0 1 Setting RAM Data “H” LCD ON voltage (normal) RAM Data “L” LCD ON voltage (reverse) Display All Points ON/OFF This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 0 0 1 Setting Normal display mode Display all points ON When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the (20) Power Save section. LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. E R/W Select Status A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 SED1565*** SED1566*** SED1567*** SED1568*** SED1569*** 0 1 0 1 0 1 0 0 0 1 0 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias 1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias Read/Modify/Write This command is used paired with the “END” command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 0 0 * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. However, the column address set command cannot be used. 8–50 EPSON SED1565 Series • The sequence for cursor display Page address set Column address set Read/modify/write Dummy read Data read Data process Data write No Change complete? Yes End Figure 24 End This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 1 1 1 0 Return N N+1 N+2 N+3 Read/modify/write mode set ••• N+m N SED1565 Series Column address End Figure 25 Reset This command initializes the display start line, the column address, the page address, the common output mode, the V5 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/ write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in “Reset” for details. The reset operation is performed after the reset command is entered. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 0 The initialization when the power supply is applied must be done through applying a reset signal to the RES terminal. The reset command must not be used instead. EPSON 8–51 SED1565 Series Common Output Mode Select This command can select the scan direction of the COM output terminal. For details, see the function explanation in “Common Output Mode Select Circuit.” E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 0 0 * 1 SED1565*** SED1566*** Selected Mode SED1567*** SED1568*** SED1569*** * * Normal COM0→COM63 COM0→COM47 COM0→COM31 COM0→COM53 COM0→COM51 Reverse COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0 * Disabled bit Power Controller Set This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode 0 1 0 0 0 1 0 1 0 Booster circuit: OFF 1 Booster circuit: ON 0 Voltage regulator circuit: OFF 1 Voltage regulator circuit: ON 0 Voltage follower circuit: OFF 1 Voltage follower circuit: ON [Translator’s Note: the abbreviations explained within these parentheses for V and V/F have been written out in the English translation and are therefore no longer necessary.] V5 Voltage Regulator Internal Resistor Ratio Set This command sets the V5 voltage regulator internal resistor ratio. For details, see the function explanation is “The Power Supply Circuits.” E R/W A0 RD WR D7 D6 D5 D4 D3 D2 0 1 0 0 0 1 0 0 0 0 0 D1 0 0 1 ↓ 1 1 1 1 D0 0 1 0 Rb/Ra Ratio Small ↓ 0 1 Large The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. • The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 1 8–52 EPSON SED1565 Series • Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. E R/W A0 RD WR D7 D6 D5 0 1 0 * * 0 0 1 0 * * 0 0 1 0 * * 0 0 0 1 1 0 0 * * * * 1 1 D4 0 0 0 1 1 ↓ D3 0 0 0 D2 0 0 0 D1 0 1 1 D0 1 0 1 1 1 1 1 1 1 0 1 | V5 | Small ↓ Large * Inactive bit When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0) • The Electronic Volume Register Set Sequence Electronic volume mode set Electronic volume register set No Electronic volume mode clear Changes complete? Yes Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.) • Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 0 0 1 Static Indicator OFF ON EPSON 8–53 SED1565 Series Figure 26 SED1565 Series • Static Indicator Register Set This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 0 1 0 * * * * * * 0 0 1 1 D0 0 1 0 1 Indicator Display State OFF ON (blinking at approximately one second intervals) ON (blinking at approximately 0.5 second intervals) ON (constantly on) * Disabled bit • Static Indicator Register Set Sequence Static indicator mode set Static indicator register set Static indicator mode clear No Changes complete? Yes Figure 27 Power Save (Compound Command) When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption. The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered. In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the MPU is still able to access the display data RAM. Refer to figure 26 for power save off sequence. Static indicator OFF Static indicator ON Power saver (compound command) Sleep mode Standby mode Power save OFF (compound command) Display all points OFF command Static indicator ON (2 bytes command) Power save OFF (Display all points OFF command) Sleep mode cancel Standby mode cancel Figure 28 8–54 EPSON SED1565 Series • Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1 The oscillator circuit and the LCD power supply circuit are halted. 2 All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level. • Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1 The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. * When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The SED1565 series chips have a liquid crystal display blanking control terminal DOF. This terminal enters an “L” state when the power saver mode is launched. Using the output of DOF, it is possible to stop the function of an external power supply circuit. * When the master is turned on, the oscillator circuit is operable immediately after the powering on. NOP Non-OPeration Command E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 1 Test E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 * * * * * Inactive bit Note: The SED1565 Series chips maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the SED1565 Series chip. Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise. EPSON 8–55 SED1565 Series This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a “L” signal to the RES input by the reset command or by using an NOP. SED1565 Series Table 16 Table of SED1565 Series Commands Command Code D6 D5 D4 0 1 0 (1) Command Display ON/OFF A0 0 RD 1 WR 0 D7 1 (2) Display start line set 0 1 0 0 1 (3) Page address set 0 1 0 1 0 1 1 Page address (4) Column address set upper bit 0 1 0 0 0 0 1 Most significant column address Column address set lower bit Status read Display data write Display data read ADC select 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 (10) Display all points ON/OFF 0 1 0 1 0 1 0 0 1 0 0 1 (11) LCD bias set 0 1 0 1 0 1 0 0 0 1 0 1 (12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 (13) End (14) Reset (15) Common output mode select 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 * 1 1 * 0 0 * (16) Power control set 0 1 0 0 0 1 0 1 (17) V5 voltage regulator internal resistor ratio set (18) Electronic volume mode set Electronic volume register set (19) Static indicator ON/OFF Static indicator register set (20) Power saver 0 1 0 0 0 1 0 0 Operating mode Resistor ratio 0 1 0 1 0 0 0 0 0 0 1 0 * * 0 1 0 1 0 1 0 1 1 0 1 0 * * * * * * (5) (6) (7) (8) (9) Display normal/ reverse (21) NOP (22) Test 8–56 0 0 1 1 0 0 1 1 D2 1 D1 1 D0 0 1 Display start address Status 1 1 D3 1 Least significant column address 0 0 0 0 Write data Read data 0 0 0 0 0 1 0 1 Electronic volume value 1 1 0 1 EPSON 0 * 0 * 0 0 1 Mode 1 * Function LCD display ON/OFF 0: OFF, 1: ON Sets the display RAM display start line address Sets the display RAM page address Sets the most significant 4 bits of the display RAM column address. Sets the least significant 4 bits of the display RAM column address. Reads the status data Writes to the display RAM Reads from the display RAM Sets the display RAM address SEG output correspondence 0: normal, 1: reverse Sets the LCD display normal/ reverse 0: normal, 1: reverse Display all points 0: normal display 1: all points ON Sets the LCD drive voltage bias ratio SED1565*** ....... 0: 1/9, 1: 1/7 SED1566*** /SED1568*** /SED1569*** ...... 0: 1/8, 1: 1/6 SED1567*** ....... 0: 1/6, 1: 1/5 Column address increment At write: +1 At read: 0 Clear read/modify/write Internal reset Select COM output scan direction 0: normal direction, 1: reverse direction Select internal power supply operating mode Select internal resistor ratio (Rb/Ra) mode 1 * Set the V5 output voltage electronic volume register 0: OFF, 1: ON Set the flashing mode Display OFF and display all points ON compound command Command for non-operation Command for IC test. Do not use this command (Note) *: disabled data SED1565 Series COMMAND DESCRIPTION Instruction Setup: Reference (reference) (1) Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1 When the built-in power is being used immediately after turning on the power: Turn ON the VDD-VSS power keeping the RES pin = “L”. When the power is stabilized Release the reset state. (RES pin = “H”) Initialized state (Default) *1 Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 (In case of SED1565DBB, SED1566DBB, SED1567DBB, SED1568DBB and SED1569DBB) Arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms. This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting EPSON 8–57 SED1565 Series Function setup by command input (User setup) (16) Power control setting *7 SED1565 Series COMMAND DESCRIPTION Instruction Setup: Reference (reference) 2 When the built-in power is not being used immediately after turning on the power: Turn ON the VDD-VSS power keeping the RES pin = “L”. When the power is stabilized Release the reset state. (RES pin = “H”) Initialized state (Default) *1 Power saver START (multiple commands) *8 (In case of SED1565DBB, SED1566DBB, SED1567DBB, SED1568DBB and SED1569DBB) Arrange to start the power saver within 5ms after releasing the reset state. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms. Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 Power saver OFF *8 Function setup by command input (User setup) (16) Power control setting *7 Arrange to start power control setting within 5ms after turning OFF the power saver. This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting *8: The power saver ON state can either be in sleep state or stand-by state. Command description; Power saver START (multiple commands) 8–58 EPSON SED1565 Series (2) Data Display End of initialization Function setup by command input (User setup) (2) Display start line set *9 (3) Page address set *10 (4) Column address set *11 Function setup by command input (User setup) (6) Display data write *12 Function setup by command input (User setup) (1) Display ON/OFF *13 End of data display Notes: Reference items *9: Command Description; Display start line set *10: Command Description; Page address set *11: Command Description; Column address set *12: Command Description; Display data write *13: Command Description; Display ON/OFF Avoid displaying all the data at the data display start (when the display is ON) in white. (3) Power OFF *14 • In case of SED1565DBB, SED1566DBB, SED1567DBB, SED1568DBB and SED1569DBB, Optional status Function setup by command input (User setup) (20) Power save *15 Reset active (RES pin = “L”) VDD – VSS power OFF Set the time (tL) from reset active to turning off the VDD - VSS power (VDD - VSS = 1.8 V) longer than the time (tH) when the potential of V5 ~ V1 becomes below the threshold voltage (approximately 1 V) of the LCD panel. For tH, refer to the <Reference Data> of this event. When tH is too long, insert a resistor between V5 and VDD to reduce it. • In case of other models, Function setup by command input (User setup) (20) Power save *15 VDD – VSS power OFF SED1565 Series Optional status Set the time (tL) from power save to turning off the VDD - VSS power (VDD - VSS = 1.8 V) longer than the time (tH) when the potential of V5 ~ V1 becomes below the threshold voltage (approximately 1V) of the LCD panel. • tH is determined depending on the voltage regulator external resistors Ra and Rb and the time constant of V5 ~ V1 smoothing capacity C2. • When an internal resistor is used, it is recommended to insert a resistor R between VDD and V5 to reduce tH. Notes: Reference items *14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures: • After turning off the internal power supply, make sure that the potential V5 ~ V1 has become below the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS). 6. Description of Function, 6.7 Power Circuit *15: After inputting the power save command, be sure to reset the function using the RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save *16: After inputting the power save command, do not reset the function using the RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save EPSON 8–59 SED1565 Series Refresh It is recommended to turn on the refresh sequence regularly at a specified interval. Refresh sequence Reset command or NOP command Set all commands to the ready state Refreshing of DRAM Precautions on Turning off the power • In case of SED1565DBB, SED1566DBB, SED1567DBB, SED1568DBB and SED1569DBB, Observe Paragraph 1) as the basic rule. <Turning the power (VDD - VSS) off> 1) Power Save (The LCD powers (VDD - V5) are off.) → Reset input → Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of V5 ~ V1) and the driver’s discharging capacity. Power save Reset Power Off tL VDD 1.8 V RES VDD SEG Since the power (VDD-VSS) is cut off, the output comes not to be fixed. VDD COM V1 V2 V3 V4 V5 8–60 About 1 V: Below Vth of the LCD panel tH For tH, see Figure 29. EPSON SED1565 Series <Turning the power (VDD - VSS) off : When command control is not possible.> 2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. For tL , make the power (VDD - VSS) falling characteristics longer or consider any other method. tH is determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging capacity. Reset Power Off tL VDD 1.8 V RES VDD SEG Since the power (VDD-VSS) is cut off, the output comes not be fixed. VDD COM V1 V2 V3 V4 V5 About 1 V: Below Vth of the LCD panel tH For tH, see Figure 29. <Reference Data> V5 voltage falling (discharge) time (tH) after the process of operation → power save → reset. V5 voltage falling (discharge) time (tH) after the process of operation → reset. VDD-VSS(V) 1.8 SED1565 Series V5 voltage falling time (mSec) 100 2.4 50 3.0 4.0 5.0 0 0.5 1.0 C2: V1 to V5 capacity (uF) Figure 29 EPSON 8–61 SED1565 Series • In case of other models than the above <Turning the power (VDD - VSS) off> Power save (The LCD powers (VDD - VSS) are off.) -> Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C (smoothing capacity of V5 to V1) and the external resisters Ra + Rb (for V5 voltage regulation) Power save Power Off tL VDD 1.8 V SEG Since the power (VDD-VSS) is cut off, the output comes not be fixed. COM V1 V2 V3 V4 V5 About 1 V: Below Vth of the LCD panel tH tH is determined depending on the time constant of (Ra + Rb) C. 8–62 EPSON SED1565 Series ABSOLUTE MAXIMUM RATINGS Unless otherwise noted, VSS = 0 V Table 17 Parameter Power Supply Voltage Power supply voltage (2) With Triple step-up (VDD standard) With Quad step-up Power supply voltage (3) (VDD standard) Power supply voltage (4) (VDD standard) Input voltage Output voltage Operating temperature Storage temperature TCP Bare chip Symbol VDD VSS2 V5, VOUT V 1 , V2 , V3 , V 4 VIN VO TOPR TSTR VCC VDD GND VSS Conditions –0.3 to +7.0 –7.0 to +0.3 –6.0 to +0.3 –4.5 to +0.3 –18.0 to +0.3 V5 to +0.3 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –40 to +85 –55 to +100 –55 to +125 Unit V V V V V V °C °C VDD VSS2, V1 to V4 V5, VOUT System (MPU) side SED1565 Series chip side Notes and Cautions 1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well. EPSON 8–63 SED1565 Series Figure 30 SED1565 Series DC CHARACTERISTICS Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = –40 to 85°C Table 18 Item Symbol Operating RecomVDD Voltage (1) mended Voltage Possible Operating Voltage Operating RecomVSS2 Voltage (2) mended Voltage Possible VSS2 Operating Voltage Operating Possible V5 Voltage (3) Operating Voltage Possible V1, V2 Operating Voltage Possible V3, V4 Operating Voltage High-level Input VIHC Voltage Low-level Input VILC Voltage High-level Output VOHC Voltage Low-level Output VOLC Voltage Input leakage ILI current Output leakage ILO current Liquid Crystal Driver RON ON Resistance Static Consumption ISSQ Current Output Leakage I5Q Current Input Terminal CIN Capacitance Oscillator Internal fOSC Frequency Oscillator External fCL Input Internal fOSC Oscillator External fCL Input 8–64 Min. 2.7 Rating Typ. — Max. 3.3 V Applicable Pin VDD*1 1.8 — 5.5 V VDD*1 (Relative to VDD) –3.3 — –2.7 V VSS2 (Relative to VDD) –6.0 — –1.8 V VSS2 (Relative to VDD) –16.0 — –4.5 V V5 *2 (Relative to VDD) 0.4 × V5 — VDD V V1, V2 (Relative to VDD) V5 — 0.6 × V5 V V3, V4 0.8 × VDD — VDD V *3 VSS — 0.2 × VDD V *3 0.8 × VDD — VDD V *4 IOL = 0.5 mA VSS — 0.2 × VDD V *4 VIN = VDD or VSS –1.0 — 1.0 µA *5 –3.0 — 3.0 µA *6 Ta = 25°C V5 = –14.0 V (Relative To VDD) V5 = –8.0 V — — — 2.0 3.2 0.01 3.5 5.4 5 KΩ KΩ µA SEGn COMn *7 VSS, VSS2 V5 = –18.0 V (Relative To VDD) Ta = 25°C f = 1 MHz — 0.01 15 µA V5 — 5.0 8.0 pF Ta = 25°C 18 22 26 kHz *8 18 22 26 kHz CL 27 33 39 kHz *8 14 17 20 kHz CL Condition IOH = –0.5 mA SED1565 **/1567 ** * * Ta = 25°C SED1566 **/1568 **/ * 1569* ** * EPSON Units SED1565 Series Table 19 Input voltage Symbol VSS2 Internal Power VSS2 Supply Step-up VOUT output voltage Circuit Voltage regulator VOUT Circuit Operating Voltage V5 Voltage Follower Circuit Operating Voltage Base Voltage VREG0 VREG1 V Applicable Pin VSS2 –1.8 V VSS2 — — V VOUT –18.0 — –6.0 V VOUT (Relative to VDD) –16.0 — –4.5 V V5 *9 Ta = 25°C –0.05%/°C (Relative to VDD) –0.2%/°C –2.04 –4.65 –2.10 –4.9 –2.16 –5.15 V V *10 *10 Condition Min. –6.0 Rating Typ. — Max. –1.8 With Triple (Relative To VDD) With Quad (Relative To VDD) (Relative to VDD) –4.5 — –18.0 (Relative to VDD) Units SED1565 Series Item EPSON 8–65 SED1565 Series • Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used. Table 20 Display Pattern OFF Item SED1565 ** * Symbol Condition IDD (1) VDD = 5.0 V, V5 – VDD = –11.0 V VDD = 3.0 V, V5 – VDD = –11.0 V VDD = 3.0 V, V5 – VDD = –11.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V SED1566 ** * SED1567 ** * SED1568 **/ * SED1569 ** * Ta = 25°C Rating Units Notes Min. Typ. Max. — 18 30 µA *11 — 16 27 — 13 22 — 11 19 — 9 15 — 8 13 — 7 12 — 12 20 — 10 17 Table 21 Display Pattern Checker Item SED1565 ** * Symbol Condition IDD (1) VDD = 5.0 V, V5 – VDD = –11.0 V VDD = 3.0 V, V5 – VDD = –11.0 V VDD = 3.0 V, V5 – VDD = –11.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V SED1566 ** * SED1567 ** * SED1568 **/ * SED1569 ** * Ta = 25°C Rating Units Notes Min. Typ. Max. — 23 38 µA *11 — 21 35 — 17 29 — 14 24 — 12 20 — 11 18 — 10 17 — 15 25 — 13 22 • Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON Table 22 Display Pattern OFF Ta = 25°C Item SED1565 ** * SED1566 ** * SED1567 ** * SED1568 **/ * SED1569 ** * 8–66 Symbol Condition IDD (2) VDD = 5.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 3.0 V, Quad step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Quad step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode EPSON Rating Units Notes Min. Typ. Max. — 67 112 µA *12 — 114 190 — 81 135 — 138 230 — 35 59 — 64 107 — 43 72 — 84 140 — 72 121 — 128 214 — 26 44 — 60 100 — 29 49 — 73 122 — 37 62 — 67 112 — 46 77 — 87 145 SED1565 Series Table 23 Display Pattern Checker Item SED1565 ** * SED1566 ** * SED1567*** SED1568***/ SED1569 ** * Symbol Condition IDD (2) VDD = 5.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 3.0 V, Quad step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Quad step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode Ta = 25°C Rating Units Notes Min. Typ. Max. — 81 135 µA *12 — 127 212 — 96 160 — 153 255 — 41 69 — 71 119 — 51 85 — 92 154 — 85 142 — 142 237 — 32 53 — 62 103 — 44 73 — 89 148 — 44 74 — 74 127 — 54 90 — 95 159 • Consumption Current at Time of Power Saver Mode, VSS = 0 V, VDD = 3.0 V ± 10% Item Sleep mode Standby Mode Sleep mode Standby Mode Sleep mode Standby Mode Sleep mode SED1565*** SED1565*** SED1566*** SED1566*** SED1567*** SED1567*** SED1568***/ SED1569*** Standby Mode SED1568***/ SED1569*** TBD: To Be Determined Symbol Condition IDDS1 IDDS2 IDDS1 IDDS2 IDDS1 IDDS2 IDDS1 — — — — — — — IDDS2 — EPSON Ta = 25°C Rating Units Notes Min. Typ. Max. 0.01 5 µA 4 8 µA 0.01 5 µA 4 8 µA 0.01 5 µA 3 6 µA 0.01 5 µA 4 8 µA 8–67 SED1565 Series Table 24 SED1565 Series Reference Data 1 • Dynamic Consumption Current (1) During LCD Display Using an External Power Supply IDD (1) (ISS + I5) [µA] 40 Conditions: Internal power supply OFF External power supply in use SED1565/SED1566 (–11.0V): V5 – VDD = –11.0 V SED1566 (–8.0V)/SED1567: V5 – VDD = –8.0 V Display pattern: OFF Ta = 25°C 30 20 SED1565 SED1566 (–11.0V) SED1568/SED1569 (–8.0V) SED1566 (–8.0V) 10 SED1567 Note: *11 0 0 2 4 VDD [V] 6 8 Figure 31 IDD (1) (ISS + I5) [µA] 40 Conditions: Internal power supply OFF External power supply in use SED1565/SED1566 (–11.0V): V5 – VDD = –11.0 V SED1566 (–8.0V)/SED1567: V5 – VDD = –8.0 V Display pattern: Checker Ta = 25°C 30 SED1565 20 SED1566 (–11.0V) SED1568/SED1569 (–8.0V) SED1566 (–8.0V) SED1567 10 Note: *11 0 0 2 4 VDD [V] 6 8 Figure 32 8–68 EPSON SED1565 Series Reference Data 2 • Dynamic Consumption Current (2) During LCD display using the internal power supply Conditions: Internal power supply ON SED1565/SED1566 (×4, –11.0V): 4× step-up voltage: V5 – VDD = –11.0 V SED1566 (×3, –8.0V)/SED1567: 3× step-up voltage: V5 – VDD = –8.0 V Normal mode Display pattern: OFF SED1565 Ta = 25°C SED1566 (×4, –11.0V) SED1568/SED1569 (×3, –8.0V) SED1568/SED1569 (×2, –8.0V) SED1566 (×3, –8.0V) SED1567 140 120 IDD (2) [µA] 100 80 60 40 20 0 0 Note: *12 2 4 VDD [V] 6 8 Conditions: Internal power supply ON SED1565/SED1566 (×4, –11.0V): 4× step-up voltage: V5 – VDD = –11.0 V SED1566 (×3, –8.0V)/SED1567: 3× step-up voltage: V5 – VDD = –8.0 V Normal mode SED1565 Display pattern: Checker SED1566 (×4, –11.0V) Ta = 25°C SED1568/SED1569 (×3, –8.0V) SED1568/SED1569 (×2, –8.0V) SED1566 (×3, –8.0V) SED1567 120 IDD (2) [µA] 100 80 60 40 20 0 0 Note: *12 2 4 VDD [V] 6 8 Figure 34 EPSON 8–69 SED1565 Series Figure 33 SED1565 Series Reference Data 3 • Dynamic Consumption Current (3) During access 10 This figure indicates the consumption current while the checker pattern is constantly written through fCYC. If there is no access, then only (1) remains. Conditions: Internal power supply OFF, external power supply used SED1565: VDD – VSS = 3.0 V, V5=–11.0 V SED1566/SED1567: VDD – VSS = 3.0 V, V5=–8.0 V Ta = 25°C IDD(3)[mA] 1 0.1 SED1565 SED1566 SED1567 SED1568/SED1569 0.01 0.001 0.01 0.1 1 10 fCYC[MHz] Figure 35 Reference Data 4 • Operating voltage range of VSS and V5 systems –20 SED1565 Series Note: *2 –16 V5-VDD[V] –15 Operating range –10 –7.2 –5 –4.5 1.8 0 0 3.0 2 5.5 4 6 VDD[V] Figure 36 8–70 EPSON 8 SED1565 Series • The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate Frequency fFR Table 25 SED1565*** Item When the internal oscillator circuit is used When the internal oscillator circuit is not used SED1566*** When the internal oscillator circuit is used When the internal oscillator circuit is not used SED1567*** When the internal oscillator circuit is used When the internal oscillator circuit is not used SED1568*** When the internal oscillator circuit is used When the internal oscillator circuit is not used SED1569*** When the internal oscillator circuit is used When the internal oscillator circuit is not used fCL fFR fOSC ____ 4 External input (fCL) fOSC _____ 4 × 65 fCL ____ 260 f OSC _____ fOSC ____ 8 External input (fCL) 8 × 49 fCL ____ fOSC ____ 8 External input (fCL) 196 fOSC _____ 8 × 33 fCL ____ fOSC ____ 8 External input (fCL) 264 fOSC _____ 8 × 55 fCL ____ fOSC ____ 8 External input (fCL) 220 f OSC _____ 8 × 53 fCL ____ 212 References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The operating voltage range for the VDD system and the V5 system is as shown in Figure 33. This applies when the external power supply is being used. *3 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S, DOF, RES, IRS, and HPM terminals. *4 The D0 to D7, FR, FRS, DOF, and CL terminals. *5 The A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS, and HPM terminals. *6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF terminals are in a high impedance state. *7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage (3) range. RON = 0.1 V/∆ I (Where ∆ I is the current that flows when 0.1 V is applied while the power supply is ON.) *8 See Table 9-7 for the relationship between the oscillator frequency and the frame rate frequency. *9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the SED1565 Series chips, the temperature range can come in three types as VREG options: (1) approximately –0.05%/°C, (2) – 0.2%/°C, and (3) external input. *11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. The SED1565 is 1/9 biased, SED1566 is 1/8 biased and SED1567 is 1/6 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU. *12 It is the value on a model having the VREG option temperature gradient is –0.05%/°C when the V5 voltage regulator internal resistor is used. EPSON 8–71 SED1565 Series (fFR is the liquid crystal alternating current period, and not the FR signal period.) SED1565 Series TIMING CHARACTERISTICS System Bus Read/Write Characteristics 1 (For the 8080 Series MPU) A0 tAW8 tAH8 CS1 (CS2="1") tCYC8 tCCLR, tCCLW WR, RD tCCHR, tCCHW tDS8 tDS8 D0 to D7 (Write) tACC8 tOH8 D0 to D7 (Read) Figure 37 Table 26 Item Signal Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Address hold time RD access time Output disable time A0 8–72 A0 WR RD WR RD D0 to D7 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 EPSON (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 0 — ns 0 — ns 166 — ns 30 — ns 70 — ns 30 — ns 30 — ns 30 — ns 10 — ns CL = 100 pF — 70 ns 5 50 ns SED1565 Series Table 27 Item Signal Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Address hold time RD access time Output disable time A0 A0 WR RD WR RD D0 to D7 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 0 — ns 0 — ns 300 — ns 60 — ns 120 — ns 60 — ns 60 — ns 40 — ns 15 — ns CL = 100 pF — 140 ns 10 100 ns Table 28 Signal Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Address hold time RD access time Output disable time A0 A0 WR RD WR RD D0 to D7 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≤ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≤ (tCYC8 – tCCLR – tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and WR and RD being at the “L” level. EPSON 8–73 SED1565 Series Item (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 0 — ns 0 — ns 1000 — ns 120 — ns 240 — ns 120 — ns 120 — ns 80 — ns 30 — ns CL = 100 pF — 280 ns 10 200 ns SED1565 Series System Bus Read/Write Characteristics 2 (6800 Series MPU) A0 R/W tAW6 tAH6 CS1 (CS2="1") tCYC6 tEWHR, tEWHW E tEWLR, tEWLW tDS6 tDH6 D0 to D7 (Write) tACC6 tOH6 D0 to D7 (Read) Figure 38 Table 29 Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse time Enable L pulse time 8–74 Signal A0 A0 D0 to D7 Read Write Read Write E E Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW EPSON (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 0 — ns 0 — ns 166 — ns 30 — ns 10 — ns CL = 100 pF — 70 ns 10 50 ns 70 — ns 30 — ns 30 — ns 30 — ns SED1565 Series Table 30 Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse time Enable L pulse time Signal A0 A0 D0 to D7 Read Write Read Write E E Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 0 — ns 0 — ns 300 — ns 40 — ns 15 — ns CL = 100 pF — 140 ns 10 100 ns 120 — ns 60 — ns 60 — ns 60 — ns Table 31 Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse time Enable L pulse time Signal A0 A0 D0 to D7 Read Write Read Write E E Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≤ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≤ (tCYC6 – tEWLR – tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E. EPSON 8–75 SED1565 Series Item (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 0 — ns 0 — ns 1000 — ns 80 — ns 30 — ns CL = 100 pF — 280 ns 10 200 ns 240 — ns 120 — ns 120 — ns 120 — ns SED1565 Series The Serial Interface tCSS CS1 (CS2="1") tCSH tSAS tSAH A0 tSCYC tSLW SCL tSHW tf tr tSDS tSDH SI Figure 39 Table 32 Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time 8–76 Signal SCL A0 SI CS Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH EPSON (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 200 — ns 75 — ns 75 — ns 50 — ns 100 — ns 50 — ns 50 — ns 100 — ns 100 — ns SED1565 Series Table 33 Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal SCL A0 SI CS Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 250 — ns 100 — ns 100 — ns 150 — ns 150 — ns 100 — ns 100 — ns 150 — ns 150 — ns Table 34 Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal SCL A0 SI CS Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C ) Rating Condition Units Min Max 400 — ns 150 — ns 150 — ns 250 — ns 250 — ns 150 — ns 150 — ns 250 — ns 250 — ns SED1565 Series *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. EPSON 8–77 SED1565 Series Display Control Output Timing CL (OUT) tDFR FR Figure 40 Table 35 Item FR delay time Signal Symbol FR tDFR (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C) Rating Condition Units Min Typ Max CL = 50 pF — 10 40 ns Table 36 Item FR delay time Signal Symbol FR tDFR (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C) Rating Condition Units Min Typ Max CL = 50 pF — 20 80 ns Table 37 Item FR delay time Signal Symbol FR tDFR (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C) Rating Condition Units Min Typ Max CL = 50 pF — 50 200 ns *1 Valid only when the master mode is selected. *2 All timing is based on 20% and 80% of VDD. 8–78 EPSON SED1565 Series Reset Timing tRW RES tR Internal status During reset Reset complete Figure 41 Table 38 Item Reset time Reset “L” pulse width Signal Symbol RES tR tRW (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C) Rating Condition Units Min Typ Max — — 0.5 µs 0.5 — — µs Table 39 Item Reset time Reset “L” pulse width Signal Symbol RES tR tRW (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C) Rating Condition Units Min Typ Max — — 1 µs 1 — — µs Item Reset time Reset “L” pulse width Signal Symbol tR RES tRW (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C) Rating Condition Units Min Typ Max — — 1.5 µs 1.5 — — µs *1 All timing is specified with 20% and 80% of VDD as the standard. EPSON 8–79 SED1565 Series Table 40 SED1565 Series THE MPU INTERFACE (REFERENCE EXAMPLES) The SED1565 Series can be connected to either 80 × 86 Series MPUs or to 68000 Series MPUs. Moreover, using the serial interface it is possible to operate the SED1565 series chips with fewer signal lines. The display area can be enlarged by using multiple SED1565 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs VDD VDD A0 MPU A1 to A7 IORQ D0 to D7 RD WR RES GND Decoder RESET A0 C86 CS1 CS2 SED1565 Series VCC D0 to D7 RD WR RES VSS P/S VSS Figure 42-1 (2) 6800 Series MPUs VDD VDD MPU A0 A1 to A15 VMA D0 to D7 E R/W RES GND Decoder RESET A0 C86 CS1 CS2 SED1565 Series VCC D0 to D7 E R/W RES VSS P/S VSS Figure 42-2 (3) Using the Serial Interface VDD or VSS VDD A0 MPU A1 to A7 Decoder Port 1 Port 2 RES GND RESET A0 C86 CS1 CS2 SED1565 Series VCC SI SCL RES VSS P/S VSS Figure 42-3 8–80 EPSON SED1565 Series CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) The liquid crystal display area can be enlarged with ease through the use of multiple SED1565 Series chips. Use a same equipment type. (1) SED1565 (master) ↔ SED1565 (slave) VDD FR CL CL DOF DOF Output Input VSS Figure 43 SED1565 Series SED1565 Series Master FR SED1565 Series Slave M/S M/S EPSON 8–81 SED1565 Series CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) The liquid crystal display area can be enlarged with ease through the use of multiple SED1565 Series chips. Use a same equipment type, in the composition of these chips. (1) Single-chip Structure 132 x 65 Dots COM SEG COM SED1565 Series Master Figure 44-1 (2) Double-chip Structure, #1 264 x 65 Dots COM SEG SEG SED1565 Series Master SED1565 Series Slave Figure 44-2 8–82 EPSON COM SED1565 Series A SAMPLE TCP PIN ASSIGNMENT SED1565T0B TCP Pin Layout Note: The following does not specify dimensions of the TCP pins. An example FR FR FRS CL DOF COM S CS1 COM 63 CS2 RES A0 • WR,R/W RD, E D0 • D1 • D2 D3 • • COM 33 D5 D6, SCL D7, SI COM 32 VSS VSS2 VOUT CAP3CAP1+ CAP1CAP2- SEG 131 SEG 130 • • • • • CAP2+ VRS VDD SEG 1 V1 SEG 0 V2 COM S SED1565 Series VDD CHIP TOP VIEW D4 V3 COM 0 V4 V5 • VR VDD • M/S CLS C86 P/S HPM IRS • • • COM 30 COM 31 EPSON 8–83 8–84 EPSON (Mold, marking area) (Mold, marking area) Section A Output terminal pattern shape Section B Test pat detailed view (Mold, marking area) Specifications • Base: U-rexS, 75µm • Copper foil: Electrolytic copper foil, 25µm • Sn plating • Product pitch: 41P (19.0mm) • Solder resist positional tolerance: ±0.3 (Mold, marking area) Section A Section A SED1565 Series EXTERNAL VIEW OF TCP PINS SED1565 Series NOTICE Please be advised on the following points in the use of this development manual. 1. This manual is subject to change without previous notice. 2. This manual does not guarantee or furnish the industrial property right nor its execution. Application examples in the manual are intended to ensure your better understanding of the product. Thus, the manufacturer shall not be liable for any trouble arising in your circuits from using such application example. Numerical values provided in the property table of this manual are represented with their magnitude on the numerical line. 3. No part of this manual may not be reproduced, copied or used for commercial purposes without a written permission from the manufacturer. SED1565 Series In handling of semiconductor devices, your attention is required to the following points. [Precautions on Light] Property of semiconductor devices may be affected when they are exposed to light, possibly resulting in malfunctioning of the ICs. To prevent such malfunctioning of the ICs mounted on the boards or products, make sure that: (1) Your design and mounting layout done are so that the IC is not exposed to light in actual use. (2) The IC is protected from light in the inspection process. (3) The IC is protected from light in its front, rear and side faces. EPSON 8–85