SITRONIX ST7565R

ST
Sitronix
ST7565R
65 x 132 Dot Matrix LCD Controller/Driver
Features
Directly display RAM data through Display Data RAM.
RAM capacity : 65 x 132 = 8580 bits
Display duty selectable by select pin
1/65 duty : 65 common x 132 segment
1/49 duty : 49 common x 132 segment
1/33 duty : 33 common x 132 segment
1/55 duty : 55 common x 132 segment
1/53 duty : 53 common x 132 segment
High-speed 8-bit MPU interface:
ST7565R can be connected directly to both the 80x86
series MPUs and the 6800 series MPUs.
Serial interface (SPI-4) is also supported.
Abundant command functions
Display data Read/Write, display ON/OFF, Normal/
Reverse display mode, page address set, display start
line set, column address set, status read, display all
points ON/OFF, LCD bias set, electronic volume,
read/modify/write, segment driver direction selects,
power saver, common output status select, V0 voltage
regulation internal resistor ratio set.
Embedded analog power supply circuits for Liquid
Crystal driving: Booster, Regulator and Follower.
Embedded Booster circuit:
2X,3X,4X,5X and 6X boost ratios are supported.
Independent input (VDD2) for boost reference voltage.
High-accuracy Regulator circuit:
Build-in Electronic volume function for the contrast
control. Thermal gradient = –0.05%/°C.
Embedded voltage Follower circuit for LCD driving.
Embedded R-C oscillator circuit.
The external clock is also supported.
Extremely low power consumption: 60uA, bare dice
(using the internal power). Settings:
VDD – VSS = VDD2 – VSS =3.0 V, Booster Ratio=4,
V0 – VSS = 11.0 V. Display OFF and the normal mode is
selected.
Logic power supply : VDD – VSS = 2.4V to 3.3 V
Analog Power (Boost reference voltage):
VDD2 – VSS = 2.4V to 3.3V
Booster maximum voltage limited
VOUT= 13.5V
Liquid crystal drive power supply:
V0 – VSS = 3.0V to 12.0 V
Wide range of operating temperatures: –30 to 85°C
Package type: COG only.
The chip is not designed to resist the light or to resist
the radiation.
Support LCD Module Size up to 2"
General Description
The ST7565R is a single-chip dot matrix LCD driver that can
be connected directly to a microprocessor bus. 8-bit parallel
or 4-line SPI display data sent from the microprocessor is
stored in the internal display data RAM and the chip
generates a LCD drive signal independent of the
microprocessor. Because the chips in the ST7565R contain
65x132 bits of display data RAM and there is a 1-to-1
correspondence between the LCD panel pixels and the
internal RAM bits, these chips enable displays with a high
degree of freedom.
The ST7565R chips contain 65 common output circuits and
PART NO.
ST7565R
Ver 1.7c
132 segment output circuits, so that a single chip can drive a
65x132 dot display (capable of displaying 8 columns x4 rows
of a 16x16 dot kanji font).
The chips are able to minimize power consumption because
no external operating clock is necessary for the display data
RAM read/write operation. Furthermore, because each chip
is equipped internally with a low-power LCD driver power
supply, resistors for LCD driver power voltage adjustment
and a display clock CR oscillator circuit, the ST7565R can be
used to create the lowest power display system with the
fewest components for high-performance portable devices.
VRS temperature gradient
-0.05%/°C
1/72
VRS range
2.1V ±0.03V
2009/09/14
ST7565R
ST7565R Pad Arrangement (COG)
Chip Size:
Bump Pitch:
Bump Size:
5900µm x 1000µm
34µm(Min.)
PAD No. 001～067
PAD No. 068～073
PAD No. 074～084
PAD No. 085～282
42µm x 54µm
56µm x 54µm
42µm x 54µm
17µm x 118µm
Bump Height:
15µm
Chip Thickness: 480µm
Recommend panel size is small than 1.8” (A.A.).
Ver 1.7c
2/72
2009/09/14
ST7565R
Pad Center Coordinates (1/65 Duty)
Units: µm
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
TEST[6]
FR
CL
DOF
VSS
CS1B
CS2
VDD
RST
A0
VSS
/WR(R/W)
/RD(E)
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VDD2
VDD2
VSS
VSS
VSS
VSS
VOUT
VOUT
CAP5P
CAP5P
CAP1N
CAP1N
CAP3P
CAP3P
CAP1N
CAP1N
CAP1P
CAP1P
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VSS
2575
2515
2455
2395
2335
2275
2215
2155
2095
2035
1975
1915
1855
1795
1735
1675
1615
1555
1495
1435
1375
1315
1255
1195
1135
1075
1015
955
895
821
761
701
641
581
521
461
401
341
281
221
161
101
41
-19
-79
-139
-199
-273
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
VSS
VRS
VRS
VDD2
VDD
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VR
VR
VDD
VDD2
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
TEST[7]
CLS
C86
PSB
HPMB
IRS
SEL1
SEL2
SEL3
VSS
COM[31]
COM[30]
COM[29]
COM[28]
COM[27]
COM[26]
COM[25]
COM[24]
COM[23]
COM[22]
COM[21]
COM[20]
-333
-408
-468
-542
-602
-676
-736
-796
-856
-916
-976
-1036
-1096
-1156
-1216
-1276
-1336
-1410
-1470
-1537
-1611
-1685
-1759
-1833
-1907
-1974
-2034
-2094
-2154
-2214
-2274
-2334
-2394
-2454
-2514
-2574
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
373
339
305
271
237
203
169
135
101
67
33
-1
Ver 1.7c
3/72
2009/09/14
ST7565R
PAD No.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Ver 1.7c
PIN Name
COM[19]
COM[18]
COM[17]
COM[16]
COM[15]
COM[14]
COM[13]
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COM[0]
COMS2
SEG[0]
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
X
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2573
-2539
-2505
-2471
-2437
-2403
-2369
-2335
-2301
-2267
-2227
-2193
-2159
-2125
-2091
-2057
-2023
-1989
-1955
-1921
-1887
-1853
-1819
-1785
-1751
-1717
-1683
-1649
-1615
-1581
-1547
-1513
-1479
-1445
-1411
-1377
-1343
-1309
-1275
-1241
-1207
Y
-35
-69
-103
-137
-171
-205
-239
-273
-307
-341
-375
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
4/72
PIN Name
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
X
-1173
-1139
-1105
-1071
-1037
-1003
-969
-935
-901
-867
-833
-799
-765
-731
-697
-663
-629
-595
-561
-527
-493
-459
-425
-391
-357
-323
-289
-255
-221
-187
-153
-119
-85
-51
-17
17
51
85
119
153
187
221
255
289
323
357
391
425
459
493
527
561
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
2009/09/14
ST7565R
PAD No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
Ver 1.7c
PIN Name
SEG[83]
SEG[84]
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
SEG[98]
SEG[99]
SEG[100]
SEG[101]
SEG[102]
SEG[103]
SEG[104]
SEG[105]
SEG[106]
SEG[107]
SEG[108]
SEG[109]
SEG[110]
SEG[111]
SEG[112]
SEG[113]
SEG[114]
SEG[115]
SEG[116]
SEG[117]
SEG[118]
SEG[119]
SEG[120]
SEG[121]
SEG[122]
SEG[123]
SEG[124]
SEG[125]
SEG[126]
SEG[127]
X
595
629
663
697
731
765
799
833
867
901
935
969
1003
1037
1071
1105
1139
1173
1207
1241
1275
1309
1343
1377
1411
1445
1479
1513
1547
1581
1615
1649
1683
1717
1751
1785
1819
1853
1887
1921
1955
1989
2023
2057
2091
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
5/72
PIN Name
SEG[128]
SEG[129]
SEG[130]
SEG[131]
COM[32]
COM[33]
COM[34]
COM[35]
COM[36]
COM[37]
COM[38]
COM[39]
COM[40]
COM[41]
COM[42]
COM[43]
COM[44]
COM[45]
COM[46]
COM[47]
COM[48]
COM[49]
COM[50]
COM[51]
COM[52]
COM[53]
COM[54]
COM[55]
COM[56]
COM[57]
COM[58]
COM[59]
COM[60]
COM[61]
COM[62]
COM[63]
COMS1
X
2125
2159
2193
2227
2267
2301
2335
2369
2403
2437
2471
2505
2539
2573
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-375
-341
-307
-273
-239
-205
-171
-137
-103
-69
-35
-1
33
67
101
135
169
203
237
271
305
339
373
2009/09/14
ST7565R
Pad Center Coordinates (1/49 Duty)
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Ver 1.7c
PIN Name
TEST[6]
FR
CL
DOF
VSS
CS1B
CS2
VDD
RST
A0
VSS
/WR(R/W)
/RD(E)
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VDD2
VDD2
VSS
VSS
VSS
VSS
VOUT
VOUT
CAP5P
CAP5P
CAP1N
CAP1N
CAP3P
CAP3P
CAP1N
CAP1N
CAP1P
CAP1P
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VSS
VSS
X
2575
2515
2455
2395
2335
2275
2215
2155
2095
2035
1975
1915
1855
1795
1735
1675
1615
1555
1495
1435
1375
1315
1255
1195
1135
1075
1015
955
895
821
761
701
641
581
521
461
401
341
281
221
161
101
41
-19
-79
-139
-199
-273
-333
Y
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
Units: µm
PAD No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
6/72
PIN Name
VRS
VRS
VDD2
VDD
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VR
VR
VDD
VDD2
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
TEST[7]
CLS
C86
PSB
HPMB
IRS
SEL1
SEL2
SEL3
VSS
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
COM[23]
COM[22]
COM[21]
COM[20]
COM[19]
COM[18]
X
-408
-468
-542
-602
-676
-736
-796
-856
-916
-976
-1036
-1096
-1156
-1216
-1276
-1336
-1410
-1470
-1537
-1611
-1685
-1759
-1833
-1907
-1974
-2034
-2094
-2154
-2214
-2274
-2334
-2394
-2454
-2514
-2574
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
Y
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
373
339
305
271
237
203
169
135
101
67
33
-1
-35
-69
2009/09/14
ST7565R
PAD No.
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Ver 1.7c
PIN Name
COM[17]
COM[16]
COM[15]
COM[14]
COM[13]
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COM[0]
COMS2
SEG[0]
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
X
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2573
-2539
-2505
-2471
-2437
-2403
-2369
-2335
-2301
-2267
-2227
-2193
-2159
-2125
-2091
-2057
-2023
-1989
-1955
-1921
-1887
-1853
-1819
-1785
-1751
-1717
-1683
-1649
-1615
-1581
-1547
-1513
-1479
-1445
-1411
-1377
-1343
-1309
-1275
-1241
-1207
-1173
-1139
Y
-103
-137
-171
-205
-239
-273
-307
-341
-375
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
7/72
PIN Name
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
X
-1105
-1071
-1037
-1003
-969
-935
-901
-867
-833
-799
-765
-731
-697
-663
-629
-595
-561
-527
-493
-459
-425
-391
-357
-323
-289
-255
-221
-187
-153
-119
-85
-51
-17
17
51
85
119
153
187
221
255
289
323
357
391
425
459
493
527
561
595
629
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
2009/09/14
ST7565R
PAD No.
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
Ver 1.7c
PIN Name
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
SEG[98]
SEG[99]
SEG[100]
SEG[101]
SEG[102]
SEG[103]
SEG[104]
SEG[105]
SEG[106]
SEG[107]
SEG[108]
SEG[109]
SEG[110]
SEG[111]
SEG[112]
SEG[113]
SEG[114]
SEG[115]
SEG[116]
SEG[117]
SEG[118]
SEG[119]
SEG[120]
SEG[121]
SEG[122]
SEG[123]
SEG[124]
SEG[125]
SEG[126]
SEG[127]
X
663
697
731
765
799
833
867
901
935
969
1003
1037
1071
1105
1139
1173
1207
1241
1275
1309
1343
1377
1411
1445
1479
1513
1547
1581
1615
1649
1683
1717
1751
1785
1819
1853
1887
1921
1955
1989
2023
2057
2091
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
8/72
PIN Name
SEG[128]
SEG[129]
SEG[130]
SEG[131]
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
COM[24]
COM[25]
COM[26]
COM[27]
COM[28]
COM[29]
COM[30]
COM[31]
COM[32]
COM[33]
COM[34]
COM[35]
COM[36]
COM[37]
COM[38]
COM[39]
COM[40]
COM[41]
COM[42]
COM[43]
COM[44]
COM[45]
COM[46]
COM[47]
COMS1
X
2125
2159
2193
2227
2267
2301
2335
2369
2403
2437
2471
2505
2539
2573
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-375
-341
-307
-273
-239
-205
-171
-137
-103
-69
-35
-1
33
67
101
135
169
203
237
271
305
339
373
2009/09/14
ST7565R
Pad Center Coordinates (1/33 Duty)
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Ver 1.7c
PIN Name
TEST[6]
FR
CL
DOF
VSS
CS1B
CS2
VDD
RST
A0
VSS
/WR(R/W)
/RD(E)
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VDD2
VDD2
VSS
VSS
VSS
VSS
VOUT
VOUT
CAP5P
CAP5P
CAP1N
CAP1N
CAP3P
CAP3P
CAP1N
CAP1N
CAP1P
CAP1P
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VSS
VSS
X
2575
2515
2455
2395
2335
2275
2215
2155
2095
2035
1975
1915
1855
1795
1735
1675
1615
1555
1495
1435
1375
1315
1255
1195
1135
1075
1015
955
895
821
761
701
641
581
521
461
401
341
281
221
161
101
41
-19
-79
-139
-199
-273
-333
Y
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
Units: µm
PAD No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
9/72
PIN Name
VRS
VRS
VDD2
VDD
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VR
VR
VDD
VDD2
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
TEST[7]
CLS
C86
PSB
HPMB
IRS
SEL1
SEL2
SEL3
VSS
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
RESERVED
RESERVED
RESERVED
RESERVED
X
-408
-468
-542
-602
-676
-736
-796
-856
-916
-976
-1036
-1096
-1156
-1216
-1276
-1336
-1410
-1470
-1537
-1611
-1685
-1759
-1833
-1907
-1974
-2034
-2094
-2154
-2214
-2274
-2334
-2394
-2454
-2514
-2574
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
Y
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
373
339
305
271
237
203
169
135
101
67
33
-1
-35
-69
2009/09/14
ST7565R
PAD No.
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Ver 1.7c
PIN Name
RESERVED
RESERVED
COM[15]
COM[14]
COM[13]
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COM[0]
COMS2
SEG[0]
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
X
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2573
-2539
-2505
-2471
-2437
-2403
-2369
-2335
-2301
-2267
-2227
-2193
-2159
-2125
-2091
-2057
-2023
-1989
-1955
-1921
-1887
-1853
-1819
-1785
-1751
-1717
-1683
-1649
-1615
-1581
-1547
-1513
-1479
-1445
-1411
-1377
-1343
-1309
-1275
-1241
-1207
-1173
-1139
Y
-103
-137
-171
-205
-239
-273
-307
-341
-375
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
10/72
PIN Name
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
X
-1105
-1071
-1037
-1003
-969
-935
-901
-867
-833
-799
-765
-731
-697
-663
-629
-595
-561
-527
-493
-459
-425
-391
-357
-323
-289
-255
-221
-187
-153
-119
-85
-51
-17
17
51
85
119
153
187
221
255
289
323
357
391
425
459
493
527
561
595
629
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
2009/09/14
ST7565R
PAD No.
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
Ver 1.7c
PIN Name
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
SEG[98]
SEG[99]
SEG[100]
SEG[101]
SEG[102]
SEG[103]
SEG[104]
SEG[105]
SEG[106]
SEG[107]
SEG[108]
SEG[109]
SEG[110]
SEG[111]
SEG[112]
SEG[113]
SEG[114]
SEG[115]
SEG[116]
SEG[117]
SEG[118]
SEG[119]
SEG[120]
SEG[121]
SEG[122]
SEG[123]
SEG[124]
SEG[125]
SEG[126]
SEG[127]
X
663
697
731
765
799
833
867
901
935
969
1003
1037
1071
1105
1139
1173
1207
1241
1275
1309
1343
1377
1411
1445
1479
1513
1547
1581
1615
1649
1683
1717
1751
1785
1819
1853
1887
1921
1955
1989
2023
2057
2091
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
11/72
PIN Name
SEG[128]
SEG[129]
SEG[130]
SEG[131]
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
COM[16]
COM[17]
COM[18]
COM[19]
COM[20]
COM[21]
COM[22]
COM[23]
COM[24]
COM[25]
COM[26]
COM[27]
COM[28]
COM[29]
COM[30]
COM[31]
COMS1
X
2125
2159
2193
2227
2267
2301
2335
2369
2403
2437
2471
2505
2539
2573
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-375
-341
-307
-273
-239
-205
-171
-137
-103
-69
-35
-1
33
67
101
135
169
203
237
271
305
339
373
2009/09/14
ST7565R
Pad Center Coordinates (1/55 Duty)
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Ver 1.7c
PIN Name
TEST[6]
FR
CL
DOF
VSS
CS1B
CS2
VDD
RST
A0
VSS
/WR(R/W)
/RD(E)
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VDD2
VDD2
VSS
VSS
VSS
VSS
VOUT
VOUT
CAP5P
CAP5P
CAP1N
CAP1N
CAP3P
CAP3P
CAP1N
CAP1N
CAP1P
CAP1P
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VSS
VSS
X
2575
2515
2455
2395
2335
2275
2215
2155
2095
2035
1975
1915
1855
1795
1735
1675
1615
1555
1495
1435
1375
1315
1255
1195
1135
1075
1015
955
895
821
761
701
641
581
521
461
401
341
281
221
161
101
41
-19
-79
-139
-199
-273
-333
Y
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
Units: µm
PAD No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
12/72
PIN Name
VRS
VRS
VDD2
VDD
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VR
VR
VDD
VDD2
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
TEST[7]
CLS
C86
PSB
HPMB
IRS
SEL1
SEL2
SEL3
VSS
Reserve
Reserve
Reserve
Reserve
Reserve
COM[26]
COM[25]
COM[24]
COM[23]
COM[22]
COM[21]
COM[20]
COM[19]
COM[18]
X
-408
-468
-542
-602
-676
-736
-796
-856
-916
-976
-1036
-1096
-1156
-1216
-1276
-1336
-1410
-1470
-1537
-1611
-1685
-1759
-1833
-1907
-1974
-2034
-2094
-2154
-2214
-2274
-2334
-2394
-2454
-2514
-2574
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
Y
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
373
339
305
271
237
203
169
135
101
67
33
-1
-35
-69
2009/09/14
ST7565R
PAD No.
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Ver 1.7c
PIN Name
COM[17]
COM[16]
COM[15]
COM[14]
COM[13]
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COM[0]
COMS2
SEG[0]
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
X
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2573
-2539
-2505
-2471
-2437
-2403
-2369
-2335
-2301
-2267
-2227
-2193
-2159
-2125
-2091
-2057
-2023
-1989
-1955
-1921
-1887
-1853
-1819
-1785
-1751
-1717
-1683
-1649
-1615
-1581
-1547
-1513
-1479
-1445
-1411
-1377
-1343
-1309
-1275
-1241
-1207
-1173
-1139
Y
-103
-137
-171
-205
-239
-273
-307
-341
-375
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
13/72
PIN Name
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
X
-1105
-1071
-1037
-1003
-969
-935
-901
-867
-833
-799
-765
-731
-697
-663
-629
-595
-561
-527
-493
-459
-425
-391
-357
-323
-289
-255
-221
-187
-153
-119
-85
-51
-17
17
51
85
119
153
187
221
255
289
323
357
391
425
459
493
527
561
595
629
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
2009/09/14
ST7565R
PAD No.
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
Ver 1.7c
PIN Name
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
SEG[98]
SEG[99]
SEG[100]
SEG[101]
SEG[102]
SEG[103]
SEG[104]
SEG[105]
SEG[106]
SEG[107]
SEG[108]
SEG[109]
SEG[110]
SEG[111]
SEG[112]
SEG[113]
SEG[114]
SEG[115]
SEG[116]
SEG[117]
SEG[118]
SEG[119]
SEG[120]
SEG[121]
SEG[122]
SEG[123]
SEG[124]
SEG[125]
SEG[126]
SEG[127]
X
663
697
731
765
799
833
867
901
935
969
1003
1037
1071
1105
1139
1173
1207
1241
1275
1309
1343
1377
1411
1445
1479
1513
1547
1581
1615
1649
1683
1717
1751
1785
1819
1853
1887
1921
1955
1989
2023
2057
2091
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
14/72
PIN Name
SEG[128]
SEG[129]
SEG[130]
SEG[131]
Reserve
Reserve
Reserve
Reserve
Reserve
COM[27]
COM[28]
COM[29]
COM[30]
COM[31]
COM[32]
COM[33]
COM[34]
COM[35]
COM[36]
COM[37]
COM[38]
COM[39]
COM[40]
COM[41]
COM[42]
COM[43]
COM[44]
COM[45]
COM[46]
COM[47]
COM[48]
COM[49]
COM[50]
COM[51]
COM[52]
COM[53]
COMS1
X
2125
2159
2193
2227
2267
2301
2335
2369
2403
2437
2471
2505
2539
2573
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
2810
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-375
-341
-307
-273
-239
-205
-171
-137
-103
-69
-35
-1
33
67
101
135
169
203
237
271
305
339
373
2009/09/14
ST7565R
Pad Center Coordinates (1/53 Duty)
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Ver 1.7c
PIN Name
TEST[6]
FR
CL
DOF
VSS
CS1B
CS2
VDD
RST
A0
VSS
/WR(R/W)
/RD(E)
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VDD2
VDD2
VSS
VSS
VSS
VSS
VOUT
VOUT
CAP5P
CAP5P
CAP1N
CAP1N
CAP3P
CAP3P
CAP1N
CAP1N
CAP1P
CAP1P
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VSS
VSS
X
2575
2515
2455
2395
2335
2275
2215
2155
2095
2035
1975
1915
1855
1795
1735
1675
1615
1555
1495
1435
1375
1315
1255
1195
1135
1075
1015
955
895
821
761
701
641
581
521
461
401
341
281
221
161
101
41
-19
-79
-139
-199
-273
-333
Y
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
Units: µm
PAD No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
15/72
PIN Name
VRS
VRS
VDD2
VDD
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VR
VR
VDD
VDD2
TEST[0]
TEST[1]
TEST[2]
TEST[3]
TEST[4]
TEST[5]
VDD
MS
CLS
C86
PSB
HPMB
IRS
SEL1
SEL2
SEL3
VSS
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
COM[25]
COM[24]
COM[23]
COM[22]
COM[21]
COM[20]
COM[19]
COM[18]
X
-408
-468
-542
-602
-676
-736
-796
-856
-916
-976
-1036
-1096
-1156
-1216
-1276
-1336
-1410
-1470
-1537
-1611
-1685
-1759
-1833
-1907
-1974
-2034
-2094
-2154
-2214
-2274
-2334
-2394
-2454
-2514
-2574
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
Y
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
392
373
339
305
271
237
203
169
135
101
67
33
-1
-35
-69
2009/09/14
ST7565R
PAD No.
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Ver 1.7c
PIN Name
COM[17]
COM[16]
COM[15]
COM[14]
COM[13]
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COM[0]
COMS2
SEG[0]
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
X
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2810
-2573
-2539
-2505
-2471
-2437
-2403
-2369
-2335
-2301
-2267
-2227
-2193
-2159
-2125
-2091
-2057
-2023
-1989
-1955
-1921
-1887
-1853
-1819
-1785
-1751
-1717
-1683
-1649
-1615
-1581
-1547
-1513
-1479
-1445
-1411
-1377
-1343
-1309
-1275
-1241
-1207
-1173
-1139
Y
-103
-137
-171
-205
-239
-273
-307
-341
-375
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
16/72
PIN Name
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
X
-1105
-1071
-1037
-1003
-969
-935
-901
-867
-833
-799
-765
-731
-697
-663
-629
-595
-561
-527
-493
-459
-425
-391
-357
-323
-289
-255
-221
-187
-153
-119
-85
-51
-17
17
51
85
119
153
187
221
255
289
323
357
391
425
459
493
-207
-149
-91
-33
Y
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-374
-374
-374
-374
2009/09/14
ST7565R
PAD No.
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
Ver 1.7c
PIN Name
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
SEG[98]
SEG[99]
SEG[100]
SEG[101]
SEG[102]
SEG[103]
SEG[104]
SEG[105]
SEG[106]
SEG[107]
SEG[108]
SEG[109]
SEG[110]
SEG[111]
SEG[112]
SEG[113]
SEG[114]
SEG[115]
SEG[116]
SEG[117]
SEG[118]
SEG[119]
SEG[120]
SEG[121]
SEG[122]
SEG[123]
SEG[124]
SEG[125]
SEG[126]
SEG[127]
X
25
83
141
199
257
315
373
431
489
547
605
663
721
779
837
895
953
1011
1069
1127
1185
1243
1301
1359
1417
1475
1533
1591
1649
1707
1765
1823
1881
1939
1997
2055
2113
2171
2229
2287
2345
2403
2461
Y
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
PAD No.
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
17/72
PIN Name
SEG[128]
SEG[129]
SEG[130]
SEG[131]
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
COM[26]
COM[27]
COM[28]
COM[29]
COM[30]
COM[31]
COM[32]
COM[33]
COM[34]
COM[35]
COM[36]
COM[37]
COM[38]
COM[39]
COM[40]
COM[41]
COM[42]
COM[43]
COM[44]
COM[45]
COM[46]
COM[47]
COM[48]
COM[49]
COM[50]
COM[51]
COMS1
X
2519
2577
2635
2693
2751
2809
2867
2925
2983
3041
3099
3157
3215
3273
3331
3389
3447
3505
3563
3621
3679
3737
3795
3853
3911
3969
4027
4085
4143
4201
4259
4542
4542
4542
4542
4542
4542
Y
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-374
-345
-287
-229
-171
-113
-55
2009/09/14
ST7565R
Block Diagram
COMS
COM63
COM0
SEG131
SEG0
VDD
132 SEGMENT
DRIVERS
COMS
V0
V1
V2
V3
V4
VSS
64 COMMON
DRI VERS
COM output control circuit
Display data latch
circuit
VR
VRS
IRS
Voltage
Regulator
circuit
I/O buffer
Page address
circuit
V0
65 X 132 = 8580 Bits
VOUT
VDD2
Power Supply
Circuit
Command
decoder
Status
VSS
FRS
M/S
CL
DOF
FR
Column address circuit
Voltage
booster
circuit
Oscillator
circuit
CAP1N
CAP1P
CAP2N
CAP2P
CAP3N
CAP4P
CAP5P
DISPLAY DATA RAM
Line address circuit
Voltage
follower
circuit
Display timing generator circuit
HPM
CLS
Bus holder
MPU INTERFACE ( Parallel and Serial )
D7(SI)
D6(SCL)
D5
D4
D3
D2
D1
D0
18/72
P/S
C86
/RES
CS2
CS1
A0
RW(/WR)
E(/RD)
SEL3
SEL2
SEL1
Ver 1.7c
2009/09/14
ST7565R
Pin Descriptions
Power Supply Pins
Pin Name
I/O
Function
No. of Pins
VDD
Power
Supply
Power supply
13
VDD2
Power
Supply
Power supply
10
VSS
Power
Supply
Ground
2
VRS
Power This is the internal-output VREG power supply for the LCD power supply voltage
Supply regulator.
2
This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is
determined by the liquid crystal cell, and is changed through the use of a resistive voltage
divided or through changing the impedance using an op. amp. Voltage levels are
determined based on Vss, and must maintain the relative magnitudes shown below.
V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss
V0, V1,
V2, V3,
V4,Vss
Power When the power supply turns ON, the internal power supply circuits produce the V1 to V4
Supply voltages shown below. The voltage settings are selected using the LCD bias set
command.
V1
V2
V3
V4
1/65 DUTY
8/9*V0,6/7*V0
7/9*V0,5/7*V0
2/9*V0,2/7*V0
1/9*V0,1/7*V0
1/49 DUTY
7/8*V0,5/6*V0
6/8*V0,4/6*V0
2/8*V0,2/6*V0
1/8*V0,1/6*V0
1/33 DUTY
5/6*V0,4/5*V0
4/6*V0,3/5*V0
2/6*V0,2/5*V0
1/6*V0,1/5*V0
1/55 DUTY
7/8*V0,5/6*V0
6/8*V0,4/6*V0
2/8*V0,2/6*V0
1/8*V0,1/6*V0
10
1/53 DUTY
7/8*V0,5/6*V0
6/8*V0,4/6*V0
2/8*V0,2/6*V0
1/8*V0,1/6*V0
LCD Power Supply Pins
Pin Name
I/O
CAP1P
O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N
terminal.
4
CAP1N
O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1P
terminal.
2
CAP2P
O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N
terminal.
2
CAP2N
O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2P
terminal.
2
CAP3P
O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N
terminal.
2
CAP4P
O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N
terminal.
2
CAP5P
O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N
terminal.
2
VOUT
O
VR
I
Ver 1.7c
Function
DC/DC voltage converter. Connect a capacitor between this terminal and VSS or VDD
terminal.
Output voltage regulator terminal. Provides the voltage between VSS and V0 through a
resistive voltage divider.
IRS = “L” : the V0 voltage regulator internal resistors are not used.
IRS = “H” : the V0 voltage regulator internal resistors are used.
19/72
No. of Pins
2
2
2009/09/14
ST7565R
System Bus Connection Pins
Pin Name
I/O
D5 to D0
D6 (SCL)
D7 (SI)
I/O
A0
I
/RES
I
CS1B
CS2
I
/RD
(E)
I
/WR
(R/W)
I
C86
I
P/S
I
Function
No. of Pins
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU
data bus.
When the serial interface (SPI-4) is selected (P/S = “L”) :
D7 : serial data input (SI) ; D6 : the serial clock input (SCL).
D0 to D5 should be connected to VDD or floating.
When the chip select is not active, D0 to D7 are set to high impedance.
This is connect to the least significant bit of the normal MPU address bus, and it
determines whether the data bits are data or command.
A0 = “H”: Indicates that D0 to D7 are display data.
A0 = “L”: Indicates that D0 to D7 are control data.
When /RES is set to “L”, the register settings are initialized (cleared).
The reset operation is performed by the /RES signal level.
This is the chip select signal. When CS1B = “L” and CS2 = “H”, then the chip select
becomes active, and data/command I/O is enabled.
• When connected to 8080 series MPU, this pin is treated as the “/RD” signal of the 8080
MPU and is LOW-active.
The data bus is in an output status when this signal is “L”.
• When connected to 6800 series MPU, this pin is treated as the “E” signal of the 6800
MPU and is HIGH-active.
This is the enable clock input terminal of the 6800 Series MPU.
• When connected to 8080 series MPU, this pin is treated as the “/WR” signal of the 8080
MPU and is LOW-active.
The signals on the data bus are latched at the rising edge of the /WR signal.
• When connected to 6800 series MPU, this pin is treated as the “R/W” signal of the 6800
MPU and decides the access type :
When R/W = “H”: Read.
When R/W = “L”: Write.
This is the MPU interface selection pin.
C86 = “H”: 6800 Series MPU interface.
C86 = “L”: 8080 Series MPU interface.
This pin configures the interface to be parallel mode or serial mode.
P/S = “H”: Parallel data input/output.
P/S = “L”: Serial data input.
The following applies depending on the P/S status:
P/S
Data/Command
Data
“H”
A0
D0 to D7
/RD, /WR
X
“L”
A0
SI (D7)
Write only
SCL (D6)
8
1
1
2
1
1
1
Read/Write 4-line SPI Clock
1
When P/S = “L”, D0 to D5 must be fixed to “H”.
/RD (E) and /WR (R/W) are fixed to either “H” or “L”.
The serial access mode does NOT support read operation.
Ver 1.7c
20/72
2009/09/14
ST7565R
Pin Name
I/O
CLS
I
Function
Selection pin to enable or disable the internal display clock oscillator circuit.
CLS = “H” : use internal oscillator circuit .
CLS = “L” : use external clock input (internal oscillator is disabled).
When CLS = “L”, input the external display clock through the CL terminal.
No. of Pins
1
This is the display clock input terminal
The following is true depending on the CLS status.
CLS
CL
“H”
“L”
“H”
“L”
Output
Input
Input
Input
CL
I/O
FR
O
This is the liquid crystal alternating current signal terminal.
1
/DOF
O
This is the LCD blanking control terminal.
1
IRS
I
/HPM
I
SEL3
SEL2
SEL1
TEST0 ~ 7
Ver 1.7c
I
I
1
This terminal selects the resistors for the V0 voltage level adjustment.
IRS = “H”: Use the internal resistors
IRS = “L”: Do not use the internal resistors. The V0 voltage level is
regulated by an external resistive voltage divider attached to the VR terminal
This is the power control terminal for the power supply circuit for liquid crystal drive.
/HPM = “H”: Normal mode
/HPM = “L”: High power mode (suggested)
These pins are DUTY selection.
SEL 3, 2, 1
DUTY
BIAS
0, 0, 0
1/65
1/9 or 1/7
0, 0, 1
1/49
1/8 or 1/6
0, 1, 0
1/33
1/6 or 1/5
0, 1, 1
1/55
1/8 or 1/6
1, 0, 0
1/53
1/8 or 1/6
1, X, X
-----
-----
These are terminals for IC testing.
TEST0 ~ 6: left them open.
TEST7 must connected to VDD
1
1
3
6
21/72
2009/09/14
ST7565R
LCD Driver Pins
Pin Name
I/O
Function
No. of Pins
These are the LCD segment drive outputs. Through a combination of the contents of the
display RAM and with the FR signal, a single level is selected from VSS, V3, V2, and V0.
Output Voltage
RAM DATA
FR
Normal Display
Reverse Display
SEG0
to
SEG131
O
H
H
V0
V2
H
L
VSS
V3
L
H
V2
V0
L
L
V3
Power save
132
Vss
VSS
Through a combination of the contents of the scan data and with the FR signal, a single
level is selected from VSS, V4, V1, and V0.
Scan Data
FR
Output Voltage
COM0
to
COMn
O
H
H
VSS
H
L
V0
L
H
V1
L
L
V4
Power save
COMS
O
67
VSS
These are the COM output terminals for the indicator. Both terminals output the same
signal.
Leave these open if they are not used.
ST7565R I/O PIN ITO Resister Limitation
PIN Name
CL, FR, /DOF, C86, PSB, HPMB, SEL1…SEL3, CLS, IRS
TEST0 ~ 7, VRS
VDD, VDD2, VSS, VOUT, VR
V0, V1, V2, V3, V4, CAP1P, CAP1N, CAP2P, CAP2N, CAP3P, CAP4P, CAP5P
CS1B, CS2, /RD, /WR, A0, D0 …D7
RST
Ver 1.7c
22/72
2
ITO Resister
No Limitation
Floating
<100Ω
<300Ω
<1KΩ
<10KΩ
2009/09/14
ST7565R
Description Of Functions
The MPU Interface
Selecting the Interface Type
With the ST7565R chips, data transfers are done through an
8-bit parallel data bus (D7 to D0) or through a 4-line SPI
data input (SI). Through selecting the P/ S terminal polarity
to the “H” or “L” it is possible to select either parallel
data input or 4-line SPI data input as shown in Table 1.
Table 1
P/S
H: Parallel Input
/CS1
CS2
A0
/RD
/WR
C86
D7
D6
D5~D0
/CS1
CS2
A0
/RD
/WR
C86
D7
D6
D5~D0
CS2
A0
—
—
—
SI
SCL
(HZ)
L: 4-line SPI Input
/CS1
“—” indicates fixed to “H”
The Parallel Interface
When the parallel interface has been selected (P/S =“H”),
then it is possible to connect directly to either an
8080-system MPU or a 6800 Series MPU (shown in Table 2)
by selecting the C86 terminal to either “H” or to “L”.
Table 2
(P/S=H)
/CS1
CS2
A0
H: 6800 Series
/CS1
CS2
A0
E
R/W
D7~D0
L: 8080 Series
/CS1
CS2
A0
/RD
/WR
D7~D0
C86
E(/RD) R/W(/WR) D7~D0
Moreover, data bus signals are recognized by a combination
of A0, /RD (E), /WR (R/W) signals, as shown in Table 3.
Table 3
Shared
6800 Series
8080 Series
A0
R/W
/RD
/WR
1
1
0
1
Reads the display data
1
0
1
0
Writes the display data
0
1
0
1
Status read
0
0
1
0
Write control data (command)
Function
Ver 1.7c
23/72
2009/09/14
ST7565R
The 4-line SPI Interface
When the 4-line SPI interface has been selected (P/S = “L”)
then when the chip is in active state (/CS1 = “L” and CS2 =
“H”) the 4-line SPI data input (SI) and the 4-line SPI clock
input (SCL) can be received. The 4-line SPI data is read from
the 4-line SPI data input pin in the rising edge of the 4-line
SPI clocks D7, D6 through D0, in this order. This data is
converted to 8 bits parallel data in the rising edge of the
eighth 4-line SPI clock for the processing. The A0 input is
used to determine whether or the 4-line SPI data input is
display data or command data; when A0 = “H”, the data is
display data, and when A0 = “L” then the data is command
data. The A0 input is read and used for detection every 8th
rising edge of the 4-line SPI clock after the chip becomes
active. Figure 1 is a 4-line SPI interface signal chart.
CS1
CS2
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A0
Figure 1
* When the chip is not active, the shift registers and the counter are reset to their initial states.
* Reading is not possible while in 4-line SPI interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation
be rechecked on the actual equipment.
The Chip Select
The ST7565R have two chip select terminals: /CS1 and
CS2. The MPU interface or the 4-line SPI interface is
enabled only when /CS1 = “L” and CS2 = “H”.
When the chip select is inactive, D0 to D7 enter a high
impedance state, and the A0, /RD, and /WR inputs are
inactive. When the 4-line SPI interface is selected, the shift
register and the counter are reset.
The Accessing the Display Data RAM and the Internal Registers
Data transfer at a higher speed is ensured since the MPU is
required to satisfy the cycle time (tCYC) requirement alone in
accessing the ST7565R. Wait time may not be considered.
And, in the ST7565R, each time data is sent from the MPU, a
type of pipeline process between LSIs is performed through
the bus holder attached to the internal data bus. Internal
data bus.
For example, when the MPU writes data to the display data
RAM, once the data is stored in the bus holder, then it is
written to the display data RAM before the next data write
cycle. Moreover, when the MPU reads the display data RAM,
the first data read cycle (dummy) stores the read data in the
bus holder, and then the data is read from the bus holder to
the system bus at the next data read cycle.
There is a certain restriction in the read sequence of the
display data RAM. Please be advised that data of the
specified address is not generated by the read instruction
issued immediately after the address setup. This data is
generated in data read of the second time. Thus, a dummy
read is required whenever the address setup
or write cycle operation is conducted.
This relationship is shown in Figure 2.
The Busy Flag
When the busy flag is “1” it indicates that the ST7565R is
running internal processes, and at this time no command
aside from a status read will be received. The busy flag is
outputted to D7 pin with the read instruction. If the cycle time
Ver 1.7c
(tCYC) is maintained, it is not necessary to check for this flag
before each command. This makes vast improvements in
MPU processing capabilities possible.
24/72
2009/09/14
ST7565R
MPU
Writing
WR
Internal Timing
DATA
N
BUS
Holder
N+1
N+2
N
N+1
N+3
N+2
N+3
Write
Signal
Reading
MPU
WR
RD
Internal Timing
DATA
N
N
n
n+1
N+2
Address
Preset
Read
Signal
Column
Address
Preset N
Increment N+1
Bus Holder
N
n
Address
Set #n
Dummy
Read
n+1
Data Read
#n
n+2
Data Read
#n+1
Figure 2
Ver 1.7c
25/72
2009/09/14
ST7565R
Display Data RAM
The display data RAM stores the dot data for the LCD. It has
a 65 (8 page x 8 bit +1) x 132 bit structure.
As is shown in Figure 3, the D7 to D0 display data from the
MPU corresponds to the LCD display common direction;
there are few constraints at the time of display data transfer
when multiple ST7565R are used, thus and display
structures can be created easily and with a high degree of
freedom.
Moreover, reading from and writing to the display RAM from
the MPU side is performed through the I/O buffer, which is
an independent operation from signal reading for the liquid
crystal driver. Consequently, even if the display data RAM is
accessed asynchronously during liquid crystal display, it will
not cause adverse effects on the display (such as flickering).
D0
0
1
1
1
0
COM0
D1
1
0
0
0
0
COM1
D2
0
0
0
0
0
COM2
D3
0
1
1
1
0
COM3
D4
1
0
0
0
0
COM4
-
-
Display data RAM
Liquid crystal display
Figure 3
The Page Address Circuit
Page address of the display data RAM is specified through
the Page Address Set Command. The page address must
be specified again when changing pages to perform access.
Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special
RAM for icons, and only display data D0 is used.
(see Figure 4)
The Column Addresses
The display data RAM column address is specified by the
Column Address Set command. The specified column
address is incremented (+1) with each display data
read/write command. This allows the MPU display data to be
accessed continuously. Moreover, the incrementing of
column addresses stops with 83H. Because the column
address is independent of the page address, when moving,
for example, from page 0 column 83H to page 1 column 00H,
it is necessary to respective both the page address and the
column address.
Furthermore, as is shown in Table 4, the ADC command
(segment driver direction select command) can be used to
reverse the relationship between the display data RAM
column address and the segment output. Because of this,
the constraints on the IC layout when the LCD module is
assembled can be minimized. As is shown in Figure 4,
Table 4
SEG Output
ADC
(D0) “0”
(D0) “1”
SEG0
0 (H)
83 (H)
→ Column Address →
← Column Address ←
SEG 131
83 (H)
0 (H)
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies the
line address relating to the COM output when the contents of
the display data RAM are displayed. Using the display start
line address set command, what is normally the top line of
the display can be specified (this is the COM0 output when
the common output mode is normal, and the COM63 output
Ver 1.7c
for ST7565R, the detail is shown page.11 The display area
is a 65 line area for the ST7565R.
If the line addresses are changed dynamically using the
display start line address set command, screen scrolling,
page swapping, etc. can be performed.
26/72
2009/09/14
ST7565R
ADC
0
1
Column
address
83
D0 D0
LCD
Out
82
00
S131
81
01
S130
80
02
S129
7F
03
S128
7E
04
S127
7D
COM
Output
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
Page 8
05
0
06
0
S126
0
S125
1
Page 7
7B
1
7C
1
07
1
08
0
Page 6
S124
0
S123
1
08
1
07
0
Page 5
7B
1
S8
0
06
1
7C
0
Page 4
S7
0
05
0
7D
1
S6
0
Page 3
04
1
7E
1
S5
0
03
0
Page 2
7F
0
S4
1
02
0
80
0
Page 1
S3
1
01
0
81
0
S2
0
When the common
output is normal
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
00
0
82
0
83
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
S0
0
Line
Address
Data
S1
Page Address
D3 D2 D1 D0
Regardless of the display
start line address,
1/65duty => 64th line,
1/49duty =>48th line.
1/33duty =>32th line,
1/55duty =>54th line,
1/53duty =>52th line.
Figure 4
Ver 1.7c
27/72
2009/09/14
ST7565R
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily
stores the display data that is output to the liquid crystal
driver circuit from the display data RAM.
Because the display normal/reverse status, display ON/OFF
status, and display all points ON/OFF commands control
only the data within the latch, they do not change
the data within the display data RAM itself.
The Oscillator Circuit
This is a CR-type oscillator that produces the display clock.
The oscillator circuit is only enabled when CLS = “H”.
When CLS = “L” the oscillation stops, and the external
clock is input through the CL terminal.
Display Timing Generator Circuit
The display timing generator circuit generates the timing
signal to the line address circuit and the display data latch
circuit using the display clock. The display data is latched
into the display data latch circuit synchronized with the
display clock, and is output to the data driver output terminal.
Reading to the display data liquid crystal driver circuits is
completely independent of accesses to the display data
RAM by the MPU. Consequently, even if the display data
RAM is accessed asynchronously during liquid crystal
display, there is absolutely no adverse effect (such as
flickering) on the display.
Moreover, the display timing generator circuit generates the
common timing and the liquid crystal alternating current
signal (FR) from the display clock. It generates a drive wave
form using a 2 frame alternating current drive method, as is
shown in Figure 5, for the liquid crystal drive circuit.
Two-frame alternating current drive waveform
64
65
1
2
3
4
5
6
60
61
62
63
64
65
1
2
3
4
5
6
CL
FR
V0
V1
COM0
V4
VSS
V0
V1
COM1
V4
Vss
RAM
Data
V0
V2
SEGn
V3
VSS
Figure 5
Ver 1.7c
28/72
2009/09/14
ST7565R
The Common Output Status Select Circuit
In the ST7565R chips, the COM output scan direction can be
selected by the common output status select command.
(See Table 6.) Consequently, the constraints in IC layout at
the time of LCD module assembly can be minimized.
Table 6
COM Scan Direction
Status
1/65 DUTY
Normal
Reverse
Duty
COM
dir
1/65
1/49
1/33
1/55
1/53
Ver 1.7c
COM[0:15]
1/55 DUTY
1/53 DUTY
COM[16:23] COM[24:26] COM[27:36] COM[37:39] COM[40:47] COM[48:63] COMS
COM[0:63]
1
1
1/33 DUTY
Common output pins
0
0
1/49 DUTY
COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51
COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0
COMS
COM[63:0]
COMS
COM[0:23]
Reserved
COM[24:47]
COMS
COM[47:24]
Reserved
COM[23:0]
COMS
0
COM[0:15]
Reserved
COM[16:31] COMS
1
COM[31:16]
Reserved
COM[15:0]
COMS
0
COM[0:26]
Reserved
COM[27:53]
COMS
1
COM[53:27]
Reserved
COM[26:0]
COMS
0
COM[0:25]
Reserved
COM[26:51]
COMS
1
COM[51:26]
Reserved
COM[25:0]
COMS
29/72
2009/09/14
ST7565R
The LCD Driver Circuits
These are a 187-channel that generates four voltage levels
for driving the LCD . The combination of the display data, the
COM scan signal, and the FR signal produces the liquid
COM0
crystal drive voltage output.
Figure 6 shows examples of the SEG and COM output
wave form.
M
VDD
VSS
COM0
V0
V1
V2
V3
V4
VSS
COM1
V0
V1
V2
V3
V4
VSS
COM2
V0
V1
V2
V3
V4
VSS
SEG0
V0
V1
V2
V3
V4
VSS
SEG1
V0
V1
V2
V3
V4
VSS
COM0
to
SEG0
V0
V1
V2
V3
V4
VSS
-V4
-V3
-V2
-V1
-V0
COM0
to
SEG1
V0
V1
V2
V3
V4
VSS
-V4
-V3
-V2
-V1
-V0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG 0
1
2
3
4
Figure 6
Ver 1.7c
30/72
2009/09/14
ST7565R
The Power Supply Circuits
The power supply circuits are low-power consumption power
supply circuits that generate the voltage levels required for
the LCD drivers. They are Booster circuits, voltage regulator
circuits, and voltage follower circuits. The power supply
circuits can turn the Booster circuits, the voltage regulator
circuits, and the voltage follower circuits ON or OFF
independently through the use of the Power Control Set
command. Consequently, it is possible to make an external
power supply and the internal power supply function
somewhat in parallel. Table 7 shows the Power Control Set
Command 3-bit data control function, and Table 8 shows
reference
combinations.
Table 7
bit
D2
D1
D0
Status
“1” “0”
function
Booster circuit control bit
Voltage regulator circuit control bit (V/R circuit)
Voltage follower circuit control bit (V/F circuit)
ON OFF
ON OFF
ON OFF
The Control Details of Each Bit of the Power Control Set Command
Table 8
Use Settings
Voltage Voltage Voltage
booster regulator follower
External
Step-up
voltage
voltage
input
D2
D1
D0
Only the internal power supply is used
1
1
1
ON
ON
ON
Only the voltage regulator circuit and the
voltage follower circuit are used
0
1
1
OFF
ON
ON
VOUT, VDD2
Open
Only the V/F circuit is used
0
0
1
OFF
OFF
ON
V0, VDD2
Open
Only the external power supply is used
0
0
0
OFF
OFF
OFF
V0 to V4
Open
VDD2
Used
Reference Combinations
* The “step-up system terminals” refer CAP1N, CAP1P, CAP2N, CAP2P, and CAP3N.
* While other combinations, not shown above, are also possible, these combinations are not recommended
because they have no practical use.
The Step-up Voltage Circuits
Using the step-up voltage circuits equipped within the
ST7565R chips it is possible to product a 2X,3X,4X,5X or 6X
step-up of the VSS – VDD2 voltage levels.
6X step-up: Connect capacitor C1 between CAP1N and
CAP1P, between CAP2N and CAP2P, between
CAP1N and CAP3P, between CAP2N and
CAP4P,between CAP1N and CAP5P, and
between VDD2 and VOUT, to produce a voltage
level in the positive direction at the VOUT
terminal that is 6 times the voltage level
between VSS and VDD2.
5X step-up: Connect capacitor C1 between CAP1N and
CAP1P, between CAP2N and CAP2P, between
CAP1N and CAP3P, between CAP2N and
CAP4P,and between VDD2 and VOUT, to
produce a voltage level in the positive direction
at the VOUT terminal that is 5 times the voltage
level between VSS and VDD2.
Ver 1.7c
4X step-up: Connect capacitor C1 between CAP1N and
CAP1P, between CAP2N and CAP2P, between
CAP1N and CAP3P, and between VDD2 and
VOUT, to produce a voltage level in the positive
direction at the VOUT terminal that is 4 times the
voltage level between VSS and VDD2.
3X step-up: Connect capacitor C1 between CAP1N and
CAP1P, between CAP2N and CAP2P and between
VDD2 and VOUT, and short between CAP3P and
VOUT to produce voltages level in the positive direction
at the VOUT terminal that is 3 times the voltage difference
between VSS and VDD2.
2X step-up: Connect capacitor C1 between CAP1N and
CAP1P, and between VDD2 and VOUT, leave
CAP2N open, and short between CAP2P,
CAP3P and VOUT to produce a voltage in the
positive direction at the VOUT terminal that Is
twice the voltage between VSS and VDD2.
The step-up voltage relationships are shown in Figure 7.
31/72
2009/09/14
ST7565R
VDD2 or VSS
C1
VDD2 or VSS
C1
VDD2 or VSS
C1
VOUT
VOUT
CAP3P
CAP3P
VOUT
CAP3P
C1
CAP1N
C1
CAP1N
C1
CAP1N
C1
CAP1P
CAP1P
CAP2P
CAP1P
CAP2P
C1
CAP2P
C1
OPEN CAP2N
CAP2N
CAP2N
OPEN CAP4P
OPEN CAP4P
OPEN CAP4P
OPEN CAP5P
OPEN CAP5P
OPEN CAP5P
2x voltage booster circuit
3x voltage booster circuit
4x voltage booster circuit
VOUT<=2xVDD2
Do NOT over voltage
limitation
VDD2
VSS
2x boost voltage relationship
VOUT<=3xVDD2
Do NOT over voltage
limitation
VDD2
VSS
3x boost voltage relationship
VOUT<=4xVDD2
Do NOT over voltage
limitation
VDD2
VSS
4x boost voltage relationship
VDD2 or VSS
C1
VDD2 or VSS
C1
VOUT
VOUT
CAP3P
C1
CAP3P
C1
CAP1N
C1
CAP1N
C1
CAP1P
CAP1P
CAP2P
C1
CAP2P
C1
CAP2N
C1
CAP2N
C1
CAP4P
OPEN CAP5P
CAP4P
C1
CAP5P
5x voltage booster circuit
6x voltage booster circuit
VOUT<=5xVDD2
Do NOT over voltage
limitation
VDD2
VSS
5x boost voltage relationship
VOUT<=6xVDD2
Do NOT over voltage
limitation
VDD2
VSS
6x boost voltage relationship
Figure 7
* The VDD2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value.
* The maximum voltage of the booster capacitor terminals are :
VMAX: CAP5P > CAP4P > CAP3P > CAP2P > CAP1P > CAP2N = CAP1N.
Ver 1.7c
32/72
2009/09/14
ST7565R
The Voltage Regulator Circuit
function and internal resistors for the V0 voltage regulator,
systems can be constructed without having to include
high-accuracy voltage regulator circuit components.
(VREG thermal gradients approximate -0.05%/°C)
The step-up voltage generated at VOUT outputs the LCD
driver voltage V 0 through the voltage regulator circuit.
Because the ST7565R chips have an internal high-accuracy
fixed voltage power supply with a 64-level electronic volume
(A) When the V0 Voltage Regulator Internal Resistors Are Used
Through the use of the V0 voltage regulator internal resistors
and the electronic volume function the liquid crystal power
supply voltage V0 can be controlled by commands alone
(without adding any external resistors), making it possible to
adjust the liquid crystal display brightness. The V0 voltage
can be calculated using equation A-1 over the range where
| V0 | < | VOUT |.
V
( Rb
Ra )
Rb
α
=( 1 +
1V
)
(
Ra
162 )
α
[∵ V = ( 1 - 162
) V ]
V0 = 1 +
EV
REG
EV
REG
VSS
VEV(constant voltage supply+electronic volume)
Internal Ra
V0
Internal Rb
Figure 8
VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9.
Table 9
Part no.
ST7565R
Equipment Type
Internal Power Supply
Thermal Gradient
VREG
–0.05 %/°C
2.1V
α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic
volume registers. Table 10 shows the value for α depending on the electronic volume register settings.
Rb/Ra is the V0 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V0 voltage regulator
internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data
settings in the V0 voltage regulator internal resistor ratio register.
Ver 1.7c
33/72
2009/09/14
ST7565R
Table 10
D5
D4
D3
D2
D1
D0
α
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
:
:
1
1
1
0
1
1
1
0
1
63
62
61
:
:
2
1
0
V0 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value)
Table 11
Register
ST7565R
D2
D1
D0
(1) –0.05 %/°C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Figures 9, 10 show V0 voltage measured by values of the internal resistance ratio resistor for V0 voltage adjustment and electric
volume resister for each temperature grade model.
V0
UNIT:V
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
00H
Ta = 25 °C and booster off ,regulator,follower on
VDD=3V
111
110
101
100
011
010
001
000
V0 voltage regulator
internal resistor ratio
set D2,D1,D0
Electronic volume
registered
D5 ~ D0
3FH
1FH
Figure 9 : (1) For ST7565R the Thermal Gradient = -0.05%/°C
The V0 voltage as a function of the V0 voltage regulator internal resistor ratio register and the electronic volume register.
Setup example: When selecting Ta = 25°C and V 0 = 7V for an ST7565R on which Temperature gradient = –0.05%/°C.
Using Figure 9 and the equation A-1, the following setup is enabled.
At this time, the variable range and the notch width of the V0 voltage is, as shown Table 13, as dependent on the electronic
volume.
Ver 1.7c
34/72
2009/09/14
ST7565R
Table 12
Contents
D5
—
For V0 voltage regulator
Electronic Volume
Register
D3
D2
—
0
D4
—
1
0
0
1
D1
1
D0
0
0
1
Table 13
V0
Min
Typ
Max
Units
Variable Range
Notch width
5.1 (63 levels)
7.0 (central value)
51
8.4 (0 level)
[V]
[mV]
(B) When an External Resistance is Used (The V0 Voltage Regulator Internal Resistors Are Not Used) (1)
The liquid crystal power supply voltage V0 can also be set
without using the V0 voltage regulator internal resistors (IRS
terminal = “L”) by adding resistors Ra’ and Rb’ between VDD
and VR, and between VR and V0, respectively. When this is
done, the use of the electronic volume function makes it
possible to adjust the brightness of the liquid crystal display
by controlling the liquid crystal power supply voltage V0
through commands.
In the range where | V0 | < | VOUT |, the V0 voltage can be
calculated using equation B-1 based on the external
resistances Ra’ and Rb’.
V
( Rb'
Ra' )
Rb'
α
=( 1 +
1V
Ra' ) (
162 )
α
[∵ V = ( 1 - 162
) V ]
V0 = 1 +
EV
REG
EV
REG
VSS
VEV(fixed voltage power supply+electronic volume)
External
resistor Ra'
V0
External
resistor Rb'
Figure 11
Setup example: When selecting Ta = 25°C and V 0 = 7 V for
ST7565R the temperature gradient = –0.05%/°C.
When the central value of the electron volume register is
(D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and
VREG = 2.1V so, according to equation B-1,
α
1( Rb'
Ra' ) (
162 )
Rb'
31
7V = ( 1 +
1Ra' ) (
162 )
V0 = 1 +
Ver 1.7c
Moreover, when the value of the current running through
Ra’ and Rb’ is set to 5 uA,
Ra’ + Rb’ = 1.4MΩ
(Equation B-3)
Consequently, by equations B-2 and B-3,
Rb'
= 3.12
Ra'
VREG
Ra' = 340kΩ
(2.1)
Rb' = 1060kΩ
35/72
2009/09/14
ST7565R
At this time, the V0 voltage variable range and notch width, based on the electron volume function, is as given in Table 14.
Table 14
V0
Min
Typ
Max
Units
Variable Range
Notch width
5.3 (63 levels)
7.0 (central value)
52
8.6 (0 level)
[V]
[mV]
(C) When External Resistors are Used (The V0 Voltage Regulator Internal Resistors Are Not Used) (2)
W hen the external resistor described above are used,
adding a variable resistor as well makes it possible to
perform fine adjustments on Ra’ and Rb’, to set the liquid
crystal drive voltage V0. In this case, the use of the electronic
volume function makes it possible to control the liquid crystal
power supply voltage V0 by commands to adjust the liquid
crystal display brightness.
In the range where | V0 | < | VOUT | the V0 voltage can be
calculated by equation C-1 below based on the R1 and R2
(vari a bl e re s is tor) and R 3 settings, where R 2 can
be subjected to fine adjustments (Δ R2).
ΔR2
V
( R3+R2R1+ΔR2 )
R3+R2-ΔR2
α
=( 1 +
1R1+ΔR2 ) (
162 )
α
[∵ V = ( 1 - 162
) V ]
V0 = 1 +
EV
EV
VREG
REG
VSS
Ra'
External
resistor R2
Rb'
VEV(fixed voltage power supply+electronic volume)
External
resistor R1
ΔR2
V0
VR
External
resistor R3
Figure 12
Setup example: When selecting Ta = 25°C and V 0= 5 to 9 V
(using R2) for an ST7565R the temperature gradient
= –0.05%/°C.
When the central value for the electronic volume register is
set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α =
31 and VREG = 2.1 V so, according to equation C-1, when Δ
R2 = 0 Ω, in order to make V0 = 9 V,
(
9V = 1 +
R3+R2
R1
31
) ( 1 - 162
)
(2.1)
R1 + R2 + R3 = 1.4MΩ
(Equation C-4)
With this, according to equation C-2, C-3 and C-4,
R1 = 264kΩ
R2 = 211kΩ
R3 = 925kΩ
The V0 voltage variable range and notch width based on the
electron volume function is as shown in Table 15.
When ΔR2 = R2, in order to make V = –5 V,
(
5V = 1 +
R3
R1+R2
31
) ( 1 - 162
)
(2.1)
When the current flowing VDD and V0 is set to 5 uA,
Ver 1.7c
36/72
2009/09/14
ST7565R
Table 15
V0
Min
Typ
Max
Units
Variable Range
Notch width
5.3 (63 levels)
7.0 (central value)
53
8.7 (0 level)
[V]
[mV]
* When the V0 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the
voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands.
Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF.
* The VR terminal is enabled only when the V0 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”).
When the V0 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the VR terminal is left open.
* Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables,
etc. to handle noise.
The LCD Voltage Generator Circuit
The V0 voltage is produced by a resistive voltage divider
within the IC, and can be produced at the V1, V2, V3, and V4
voltage levels required for liquid crystal driving. Moreover,
when the voltage follower changes the impedance, it
provides V1, V2, V3 and V4 to the liquid crystal drive circuit.
High Power Mode
The power supply circuit equipped in the ST7565R chips has
very low power consumption (normal mode: HPM = “H”).
However, for LCD panels with large loads (size), this
low-power power supply may cause display quality to
degrade. When this occurs, set the HPM terminal to “L”
(high power mode) can improve the display quality.
SITRONIX recommends that the display be checked on
actual equipment to determine whether or not to use this
mode. Moreover, if the improvement to the display is
inadequate even after high power mode has been set, then it
is necessary to add a liquid crystal drive power supply
externally.
The Internal Power Supply Shutdown Command Sequence
The sequence shown in Figure 13 is recommended for
shutting down the internal power supply, first placing the
internal power supply in power saver mode and then turning
Sequence
the internal power supply OFF. The power consumption can
be reduced by this sequence. Please refer to the “Sleep
Mode Set” section for the detailed power saving information.
Step1
Details
(Command, status)
Display OFF
Command address
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1 1 1 0
Power saver
Step2
Display all points ON
1
commands
End
Internal power supply OFF
0 1
0 0
1 0
1
(compound)
Figure 13
Ver 1.7c
37/72
2009/09/14
ST7565R
Reference Circuit Examples
1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit
(2) When the voltage regulator internal resistor
(1) When the voltage regulator internal resistor
is not used.
is used.
(Example where VDD2 = VDD, with 4x step-up)
(Example where VDD2 = VDD, with 4x step-up)
VDD
VSS
IRS
M/S
IRS
VDD2 or VSS
VDD2 or VSS
VDD
M/S
VDD2 or VSS
C1
VDD2 or VSS
C1
VOUT
VOUT
CAP3P
CAP4P
CAP1N
CAP5P
C1
CAP3P
CAP4P
CAP1N
CAP5P
C1
C1
C1
CAP1P
CAP1P
CAP2N
CAP2N
C1
C1
VR
VSS
R2
V1
C2
V2
C2
V3
C2
V0
C2
V2
C2
R3
C2
V1
C2
VR
R1
V0
C2
ST7565R
VSS
C2
CAP2P
ST7565R
CAP2P
V3
C2
V4
VDD2 or VSS
V4
VDD2 or VSS
2. When the voltage regulator circuit and V/F circuit alone are used
(1) W hen the V 0 voltage regulator internal resistor
(2) W hen the V 0 voltage regulator internal resistor
is not used.
is used.
VSS
IRS
VDD
VDD
M/S
IRS
VDD2 or VSS
VDD2 or VSS
VDD2 or VSS
VDD2 or VSS
VOUT
External
power
supply
CAP4P
CAP1N
CAP5P
C2
C2
CAP5P
CAP2P
VSS
VR
C2
V0
C2
V1
C2
V2
C2
V3
C2
V4
VDD2 or VSS
ST7565R
C2
CAP1N
CAP2N
ST7565R
C2
CAP4P
CAP2N
R3
C2
CAP3P
CAP1P
VR
R1
External
power
supply
CAP1P
VSS
R2
VOUT
CAP3P
CAP2P
Ver 1.7c
M/S
V0
V1
V2
V3
V4
VDD2 or VSS
38/72
2009/09/14
ST7565R
(3) When the V/F circuit alone is used
(4) When the built-in power is not used
VDD
VDD
IRS
M/S
IRS
VDD2 or VSS
VSS
M/S
VSS
VDD2 or VSS
VOUT
VOUT
CAP3P
CAP4P
CAP1N
CAP5P
C2
C2
C2
C2
VSS
VR
V0
V0
V1
V1
V2
External power supply
V3
V4
ST7565R
C2
VR
CAP5P
CAP2P
ST7565R
VSS
CAP1N
CAP2N
CAP2N
External
power
supply
CAP4P
CAP1P
CAP1P
CAP2P
CAP3P
V2
V3
VDD2 or VSS
V4
VDD2 or VSS
VDD2 or VSS
Item
Set value
unit
C1
1 ~ 2.2
uF
C2
0.1 ~ 1
uF
Note:
C1 ~ C2 are determined by the size of the LCD being driven.
The recommended panel size is smaller than 1.8”.
If the panel loading is too heavy and cause poor display quality, adding V0 capacitor can improve display quality.
* 1. Because the VR terminal input impedance is high, use short leads and shielded lines.
* 2. C1 ~ C2 are determined by the LCD loading (size). Select a suitable value that matches the module.
Example of the Process by which to Determine the Settings:
• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting the capacitor that
stabilizes the liquid crystal drive voltages (V0 to V4). Note that all C2 capacitors must have the same capacitance value.
• Next, remove external VOUT and turn all internal power supplies ON and then select C1.
Ver 1.7c
39/72
2009/09/14
ST7565R
The Reset Circuit
When the /RES input comes to the “L” level, these LSIs
return to the default state. Their default states are as follows:
1. Display OFF
2. Normal display
3. ADC select: Normal (ADC command D0 = “L”)
4. Power control register: (D2, D1, D0) = (0, 0, 0)
5. 4-line SPI interface internal register data clear
6. LCD power supply bias rate:
1/65 DUTY = 1/9 bias
1/49,1/55,1/53 DUTY = 1/8 bias
1/33 DUTY = 1/6 bias
7. Power saving clear
8. V 0 voltage regulator internal resistors Ra and Rb
separation
9 . O utp u t c o nd it io ns o f SE G a nd CO M terminals
SEG=VSS, COM=VSS
10. Read modify write OFF
11. Display start line set to first line
12. Column address set to Address 0
13. Page address set to Page 0
14. Common output status normal
15. V0 voltage regulator internal resistor ratio set mode clear
16. Electronic volume register set mode clear Electronic
volume register :
(D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0,0)
17. Test mode clear
Ver 1.7c
On the other hand, when the reset command is used, the
above default settings from 11 to 17 are only executed.
When the power is turned on, the IC internal state becomes
unstable, and it is necessary to initialize it using the /RES
terminal. After the initialization, each input terminal should
be controlled normally.
Moreover, when the control signal from the MPU is in the
high impedance, an over current may flow to the IC. After
applying a current, it is necessary to take proper measures
to prevent the input terminal from getting into the high
impedance state.
If the internal liquid crystal power supply circuit is not used
on ST7565R,it is necessary that /RES is “H” when the
external liquid crystal power supply is turned on. This IC has
the function to discharge V0 when /RES is “L,” and the
external power supply short-circuits to Vss when /RES is “L.”
This means that an internal resistor is connected between
VSS and V0.
While /RES is “L,” the oscillator works but the display timing
generator stops, and the CL, FR and /DOF terminals are
fixed to “H.” The terminals D0 to D7 are not affected. The
VSS level is output to the SEG and COM output terminals
after a successful hardware reset.
40/72
2009/09/14
ST7565R
Commands
The ST7565R identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and
execution does not depend on the external clock, but rather is performed through internal timing only, and
thus the processing is fast enough that normally a busy check is not required.
In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low
pulse to the /WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H”
signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the
command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than
the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display
data read /RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU
interface as the example.
When the 4-line SPI interface is selected, the data is input in sequence starting with D7.
<Explanation of Commands>
Display ON/OFF
This command turns the display ON and OFF.
E
R/W
D7
D6
D5
A0
/RD
/WR
0
1
0
1
0
1
D4
D3
D2
D1
0
1
1
1
D0
Setting
1
Display ON
0
Display OFF
When the display OFF command is executed when in the display all points ON mode, Sleep mode is entered. See the
section on the Sleep Mode Set for details.
Display Start Line Set
This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details
see the explanation of this function in “The Line Address Circuit”.
E
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Line address
A0
/RD
/WR
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
↓
↓
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Page Address Set
This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM
(see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM.
Changing the page address does not accompany a change in the status display.
A0
0
Ver 1.7c
E
/RD
1
R/W
/WR
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
0
0
0
↓
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
41/72
Page address
0
1
2
↓
7
8
2009/09/14
ST7565R
Column Address Set
This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two
sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM
is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write
to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See
the function explanation in “The Column Address Circuit,” for details.
E R/W
Column
D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0
address
A0 /RD /WR
0 0 0 0 1 A7 A6 A5 A4 0 0 0 0 0 0 0 0
0
High bits → 0 1
0 A3 A2 A1 A0 0 0 0 0 0 0 0 1
1
Low bits →
0 0 0 0 0 0 1 0
2
↓
↓
1 0 0 0 0 0 1 0
130
1 0 0 0 0 0 1 1
131
Status Read
A0
0
E
/RD
R/W
/WR
0
1
D7 D6
BUSY
D5
ADC
D4
D3
ON/OFF RESET 0
D2
D1
D0
0
0
0
BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process.
BUSY = 0: A new command can be accepted . if the cycle time can be satisfied, there is no need to check for
BUSY conditions.
BUSY
This shows the relationship between the column address and the segment driver.
0: Reverse (column address 131-n ↔ SEG n)
1: Normal (column address n ↔ SEG n)
(The ADC command switches the polarity.)
ADC
ON/OFF
ON/OFF: indicates the display ON/OFF state.
0: Display ON
1: Display OFF
(This display ON/OFF command switches the polarity.)
This indicates that the chip is in the process of initialization either because of a /RES signal or because of a reset
command.
0: Operating state
RESET
1: Reset in progress
Display Data Write
This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically
incremented by “1” after the write, the MPU can write the display data.
A0
1
E
/RD
R/W
/WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data
Display Data Read
This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically
incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately
after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the
internal registers. When the 4-line SPI interface is used, reading of the display data becomes unavailable.
A0
1
Ver 1.7c
E
/RD
R/W
/WR
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data
42/72
2009/09/14
ST7565R
ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence between the display RAM data column address and the segment driver output.
Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit for the
detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done
according to the column address indicated in Figure 4.
A0
E
/RD
R/W
/WR
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
1
0
0
0
0
0
1
Normal
Reverse
Display Normal/Reverse
This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done
the display data RAM contents are maintained.
A0
0
E
/RD
1
R/W
/WR
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
1
1
0
Setting
RAM Data “H”
LCD ON voltage (normal)
RAM Data “L”
LCD ON voltage (reverse)
1
Display All Points ON/OFF
This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents
of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse
command.
A0
E
/RD
R/W
/WR
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
1
0
0
1
Setting
Normal display mode
Display all points ON
When the display is in an OFF mode, executing the display all points ON command will place the display in sleep mode.
For details, see the Sleep Mode Set section.
LCD Bias Set
This command selects the voltage bias ratio required for the liquid crystal display.
A0
0
E
/RD
R/W
/WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
0
1
Select Status
1/65duty
1/49duty
1/33duty
1/55duty
1/53duty
0
1/9 bias
1/8 bias
1/6 bias
1/8 bias
1/8 bias
1
1/7 bias
1/6 bias
1/5 bias
1/6 bias
1/6 bias
Read-Modify-Write
This command is used paired with the “END” command. Once this command has been input, the display data read command
does not change the column address, but only the display data write command increments (+1) the column address. This
mode is maintained until the END command is input. When the END command is input, the column address returns to the
address it was at when the Read-Modify-Write command was entered. This function makes it possible to reduce the load on
the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor.
A0
0
E
/RD
R/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
0
0
0
0
0
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
Ver 1.7c
43/72
2009/09/14
ST7565R
Read-Modify-Write
Page Address Set
Column Address Set
Read-Modify-Write Cycle
Dummy Read
Data Read
No
Modify Data
Data Write (at same Address)
Finished?
Yes
Done
Figure 24 Command Sequence For read modify write
Return
Column address
N
N+2
N+1
N+3
N+m
N
Read-modify-write mode set
End
Figure 25
End
This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode
was entered.
A0
0
E
/RD
R/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
0
1
1
1
0
Reset
This command initializes the display start line, the column address, the page address, the common output mode, the V0 voltage
regulator internal resistor ratio, the electronic volume, and the read/modify/write mode and test mode are released. There is no
impact on the display data RAM. See the function explanation in “Reset” for details.
The reset operation is performed after the reset command is entered.
A0
0
E
/RD
R/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
0
0
0
1
0
The initialization when the power supply is applied must be done through applying a reset signal to the /RES terminal. The reset
command must not be used instead.
Ver 1.7c
44/72
2009/09/14
ST7565R
Common Output Mode Select
This command can select the scan direction of the COM output terminal. For details, see the function explanation in
“Common Output Mode Select Circuit.”
E R/W
A0 /RD /WR
0
1
0
Selected Mode
D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
0
0
1
*
*
*
1/65duty
1/49duty
1/33duty
1/55duty
1/53duty
Normal COM0→COM63 COM0→COM47 COM0→COM31 COM0→COM53 COM0→COM51
Reverse COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0
* Disabled bit
Power Controller Set
This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details
A0
0
E
/RD
1
R/W
/WR
D7
D6
D5
D4
D3
D2
0
0
1
0
1
0
1
D1
D0
0
1
0
0
1
Selected Mode
Booster circuit: OFF
Booster circuit: ON
Voltage regulator circuit: OFF
Voltage regulator circuit: ON
Voltage follower circuit: OFF
Voltage follower circuit: ON
V0 Voltage Regulator Internal Resistor Ratio Set
This command sets the V0 voltage regulator internal resistor ratio. For details, see the function explanation is “The Voltage
Regulator circuit " and table 11 .
A0
0
E
/RD
1
R/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
0
↓
Rb/Ra Ratio
Small
↓
Large
The Electronic Volume (Double Byte Command)
This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V0
through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte
command used as a pair with the electronic volume mode set command and the electronic volume register set
command, and both commands must be issued one after the other.
The Electronic Volume Mode Set
When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume
mode has been set, no other command except for the electronic volume register command can be used. Once the electronic
volume register set command has been used to set data into the register, then the electronic volume mode is released.
A0
0
Ver 1.7c
E
/RD
R/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
0
0
0
0
1
45/72
2009/09/14
ST7565R
Electronic Volume Register Set
By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V0 assumes one
of the 64 voltage levels.
When this command is input, the electronic volume mode is released after the electronic volume register has been set.
A0
0
E
/RD
1
R/W
/WR
0
D7
D6
D5
D4
D3
D2
D1
D0
| V0 |
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Small
*
*
*
*
1
1
1
1
1
1
1
1
0
1
1
↓
1
1
↓
0
1
Large
* Inactive bit (set “0”)
When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0)
The Electronic Volume Register Set Sequence
Figure 26
Ver 1.7c
46/72
2009/09/14
ST7565R
Sleep Mode Set (Double Byte Command)
This command is a two byte command used as a pair with preceding command and following command, and both commans
must issued one after the other.
This command stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the
consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows:
1. The oscillator circuit and the LCD power supply circuit are halted.
2. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VSS level.
Preceding Command
Following Command
* Disabled bit (set “0”)
A0
E
/RD
R/W
/WR
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Status
1
0
1
0
1
1
0
Sleep Mode
Normal Mode
*
*
*
*
*
*
0
0
1
0
Figure 27
In the sleep mode, the MPU is still able to access the display data RAM.
Refer to figure 28 for sleep mode sequence.
Normal Mode
Sleep Mode Setting (Sleep Mode)
Display OFF
Display all points ON
Sleep Mode
Display all points OFF
Sleep Mode Setting (Normal Mode)
Normal Mode
(Exit Sleep Mode)
Figure 28
Ver 1.7c
47/72
2009/09/14
ST7565R
The Booster Ratio (Double Byte Command)
This command makes it possible to select step-up ratio. It is used when the power control set have turn on the internal booster
circuit. This command is a two byte command used as a pair with the booster ratio select mode set command and the booster
ratio register set command, and both commands must be issued one after the other.
Booster Ratio Select Mode Set
When this command is input, the Booster ratio register set command becomes enabled. Once the booster ratio select mode
has been set, no other command except for the booster ratio register command can be used. Once the booster ratio register
set command has been used to set data into the register, then the booster ratio select mode is released.
A0
0
E
/RD
R/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
1
1
0
0
0
Booset Ratio Register Set
By using this command to set two bits of data to the booster ratio register, it can be select what kind of the booster ratio can be
used.
When this command is input, the booster ratio select mode is released after the booster ratio register has been set.
A0
0
E
/RD
R/W
/WR
1
0
D7
*
*
*
D6
D5
D4
D3
D2
D1
D0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
1
0
1
1
Booster
ratio select
2x,3x,4x
5x
6x
* Inactive bit (set “0”)
When the booster ratio select function is not used, set this to (0, 0) 2x,3x,4x step-up mode
The booster ratio Register Set Sequence
Booster Ratio Set
Booster Ratio Select Mode
Set
Booster Ratio Register Set
Set Complete?
No
Yes
Done
Figure 29
Ver 1.7c
48/72
2009/09/14
ST7565R
NOP
Non-Operation Command
A0
0
E
/RD
R/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
0
0
0
1
1
Test
This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by
applying a “L” signal to the /RES input by the reset command or by using an NOP.
A0
0
E
/RD
R/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
1
1
1
*
*
* Inactive bit
Note: The ST7565R maintain their operating modes until something happens to change them. Consequently, excessive
external noise, etc., can change the internal modes of the ST7565R . Thus in the packaging and system design it is
necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is
recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated
noise.
Ver 1.7c
49/72
2009/09/14
ST7565R
Command
(1) Display ON/OFF
Table 16: Table of ST7565R Commands
Command Code
(Note) *: ignored data
Function
D0
0 LCD display ON/OFF
1 0: OFF, 1: ON
Sets the display RAM display start line
Display start address
address
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1
1
0
1
0
1
1
1
0
1
0
(2) Display start line set
0
1
0
0
1
(3) Page address set
0
1
0
1
0
1
1
(4) Column address set
upper bit
Column address set
lower bit
0
0
0
1
0
1
0
0
0
0
0
(5) Status read
0
0
1
(6) Display data write
1
1
0
Write data
Writes to the display RAM
(7) Display data read
1
0
1
Read data
Reads from the display RAM
(8) ADC select
0
1
0
(9) Display normal/
reverse
0
1
0
(10) Display all points
ON/OFF
0
1
0
Status
Page address
Sets the display RAM page address
Most significant
column address
Least significant
column address
Sets the most significant 4 bits of the display
RAM column address.
Sets the least significant 4 bits of the display
RAM column address.
0
Reads the status data
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0
0
0
1
1
0
1
1
0
1
0
Sets the display RAM address SEG output
correspondence
0: normal, 1: reverse
Sets the LCD display normal/ reverse
0: normal, 1: reverse
Display all points
0: normal display
1: all points ON
Sets the LCD drive voltage bias ratio
0: 1/9 bias, 1: 1/7 bias (ST7565R)
Column address increment
At write: +1
At read: 0
(11) LCD bias set
0
1
0
(12) Read-modify-write
0
1
0
1
1
1
0
0
0
0
0
(13) End
0
1
0
1
1
1
0
1
1
1
0
(14) Reset
0
1
0
1
1
1
0
0
0
1
0
Internal reset
*
Select COM output scan direction
0: normal direction
1: reverse direction
1
1
0
0
0
*
*
Clear read/modify/write
(15) Common output
mode select
0
1
0
(16) Power control set
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
Resistor ratio Select internal resistor ratio(Rb/Ra) mode
1
0
0
0
0
0
0
1
0
0
0
1
0
(17) V0 voltage
regulator internal
resistor ratio set
(18) Electronic volume
mode set
Electronic volume
register set
(19) Sleep mode set
(20) Booster ratio set
0
0
1
1
1
Operating
mode
0
1
Electronic volume value
1
0
1
1
0
0
0
Select internal power supply operating mode
Set the V0 output voltage
electronic volume register
0: Sleep mode, 1: Normal mode
1
*
*
*
*
*
*
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
select booster ratio
00: 2x,3x,4x
step-up 01: 5x
11: 6x
value
(21) NOP
0
1
0
1
1
1
0
0
0
1
1
Command for non-operation
(22) Test
0
1
0
1
1
1
1
*
*
*
*
Command for IC test. Do not
use this command
Ver 1.7c
50/72
2009/09/14
ST7565R
Command Description
Instruction Setup: Reference
(1) Initialization
Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM
pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing
capacitor connecting between the LCD driving voltage output pins (V0 ~ V4) and the VSS pin, the picture on the display may
become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the
following flow when turning on the power.
1. When the built-in power is being used immediately after turning on the power:
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.
*1: Description of functions; Resetting circuit
*2: Command description; LCD bias setting
*3: Command description; ADC selection
*4: Command description; Common output state selection
*5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of
the V0 voltage
*6: Description of functions; Power circuit & Command description; Electronic volume control
*7: Description of functions; Power circuit & Command description; Power control setting
Ver 1.7c
51/72
2009/09/14
ST7565R
2. When the built-in power is not being used immediately after turning on the power:
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.
*1: Description of functions; Resetting circuit
*2: Command description; LCD bias setting
*3: Command description; ADC selection
*4: Command description; Common output state selection
*5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V0
voltage
*6: Description of functions; Power circuit & Command description; Electronic volume control
*7: Description of functions; Power circuit & Command description; Power control setting
*8: Command description; Sleep mode (multiple commands)
Ver 1.7c
52/72
2009/09/14
ST7565R
(2) Data Display
Write Display Data (After Initialized)
Function setup by command
(user setting)
(2) Display Start Line Set ...* 9
(3) Page Address Set ...* 10
(4) Column Address Set ...* 11
Data setup by Data Write
(6) Display Data Write ...* 12
Function setup by command
(user setting)
(1) Display ON/ OFF ...* 13
End of Write Display Data
Notes: Reference items
*9: Command Description; Display start line set
*10: Command Description; Page address set
*11: Command Description; Column address set
*12: Command Description; Display data write
*13: Command Description; Display ON/OFF
Avoid displaying all the data at the data display start (when the display is ON) in white.
(3) Power OFF *14
Notes: Reference items
*14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply VSS –V0. So, if the
power supply VDD - VSS is cut off when the LCD power supply VSS –V0 has still any residual voltage, the driver
(COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic
procedures:
• After turning off the internal power supply, make sure that the potential V0 ~ V4 has become below the threshold
voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS). 6. Description of Function, 6.7
Power Circuit
*15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power
supply VDD - VSS is turned off. 7. Command Description (19) Sleep Mode Set
*16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply
VDD - VSS is turned off. 7. Command Description (19) Sleep Mode Set
Ver 1.7c
53/72
2009/09/14
ST7565R
Refresh
It is recommended to turn on the refresh sequence regularly at a specified interval.
Precautions on Turning off the power
<Turning the power (VDD - VSS) off>
1) Power Save (The LCD powers (V0 - VSS) are off.) → Reset input → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of
V0 ~ V4) and the driver’s discharging capacity.
Power
save
Power Off
Reset
tL
VDD
1.8V
RES
Since the power (VDD-VSS) is cut off,
the output comes not to be fixed.
SEG
VSS
COM
VSS
VOUT
V0
V1
V2
V3
V4
Above Vth of the LCD Panel.
Under Vth of the LCD Panel.
Depends on the LCD Module
characteristic (around 0.2~1V).
tH
Ver 1.7c
54/72
2009/09/14
ST7565R
<Turning the power (VDD - VSS) off : When command control is not possible.>
2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
For tL, make the power (VDD - VSS) falling characteristics longer or consider any other method.
tH is determined according to the external capacity C2 (smoothing capacity of V0 to V4) and the driver’s discharging capacity.
Power Off
Reset
tL
VDD
1.8V
RES
Since the power (VDD-VSS) is cut
off,the output comes not be fixed.
SEG
VSS
COM
VSS
VOUT
V0
V1
V2
V3
V4
Above Vth of the LCD Panel.
Under Vth of the LCD Panel.
Depends on the LCD Module
characteristic (around 0.2~1V).
tH
<Reference Data>
V0 voltage falling (discharge) time (tH) after the process of operation → power save → reset.
V0 voltage falling (discharge) time (tH) after the process of operation → reset.
100
V0 voltage falling time (mSec)
VDD-VSS(V)
1.8
2.4
50
3.0
4.0
5.0
0
0.5
1.0
C2 : V0 to V4 capacity (uF)
Figure 31
Ver 1.7c
55/72
2009/09/14
ST7565R
Absolute Maximum Ratings
Unless otherwise noted, Vss = 0V
Table 17
Parameter
Symbol
Conditions
Unit
Power Supply Voltage
VDD
-0.3 ~ 3.6
V
Power supply voltage (VDD standard)
VDD2
-0.3 ~ 3.6
V
Power supply voltage (VDD standard)
V0, VOUT
-0.3 ~ 13.5
V
Power supply voltage (VDD standard)
V1, V2, V3, V4
-0.3 to V0
V
TOPR
–30 to +85
°C
TSTR
–65 to +150
°C
Operating temperature
Storage temperature
Bare chip
V0
V1 to V4
VDD
VDD
VSS
VSS
System (MPU) side
VSS
ST7565R chip side
Figure 30
Notes and Cautions
1. The VDD2, V0 to V4 and VOUT are relative to the VSS = 0V reference.
2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VOUT ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4.
3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is
recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI
outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI
reliability as well.
Ver 1.7c
56/72
2009/09/14
ST7565R
DC Characteristics
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V, Ta = –30 to 85°C
Table 18
Min.
Rating
Typ.
Max.
Units
Applicable
Pin
2.4
—
3.3
V
VDD*1
2.4
—
3.3
V
VDD
VIHC
0.8 x VDD
—
VDD
V
*3
Low-level Input Voltage
VILC
VSS
—
0.2 x VDD
V
*3
High-level Output Voltage
VOHC
IOH = –0.5 mA
0.8 x VDD
—
VDD
V
*4
Low-level Output Voltage
VOLC
IOL = 0.5 mA
VSS
—
0.2 x VDD
V
*4
Input leakage current
ILI
VIN = VDD or VSS
–1.0
—
1.0
µA
*5
Output leakage current
ILO
VIN = VDD or VSS
–3.0
—
3.0
µA
*6
Liquid Crystal Driver ON
Resistance
RON
Ta = 25°C V0 = 13.0 V
(Relative
V0 = 8.0 V
to VSS)
—
2.0
3.5
KΩ
—
3.2
5.4
SEGn
COMn *7
Static Consumption Current
ISSQ
—
0.01
2
µA
VDD, VDD2
Output Leakage Current
I0Q
—
0.01
10
µA
V0
Input Terminal Capacitance
CIN
—
5.0
8.0
pF
17
20
24
kHz
*8
17
20
24
kHz
CL
25
30
35
kHz
*8
25
30
35
kHz
CL
Item
Symbol
Operating Voltage (1)
VDD
Operating Voltage (2)
VDD2
High-level Input Voltage
Oscillator
Frequency
Internal
Oscillator
External
Input
Internal
Oscillator
External
Input
fOSC
fCL
fOSC
fCL
Condition
(Relative to VSS)
V0 = 13.0 V
(Relative To VSS)
Ta = 25°C, f = 1 MHz
1/65 duty
1/33 duty
Ta = 25°C
1/49 duty
1/53 duty
1/55 duty
Ta = 25°C
Table 19
Item
Internal Power
Input voltage
Supply Step-up output
voltage Circuit
Voltage regulator
Circuit Operating
Voltage
Voltage Follower
Circuit Operating
Voltage
Base Voltage
Ver 1.7c
Symbol
Condition
Min.
Rating
Typ.
Max.
Units
Applicable
Pin
VDD2
(Relative To VSS)
2.4
—
3.3
V
VDD
VOUT
(Relative To VSS)
—
—
13.5
V
VOUT
VOUT
(Relative To VSS)
6.0
—
13.5
V
VOUT
V0
(Relative To VSS)
4.0
—
13.5
V
V0 * 9
2.07
2.10
2.13
V
*10
VRS
Ta = 25°C, (Relative To V SS)
–0.05%/°C
57/72
2009/09/14
ST7565R
• Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs
when an external power supply is used .
Table 20
Rating
Test pattern
Symbol
Condition
Units
Notes
Min.
Typ.
Max.
Display Pattern
OFF
IDD
VDD = 3.0 V,
V0 – VSS = 11.0 V
—
16
27
µA
*11
Display Pattern
Checker
IDD
VDD = 3.0 V,
V0 – VSS = 11.0 V
—
19
32
µA
*11
• Dynamic Consumption Current : During Display, with the Internal Power Supply ON
Table 21
Rating
Test pattern Symbol
Condition
Min.
Typ.
Display
Pattern OFF
IDD
Display
Pattern
Checker
IDD
VDD = 3.0 V,
Quad step-up voltage.
V0 – VSS = 11.0 V
VDD = 3.0 V,
Quad step-up voltage.
V0 – VSS = 11.0 V
Units Notes
Max.
Normal Mode
—
90
130
High-Power Mode
—
128
193
Normal Mode
—
100
147
High-Power Mode
—
135
205
µA
*12
µA
*12
• Consumption Current at Time of Power Saver Mode : VDD = 3.0 V
Table 22
Item
Symbol
Condition
Sleep mode
IDD
Ta = 25°C
Min.
—
Rating
Typ.
0.1
Max.
4
Units
Notes
µA
• The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate
Frequency fFR
Table 23
fCL
fFR
Used internal oscillator circuit
fOSC / 4
fOSC / (4*65)
Used external display clock
External input (fCL)
fCL / 260
Used internal oscillator circuit
fOSC / 4
fOSC / (4*49)
Used external display clock
External input (fCL)
fCL / 196
Used internal oscillator circuit
fOSC / 8
fOSC / (8*33)
Used external display clock
External input (fCL)
fCL / 264
Used internal oscillator circuit
fOSC / 4
fOSC / (4*55)
Used external display clock
External input (fCL)
fCL / 220
Used internal oscillator circuit
fOSC / 4
fOSC / (4*53)
Used external display clock
External input (fCL)
fCL / 212
Item
1/65 DUTY
1/49 DUTY
1/33 DUTY
1/55 DUTY
1/53 DUTY
(fFR is the liquid crystal alternating current period, and not the FR signal period.)
Ver 1.7c
58/72
2009/09/14
ST7565R
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
*2 The operating voltage range for the VSS system and the V0 system is. This applies when the external power supply is
being used.
*3 The A0, D0 to D5, D6 (SCL), D7 (SI), /RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, C86, P/S, /DOF, /RES, IRS, and /HPM
terminals.
*4 The D0 to D7, FR, /DOF, and CL terminals.
*5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, C86, P/S, /RES, IRS, and /HPM terminals.
*6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state.
*7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the
various power supply terminals (V1, V 2, V 3, and V4). These are specified for the operating voltage (3) range.
RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.)
*8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency.
*9 The V0 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
*10 This is the internal voltage reference supply for the V0 voltage regulator circuit. In the ST7565R, the temperature range
approximately –0.05%/°C.
*11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
The ST7565R is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity.
Applicable only when there is no access from the MPU.
*12 It is the value on a ST7565R having the VREG temperature gradient is –0.05%/°C when the V 0 voltage regulator
internal resistor is used.
Ver 1.7c
59/72
2009/09/14
ST7565R
Timing Characteristics
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
CS1
(CS2="1")
tCYC8
tCCLR,tCCLW
WR,RD
tCCHR,tCCHW
tDH8
tDS8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 37
Table 24
Item
Signal
Symbol
Condition
(VDD = 3.3V, Ta = –30 to 85°C)
Rating
Units
Min.
Max.
tAH8
0
—
tAW8
0
—
tCYC8
240
—
tCCLW
80
—
tCCHW
80
—
tCCLR
140
—
Enable H pulse width (READ)
tCCHR
80
WRITE Data setup time
tDS8
40
—
tDH8
0
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
WRITE Address hold time
RD
D0 to D7
READ access time
tACC8
CL = 100 pF
—
70
READ Output disable time
tOH8
CL = 100 pF
5
50
Ver 1.7c
60/72
Ns
2009/09/14
ST7565R
Table 25
Item
Signal
Symbol
Condition
(VDD = 2.7V,Ta = –30 to 85°C)
Rating
Units
Min.
Max.
tAH8
0
—
tAW8
0
—
tCYC8
400
—
tCCLW
220
—
tCCHW
180
—
tCCLR
220
—
Enable H pulse width (READ)
tCCHR
180
—
WRITE Data setup time
tDS8
40
—
tDH8
0
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
WRITE Address hold time
RD
D0 to D7
READ access time
tACC8
CL = 100 pF
—
140
READ Output disable time
tOH8
CL = 100 pF
10
100
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW ) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.
Ver 1.7c
61/72
2009/09/14
ST7565R
System Bus Read/Write Characteristics 2 (For the 6800 Series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
tCYC6
tewLR,tewLW
E
tewHR,tewHW
tDH6
tDS6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 38
Table 26
Item
Signal
Symbol
Condition
(VDD = 3.3V,Ta = –30 to 85°C)
Rating
Units
Min.
Max.
tAH6
0
—
tAW6
0
—
tCYC6
240
—
tEWLW
80
—
tEWHW
80
—
tEWLR
80
—
Enable H pulse width (READ)
tEWHR
140
WRITE Data setup time
tDS6
40
—
tDH6
0
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
WRITE Address hold time
RD
D0 to D7
READ access time
tACC6
CL = 100 pF
—
70
READ Output disable time
tOH6
CL = 100 pF
5
50
Ver 1.7c
62/72
ns
2009/09/14
ST7565R
Table 27
Item
Signal
Symbol
Condition
(VDD = 2.7V,Ta = –30 to 85°C)
Rating
Units
Min.
Max.
tAH6
0
—
tAW6
0
—
tCYC6
400
—
tEWLW
220
—
tEWHW
180
—
tEWLR
220
—
Enable H pulse width (READ)
tEWHR
180
—
WRITE Data setup time
tDS6
40
—
tDH6
0
—
Address hold time
Address setup time
A0
System cycle time
Enable L pulse width (WRITE)
WR
Enable H pulse width (WRITE)
Enable L pulse width (READ)
WRITE Address hold time
RD
D0 to D7
READ access time
tACC6
CL = 100 pF
—
140
READ Output disable time
tOH6
CL = 100 pF
10
100
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW ) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.
Ver 1.7c
63/72
2009/09/14
ST7565R
The 4-line SPI Interface
tCCSS
tCSH
CS1
(CS2="1")
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Figure 39
Table 28
Item
Signal
4-line SPI Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
A0
SI
Data hold time
CS-SCL time
CS
CS-SCL time
Symbol
Condition
Tscyc
Tshw
TSLW
TSAS
Tsah
Tsds
TSDH
Tcss
Tcsh
(VDD = 3.3V,Ta = –30 to 85°C)
Rating
Units
Min.
Max.
50
—
25
—
25
—
20
—
10
—
20
—
10
—
20
—
40
—
ns
Table 29
Item
Signal
4-line SPI Clock Period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
CS-SCL time
Ver 1.7c
A0
SI
CS
Symbol
Tscyc
TSHW
TSLW
TSAS
TSAH
TSDS
TSDH
TCSS
TCSH
64/72
Condition
(VDD = 2.7V,Ta = –30 to 85°C)
Rating
Units
Min.
Max.
100
—
50
—
50
—
30
—
20
—
30
—
20
—
30
—
60
—
ns
2009/09/14
ST7565R
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Reset Timing
tRW
RES
tR
Internal
status
During reset
Reset complete
Figure 41
Table 30
Item
Reset time
Reset “L” pulse width
Signal
/RES
Symbol
Condition
tR
tRW
(VDD = 3.3V,Ta = –30 to 85°C)
Rating
Units
Min.
Typ.
Max.
—
—
1.0
us
1.0
—
—
us
Table 31
Item
Reset time
Reset “L” pulse width
Signal
/RES
Symbol
Condition
tR
tRW
(VDD = 2.7V,Ta = –30 to 85°C)
Rating
Units
Min.
Typ.
Max.
—
—
2.0
us
2.0
—
—
us
*1 All timing is specified with 20% and 80% of VDD as the standard.
Ver 1.7c
65/72
2009/09/14
ST7565R
The MPU Interface (Reference Examples)
The ST7565R Series can be connected to either 80X86 Series MPUs or to 68000 Series MPUs. Moreover, using the 4-line SPI
interface it is possible to operate the ST7565R series chips with fewer signal lines.
The display area can be enlarged by using multiple ST7565R Series chips. When this is done, the chip select signal can be
used to select the individual ICs to access.
(1) 8080 Series MPUs
VDD
VCC
A1 to A7
IORQ
CS1
CS2
Decoder
DO to D7
RD
WR
RES
DO to D7
RD
WR
RES
GND
VDD
C86
A0
ST7565R
MPU
A0
P/S
VSS
RESET
VSS
Figure 42-1
(2) 6800 Series MPUs
VDD
VCC
A1 to A15
VMA
CS1
CS2
Decoder
DO to D7
E
R/W
RES
GND
VDD
C86
A0
ST7565R
MPU
A0
DO to D7
E
R/W
RES
P/S
VSS
RESET
VSS
Figure 42-2
(3) Using the 4-line SPI Interface
VDD or VSS
VCC
A0
Port 1
Port 2
RES
GND
VDD
C86
ST7565R
CS1
CS2
Decoder
MPU
A1 to A7
A0
SI
SCL
RES
P/S
VSS
RESET
VSS
Figure 42-3
Ver 1.7c
66/72
2009/09/14
ST7565R
Connections Between LCD Drivers (Reference Example)
Figure 43
Ver 1.7c
67/72
2009/09/14
ST7565R
Application Notes
(1)
4-line interface, 4x booster, 65 duty, internal resistor, high power mode, internal oscillator
C2
C2
C2
C2
C2
C1
C1
C1
C1
Ver 1.7c
68/72
2009/09/14
ST7565R
(2)
80 interface, 3x booster, 49 duty, internal resistor, high power mode, internal oscillator
Ver 1.7c
69/72
2009/09/14
ST7565R
68 interface, 3x booster, 55 duty, internal resistor, high power mode, internal oscillator
(3)
COM26
COM9
VS
SE
SL
3
C
O
M
8
SS I H PCCT V T T
EERPS8 LED E E
L L SMB 6 S S D S S
21 B
T T T
5 4
7
C
CO S
OM E
MS G
02 0
T
E
S
T
3
T
E
S
T
2
T
E
S
T
1
T
E
S
T
0
V
S
S
V
D
D
DDDDDDDD
7 65 43 21 0
R AR
E / 0S
T
W
C
S
1
B
C
O
M
2
7
COMS1
COM32
V / / V RVCCV D
VV
V V V V V V CC CC C CCC CC C CCCC CV V V V V V V V V
T COM53
D D V V V V V V V V V V V V D D R R S S A A A A A A A A A A A A A A A A O O S S S S D D D D D D D D D D D D R WS A S D S S S O C F E
DD R R 0 0 1 1 2 2 3 3 4 4 DD S S S S PP PP P P P P P P P P P P P PU U S S S SD DD 7 6 5 4 3 2 1 0 DDR S 0 TD 2 1 S F L RS
2
T
B
2
2
44 22 2 2 11 11 3 3115 5T T
6
PP NN P P P P NN P PNNP P
S
E
G
1
3
1
2009/09/14
70/72
Ver 1.7c
ST7565R
Recommend LCD Setting
Item
C1
C2
Set value
1 ~ 2.2
0.1~ 1
unit
uF
uF
Item
C1
C2
Set value
1 ~ 2.2
0.1~ 1
Recommend Setting:
VDD = VDD2 = 3.0V
Booster = X3
BIAS = 1/6
Vop = 5.5~6.7V
Duty = 1/33
Recommend Setting 1:
VDD = VDD2 = 3.0V
Booster = X3
BIAS = 1/6
Vop = 6.0~7.0V
Duty = 1/49
Recommend Setting:
VDD = VDD2 = 3.0V
Booster = X3
BIAS = 1/5
Vop = 5.0~6.1V
Duty = 1/33
Recommend Setting 2:
VDD = VDD2 = 3.0V
Booster = X4
BIAS = 1/8
Vop = 7.0~8.5V
Duty = 1/49
Item
C1
C2
Set value
1 ~ 2.2
0.1~ 1
unit
uF
uF
Item
C1
C2
Recommend Setting 1:
VDD = VDD2 = 3.0V
Booster = X3
BIAS = 1/6
Vop = 6.0~7.5V
Duty = 1/55
Set value
1 ~ 2.2
0.1~ 1
unit
uF
uF
unit
uF
uF
Recommend Setting:
VDD = VDD2 = 3.0V
Booster = X4
BIAS = 1/7
Vop = 7.0~8.5V
Duty = 1/65
Recommend Setting 2:
VDD = VDD2 = 3.0V
Booster = X4
BIAS = 1/8
Vop = 7.0~8.5V
Duty = 1/55
Ver 1.7c
71/72
2009/09/14
ST7565R
Change Notes:
2005/03/24
2005/05/20
Ver 0.1
Ver 0.2
2005/08/10
Ver 0.3
2005/09/29
Ver 0.4
2005/10/20
Ver 1.0
2005/10/21
Ver 1.1
2005/11/07
Ver 1.2
2005/11/25
Ver 1.3
2006/02/13
Ver 1.4
2006/03/10
Ver 1.5
2007/04/24
Ver 1.6
2007/05/14
Ver 1.6a
2007/06/01
Ver 1.7
2007/07/24
2009/02/23
2009/09/14
Ver 1.7a
Ver 1.7b
Ver 1.7c
Ver 1.7c
Preliminary
Bump Height
Shipping Forms
Pad Arrangement, Bump Height, Bump Pitch, Bump Height
Pad Names- remove ”:P”, “:g”, rename FUSE, VSSF as TEST
Connections Between LCD Drivers
Application Notes
Unused Data Pin In 4-Line SPI Fixed To ‘H’
ITO Resister Limitation
Modify the Absolute Maximum Ratings.
Modify the operating range of VDD, VDD2, VOUT and V0.
Modify the description of features.
Modify the Operating Temperature.
Modify the Ta value of DC Characteristics and Reset Timing.
Remove redundant features on Page 2.
Remove Preliminary
Modify the Pad Arrangement(COG) on Page 2.
Modify the I/O PIN ITO Resister Limitation on Page 22.
Modify the Operating Temperature
Unused Data Pin In 4-Line C86 Fixed To ‘H’
Unused Data Pin In 4-Line /RD Fixed To ‘H’
Unused Data Pin In 4-Line /WR Fixed To ‘H’
Modify the flow chart on Page 46, 47 and 49.
Modify the description of DC characteristics.
Modify function description.
Redraw figures.
Redraw the PAD DIAGRAM.
Highlight the HPM (High Power Mode) description.
Put emphasis on the power OFF procedure (Page 54-55).
Fix Ver. 1.4: Booster Circuit mistake (Booster X6, Page 32).
Add V0 capacitor notes.
Add application notes.
Modify ITO resistance limitation.
Modify operation voltage.
Add a section for “Recommend LCD Setting”.
Modify the recommend setting of “Recommend LCD Setting”.
Remove slave function.
Remove static indicator function.
Modify version mark mistake.
Modify mistake of Status Read.
Modify the mistake of The Reset Circuit.
72/72
2009/09/14