ST7789S - NewHaven Display

ST7789S
240RGB x 320 dot 262K Color with Frame Memory
Single-Chip TFT Controller/Driver
Datasheet
Version 1.5
2013/04
Sitronix Technology Corp. reserves the right to change the contents in this
document without prior notice.
ST7789S
LIST OF CONTENT
1 GENERAL DESCRIPTION..................................................................... 11
2 FEATURES ............................................................................................ 12
3 PAD ARRANGEMENT........................................................................... 14
3.1
3.2
3.3
3.4
OUTPUT BUMP DIMENSION ........................................................................................14
INPUT BUMP DIMENSION ...........................................................................................15
ALIGNMENT MARK DIMENSION ...................................................................................16
CHIP INFORMATION ...................................................................................................16
4 PAD CENTER COORDINATES ............................................................. 17
5 BLOCK DIAGRAM................................................................................. 30
6 PIN DESCRIPTION ................................................................................ 31
6.1
6.2
6.3
6.4
POWER SUPPLY PINS ...............................................................................................31
INTERFACE LOGIC PINS .............................................................................................32
DRIVER OUTPUT PINS ...............................................................................................35
TEST AND OTHER PINS ..............................................................................................35
7 DRIVER ELECTRICAL CHARACTERISTICS........................................ 36
7.1
7.2
7.3
7.4
ABSOLUTE OPERATION RANGE ..................................................................................36
DC CHARACTERISTICS ..............................................................................................37
POWER CONSUMPTION .............................................................................................39
AC CHARACTERISTICS ..............................................................................................40
7.4.1
8080 Series MCU Parallel Interface Characteristics: 18/16/9/8-bit Bus..................................................... 40
7.4.2
Serial Interface Characteristics (3-line serial): ........................................................................................... 42
7.4.3
Serial Interface Characteristics (4-line serial): ........................................................................................... 43
7.4.4
RGB Interface Characteristics: .................................................................................................................. 45
7.4.5
Reset Timing: ............................................................................................................................................ 46
8 FUNCTION DESCRIPTION.................................................................... 48
8.1
8.2
MPU INTERFACE TYPE SELECTION ............................................................................48
8080-Ⅰ SERIES MCU PARALLEL INTERFACE ............................................................49
8.2.1
Write cycle sequence ................................................................................................................................ 49
8.2.2
Read cycle sequence ................................................................................................................................ 50
8.3
8080-Ⅱ
SERIES MCU PARALLEL INTERFACE .............................................................52
8.4
SERIAL INTERFACE ...................................................................................................53
8.4.1
Pin description........................................................................................................................................... 53
8.4.2
Command write mode ............................................................................................................................... 54
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8.4.3
Read function ............................................................................................................................................ 56
8.4.4
3-line serial interface Ⅰ/Ⅱ protocol......................................................................................................... 56
8.4.5
4-line serial protocol .................................................................................................................................. 58
8.4.6
2 data lane serial Interface ........................................................................................................................ 60
8.5
8.6
DATA TRANSFER BREAK AND RECOVERY ...................................................................64
DATA TRANSFER PAUSE ...........................................................................................66
8.6.1
8.7
Parallel interface pause............................................................................................................................. 66
DATA TRANSFER MODE ............................................................................................66
8.7.1
Method 1 ................................................................................................................................................... 66
8.7.2
Method 2 ................................................................................................................................................... 67
8.8
DATA COLOR CODING ...............................................................................................68
8.8.1
8080-Ⅰ series 8-bit Parallel Interface ...................................................................................................... 68
8.8.2
8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah=”03h” .............................................. 68
8.8.3
8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3Ah=”05h” ............................................ 69
8.8.4
8-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h” .......................................... 70
8.8.5
8080-Ⅱ series 8-bit Parallel Interface ...................................................................................................... 71
8.8.6
8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3Ah=”05h” ............................................ 71
8.8.7
8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3Ah=”06h” .......................................... 72
8.8.8
8080-Ⅰ series 16-Bit Parallel Interface .................................................................................................... 73
8.8.9
16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah=”03h” ............................................ 74
8.8.10
16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input) 65K-Color, 3Ah=”05h” ............................................. 75
8.8.11
16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”, MDT[1:0]=”00b” ............. 76
8.8.12
16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”, MDT[1:0]=”01b” ............. 77
8.8.13
16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”, MDT[1:0]=”10b” ............. 78
8.8.14
16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”, MDT[1:0]=”11b” ............. 79
8.8.15
8080-Ⅱ series 16-Bit Parallel Interface .................................................................................................... 80
8.8.16
16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input) 65K-Color, 3Ah=”05h” ............................................. 80
8.8.17
16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”, MDT[1:0]=”00b” ............. 81
8.8.18
16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”, MDT[1:0]=”01b” ............. 82
8.8.19
16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”, MDT[1:0]=”10b” ............. 82
8.8.20
16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”, MDT[1:0]=”11b” ............. 84
8.8.21
8080-Ⅰ series 9-Bit Parallel Interface ...................................................................................................... 85
8.8.22
Write 9-bit data for RGB 5-6-5-bit input (65K-Color), 3Ah=”05h”............................................................... 85
8.8.23
Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah=”06h”, MDT[1:0]=”00b”.................................. 86
8.8.24
Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah=”06h”, MDT[1:0]=”01b”.................................. 87
8.8.25
8080-Ⅱ series 9-bit Parallel Interface ...................................................................................................... 88
8.8.26
Write 9-bit data for RGB 5-6-5-bit input (65K-Color), 3Ah=”05h”............................................................... 88
8.8.27
Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah=”06h”, MDT[1:0]=”00b”.................................. 89
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8.8.28
Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah=”06h”, MDT[1:0]=”01b”.................................. 90
8.8.29
8080-Ⅰ series 18-Bit Parallel Interface .................................................................................................... 91
8.8.30
18-bit data bus for 12-bit/pixel (RGB-4-4-4-bit input), 4K-colors, 3Ah=”03h” ............................................. 92
8.8.31
18-bit data bus for 16-bit/pixel (RGB-5-6-5-bit input), 65K-colors, 3Ah=”05h” ........................................... 93
8.8.32
18-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-colors, 3Ah=”06h” ......................................... 94
8.8.33
8080-Ⅱ series 18-Bit Parallel Interface .................................................................................................... 95
8.8.34
18-bit data bus for 16-bit/pixel (RGB-5-6-5-bit input), 65K-colors, 3Ah=”05h” ........................................... 96
8.8.35
18-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-colors, 3Ah=”06h” ......................................... 97
8.8.36
3-Line Serial Interface ............................................................................................................................... 98
8.8.37
Write data for 12-bit/pixel (RGB-4-4-4 bit input), 4K-Colors, 3Ah=”03h”.................................................... 98
8.8.38
Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3Ah=”05h”.................................................. 99
8.8.39
Write data for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”................................................ 99
8.8.40
4-Line Serial Interface ............................................................................................................................. 100
8.8.41
Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah=”03h”.................................................. 100
8.8.42
Write data for 16-bit/pixel (RGB-5-6-5-bit input), 65K-Colors, 3Ah=”05h”................................................ 101
8.8.43
Write data for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”.............................................. 102
8.9
RGB INTERFACE ....................................................................................................103
8.9.1
RGB interface Selection .......................................................................................................................... 103
8.9.2
RGB Color Format................................................................................................................................... 103
8.9.3
RGB Interface Definition.......................................................................................................................... 109
8.9.4
RGB Interface Mode Selection ................................................................................................................ 110
8.9.5
RGB Interface Timing.............................................................................................................................. 110
8.10
VSYNC INTERFACE ............................................................................................113
8.10.1
18-bit RGB Interface................................................................................................................................ 113
8.10.2
VSYNC Interface Mode ........................................................................................................................... 115
8.11
DISPLAY DATA RAM............................................................................................117
8.11.1
Configuration ........................................................................................................................................... 117
8.11.2
Memory to display address mapping....................................................................................................... 118
8.12
8.13
8.14
ADDRESS CONTROL ............................................................................................119
NORMAL DISPLAY ON OR PARTIAL MODE ON, VERTICAL SCROLL OFF .....................121
VERTICAL SCROLL MODE .....................................................................................123
8.14.1
Rolling scroll ............................................................................................................................................ 123
8.14.2
Vertical Scroll Example............................................................................................................................ 125
8.15
TEARING EFFECT ................................................................................................127
8.15.1
Tearing effect line modes ........................................................................................................................ 127
8.15.2
Tearign effect line timings........................................................................................................................ 128
8.15.3
Example 1: MPU Write is faster than panel read..................................................................................... 129
8.15.4
Example 2: MPU write is slower than panel read .................................................................................... 130
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8.16
POWER ON/OFF SEQUENCE ...............................................................................131
8.16.1
Uncontrolled Power Off ........................................................................................................................... 132
POWER LEVEL DEFINITION ...................................................................................133
8.17
8.17.1
Power Level............................................................................................................................................. 133
POWER FLOW CHART ..........................................................................................134
GAMMA CORRECTION ..........................................................................................135
GRAY VOLTAGE GENERATOR FOR DIGITAL GAMMA CORRECTION...............................140
DISPLAY DIMMING ...............................................................................................141
8.18
8.19
8.20
8.21
8.21.1
General Description................................................................................................................................. 141
8.21.2
Dimming Requirement............................................................................................................................. 141
8.21.3
Definition of brightness transition time..................................................................................................... 143
CONTENT ADAPTIVE BRIGHTNESS CONTROL (CABC) ............................................144
8.22
8.22.1
Definition of CABC .................................................................................................................................. 144
8.22.2
Minimum brightness setting of CABC function ........................................................................................ 148
9 COMMAND .......................................................................................... 150
9.1
SYSTEM FUNCTION COMMAND TABLE 1....................................................................150
9.1.1
NOP (00h) ............................................................................................................................................... 155
9.1.2
SWRESET (01h): Software Reset........................................................................................................... 156
9.1.3
RDDID (04h): Read Display ID................................................................................................................ 158
9.1.4
RDDST (09h): Read Display Status ........................................................................................................ 160
9.1.5
RDDPM (0Ah): Read Display Power Mode ............................................................................................. 163
9.1.6
RDDMADCTL (0Bh): Read Display MADCTL ......................................................................................... 165
9.1.7
RDDCOLMOD (0Ch): Read Display Pixel Format................................................................................... 167
9.1.8
RDDIM (0Dh): Read Display Image Mode............................................................................................... 169
9.1.9
RDDSM (0Eh): Read Display Signal Mode ............................................................................................. 171
9.1.10
RDDSDR (0Fh): Read Display Self-Diagnostic Result ............................................................................ 173
9.1.11
SLPIN (10h): Sleep in.............................................................................................................................. 175
9.1.12
SLPOUT (11h): Sleep Out....................................................................................................................... 177
9.1.13
PTLON (12h): Partial Display Mode On .................................................................................................. 179
9.1.14
NORON (13h): Normal Display Mode On................................................................................................ 180
9.1.15
INVOFF (20h): Display Inversion Off....................................................................................................... 181
9.1.16
INVON (21h): Display Inversion On......................................................................................................... 183
9.1.17
GAMSET (26h): Gamma Set................................................................................................................... 185
9.1.18
DISPOFF (28h): Display Off .................................................................................................................... 187
9.1.19
DISPON (29h): Display On...................................................................................................................... 189
9.1.20
CASET (2Ah): Column Address Set........................................................................................................ 191
9.1.21
RASET (2Bh): Row Address Set ............................................................................................................. 193
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9.1.22
RAMWR (2Ch): Memory Write ................................................................................................................ 195
9.1.23
RAMRD (2Eh): Memory Read ................................................................................................................. 197
9.1.24
PTLAR (30h): Partial Area....................................................................................................................... 199
9.1.25
VSCRDEF (33h): Vertical Scrolling Definition ......................................................................................... 201
9.1.26
TEOFF (34h): Tearing Effect Line OFF ................................................................................................... 204
9.1.27
TEON (35h): Tearing Effect Line On ....................................................................................................... 206
9.1.28
MADCTL (36h): Memory Data Access Control........................................................................................ 208
9.1.29
VSCSAD (37h): Vertical Scroll Start Address of RAM............................................................................. 211
9.1.30
IDMOFF (38h): Idle Mode Off.................................................................................................................. 213
9.1.31
IDMON (39h): Idle mode on .................................................................................................................... 215
9.1.32
COLMOD (3Ah): Interface Pixel Format.................................................................................................. 217
9.1.33
WRMEMC (3Ch): Write Memory Continue .............................................................................................. 218
9.1.34
RDMEMC (3Eh): Read Memory Continue............................................................................................... 220
9.1.35
STE (44h): Set Tear Scanline.................................................................................................................. 222
9.1.36
GSCAN (45h): Get Scanline.................................................................................................................... 224
9.1.37
WRDISBV (51h): Write Display Brightness ............................................................................................. 226
9.1.38
RDDISBV (52h): Read Display Brightness Value.................................................................................... 228
9.1.39
WRCTRLD (53h): Write CTRL Display.................................................................................................... 230
9.1.40
RDCTRLD (54h): Read CTRL Value Display .......................................................................................... 232
9.1.41
WRCACE (55h): Write Content Adaptive Brightness Control and Color Enhancement .......................... 234
9.1.42
RDCABC (56h): Read Content Adaptive Brightness Control................................................................... 236
9.1.43
WRCABCMB (5Eh): Write CABC Minimum Brightness........................................................................... 238
9.1.44
RDCABCMB (5Fh): Read CABC Minimum Brightness............................................................................ 240
9.1.45
RDID1 (Dah): Read ID1........................................................................................................................... 241
9.1.46
RDID2 (DBh): Read ID2 .......................................................................................................................... 242
9.1.47
RDID3 (DCh): Read ID3 .......................................................................................................................... 243
9.2
SYSTEM FUNCTION COMMAND TABLE 2....................................................................244
9.2.1
RAMCTRL (B0h): RAM Control............................................................................................................... 249
9.2.2
RGBCTRL (B1h): RGB Interface Control ................................................................................................ 252
9.2.3
PORCTRL (B2h): Porch Setting .............................................................................................................. 254
9.2.4
FRCTRL1 (B3h): Frame Rate Control 1 (In partial mode/ idle colors) ..................................................... 255
9.2.5
GCTRL (B7h): Gate Control .................................................................................................................... 257
9.2.6
DGMEN (Bah): Digital Gamma Enable.................................................................................................... 259
9.2.7
VCOMS (BBh): VCOM Setting ................................................................................................................ 260
9.2.8
LCMCTRL (C0h): LCM Control ............................................................................................................... 262
9.2.9
IDSET (C1h): ID Code Setting................................................................................................................. 263
9.2.10
VDVVRHEN (C2h): VDV and VRH Command Enable ............................................................................ 264
9.2.11
VRHS (C3h): VRH Set............................................................................................................................. 265
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9.2.12
VDVS (C4h): VDV Set............................................................................................................................. 267
9.2.13
VCMOFSET (C5h): VCOM Offset Set..................................................................................................... 269
9.2.14
FRCTRL2 (C6h): Frame Rate Control in Normal Mode........................................................................... 271
9.2.15
CABCCTRL (C7h): CABC Control........................................................................................................... 273
9.2.16
REGSEL1 (C8h): Register Value Selection 1.......................................................................................... 274
9.2.17
REGSEL2 (Cah): Register Value Selection 2.......................................................................................... 275
9.2.18
PWCTRL1 (D0h): Power Control 1.......................................................................................................... 276
9.2.19
VAPVANEN (D2h): Enable VAP/VAN signal output ................................................................................ 278
9.2.20
PVGAMCTRL (E0h): Positive Voltage Gamma Control .......................................................................... 279
9.2.21
NVGAMCTRL (E1h): Negative Voltage Gamma Control......................................................................... 281
9.2.22
DGMLUTR (E2h): Digital Gamma Look-up Table for Red....................................................................... 283
9.2.23
DGMLUTB (E3h): Digital Gamma Look-up Table for Blue ...................................................................... 285
9.2.24
GATECTRL (E4h): Gate Control ............................................................................................................. 287
9.2.25
SPI2EN (E7h): SPI2 Enable .................................................................................................................... 289
9.2.26
PWCTRL2 (E8h): Power Control 2.......................................................................................................... 290
9.2.27
EQCTRL (E9h): Equalize time control..................................................................................................... 291
9.2.28
PROMCTRL (ECh): Program Mode Control............................................................................................ 292
9.2.29
PROMEN (FAh): Program Mode Enable................................................................................................. 293
9.2.30
NVMSET (FCh): NVM Setting ................................................................................................................. 294
9.2.31
PROMACT (FEh): Program action .......................................................................................................... 295
APPLICATION................................................................................... 296
10.1
10.2
10.3
10.4
11
CONFIGURATION OF POWER SUPPLY CIRCUIT ........................................................296
VOLTAGE GENERATION ........................................................................................297
RELATIONSHIP ABOUT SOURCE VOLTAGE ...............................................................298
APPLIED VOLTAGE TO THE TFT PANEL ..................................................................299
REVISION HISTORY ......................................................................... 300
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LIST OF FIGURES
Figure 1 Parallel Interface Timing Characteristics (8080-Series MCU Interface).................................... 40
Figure 2 Rising and Falling Timing for I/O Signal ...................................................................................... 41
Figure 3 Write-to-Read and Read-to-Write Timing ..................................................................................... 41
Figure 4 3-line serial Interface Timing Characteristics.............................................................................. 42
Figure 5 4-line serial Interface Timing Characteristics.............................................................................. 43
Figure 6 RGB Interface Timing Characteristics.......................................................................................... 45
Figure 7 Reset Timing ................................................................................................................................... 46
Figure 8 8080-Series WRX Protocol............................................................................................................. 50
Figure 9 8080-Series Parallel Bus Protocol, Write to Register or Display RAM ..................................... 50
Figure 10 8080-series RDX protocol ............................................................................................................ 51
Figure 11 8080-series parallel bus protocol, read data from register or display RAM........................... 51
Figure 12 Serial interface data stream format ............................................................................................ 54
Figure 13 3-line serial interface write protocol (write to register with control bit in transmission) ..... 55
Figure 14 4-line serial interface write protocol (write to register with control bit in transmission) ..... 55
Figure 15 3-line serial interface read protocol............................................................................................ 57
Figure 16 4-line serial interface read protocol............................................................................................ 59
Figure 17 Hardware suggestion of 2 data lane serial interface ................................................................ 60
Figure 18 3-line serial interface write protocol (write to register with control bit in transmission) ..... 61
Figure 19 3-line serial interface read protocol............................................................................................ 63
Figure 20 Write interrupts recovery (serial interface)................................................................................ 64
Figure 21 Write interrupts recovery (both serial and parallel Interface).................................................. 65
Figure 22 Parallel bus pause protocol (paused by CSX)........................................................................... 66
Figure 23 RGB Interface Data Format........................................................................................................ 108
Figure 24 DRAM Access Area by RGB Interface...................................................................................... 109
Figure 25 Timing Chart of Signals in RGB Interface DE Mode ............................................................... 110
Figure 26 Timing chart of RGB interface HV mod.................................................................................... 111
Figure 27 Data transmission through VSYNC interface .......................................................................... 113
Figure 28 Operation through VSYNC Interface ........................................................................................ 113
Figure 29 Timing Diagram of VSYNC Interface ........................................................................................ 114
Figure 30 Operation for Leading Mode of VSYNC Interface.................................................................... 115
Figure 31 Operation for Lagging Mode of VSYNC Interface ................................................................... 115
Figure 32 Display data RAM organization................................................................................................. 117
Figure 33 Display data RAM organization................................................................................................. 120
Figure 34 Rolling Scroll Definition............................................................................................................. 123
Figure 35 Gray scale Voltage Generation (Positive) ................................................................................ 135
Figure 36 Relationship between Source Output and VCOM ................................................................... 136
Figure 37 Block diagram of digital gamma ............................................................................................... 140
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Figure 38 Power Booster Level .................................................................................................................. 297
Figure 39 Relationship about source voltage........................................................................................... 298
Figure 40 Voltage Output to TFT LCD Panel............................................................................................. 299
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LIST OF TABLES
Table 1 Absolute Operation Range.............................................................................................................. 36
Table 2 Basic DC Characteristics ................................................................................................................ 37
Table 3 Power Consumption ........................................................................................................................ 39
Table 4 8080 Parallel Interface Characteristics .......................................................................................... 41
Table 5 3-line serial Interface Characteristics ............................................................................................ 42
Table 6 4-line serial Interface Characteristics ............................................................................................ 43
Table 7 18/16 Bits RGB Interface Timing Characteristics ......................................................................... 45
Table 8 Reset Timing..................................................................................................................................... 46
Table 9 Interface Type Selection.................................................................................................................. 48
Table 10 the function of 8080-series parallel interface.............................................................................. 49
Table 11 The function of 8080-Ⅱ
Ⅱ series parallel interface ....................................................................... 52
Table 12 Selection of serial interface .......................................................................................................... 53
Table 13 pin description of serial interface................................................................................................. 54
Table 14 IM pin selection .............................................................................................................................. 60
Table 15 Pin description of 2 data lane serial interface............................................................................. 60
Table 16 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25°C) . 128
Table 17 voltage level percentage adjustment description..................................................................... 136
Table 18 System Function Command List ................................................................................................ 154
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1 GENERAL DESCRIPTION
The ST7789S is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 720
source line and 320 gate line driving circuits. This chip is capable of connecting directly to an external
microprocessor, and accepts, 8-bits/9-bits/16-bits/18-bits parallel interface. Display data can be stored in the
on-chip display data RAM of 240x320x18 bits. It can perform display data RAM read/write operation with no
external operation clock to minimize power consumption. In addition, because of the integrated power supply
circuit necessary to drive liquid crystal; it is possible to make a display system with the fewest components.
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2 FEATURES
Single chip TFT-LCD Controller/Driver with On-chip Frame Memory (FM)
Display Resolution: 240*RGB (H) *320(V)
Frame Memory Size: 240 x 320 x 18-bit = 1,382,400 bits
LCD Driver Output Circuits
-
Source Outputs: 240 RGB Channels
-
Gate Outputs: 320 Channels
-
Common Electrode Output
Display Colors (Color Mode)
-
Full Color: 262K, RGB=(666) max., Idle Mode Off
-
Color Reduce: 8-color, RGB=(111), Idle Mode On
Programmable Pixel Color Format (Color Depth) for Various Display Data input Format
-
12-bit/pixel: RGB=(444)
-
16-bit/pixel: RGB=(565)
-
18-bit/pixel: RGB=(666)
MCU Interface
-
Parallel 8080-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit)
-
6/16/18 RGB Interface(VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0])
-
Serial Peripheral Interface(SPI Interface)
-
VSYNC Interface
Display Features
-
Programmable Partial Display Duty
-
CABC for saving current consumption
-
Color enhancement
On Chip Build-In Circuits
-
DC/DC Converter
-
Adjustable VCOM Generation
-
Non-Volatile (NV) Memory to Store Initial Register Setting and Factory Default Value (Module ID,
Module Version, etc)
-
Timing Controller
-
4 preset Gamma curve with separated RGB Gamma setting
Build-In NV Memory for LCD Initial Register Setting
-
8-bits for ID1 setting
-
8-bits for ID2 setting
-
8-bits for ID3 setting
-
6-bits for VCOM Offset adjustment
Driving Algorithm
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Dot Inversion
-
Column Inversion
Wide Supply Voltage Range
-
I/O Voltage (VDDI to DGND): 1.65V ~ 3.3V (VDDI≦VDD)
-
Analog Voltage (VDD to AGND): 2.4V ~ 3.3V
On-Chip Power System
-
Source Voltage (VAP (GVDD) to VAN (GVCL)): +6.4~-4.6V
-
VCOM level: GND
-
Gate driver HIGH level (VGH to AGND): +12.2V ~ +14.97V
-
Gate driver LOW level (VGL to AGND): -12.5V ~ -7.16V
Optimized layout for COG Assembly
Operate temperature range: −30℃ to +85℃
Lower Power Consumption
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3 PAD ARRANGEMENT
3.1 Output Bump Dimension
9µm
Source : S1~S720
ST7789S
Face Up
………
………
170
G320
G318
G316
G314
G312
G310
G308
G306
180
190
………
200
210
G12
G10
G8
G6
G4
G2
DUMMY
DUMMY
DUMMY
220
A2
230
Page 14 of 300
160
Version 1.5
S712
S713
S714
S715
S716
S717
S718
S719
S720
150
DUMMY
DUMMY
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
DUMMY
DUMMY
X
140
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DUMMY
VPP
VPP
VPP
VPP
DUMMY
DUMMY
VGH
VGH
VGH
VGH
VGH
VGH
VGH
VGH
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DUMMYR1
DUMMYR2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
S361
S362
S363
S364
S365
S366
S367
S368
130
TESTO6
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VCC
VCC
Y
120
LED_PWM
LED_EN
VDDI_LED
VDDI_LED
TE2
TESTO1
TESTO2
TESTO3
TESTO4
TESTO5
110
DB12
DB13
DB14
DB15
DUMMY
DB16
DB17
TEST0
TE
SDO
S353
S354
S355
S356
S357
S358
S359
S360
100
DB4
DB5
DB6
DB7
DUMMY
DB8
DB9
DB10
DB11
DUMMY
S1
S2
S3
S4
S5
S6
90
IM2
IM1
IM0
RESX
CSX
DCX
WRX
RDX
TEST2
VSYNC
HSYNC
ENABLE
DOTCLK
DUMMY
SDA
DB0
DB1
DB2
DB3
TEST1
Bump View
80
DGND
DGND
DGND
DGND
DGND
TEST3
DUMMY
DUMMY
EXTC
IM3
70
DUMMY
DUMMY
DUMMY
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
60
V20
V20
V20
V20
V20
V20
DUMMY
DUMMY
DUMMY
DUMMY
G303
G305
G307
G309
G311
G313
G315
G317
G319
50
AVCL
AVCL
AVCL
AVCL
AVCL
VAN
VAN
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VAP
VAP
V20
40
Input Pads : Pad 12 to Pad 239
VGL
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVCL
AVCL
30
40µmx56µm
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VGL
VGL
VGL
VGL
VGL
………
Au bump size
20
Gate : G1~G320
DUMMY
DUMMY
DUMMY
G1
G3
G5
G7
G9
G 11
G 13
10
14µmx104µm
DUMMY
DUMMY
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
DUMMY
VAG
VAG
VDDS
VDDS
VDDGX
VDDGX
DUMMY
DUMMY
DUMMY
A1
Au bump height
2013/04
ST7789S
3.2 Input Bump Dimension
Output Pads
S1~S720、G1~G320、DUMMY
(No.233~1278)
Symbol
Item
Size
A
Bump Width
14 um
B
Bump Gap 1 (Horizontal)
14 um
C
Bump Height
104 um
D
Bump Gap 2 (Vertical)
31 um
Input Pads
No.1~232
E
F
G
Symbol
Item
Size
E
Bump Width
40 um
F
Bump Gap
20、32.5、45 um
G
Bump Height
56 um
H
Bump Pitch
60、72.5、85 um
H
Version 1.5
Page 15 of 300
2013/04
ST7789S
3.3 Alignment Mark Dimension
Alignment Mark : A1(X,Y)=(-7480,255)
10
30
30
30 10
20
10
30
20
30
30
10
Alignment Mark : A2(X,Y)=(+7480,255)
10
30
30
30
10
20
10
20
30
30
30
10
3.4 Chip Information
Version 1.5
Chip size
16000µm x750µm
Chip thickness
300µm
Pad Location
Pad center
Coordinate Origin
Chip center
Page 16 of 300
2013/04
ST7789S
4 PAD CENTER COORDINATES
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
1
DUMMY
-7292.5
-280
33
AVDD
-5372.5
-280
65
V20
-3452.5
-280
2
DUMMY
-7232.5
-280
34
AVDD
-5312.5
-280
66
V20
-3392.5
-280
3
VCOM
-7172.5
-280
35
AVDD
-5252.5
-280
67
DUMMY
-3332.5
-280
4
VCOM
-7112.5
-280
36
AVDD
-5192.5
-280
68
DUMMY
-3272.5
-280
5
VCOM
-7052.5
-280
37
AVDD
-5132.5
-280
69
DUMMY
-3212.5
-280
6
VCOM
-6992.5
-280
38
AVDD
-5072.5
-280
70
DUMMY
-3152.5
-280
7
VCOM
-6932.5
-280
39
AVCL
-5012.5
-280
71
DUMMY
-3092.5
-280
8
VCOM
-6872.5
-280
40
AVCL
-4952.5
-280
72
DUMMY
-3032.5
-280
9
VCOM
-6812.5
-280
41
AVCL
-4892.5
-280
73
DUMMY
-2972.5
-280
10
VCOM
-6752.5
-280
42
AVCL
-4832.5
-280
74
VDD
-2912.5
-280
11
DUMMY
-6692.5
-280
43
AVCL
-4772.5
-280
75
VDD
-2852.5
-280
12
VAG
-6632.5
-280
44
AVCL
-4712.5
-280
76
VDD
-2792.5
-280
13
VAG
-6572.5
-280
45
AVCL
-4652.5
-280
77
VDD
-2732.5
-280
14
VDDS
-6512.5
-280
46
VAN
-4592.5
-280
78
VDD
-2672.5
-280
15
VDDS
-6452.5
-280
47
VAN
-4532.5
-280
79
VDD
-2612.5
-280
16
VDDGX
-6392.5
-280
48
DUMMY
-4472.5
-280
80
VDD
-2552.5
-280
17
VDDGX
-6332.5
-280
49
DUMMY
-4412.5
-280
81
VDD
-2492.5
-280
18
DUMMY
-6272.5
-280
50
DUMMY
-4352.5
-280
82
AGND
-2432.5
-280
19
DUMMY
-6212.5
-280
51
DUMMY
-4292.5
-280
83
AGND
-2372.5
-280
20
DUMMY
-6152.5
-280
52
DUMMY
-4232.5
-280
84
AGND
-2312.5
-280
21
DUMMY
-6092.5
-280
53
DUMMY
-4172.5
-280
85
AGND
-2252.5
-280
22
DUMMY
-6032.5
-280
54
DUMMY
-4112.5
-280
86
AGND
-2192.5
-280
23
DUMMY
-5972.5
-280
55
DUMMY
-4052.5
-280
87
AGND
-2132.5
-280
24
DUMMY
-5912.5
-280
56
DUMMY
-3992.5
-280
88
AGND
-2072.5
-280
25
DUMMY
-5852.5
-280
57
DUMMY
-3932.5
-280
89
AGND
-2012.5
-280
26
VGL
-5792.5
-280
58
VAP
-3872.5
-280
90
AGND
-1952.5
-280
27
VGL
-5732.5
-280
59
VAP
-3812.5
-280
91
AGND
-1892.5
-280
28
VGL
-5672.5
-280
60
V20
-3752.5
-280
92
AGND
-1832.5
-280
29
VGL
-5612.5
-280
61
V20
-3692.5
-280
93
AGND
-1772.5
-280
30
VGL
-5552.5
-280
62
V20
-3632.5
-280
94
AGND
-1712.5
-280
31
VGL
-5492.5
-280
63
V20
-3572.5
-280
95
AGND
-1652.5
-280
32
AVDD
-5432.5
-280
64
V20
-3512.5
-280
96
AGND
-1592.5
-280
Version 1.5
Page 17 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
97
AGND
-1532.5
-280
131
DB4
645
-280
165
VDDI
3272.5
-280
98
DGND
-1472.5
-280
132
DB5
730
-280
166
VDDI
3332.5
-280
99
DGND
-1412.5
-280
133
DB6
815
-280
167
VDDI
3392.5
-280
100
DGND
-1352.5
-280
134
DB7
900
-280
168
VDDI
3452.5
-280
101
DGND
-1292.5
-280
135
DUMMY
972.5
-280
169
VCC
3512.5
-280
102
DGND
-1232.5
-280
136
DB8
1045
-280
170
VCC
3572.5
-280
103
DGND
-1172.5
-280
137
DB9
1130
-280
171
VCC
3632.5
-280
104
DGND
-1112.5
-280
138
DB10
1215
-280
172
VCC
3692.5
-280
105
DGND
-1052.5
-280
139
DB11
1300
-280
173
VCC
3752.5
-280
106
TEST3
-992.5
-280
140
DUMMY
1372.5
-280
174
VCC
3812.5
-280
107
DUMMY
-932.5
-280
141
DB12
1445
-280
175
VCC
3872.5
-280
108
DUMMY
-872.5
-280
142
DB13
1530
-280
176
VCC
3932.5
-280
109
EXTC
-812.5
-280
143
DB14
1615
-280
177
VCC
3992.5
-280
110
IM3
-752.5
-280
144
DB15
1700
-280
178
VCC
4052.5
-280
111
IM2
-692.5
-280
145
DUMMY
1772.5
-280
179
VCC
4112.5
-280
112
IM1
-632.5
-280
146
DB16
1845
-280
180
VCC
4172.5
-280
113
IM0
-572.5
-280
147
DB17
1930
-280
181
VCC
4232.5
-280
114
RESX
-512.5
-280
148
TEST0
2002.5
-280
182
VCC
4292.5
-280
115
CSX
-452.5
-280
149
TE
2075
-280
183
DUMMY
4352.5
-280
116
DCX
-392.5
-280
150
SDO
2160
-280
184
VPP
4412.5
-280
117
WRX
-332.5
-280
151
LED_PWM
2245
-280
185
VPP
4472.5
-280
118
RDX
-272.5
-280
152
LED_EN
2330
-280
186
VPP
4532.5
-280
119
TEST2
-212.5
-280
153
VDDI_LED
2402.5
-280
187
VPP
4592.5
-280
120
VSYNC
-152.5
-280
154
VDDI_LED
2462.5
-280
188
DUMMY
4652.5
-280
121
HSYNC
-92.5
-280
155
TE2
2535
-280
189
DUMMY
4712.5
-280
122
ENABLE
-32.5
-280
156
TESTO1
2620
-280
190
VGH
4772.5
-280
123
DOTCLK
27.5
-280
157
TESTO2
2705
-280
191
VGH
4832.5
-280
124
DUMMY
87.5
-280
158
TESTO3
2790
-280
192
VGH
4892.5
-280
125
SDA
160
-280
159
TESTO4
2875
-280
193
VGH
4952.5
-280
126
DB0
245
-280
160
TESTO5
2960
-280
194
VGH
5012.5
-280
127
DB1
330
-280
161
TESTO6
3032.5
-280
195
VGH
5072.5
-280
128
DB2
415
-280
162
VDDI
3092.5
-280
196
VGH
5132.5
-280
129
DB3
500
-280
163
VDDI
3152.5
-280
197
VGH
5192.5
-280
130
TEST1
572.5
-280
164
VDDI
3212.5
-280
198
DUMMY
5252.5
-280
Version 1.5
Page 18 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
199
DUMMY
5312.5
-280
233
DUMMY
7399
256
267
G64
6923
256
200
DUMMY
5372.5
-280
234
DUMMY
7385
121
268
G66
6909
121
201
DUMMY
5432.5
-280
235
DUMMY
7371
256
269
G68
6895
256
202
DUMMY
5492.5
-280
236
G2
7357
121
270
G70
6881
121
203
DUMMY
5552.5
-280
237
G4
7343
256
271
G72
6867
256
204
DUMMY
5612.5
-280
238
G6
7329
121
272
G74
6853
121
205
DUMMY
5672.5
-280
239
G8
7315
256
273
G76
6839
256
206
AGND
5732.5
-280
240
G10
7301
121
274
G78
6825
121
207
AGND
5792.5
-280
241
G12
7287
256
275
G80
6811
256
208
AGND
5852.5
-280
242
G14
7273
121
276
G82
6797
121
209
AGND
5912.5
-280
243
G16
7259
256
277
G84
6783
256
210
AGND
5972.5
-280
244
G18
7245
121
278
G86
6769
121
211
AGND
6032.5
-280
245
G20
7231
256
279
G88
6755
256
212
AGND
6092.5
-280
246
G22
7217
121
280
G90
6741
121
213
AGND
6152.5
-280
247
G24
7203
256
281
G92
6727
256
214
DUMMYR1
6212.5
-280
248
G26
7189
121
282
G94
6713
121
215
DUMMYR2
6272.5
-280
249
G28
7175
256
283
G96
6699
256
216
DUMMY
6332.5
-280
250
G30
7161
121
284
G98
6685
121
217
DUMMY
6392.5
-280
251
G32
7147
256
285
G100
6671
256
218
DUMMY
6452.5
-280
252
G34
7133
121
286
G102
6657
121
219
DUMMY
6512.5
-280
253
G36
7119
256
287
G104
6643
256
220
DUMMY
6572.5
-280
254
G38
7105
121
288
G106
6629
121
221
DUMMY
6632.5
-280
255
G40
7091
256
289
G108
6615
256
222
DUMMY
6692.5
-280
256
G42
7077
121
290
G110
6601
121
223
VCOM
6752.5
-280
257
G44
7063
256
291
G112
6587
256
224
VCOM
6812.5
-280
258
G46
7049
121
292
G114
6573
121
225
VCOM
6872.5
-280
259
G48
7035
256
293
G116
6559
256
226
VCOM
6932.5
-280
260
G50
7021
121
294
G118
6545
121
227
VCOM
6992.5
-280
261
G52
7007
256
295
G120
6531
256
228
VCOM
7052.5
-280
262
G54
6993
121
296
G122
6517
121
229
VCOM
7112.5
-280
263
G56
6979
256
297
G124
6503
256
230
VCOM
7172.5
-280
264
G58
6965
121
298
G126
6489
121
231
DUMMY
7232.5
-280
265
G60
6951
256
299
G128
6475
256
232
DUMMY
7292.5
-280
266
G62
6937
121
300
G130
6461
121
Version 1.5
Page 19 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
301
G132
6447
256
335
G200
5971
256
369
G268
5495
256
302
G134
6433
121
336
G202
5957
121
370
G270
5481
121
303
G136
6419
256
337
G204
5943
256
371
G272
5467
256
304
G138
6405
121
338
G206
5929
121
372
G274
5453
121
305
G140
6391
256
339
G208
5915
256
373
G276
5439
256
306
G142
6377
121
340
G210
5901
121
374
G278
5425
121
307
G144
6363
256
341
G212
5887
256
375
G280
5411
256
308
G146
6349
121
342
G214
5873
121
376
G282
5397
121
309
G148
6335
256
343
G216
5859
256
377
G284
5383
256
310
G150
6321
121
344
G218
5845
121
378
G286
5369
121
311
G152
6307
256
345
G220
5831
256
379
G288
5355
256
312
G154
6293
121
346
G222
5817
121
380
G290
5341
121
313
G156
6279
256
347
G224
5803
256
381
G292
5327
256
314
G158
6265
121
348
G226
5789
121
382
G294
5313
121
315
G160
6251
256
349
G228
5775
256
383
G296
5299
256
316
G162
6237
121
350
G230
5761
121
384
G298
5285
121
317
G164
6223
256
351
G232
5747
256
385
G300
5271
256
318
G166
6209
121
352
G234
5733
121
386
G302
5257
121
319
G168
6195
256
353
G236
5719
256
387
G304
5243
256
320
G170
6181
121
354
G238
5705
121
388
G306
5229
121
321
G172
6167
256
355
G240
5691
256
389
G308
5215
256
322
G174
6153
121
356
G242
5677
121
390
G310
5201
121
323
G176
6139
256
357
G244
5663
256
391
G312
5187
256
324
G178
6125
121
358
G246
5649
121
392
G314
5173
121
325
G180
6111
256
359
G248
5635
256
393
G316
5159
256
326
G182
6097
121
360
G250
5621
121
394
G318
5145
121
327
G184
6083
256
361
G252
5607
256
395
G320
5131
256
328
G186
6069
121
362
G254
5593
121
396
S720
5075
121
329
G188
6055
256
363
G256
5579
256
397
S719
5061
256
330
G190
6041
121
364
G258
5565
121
398
S718
5047
121
331
G192
6027
256
365
G260
5551
256
399
S717
5033
256
332
G194
6013
121
366
G262
5537
121
400
S716
5019
121
333
G196
5999
256
367
G264
5523
256
401
S715
5005
256
334
G198
5985
121
368
G266
5509
121
402
S714
4991
121
Version 1.5
Page 20 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
403
S713
4977
256
437
S679
4501
256
471
S645
4025
256
404
S712
4963
121
438
S678
4487
121
472
S644
4011
121
405
S711
4949
256
439
S677
4473
256
473
S643
3997
256
406
S710
4935
121
440
S676
4459
121
474
S642
3983
121
407
S709
4921
256
441
S675
4445
256
475
S641
3969
256
408
S708
4907
121
442
S674
4431
121
476
S640
3955
121
409
S707
4893
256
443
S673
4417
256
477
S639
3941
256
410
S706
4879
121
444
S672
4403
121
478
S638
3927
121
411
S705
4865
256
445
S671
4389
256
479
S637
3913
256
412
S704
4851
121
446
S670
4375
121
480
S636
3899
121
413
S703
4837
256
447
S669
4361
256
481
S635
3885
256
414
S702
4823
121
448
S668
4347
121
482
S634
3871
121
415
S701
4809
256
449
S667
4333
256
483
S633
3857
256
416
S700
4795
121
450
S666
4319
121
484
S632
3843
121
417
S699
4781
256
451
S665
4305
256
485
S631
3829
256
418
S698
4767
121
452
S664
4291
121
486
S630
3815
121
419
S697
4753
256
453
S663
4277
256
487
S629
3801
256
420
S696
4739
121
454
S662
4263
121
488
S628
3787
121
421
S695
4725
256
455
S661
4249
256
489
S627
3773
256
422
S694
4711
121
456
S660
4235
121
490
S626
3759
121
423
S693
4697
256
457
S659
4221
256
491
S625
3745
256
424
S692
4683
121
458
S658
4207
121
492
S624
3731
121
425
S691
4669
256
459
S657
4193
256
493
S623
3717
256
426
S690
4655
121
460
S656
4179
121
494
S622
3703
121
427
S689
4641
256
461
S655
4165
256
495
S621
3689
256
428
S688
4627
121
462
S654
4151
121
496
S620
3675
121
429
S687
4613
256
463
S653
4137
256
497
S619
3661
256
430
S686
4599
121
464
S652
4123
121
498
S618
3647
121
431
S685
4585
256
465
S651
4109
256
499
S617
3633
256
432
S684
4571
121
466
S650
4095
121
500
S616
3619
121
433
S683
4557
256
467
S649
4081
256
501
S615
3605
256
434
S682
4543
121
468
S648
4067
121
502
S614
3591
121
435
S681
4529
256
469
S647
4053
256
503
S613
3577
256
436
S680
4515
121
470
S646
4039
121
504
S612
3563
121
Version 1.5
Page 21 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
505
S611
3549
256
539
S577
3073
256
573
S543
2597
256
506
S610
3535
121
540
S576
3059
121
574
S542
2583
121
507
S609
3521
256
541
S575
3045
256
575
S541
2569
256
508
S608
3507
121
542
S574
3031
121
576
S540
2555
121
509
S607
3493
256
543
S573
3017
256
577
S539
2541
256
510
S606
3479
121
544
S572
3003
121
578
S538
2527
121
511
S605
3465
256
545
S571
2989
256
579
S537
2513
256
512
S604
3451
121
546
S570
2975
121
580
S536
2499
121
513
S603
3437
256
547
S569
2961
256
581
S535
2485
256
514
S602
3423
121
548
S568
2947
121
582
S534
2471
121
515
S601
3409
256
549
S567
2933
256
583
S533
2457
256
516
S600
3395
121
550
S566
2919
121
584
S532
2443
121
517
S599
3381
256
551
S565
2905
256
585
S531
2429
256
518
S598
3367
121
552
S564
2891
121
586
S530
2415
121
519
S597
3353
256
553
S563
2877
256
587
S529
2401
256
520
S596
3339
121
554
S562
2863
121
588
S528
2387
121
521
S595
3325
256
555
S561
2849
256
589
S527
2373
256
522
S594
3311
121
556
S560
2835
121
590
S526
2359
121
523
S593
3297
256
557
S559
2821
256
591
S525
2345
256
524
S592
3283
121
558
S558
2807
121
592
S524
2331
121
525
S591
3269
256
559
S557
2793
256
593
S523
2317
256
526
S590
3255
121
560
S556
2779
121
594
S522
2303
121
527
S589
3241
256
561
S555
2765
256
595
S521
2289
256
528
S588
3227
121
562
S554
2751
121
596
S520
2275
121
529
S587
3213
256
563
S553
2737
256
597
S519
2261
256
530
S586
3199
121
564
S552
2723
121
598
S518
2247
121
531
S585
3185
256
565
S551
2709
256
599
S517
2233
256
532
S584
3171
121
566
S550
2695
121
600
S516
2219
121
533
S583
3157
256
567
S549
2681
256
601
S515
2205
256
534
S582
3143
121
568
S548
2667
121
602
S514
2191
121
535
S581
3129
256
569
S547
2653
256
603
S513
2177
256
536
S580
3115
121
570
S546
2639
121
604
S512
2163
121
537
S579
3101
256
571
S545
2625
256
605
S511
2149
256
538
S578
3087
121
572
S544
2611
121
606
S510
2135
121
Version 1.5
Page 22 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
607
S509
2121
256
641
S475
1645
256
675
S441
1169
256
608
S508
2107
121
642
S474
1631
121
676
S440
1155
121
609
S507
2093
256
643
S473
1617
256
677
S439
1141
256
610
S506
2079
121
644
S472
1603
121
678
S438
1127
121
611
S505
2065
256
645
S471
1589
256
679
S437
1113
256
612
S504
2051
121
646
S470
1575
121
680
S436
1099
121
613
S503
2037
256
647
S469
1561
256
681
S435
1085
256
614
S502
2023
121
648
S468
1547
121
682
S434
1071
121
615
S501
2009
256
649
S467
1533
256
683
S433
1057
256
616
S500
1995
121
650
S466
1519
121
684
S432
1043
121
617
S499
1981
256
651
S465
1505
256
685
S431
1029
256
618
S498
1967
121
652
S464
1491
121
686
S430
1015
121
619
S497
1953
256
653
S463
1477
256
687
S429
1001
256
620
S496
1939
121
654
S462
1463
121
688
S428
987
121
621
S495
1925
256
655
S461
1449
256
689
S427
973
256
622
S494
1911
121
656
S460
1435
121
690
S426
959
121
623
S493
1897
256
657
S459
1421
256
691
S425
945
256
624
S492
1883
121
658
S458
1407
121
692
S424
931
121
625
S491
1869
256
659
S457
1393
256
693
S423
917
256
626
S490
1855
121
660
S456
1379
121
694
S422
903
121
627
S489
1841
256
661
S455
1365
256
695
S421
889
256
628
S488
1827
121
662
S454
1351
121
696
S420
875
121
629
S487
1813
256
663
S453
1337
256
697
S419
861
256
630
S486
1799
121
664
S452
1323
121
698
S418
847
121
631
S485
1785
256
665
S451
1309
256
699
S417
833
256
632
S484
1771
121
666
S450
1295
121
700
S416
819
121
633
S483
1757
256
667
S449
1281
256
701
S415
805
256
634
S482
1743
121
668
S448
1267
121
702
S414
791
121
635
S481
1729
256
669
S447
1253
256
703
S413
777
256
636
S480
1715
121
670
S446
1239
121
704
S412
763
121
637
S479
1701
256
671
S445
1225
256
705
S411
749
256
638
S478
1687
121
672
S444
1211
121
706
S410
735
121
639
S477
1673
256
673
S443
1197
256
707
S409
721
256
640
S476
1659
121
674
S442
1183
121
708
S408
707
121
Version 1.5
Page 23 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
709
S407
693
256
743
S373
217
256
777
S339
-343
256
710
S406
679
121
744
S372
203
121
778
S338
-357
121
711
S405
665
256
745
S371
189
256
779
S337
-371
256
712
S404
651
121
746
S370
175
121
780
S336
-385
121
713
S403
637
256
747
S369
161
256
781
S335
-399
256
714
S402
623
121
748
S368
147
121
782
S334
-413
121
715
S401
609
256
749
S367
133
256
783
S333
-427
256
716
S400
595
121
750
S366
119
121
784
S332
-441
121
717
S399
581
256
751
S365
105
256
785
S331
-455
256
718
S398
567
121
752
S364
91
121
786
S330
-469
121
719
S397
553
256
753
S363
77
256
787
S329
-483
256
720
S396
539
121
754
S362
63
121
788
S328
-497
121
721
S395
525
256
755
S361
49
256
789
S327
-511
256
722
S394
511
121
756
S360
-49
121
790
S326
-525
121
723
S393
497
256
757
S359
-63
256
791
S325
-539
256
724
S392
483
121
758
S358
-77
121
792
S324
-553
121
725
S391
469
256
759
S357
-91
256
793
S323
-567
256
726
S390
455
121
760
S356
-105
121
794
S322
-581
121
727
S389
441
256
761
S355
-119
256
795
S321
-595
256
728
S388
427
121
762
S354
-133
121
796
S320
-609
121
729
S387
413
256
763
S353
-147
256
797
S319
-623
256
730
S386
399
121
764
S352
-161
121
798
S318
-637
121
731
S385
385
256
765
S351
-175
256
799
S317
-651
256
732
S384
371
121
766
S350
-189
121
800
S316
-665
121
733
S383
357
256
767
S349
-203
256
801
S315
-679
256
734
S382
343
121
768
S348
-217
121
802
S314
-693
121
735
S381
329
256
769
S347
-231
256
803
S313
-707
256
736
S380
315
121
770
S346
-245
121
804
S312
-721
121
737
S379
301
256
771
S345
-259
256
805
S311
-735
256
738
S378
287
121
772
S344
-273
121
806
S310
-749
121
739
S377
273
256
773
S343
-287
256
807
S309
-763
256
740
S376
259
121
774
S342
-301
121
808
S308
-777
121
741
S375
245
256
775
S341
-315
256
809
S307
-791
256
742
S374
231
121
776
S340
-329
121
810
S306
-805
121
Version 1.5
Page 24 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
811
S305
-819
256
845
S271
-1295
256
879
S237
-1771
256
812
S304
-833
121
846
S270
-1309
121
880
S236
-1785
121
813
S303
-847
256
847
S269
-1323
256
881
S235
-1799
256
814
S302
-861
121
848
S268
-1337
121
882
S234
-1813
121
815
S301
-875
256
849
S267
-1351
256
883
S233
-1827
256
816
S300
-889
121
850
S266
-1365
121
884
S232
-1841
121
817
S299
-903
256
851
S265
-1379
256
885
S231
-1855
256
818
S298
-917
121
852
S264
-1393
121
886
S230
-1869
121
819
S297
-931
256
853
S263
-1407
256
887
S229
-1883
256
820
S296
-945
121
854
S262
-1421
121
888
S228
-1897
121
821
S295
-959
256
855
S261
-1435
256
889
S227
-1911
256
822
S294
-973
121
856
S260
-1449
121
890
S226
-1925
121
823
S293
-987
256
857
S259
-1463
256
891
S225
-1939
256
824
S292
-1001
121
858
S258
-1477
121
892
S224
-1953
121
825
S291
-1015
256
859
S257
-1491
256
893
S223
-1967
256
826
S290
-1029
121
860
S256
-1505
121
894
S222
-1981
121
827
S289
-1043
256
861
S255
-1519
256
895
S221
-1995
256
828
S288
-1057
121
862
S254
-1533
121
896
S220
-2009
121
829
S287
-1071
256
863
S253
-1547
256
897
S219
-2023
256
830
S286
-1085
121
864
S252
-1561
121
898
S218
-2037
121
831
S285
-1099
256
865
S251
-1575
256
899
S217
-2051
256
832
S284
-1113
121
866
S250
-1589
121
900
S216
-2065
121
833
S283
-1127
256
867
S249
-1603
256
901
S215
-2079
256
834
S282
-1141
121
868
S248
-1617
121
902
S214
-2093
121
835
S281
-1155
256
869
S247
-1631
256
903
S213
-2107
256
836
S280
-1169
121
870
S246
-1645
121
904
S212
-2121
121
837
S279
-1183
256
871
S245
-1659
256
905
S211
-2135
256
838
S278
-1197
121
872
S244
-1673
121
906
S210
-2149
121
839
S277
-1211
256
873
S243
-1687
256
907
S209
-2163
256
840
S276
-1225
121
874
S242
-1701
121
908
S208
-2177
121
841
S275
-1239
256
875
S241
-1715
256
909
S207
-2191
256
842
S274
-1253
121
876
S240
-1729
121
910
S206
-2205
121
843
S273
-1267
256
877
S239
-1743
256
911
S205
-2219
256
844
S272
-1281
121
878
S238
-1757
121
912
S204
-2233
121
Version 1.5
Page 25 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
913
S203
-2247
256
947
S169
-2723
256
981
S135
-3199
256
914
S202
-2261
121
948
S168
-2737
121
982
S134
-3213
121
915
S201
-2275
256
949
S167
-2751
256
983
S133
-3227
256
916
S200
-2289
121
950
S166
-2765
121
984
S132
-3241
121
917
S199
-2303
256
951
S165
-2779
256
985
S131
-3255
256
918
S198
-2317
121
952
S164
-2793
121
986
S130
-3269
121
919
S197
-2331
256
953
S163
-2807
256
987
S129
-3283
256
920
S196
-2345
121
954
S162
-2821
121
988
S128
-3297
121
921
S195
-2359
256
955
S161
-2835
256
989
S127
-3311
256
922
S194
-2373
121
956
S160
-2849
121
990
S126
-3325
121
923
S193
-2387
256
957
S159
-2863
256
991
S125
-3339
256
924
S192
-2401
121
958
S158
-2877
121
992
S124
-3353
121
925
S191
-2415
256
959
S157
-2891
256
993
S123
-3367
256
926
S190
-2429
121
960
S156
-2905
121
994
S122
-3381
121
927
S189
-2443
256
961
S155
-2919
256
995
S121
-3395
256
928
S188
-2457
121
962
S154
-2933
121
996
S120
-3409
121
929
S187
-2471
256
963
S153
-2947
256
997
S119
-3423
256
930
S186
-2485
121
964
S152
-2961
121
998
S118
-3437
121
931
S185
-2499
256
965
S151
-2975
256
999
S117
-3451
256
932
S184
-2513
121
966
S150
-2989
121
1000
S116
-3465
121
933
S183
-2527
256
967
S149
-3003
256
1001
S115
-3479
256
934
S182
-2541
121
968
S148
-3017
121
1002
S114
-3493
121
935
S181
-2555
256
969
S147
-3031
256
1003
S113
-3507
256
936
S180
-2569
121
970
S146
-3045
121
1004
S112
-3521
121
937
S179
-2583
256
971
S145
-3059
256
1005
S111
-3535
256
938
S178
-2597
121
972
S144
-3073
121
1006
S110
-3549
121
939
S177
-2611
256
973
S143
-3087
256
1007
S109
-3563
256
940
S176
-2625
121
974
S142
-3101
121
1008
S108
-3577
121
941
S175
-2639
256
975
S141
-3115
256
1009
S107
-3591
256
942
S174
-2653
121
976
S140
-3129
121
1010
S106
-3605
121
943
S173
-2667
256
977
S139
-3143
256
1011
S105
-3619
256
944
S172
-2681
121
978
S138
-3157
121
1012
S104
-3633
121
945
S171
-2695
256
979
S137
-3171
256
1013
S103
-3647
256
946
S170
-2709
121
980
S136
-3185
121
1014
S102
-3661
121
Version 1.5
Page 26 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
1015
S101
-3675
256
1049
S67
-4151
256
1083
S33
-4627
256
1016
S100
-3689
121
1050
S66
-4165
121
1084
S32
-4641
121
1017
S99
-3703
256
1051
S65
-4179
256
1085
S31
-4655
256
1018
S98
-3717
121
1052
S64
-4193
121
1086
S30
-4669
121
1019
S97
-3731
256
1053
S63
-4207
256
1087
S29
-4683
256
1020
S96
-3745
121
1054
S62
-4221
121
1088
S28
-4697
121
1021
S95
-3759
256
1055
S61
-4235
256
1089
S27
-4711
256
1022
S94
-3773
121
1056
S60
-4249
121
1090
S26
-4725
121
1023
S93
-3787
256
1057
S59
-4263
256
1091
S25
-4739
256
1024
S92
-3801
121
1058
S58
-4277
121
1092
S24
-4753
121
1025
S91
-3815
256
1059
S57
-4291
256
1093
S23
-4767
256
1026
S90
-3829
121
1060
S56
-4305
121
1094
S22
-4781
121
1027
S89
-3843
256
1061
S55
-4319
256
1095
S21
-4795
256
1028
S88
-3857
121
1062
S54
-4333
121
1096
S20
-4809
121
1029
S87
-3871
256
1063
S53
-4347
256
1097
S19
-4823
256
1030
S86
-3885
121
1064
S52
-4361
121
1098
S18
-4837
121
1031
S85
-3899
256
1065
S51
-4375
256
1099
S17
-4851
256
1032
S84
-3913
121
1066
S50
-4389
121
1100
S16
-4865
121
1033
S83
-3927
256
1067
S49
-4403
256
1101
S15
-4879
256
1034
S82
-3941
121
1068
S48
-4417
121
1102
S14
-4893
121
1035
S81
-3955
256
1069
S47
-4431
256
1103
S13
-4907
256
1036
S80
-3969
121
1070
S46
-4445
121
1104
S12
-4921
121
1037
S79
-3983
256
1071
S45
-4459
256
1105
S11
-4935
256
1038
S78
-3997
121
1072
S44
-4473
121
1106
S10
-4949
121
1039
S77
-4011
256
1073
S43
-4487
256
1107
S9
-4963
256
1040
S76
-4025
121
1074
S42
-4501
121
1108
S8
-4977
121
1041
S75
-4039
256
1075
S41
-4515
256
1109
S7
-4991
256
1042
S74
-4053
121
1076
S40
-4529
121
1110
S6
-5005
121
1043
S73
-4067
256
1077
S39
-4543
256
1111
S5
-5019
256
1044
S72
-4081
121
1078
S38
-4557
121
1112
S4
-5033
121
1045
S71
-4095
256
1079
S37
-4571
256
1113
S3
-5047
256
1046
S70
-4109
121
1080
S36
-4585
121
1114
S2
-5061
121
1047
S69
-4123
256
1081
S35
-4599
256
1115
S1
-5075
256
1048
S68
-4137
121
1082
S34
-4613
121
1116
G319
-5131
121
Version 1.5
Page 27 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
1117
G317
-5145
256
1151
G249
-5621
256
1185
G181
-6097
256
1118
G315
-5159
121
1152
G247
-5635
121
1186
G179
-6111
121
1119
G313
-5173
256
1153
G245
-5649
256
1187
G177
-6125
256
1120
G311
-5187
121
1154
G243
-5663
121
1188
G175
-6139
121
1121
G309
-5201
256
1155
G241
-5677
256
1189
G173
-6153
256
1122
G307
-5215
121
1156
G239
-5691
121
1190
G171
-6167
121
1123
G305
-5229
256
1157
G237
-5705
256
1191
G169
-6181
256
1124
G303
-5243
121
1158
G235
-5719
121
1192
G167
-6195
121
1125
G301
-5257
256
1159
G233
-5733
256
1193
G165
-6209
256
1126
G299
-5271
121
1160
G231
-5747
121
1194
G163
-6223
121
1127
G297
-5285
256
1161
G229
-5761
256
1195
G161
-6237
256
1128
G295
-5299
121
1162
G227
-5775
121
1196
G159
-6251
121
1129
G293
-5313
256
1163
G225
-5789
256
1197
G157
-6265
256
1130
G291
-5327
121
1164
G223
-5803
121
1198
G155
-6279
121
1131
G289
-5341
256
1165
G221
-5817
256
1199
G153
-6293
256
1132
G287
-5355
121
1166
G219
-5831
121
1200
G151
-6307
121
1133
G285
-5369
256
1167
G217
-5845
256
1201
G149
-6321
256
1134
G283
-5383
121
1168
G215
-5859
121
1202
G147
-6335
121
1135
G281
-5397
256
1169
G213
-5873
256
1203
G145
-6349
256
1136
G279
-5411
121
1170
G211
-5887
121
1204
G143
-6363
121
1137
G277
-5425
256
1171
G209
-5901
256
1205
G141
-6377
256
1138
G275
-5439
121
1172
G207
-5915
121
1206
G139
-6391
121
1139
G273
-5453
256
1173
G205
-5929
256
1207
G137
-6405
256
1140
G271
-5467
121
1174
G203
-5943
121
1208
G135
-6419
121
1141
G269
-5481
256
1175
G201
-5957
256
1209
G133
-6433
256
1142
G267
-5495
121
1176
G199
-5971
121
1210
G131
-6447
121
1143
G265
-5509
256
1177
G197
-5985
256
1211
G129
-6461
256
1144
G263
-5523
121
1178
G195
-5999
121
1212
G127
-6475
121
1145
G261
-5537
256
1179
G193
-6013
256
1213
G125
-6489
256
1146
G259
-5551
121
1180
G191
-6027
121
1214
G123
-6503
121
1147
G257
-5565
256
1181
G189
-6041
256
1215
G121
-6517
256
1148
G255
-5579
121
1182
G187
-6055
121
1216
G119
-6531
121
1149
G253
-5593
256
1183
G185
-6069
256
1217
G117
-6545
256
1150
G251
-5607
121
1184
G183
-6083
121
1218
G115
-6559
121
Version 1.5
Page 28 of 300
2013/04
ST7789S
PAD
PAD
PIN Name
X
No.
Y
PAD
PIN Name
X
No.
Y
PIN Name
X
Y
No.
1219
G113
-6573
256
1240
G71
-6867
121
1261
G29
-7161
256
1220
G111
-6587
121
1241
G69
-6881
256
1262
G27
-7175
121
1221
G109
-6601
256
1242
G67
-6895
121
1263
G25
-7189
256
1222
G107
-6615
121
1243
G65
-6909
256
1264
G23
-7203
121
1223
G105
-6629
256
1244
G63
-6923
121
1265
G21
-7217
256
1224
G103
-6643
121
1245
G61
-6937
256
1266
G19
-7231
121
1225
G101
-6657
256
1246
G59
-6951
121
1267
G17
-7245
256
1226
G99
-6671
121
1247
G57
-6965
256
1268
G15
-7259
121
1227
G97
-6685
256
1248
G55
-6979
121
1269
G13
-7273
256
1228
G95
-6699
121
1249
G53
-6993
256
1270
G11
-7287
121
1229
G93
-6713
256
1250
G51
-7007
121
1271
G9
-7301
256
1230
G91
-6727
121
1251
G49
-7021
256
1272
G7
-7315
121
1231
G89
-6741
256
1252
G47
-7035
121
1273
G5
-7329
256
1232
G87
-6755
121
1253
G45
-7049
256
1274
G3
-7343
121
1233
G85
-6769
256
1254
G43
-7063
121
1275
G1
-7357
256
1234
G83
-6783
121
1255
G41
-7077
256
1276
DUMMY
-7371
121
1235
G81
-6797
256
1256
G39
-7091
121
1277
DUMMY
-7385
256
1236
G79
-6811
121
1257
G37
-7105
256
1278
DUMMY
-7399
121
1237
G77
-6825
256
1258
G35
-7119
121
A1
-7480
255
1238
G75
-6839
121
1259
G33
-7133
256
A2
7480
255
1239
G73
-6853
256
1260
G31
-7147
121
Version 1.5
Page 29 of 300
2013/04
ST7789S
5 BLOCK DIAGRAM
Version 1.5
Page 30 of 300
2013/04
ST7789S
6 PIN DESCRIPTION
6.1 Power Supply Pins
Name
I/O
VDD
I
Power Supply for Analog, Digital System and Booster Circuit.
VDD
VDDI
I
Power Supply for I/O System.
VDDI
VDDI_LED
I
AGND
I
System Ground for Analog System and Booster Circuit.
GND
DGND
I
System Ground for I/O System and Digital System.
GND
Version 1.5
Description
Power Supply for LED driver.
If not used, please fix this pad to GND level.
Page 31 of 300
Connect Pin
-
2013/04
ST7789S
6.2 Interface Logic Pins
Name
I/O
Description
Connect Pin
-The MCU interface mode select.
IM3
IM2
IM1
IM0
MPU Interface Mode
Data pin
0
0
0
0
80-8bit parallel I/F
DB[7:0]
0
0
0
1
80-16bit parallel I/F
DB[15:0]
0
0
1
0
80-9bit parallel I/F
DB[8:0]
0
0
1
1
80-18bit parallel I/F
DB[17:0],
3-line 9bit serial I/F
SDA: in/out
0
1
0
1
2 data lane serial I/F
IM3, IM2,
IM1, IM0
SDA: in/out
WRX: in
DGND/VDDI
I
0
1
1
0
4-line 8bit serial I/F
SDA: in/out
1
0
0
0
80-16bit parallel I/F Ⅱ
1
0
0
1
80-8bit parallel I/F Ⅱ
DB[17:10]
1
0
1
0
80-18bit parallel I/F Ⅱ
DB[17:0],
1
0
1
1
80-9bit parallel I/F Ⅱ
DB[17:9]
1
1
0
1
3-line 9bit serial I/F Ⅱ
1
1
1
0
4-line 8bit serial I/F Ⅱ
DB[17:10],
DB[8:1]
SDA: in/
SDO: out
SDA:in/
SDO: out
-Select to access extension command (“Low”: system command 1,
EXTC
I
“High”: system command 1 and 2).
DGND/VDDI
-When programming NVM, this pin should connect to high level.
-When programming NVM, it needs external power supply voltage
VPP
I
(7.5V); the current of Ivpp must be more than 10mA.
-
-If not used, let this pin open.
-This signal will reset the device and it must be applied to properly
RESX
I
initialize the chip.
MCU
-Signal is active low.
-Chip selection pin
CSX
I
Low enable.
MCU
High disable.
-Display data/command selection pin in parallel interface.
DCX
I
-This pin is used to be serial interface clock.
MCU
DCX=’1’: display data or parameter.
Version 1.5
Page 32 of 300
2013/04
ST7789S
Name
I/O
Description
Connect Pin
DCX=’0’: command data.
-If not used, please fix this pin at VDDI or DGND.
RDX
I
-Read enable in 8080 MCU parallel interface.
-If not used, please fix this pin at VDDI or DGND.
MCU
-Write enable in MCU parallel interface.
WRX
I
- Display data/command selection pin in 4-line serial interface.
- Second Data lane in 2 data lane serial interface.
MCU
-If not used, please fix this pin at VDDI or DGND.
VSYNC
I
HSYNC
I
ENABLE
I
DOTCLK
I
-Vertical (Frame) synchronizing input signal for RGB interface operation.
-If not used, please fix to the VDDI or DGND.
-Horizontal (Line) synchronizing input signal for RGB interface operation.
- If not used, please fix to VDDI or DGND.
-Data enable signal for RGB interface operation.
-If not used, please fix this pin at VDDI or DGND.
-Dot clock signal for RGB interface operation.
-If not used, please fix this pin at VDDI or DGND.
MCU
MCU
MCU
MCU
-When IM3: Low, SPI interface input/output pin.
SDA
I/O
-When IM3: High, SPI interface input pin.
-The data is latched on the rising edge of the SCL signal.
MCU
-If not used, please fix this pin at VDDI or DGND level.
-SPI interface output pin.
SDO
O
-The data is output on the falling edge of the SCL signal.
MCU
-If not used, let this pin open.
-DB[17:0] are used as MCU parallel interface data bus.
8-bit I/F: when IM3:0, DB[7:0] are used; when IM3:1, DB[17:10] are used.
9-bit I/F: when IM3:0, DB[8:0] are used; when IM3:1, DB[17:9] are used.
16-bit I/F: when IM3:0, DB[15:0] are used; when IM3:1, DB[17:10] and
DB[8:1] are used.
DB[17:0]
I/O
18-bit I/F: DB[17:0] are used.
MCU
-DB[17:0] are used as RGB interface data bus.
6-bit RGB I/F: DB[5:0] are used.
16-bit RGB I/F: DB[17:13], DB[11:1] are used.
18-bit RGB I/F: DB[17:0] are used.
-If not used, please fix this pin at VDDI or DGND.
TE
Version 1.5
O
-Tearing effect signal is used to synchronize MCU to frame memory
writing.
Page 33 of 300
MCU
2013/04
ST7789S
Name
I/O
Description
Connect Pin
-If not used, please let this pin open
Note1. “1” = VDDI level, “0” = DGND level.
Note2. When in parallel mode, unused data pins must be connected to “1” or “0”.
Note3. When CSX=”1”, there is no influence to the parallel and serial interface.
Version 1.5
Page 34 of 300
2013/04
ST7789S
6.3 Driver Output Pins
Name
I/O
S1 to S720
O
Description
-Source driver output pad.
Connect pin
LCD
-Gate driver output pad.
G1 to G320
O
VGH: Selecting Gate Lines Level.
LCD
VGL: Non-selecting Gate Lines Level.
AVDD
O
-Power pad for analog circuit.
OPEN
VAP(GVDD)
O
- A power output of grayscale voltage generator.
OPEN
AVCL
O
- A power supply pin for generating VAN.
OPEN
VAN(GVCL)
O
- A power output (Negative) of grayscale voltage generator.
OPEN
VGH
O
- Power output pin for gate driver
OPEN
VGL
O
- Power output (Negative) pin for gate driver
OPEN
VCC
O
- Monitoring pin of internal digital reference voltage.
OPEN
VCOM
O
- A power supply for the TFT-LCD common electrode.
LED_PWM
O
LED_EN
O
-Output pad for PWM output signal to driving LED.
-If not used, keep it open.
-Output pad for enabling LED.
-If not used, keep it open.
Common
Electrode
-
-
6.4 Test and other pins
TEST3~TEST0
I
TE2
O
TESTO6~TESTO1
O
Input pins for testing.
Please open these pins.
Output pin for testing.
Please keep this pin floating.
Output pins for testing.
Please keep these pins floating.
OPEN
OPEN
OPEN
These pins are dummy (no electrical characteristic)
DUMMY
-
Can pass signal through these pads on TFT panel.
OPEN
Please open these pins.
DUMMYR1
DUMMYR2
-
These pins are dummy (no electrical characteristic).
DUMMYR1 and DUMMYR2 are connected each other internally.
OPEN
VAG
VDDS
VDDGX
O
Used for monitoring
Please keep these pins floating.
OPEN
V20
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7 DRIVER ELECTRICAL CHARACTERISTICS
7.1 Absolute Operation Range
Item
Symbol
Rating
Unit
Supply Voltage
VDD
- 0.3 ~ +4.6
V
Supply Voltage (Logic)
VDDI
- 0.3 ~ +4.6
V
Driver Supply Voltage
VGH-VGL
-0.3 ~ +30.0
V
Logic Input Voltage Range
VIN
0.5 ~ VDDI + 0.5
V
Logic Output Voltage Range
VO
0.5 ~ VDDI + 0.5
V
Operating Temperature Range
TOPR
-30 ~ +85
℃
Storage Temperature Range
TSTG
-40 ~ +125
℃
Table 1 Absolute Operation Range
Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded.
Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the recommend range.
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7.2 DC Characteristics
Parameter
Symbol
Specification
Condition
MIN.
Unit
Related
Pins
TYP.
MAX.
2.4
2.75
3.3
V
1.65
1.8
3.3
V
Power & Operation Voltage
Operating
System Voltage
VDD
Interface Operation Voltage
VDDI
Gate Driver High Voltage
VGH
12.2
14.97
V
Gate Driver Low Voltage
VGL
-12.5
-7.16
V
21.97
24.7
V
Note 5
voltage
I/O Supply
Voltage
Gate Driver Supply Voltage
| VGH-VGL |
Note 4
Input / Output
Logic-High Input Voltage
VIH
0.7VDDI
VDDI
V
Note 1
Logic-Low Input Voltage
VIL
VSS
0.3VDDI
V
Note 1
Logic-High Output Voltage
VOH
IOH = -1.0mA
0.8VDDI
VDDI
V
Note 1
Logic-Low Output Voltage
VOL
IOL = +1.0mA
VSS
0.2VDDI
V
Note 1
Logic-High Input Current
IIH
VIN = VDDI
1
uA
Note 1
Logic-Low Input Current
IIL
VIN = VSS
-1
uA
Note 1
Input Leakage Current
IIL
IOH = -1.0mA
-0.1
uA
Note 1
+0.1
VCOM Voltage
VCOM amplitude
VCOM
VSS
V
Source Driver
Source Output Range
Gamma Reference
Voltage(Positive)
Gamma Reference
Voltage(Negative)
Vsout
VAN
VAP
V
VAP
4.45
6.4
V
VAN
-4.6
-2.65
V
20
us
Note 2
35
mV
Note 3
Below with 99%
Source Output Settling Time
Tr
Output Offset Voltage
VOFFSET
precision
Note 6
Table 2 Basic DC Characteristics
Notes:
1. TA= -30 to 70℃ (to +85℃ no damage).
2. Source channel loading= 2KΩ+12pF/channel, Gate channel loading=5KΩ+40pF/channel.
3. The Max. value is between measured point of source output and gamma setting value.
4. When evaluating the maximum and minimum of VGH, VDD=2.8V.
5. The maximum value of |VGH-VGL| can no over 30V.
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6. Default register setting of Vcom and Vcomoffset is 20h
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7.3 Power Consumption
Ta=25℃, Frame rate = 60Hz, Registers setting are IC default setting.
Current Consumption
Operation Mode
Typical
Image
Maximum
IDDI
IDD
IDDI
IDD
(mA)
(mA)
(mA)
(mA)
Normal Mode
Black
0.005
6.0
0.01
7.5
Partial + Idle Mode (48 lines)
Black
0.005
5.0
0.01
6.0
Sleep-in Mode
N/A
0.005
0.015
0.01
0.03
Table 3 Power Consumption
Notes:
1. The Current Consumption is DC characteristics of ST7789S.
2. Typical: VDDI=1.8V, VDD=2.75V; Maximum: VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V
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7.4 AC Characteristics
7.4.1
8080 Series MCU Parallel Interface Characteristics: 18/16/9/8-bit Bus
Figure 1 Parallel Interface Timing Characteristics (8080-Series MCU Interface)
VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta= -30 to 70 ℃
Signal
D/CX
CSX
WRX
RDX (ID)
RDX
(FM)
D[17:0]
Version 1.5
Symbol
Parameter
Min
Max
Unit
TAST
Address setup time
0
ns
TAHT
Address hold time (Write/Read)
10
ns
TCHW
Chip select “H” pulse width
0
ns
TCS
Chip select setup time (Write)
15
ns
TRCS
Chip select setup time (Read ID)
45
ns
TRCSFM
Chip select setup time (Read FM)
355
ns
TCSF
Chip select wait time (Write/Read)
10
ns
TCSH
Chip select hold time
10
ns
TWC
Write cycle
66
ns
TWRH
Control pulse “H” duration
15
ns
TWRL
Control pulse “L” duration
15
ns
TRC
Read cycle (ID)
160
ns
TRDH
Control pulse “H” duration (ID)
90
ns
TRDL
Control pulse “L” duration (ID)
45
ns
TRCFM
Read cycle (FM)
450
ns
TRDHFM
Control pulse “H” duration (FM)
90
ns
TRDLFM
Control pulse “L” duration (FM)
355
ns
TDST
Data setup time
10
ns
Description
-
-
When read ID data
When read from
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frame memory
For CL=30pF
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TDHT
Data hold time
10
TRAT
Read access time (ID)
40
ns
TRATFM
Read access time (FM)
340
ns
TODH
Output disable time
80
ns
20
ns
Table 4 8080 Parallel Interface Characteristics
Figure 2 Rising and Falling Timing for I/O Signal
Figure 3 Write-to-Read and Read-to-Write Timing
Note: The rising time and falling time (Tr, Tf) of input signal and fall time are specified at 15 ns or less. Logic high and low levels are
specified as 30% and 70% of VDDI for Input signals.
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7.4.2
Serial Interface Characteristics (3-line serial):
Figure 4 3-line serial Interface Timing Characteristics
VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 ℃
Signal
Symbol
Parameter
Min
TCSS
Chip select setup time (write)
15
ns
TCSH
Chip select hold time (write)
15
ns
TCSS
Chip select setup time (read)
60
ns
TSCC
Chip select hold time (read)
65
ns
TCHW
Chip select “H” pulse width
40
ns
TSCYCW
Serial clock cycle (Write)
66
ns
TSHW
SCL “H” pulse width (Write)
15
ns
TSLW
SCL “L” pulse width (Write)
15
ns
TSCYCR
Serial clock cycle (Read)
150
ns
TSHR
SCL “H” pulse width (Read)
60
ns
TSLR
SCL “L” pulse width (Read)
60
ns
SDA
TSDS
Data setup time
10
ns
(DIN)
TSDH
Data hold time
10
ns
TACC
Access time
10
50
ns
For maximum CL=30pF
TOH
Output disable time
15
50
ns
For minimum CL=8pF
CSX
SCL
DOUT
Max
Unit
Description
Table 5 3-line serial Interface Characteristics
Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as
30% and 70% of VDDI for Input signals.
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7.4.3
Serial Interface Characteristics (4-line serial):
Figure 5 4-line serial Interface Timing Characteristics
VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 ℃
Signal
Symbol
Parameter
MIN
TCSS
Chip select setup time (write)
15
ns
TCSH
Chip select hold time (write)
15
ns
TCSS
Chip select setup time (read)
60
ns
TSCC
Chip select hold time (read)
65
ns
TCHW
Chip select “H” pulse width
40
ns
TSCYCW
Serial clock cycle (Write)
66
ns
TSHW
SCL “H” pulse width (Write)
15
ns
TSLW
SCL “L” pulse width (Write)
15
ns
TSCYCR
Serial clock cycle (Read)
150
ns
TSHR
SCL “H” pulse width (Read)
60
ns
TSLR
SCL “L” pulse width (Read)
60
ns
TDCS
D/CX setup time
10
ns
TDCH
D/CX hold time
10
ns
SDA
TSDS
Data setup time
10
ns
(DIN)
TSDH
Data hold time
10
ns
TACC
Access time
10
50
ns
For maximum CL=30pF
TOH
Output disable time
15
50
ns
For minimum CL=8pF
CSX
SCL
D/CX
DOUT
MAX
Unit
Description
-write command & data
ram
-read command & data
ram
Table 6 4-line serial Interface Characteristics
Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as
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30% and 70% of VDDI for Input signals.
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7.4.4
RGB Interface Characteristics:
Trgbf
Trgbr
TSYNCS
HSYNC
VSYNC
TENS
ENABLE
Trgbf
V IH
V IH
VIL
V IL
T rgbr
PWDL
V IH
DOTCLK
T ENH
V IL
V IL
PWDH
V IH
V IH
TCYCD
TPDS
TPDH
V IH
Data Bus
Write
V IH
Write Data
V IL
V IL
Figure 6 RGB Interface Timing Characteristics
VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=-30 ~ 70 ℃
Signal
HSYNC,
VSYNC
ENABLE
DOTCLK
DB
Symbol
Parameter
MIN
MAX
Unit
TSYNCS
VSYNC, HSYNC Setup Time
30
-
ns
TENS
Enable Setup Time
25
-
ns
TENH
Enable Hold Time
25
-
ns
PWDH
DOTCLK High-level Pulse Width
60
-
ns
PWDL
DOTCLK Low-level Pulse Width
60
-
ns
TCYCD
DOTCLK Cycle Time
120
-
ns
Trghr, Trghf
DOTCLK Rise/Fall time
-
20
ns
TPDS
PD Data Setup Time
50
-
ns
TPDH
PD Data Hold Time
50
-
ns
Description
Table 7 18/16 Bits RGB Interface Timing Characteristics
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7.4.5
Reset Timing:
Shorter than 5us
TRW
RESX
Display
status
TRT
Normal operation
Initial condition
(Default for H/W reset)
During reset
Figure 7 Reset Timing
VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=-30 ~ 70 ℃
Related Pins
Symbol
Parameter
MIN
MAX
Unit
TRW
Reset pulse duration
10
-
us
TRT
Reset cancel
-
5 (Note 1, 5)
ms
120 (Note 1, 6, 7)
ms
RESX
Table 8 Reset Timing
Notes:
1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NVM (or similar device) to
registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX.
2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below:
RESX Pulse
Action
Shorter than 5us
Reset Rejected
Longer than 9us
Reset
Between 5us and 9us
Reset starts
3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120
ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode.) and then return to Default condition
for Hardware Reset.
4. Spike Rejection also applies during a valid reset pulse as shown below:
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5. When Reset applied during Sleep In Mode.
6. When Reset applied during Sleep Out Mode.
7. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for
120msec.
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8 FUNCTION DESCRIPTION
8.1 MPU Interface Type Selection
ST7789S supports 8/16/9/18 bit parallel data bus for 8080 series CPU, RGB serial interfaces. Selection
of these interfaces are set by IM[3:0] pins as shown below.
IM3
IM2
IM1
IM0
Interface
Read Back Data Bus Selection
0
0
0
0
80-8bit parallel I/F
DB[7:0]
0
0
0
1
80-16bit parallel I/F
DB[15:0]
0
0
1
0
80-9bit parallel I/F
DB[8:0]
0
0
1
1
80-18bit parallel I/F
DB[17:0],
0
1
0
1
3-line 9bit serial I/F
SDA: in/out
2 data lane serial I/F
SDA: in/out, WRX: in
0
1
1
0
4-line 8bit serial I/F
SDA: in/out
1
0
0
0
80-16bit parallel I/F Ⅱ
DB[17:10], DB[8:1]
1
0
0
1
80-8bit parallel I/F Ⅱ
DB[17:10]
1
0
1
0
80-18bit parallel I/F Ⅱ
DB[17:0],
1
0
1
1
80-9bit parallel I/F Ⅱ
DB[17:9]
1
1
0
1
3-line 9bit serial I/F Ⅱ
SDA: in/ SDO: out
1
1
1
0
4-line 8bit serial I/F Ⅱ
SDA: in/ SDO: out
Table 9 Interface Type Selection
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8.2 8080-Ⅰ Series MCU Parallel Interface
The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data
parallel interface, 19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The
chip-select CSX (active low) enables/disables the parallel interface. RESX (active low) is an external reset
signal. WRX is the parallel data write enable, RDX is the parallel data read enable and D[17:0] is parallel data
bus.
The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag.
When D/CX=’1’, D[17:0] bits is either display data or command parameter. When D/C=’0’, D[17:0] bits is
command. The interface functions of 8080-series parallel interface are given in following table.
IM3
0
0
0
0
IM2
IM1
0
0
0
0
0
0
1
1
IM0
Interface
D/CX
RDX
WRX
Read back selection
0
1
↑
Write 8-bit command (D7 to D0)
8-bit
1
1
↑
Write 8-bit display data or 8-bit parameter (D7 to D0)
parallel
1
↑
1
Read 8-bit display data (D7 to D0)
1
↑
1
Read 8-bit parameter or status (D7 to D0)
0
1
↑
Write 8-bit command (D7 to D0)
16-bit
1
1
↑
Write 16-bit display data or 8-bit parameter (D15 to D0)
parallel
1
↑
1
Read 16-bit display data (D15 to D0)
1
↑
1
Read 8-bit parameter or status (D7 to D0)
0
1
↑
Write 8-bit command (D7 to D0)
9-bit
1
1
↑
Write 9-bit display data or 8-bit parameter (D8 to D0)
parallel
1
↑
1
Read 9-bit display data (D8 to D0)
1
↑
1
Read 8-bit parameter or status (D7 to D0)
0
1
↑
Write 8-bit command (D7 to D0)
18-bit
1
1
↑
Write 18-bit display data or 8-bit parameter (D17 to D0)
parallel
1
↑
1
Read 18-bit display data (D17 to D0)
1
↑
1
Read 8-bit parameter or status (D7 to D0)
0
1
0
1
Table 10 the function of 8080-series parallel interface
8.2.1
Write cycle sequence
The write cycle means that the host writes information (command / data) to the display via the interface.
Each write cycle (WRX high-low-high sequence) consists of 3 control signals (DCX, RDX, WRX) and data
signals (DB[17:0]). DCX bit is a control signal, which tells if the data is a command or a data. The data signals
are the command if the control signal is low (=’0’) and vice versa it is data (=’1’).
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Figure 8 8080-Series WRX Protocol
Note: WRX is an unsynchronized signal (It can be stopped).
Figure 9 8080-Series Parallel Bus Protocol, Write to Register or Display RAM
8.2.2
Read cycle sequence
The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via
interface. The driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads
data when there is a rising edge of RDX.
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Figure 10 8080-series RDX protocol
Note: RDX is an unsynchronized signal (It can be stopped).
Read parameter
D[17:0]
Read display data
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
D[17:0]
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
Host D[17:0]
Host to LCD
S
CMD
Driver D[17:0]
LCD to Host
S
RESX “1”
CSX
D/CX
RDX
WRX
Hi-Z
Hi-Z
DM
CMD
PA1
Hi-Z
Hi-Z
P
DM & data
CMD: write command code
PA: parameter or display data
PAN-2
PAN-1
P
Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.
Figure 11 8080-series parallel bus protocol, read data from register or display RAM
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8.3 8080-Ⅱ series MCU Parallel Interface
The MCU uses one of following interface: 11-lines with 8-data parallel interface, 12-lines with 9-data
parallel interface, 19-lines with 16-data parallel interface, or 21-lines with 18-data parallel interface. The
chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset
signal. The R/WX is the Read/Write flag and D[17:0] is parallel data bus.
The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag.
When D/CX=’1’, D[17:0] bits is either display data or command parameter. When D/C=’0’, D[17:0] bits is
command.
The 8080-Ⅱ series bi-directional interface can be used for communication between the micro controller
and LCD driver. Interface bus width can be selected with IM3, IM2, IM1 and IM0.The interface functions of
8080-Ⅱ series parallel interface are given in Table 11 The function of 8080-Ⅱ series parallel interface.
IM3 IM2 IM1 IM0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
Interface
D/CX RDX WRX
0
1
↑
Write 8-bit command (D[8:1])
1
1
↑
Write 16-bit display data or 8-bit parameter (D[17:10], D[8:1])
1
↑
1
Read 16-bit Display data (D[17:10], D[8:1])
1
↑
1
Read 8-bit parameter or status (D[8:1])
0
1
↑
Write 8-bit command (D[17:10])
1
1
↑
Write 8-bit display data or 8-bit parameter (D[17:10])
1
↑
1
Read 8-bit Display data (D[17:10])
1
↑
1
Read 8-bit parameter or status (D[17:10])
0
1
↑
Write 8-bit command (D[8:1])
1
1
↑
Write 18-bit display data or 8-bit parameter (D[17:0], D[8:1])
1
↑
1
Read 18-bit Display data (D[17:0])
1
↑
1
Read 8-bit parameter or status (D[8:1])
0
1
↑
Write 8-bit command (D[17:10])
1
1
↑
Write 9-bit display data or 8-bit parameter (D[17:9])
1
↑
1
Read 9-bit Display data (D[17:9])
1
↑
1
Read 8-bit parameter or status (D[17:10])
16-bit Parallel
8-bit Parallel
18-bit Parallel
9-bit Parallel
Function
Table 11 The function of 8080-Ⅱ series parallel interface
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8.4 Serial Interface
IM3
IM2
IM1
IM0
Interface
Read back selection
0
1
0
1
3-line serial interface Ⅰ
0
1
1
0
4-line serial interface Ⅰ
Via the read instruction (8-bit, 24-bit and 32-bit read
1
1
0
1
3-line serial interface Ⅱ
parameter)
1
1
1
0
4-line serial interface Ⅱ
Table 12 Selection of serial interface
The serial interface is either 3-lines/9-bits or 4-lines/8-bits bi-directional interface for communication
between the micro controller and the LCD driver. The 3-lines serial interface use: CSX (chip enable), SCL
(serial clock) and SDA (serial data input/output), and the 4-lines serial interface use: CSX (chip enable), D/CX
(data/ command flag), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for
interface with MCU only, so it can be stopped when no communication is necessary.
8.4.1
Pin description
3-line serial interface Ⅰ
Pin Name
Description
CSX
Chip selection signal
DCX
Clock signal
SDA
Serial input/output data
4-line serial interface Ⅰ
Pin Name
Description
CSX
Chip selection signal
WRX
Data is regarded as a command when WRX is low
Data is regarded as a parameter or data when WRX is high
DCX
Clock signal
SDA
Serial input/output data
3-line serial interface Ⅱ
Pin Name
Description
CSX
Chip selection signal
DCX
Clock signal
SDA
Serial input data
SDO
Serial output data
4-line serial interface Ⅱ
Pin Name
Description
CSX
Chip selection signal
WRX
Version 1.5
Data is regarded as a command when WRX is low
Data is regarded as a parameter or data when WRX is high
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DCX
Clock signal
SDA
Serial input data
SDO
Serial output data
Table 13 pin description of serial interface
8.4.2
Command write mode
The write mode of the interface means the micro controller writes commands and data to the LCD driver.
3-lines serial data packet contains a control bit D/CX and a transmission byte. In 4-lines serial interface, data
packet contains just transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is “low”, the
transmission byte is interpreted as a command byte. If D/CX is “high”, the transmission byte is stored in the
display data RAM (memory write command), or command register as parameter.
Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is
initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX
enables the serial interface and indicates the start of data transmission.
Figure 12 Serial interface data stream format
When CSX is “high”, SCL clock is ignored. During the high period of CSX the serial interface is initialized.
At the falling edge of CSX, SCL can be high or low. SDA is sampled at the rising edge of SCL. D/CX indicates
whether the byte is command (D/CX=’0’) or parameter/RAM data (D/CX=’1’). D/CX is sampled when first
rising edge of SCL (3-line serial interface) or 8th rising edge of SCL (4-line serial interface). If CSX stays low
after the last bit of command/data byte, the serial interface expects the D/CX bit (3-line serial interface) or D7
(4-line serial interface) of the next byte at the next rising edge of SCL..
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Figure 13 3-line serial interface write protocol (write to register with control bit in transmission)
Figure 14 4-line serial interface write protocol (write to register with control bit in transmission)
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8.4.3
Read function
The read mode of the interface means that the micro controller reads register value from the driver. To
achieve read function, the micro controller first has to send a command (read ID or register command) and
then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a
new command is send (see the below figure). The driver samples the SDA (input data) at rising edge of SCL,
but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the
rising edge of SCL.
After the read status command has been sent, the SDA line must be set to tri-state no later than at the
falling edge of SCL of the last bit.
8.4.4
3-line serial interface Ⅰ/Ⅱ protocol
3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
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3-line serial protocol (for RDDID command: 24-bit read)
3-line Serial Protocol (for RDDST command: 32-bit read)
Figure 15 3-line serial interface read protocol
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8.4.5
4-line serial protocol
4-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
S
TB
TB
P
S
CSX
SCL
D/CX
Interface-І
0
SDA
D7
D6
D5
D4
D3
D2
D1
D0
SDA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
D7
D7
Interface-!
SDO
Hi-Z
D7
D6
D5
D4
D3
D2
D1
D0
4-line serial protocol (for RDDID command: 24-bit read)
4-line Serial Protocol (for RDDST command: 32-bit read)
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Figure 16 4-line serial interface read protocol
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8.4.6
2 data lane serial Interface
Interface selection:
IM3
IM2
IM1
IM0
Interface
Read back selection
0
1
0
1
2 data lane serial interface
Via the read instruction (8-bit, 24-bit and 32-bit
read)
Table 14 IM pin selection
2-wire data lane serial interface use: CSX (chip enable), DCX (serial clock) and SDA (serial data
input/output 1), and WRX (serial data input 2). To enter this interface, command E7h need set 10h.
2 data lane hardware suggestion and Pin description:
2 data lane serial interface, IM[3:0]=0101
Figure 17 Hardware suggestion of 2 data lane serial interface
Pin Name
Description
CSX
Chip selection signal
DCX
Clock signal
SDA
Serial data input/output1
WRX
Serial data input2
Table 15 Pin description of 2 data lane serial interface
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Command write mode:
The command write protocol of 2-wire data lane serial interface is the same with the 3-line serial interface,
so users can ignore the input data of WRX.
Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is
initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX
enables the serial interface and indicates the start of data transmission.
Figure 18 3-line serial interface write protocol (write to register with control bit in transmission)
SRAM write mode:
The SRAM write mode of 2-wire data line serial interface need use SDA pin and WRX pin to be data input
pins.
Read function:
The read mode of 2-wire data lane serial interface is the same with the 3-line serial interface and WRX
pin can be ignored. To achieve read function, the micro controller first has to send a command (read ID or
register command) and then the following byte is transmitted in the opposite direction. After that CSX is
required to go to high before a new command is send (see the below figure). The driver samples the SDA
(input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro
controller is supported to read at the rising edge of SCL.
After the read status command has been sent, the SDA line must be set to tri-state no later than at the
falling edge of SCL of the last bit.
3-line serial interface Ⅰ/Ⅱ
Ⅱ protocol:
3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
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3-line serial protocol (for RDDID command: 24-bit read)
3-line Serial Protocol (for RDDST command: 32-bit read)
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Figure 19 3-line serial interface read protocol
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8.5 Data Transfer Break and Recovery
If there is a break in data transmission by RESX pulse, while transferring a command or frame memory
data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will
reject the previous bits and have reset the interface such that it will be ready to receive command data again
when the chip select line (CSX) is next activated after RESX have been HIGH state.
If there is a break in data transmission by CSX pulse, while transferring a command or frame memory
data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will
reject the previous bits and have reset the interface such that it will be ready to receive the same byte
re-transmitted when the chip select line (CSX) is next activated.
If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter
before the last one and if the host then sends a new command rather than re-transmitting the parameter that
was interrupted, then the parameters that were successfully sent are stored and the parameter where the
break occurred is rejected. The interface is ready to receive next byte as shown below.
Figure 20 Write interrupts recovery (serial interface)
If a 2 or more parameter commands are being sent and a break occurs by the other command before the
last one is sent, then the parameters that were successfully sent are stored and the other parameter of that
command remains previous value.
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Figure 21 Write interrupts recovery (both serial and parallel Interface)
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8.6 Data Transfer Pause
It will be possible when transferring a command, frame memory data or multiple parameter data to invoke
a pause in the data transmission. If the chip select line is released after a whole byte of a frame memory data
or multiple parameter data has been completed, then driver will wait and continue the frame memory data or
parameter data transmission from the point where it was paused. If the chip select Line is released after a
whole byte of a command has been completed, then the display module will receive either the command‘s
parameters (if appropriate) or a new command when the chip select line is next enabled as shown below.
This applies to the following 4 conditions:
1) Command-Pause-Command
2) Command-Pause-Parameter
3) Parameter-Pause-Command
4) Parameter-Pause-Parameter
8.6.1
Parallel interface pause
Figure 22 Parallel bus pause protocol (paused by CSX)
8.7 Data Transfer Mode
The module has three kinds color modes for transferring data to the display RAM. These are 12-bit color
per pixel, 16-bit color per pixel and 18-bit color per pixel. The data format is described for each interface. Data
can be downloaded to the frame memory by 2 methods.
8.7.1
Method 1
The image data is sent to the frame memory in successive frame writes, each time the frame memory is
filled, the frame memory pointer is reset to the start point and the next frame is written.
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8.7.2
Method 2
The image data is sent and at the end of each frame memory download, a command is sent to stop frame
memory write. Then start memory write command is sent, and a new frame is downloaded.
Note 1: These apply to all data transfer Color modes on both serial and parallel interfaces.
Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in
the frame memory.
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8.8 Data Color Coding
8.8.1
8080-Ⅰ series 8-bit Parallel Interface
The 8080-Ⅰ series 8-bit parallel interface of ST7789S can be used by setting IM[3:0]=”0000b”. Different
display data formats are available for three Colors depth supported by listed below.
- 4k colors, RGB 4,4,4-bit input.
- 65k colors, RGB 5,6,5-bit input.
- 262k colors, RGB 6,6,6-bit input.
8.8.2
RESX
8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah=”03h”
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D7
0
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
D6
0
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
D5
1
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
D4
0
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
D3
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D2
1
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D1
0
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D0
0
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
Pixel n
Pixel n+1
12 bits
12 bits
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 2 pixel data with the 12-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
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8.8.3
8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3Ah=”05h”
There is 1pixel (3 sub-pixels) per 2-byte
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D7
0
R1, Bit 4
G1, Bit 2
R2, Bit 4
G2, Bit 2
D6
0
R1, Bit 3
G1, Bit 1
R2, Bit 3
G2, Bit 1
D5
1
R1, Bit 2
G1, Bit 0
R2, Bit 2
G2, Bit 0
D4
0
R1, Bit 1
B1, Bit 4
R2, Bit 1
B2, Bit 4
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n
Pixel n+1
16 bits
16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
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8.8.4
8-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”
There is 1pixel (3 sub-pixels) per 3-bytes.
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D7
0
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
D6
0
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
D5
1
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
D4
0
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
D3
1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
D2
1
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
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8.8.5
8080-Ⅱ series 8-bit Parallel Interface
The 8080-Ⅱ series 8-bit parallel interface of ST7789S can be used by setting IM[3:0]=”1001b”. Different
display data formats are available for three Colors depth supported by listed below.
- 65k colors, RGB 5,6,5-bit input.
- 262k colors, RGB 6,6,6-bit input.
8.8.6
8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3Ah=”05h”
Note 1: The data order is as follows, MSB=D17, LSB=D10 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit
0 for Red and Blue data.
Note 2: 2-times transfer transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
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8.8.7
RESX
8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3Ah=”06h”
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
0
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
D16
0
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
D15
1
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
D14
0
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
D13
1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
D12
1
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
D11
0
-
-
-
-
D10
0
-
-
-
-
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D17, LSB=D10 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
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8.8.8
8080-Ⅰ series 16-Bit Parallel Interface
The 8080-Ⅰ series 16-bit parallel interface of ST7789S can be used by setting IM[3:0]=”0001b”. Different
display data formats are available for three colors depth supported by listed below.
- 4k colors, RGB 4,4,4-bit input
- 65k colors, RGB 5,6,5-bit input
- 262k colors, RGB 6,6,6-bit input
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8.8.9
16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah=”03h”
There is 1pixel (3 sub-pixels) per 1byte
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D15
-
-
-
-
-
D14
-
-
-
-
-
D13
-
-
-
-
-
D12
-
-
-
-
-
D11
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D10
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D9
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D8
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D7
0
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D6
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D5
1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D4
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
12 bits
12 bits
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.
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8.8.10 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input) 65K-Color, 3Ah=”05h”
There is 1 pixel (3 sub-pixels) per 1 byte
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2: 1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
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8.8.11 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
MDT[1:0]=”00b”
There are 2 pixels (6 sub-pixels) per 3 bytes
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D15
-
R1, Bit 5
B1, Bit 5
G2, Bit 5
R3, Bit 5
D14
-
R1, Bit 4
B1, Bit 4
G2, Bit 4
R3, Bit 4
D13
-
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
D12
-
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
D11
-
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
D10
-
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
D9
-
-
-
-
-
D8
-
-
-
-
-
D7
0
G1, Bit 5
R2, Bit 5
B2, Bit 5
G3, Bit 5
D6
0
G1, Bit 4
R2, Bit 4
B2, Bit 4
G3, Bit 4
D5
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D4
0
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D3
1
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D2
1
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
-
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
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8.8.12 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
MDT[1:0]=”01b”
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D15
-
R1, Bit 5
B1, Bit 5
R2, Bit 5
B2, Bit 5
D14
-
R1, Bit 4
B1, Bit 4
R2, Bit 4
B2, Bit 4
D13
-
R1, Bit 3
B1, Bit 3
R2, Bit 3
B2, Bit 3
D12
-
R1, Bit 2
B1, Bit 2
R2, Bit 2
B2, Bit 2
D11
-
R1, Bit 1
B1, Bit 1
R2, Bit 1
B2, Bit 1
D10
-
R1, Bit 0
B1, Bit 0
R2, Bit 0
B2, Bit 0
D9
-
-
-
-
-
D8
-
-
-
-
-
D7
0
G1, Bit 5
-
G2, Bit 5
-
D6
0
G1, Bit 4
-
G2, Bit 4
-
D5
1
G1, Bit 3
-
G2, Bit 3
-
D4
0
G1, Bit 2
-
G2, Bit 2
-
D3
1
G1, Bit 1
-
G2, Bit 1
-
D2
1
G1, Bit 0
-
G2, Bit 0
-
D1
0
-
-
-
-
D0
0
-
-
-
-
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
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8.8.13 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
MDT[1:0]=”10b”
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D15
-
R1, Bit 5
B1, Bit 1
R2, Bit 5
B2, Bit 1
D14
-
R1, Bit 4
B1, Bit 0
R2, Bit 4
B2, Bit 0
D13
-
R1, Bit 3
-
R2, Bit 3
-
D12
-
R1, Bit 2
-
R2, Bit 2
-
D11
-
R1, Bit 1
-
R2, Bit 1
-
D10
-
R1, Bit 0
-
R2, Bit 0
-
D9
-
G1, Bit 5
-
G2, Bit 5
-
D8
-
G1, Bit 4
-
G2, Bit 4
-
D7
0
G1, Bit 3
-
G2, Bit 3
-
D6
0
G1, Bit 2
-
G2, Bit 2
-
D5
1
G1, Bit 1
-
G2, Bit 1
-
D4
0
G1, Bit 0
-
G2, Bit 0
-
D3
1
B1, Bit 5
-
B2, Bit 5
-
D2
1
B1, Bit 4
-
B2, Bit 4
-
D1
0
B1, Bit 3
-
B2, Bit 3
-
D0
0
B1, Bit 2
-
B2, Bit2
-
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
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ST7789S
8.8.14 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
MDT[1:0]=”11b”
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D15
-
-
R1, Bit 3
-
R2, Bit 3
D14
-
-
R1, Bit 2
-
R2, Bit 2
D13
-
-
R1, Bit 1
-
R2, Bit 1
D12
-
-
R1, Bit 0
-
R2, Bit 0
D11
-
-
G1, Bit 5
-
G2, Bit 5
D10
-
-
G1, Bit 4
-
G2, Bit 4
D9
-
-
G1, Bit 3
-
G2, Bit 3
D8
-
-
G1, Bit 2
-
G2, Bit 2
D7
0
-
G1, Bit 1
-
G2, Bit 1
D6
0
-
G1, Bit 0
-
G2, Bit 0
D5
1
-
B1, Bit 5
-
B2, Bit 5
D4
0
-
B1, Bit 4
-
B2, Bit 4
D3
1
-
B1, Bit 3
-
B2, Bit 3
D2
1
-
B1, Bit 2
-
B2, Bit 2
D1
0
R1, Bit 5
B1, Bit 1
R2, Bit 5
B2, Bit 1
D0
0
R1, Bit 4
B1, Bit 0
R2, Bit 4
B2, Bit 0
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
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ST7789S
8.8.15 8080-Ⅱ series 16-Bit Parallel Interface
The 8080-Ⅱ series 16-bit parallel interface of ST7789S can be used by setting IM[3:0]=”1000b”. Different
display data formats are available for two colors depth supported by listed below.
- 65k colors, RGB 5,6,5-bit input
- 262k colors, RGB 6,6,6-bit input
8.8.16 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input) 65K-Color, 3Ah=”05h”
There is 1 pixel (3 sub-pixels) per 1 byte
Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2: 1-times transfer (D17~D10, D8~D1) is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
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ST7789S
8.8.17 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
MDT[1:0]=”00b”
There are 2 pixels (6 sub-pixels) per 3 bytes
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
-
R1, Bit 5
B1, Bit 5
G2, Bit 5
R3, Bit 5
D16
-
R1, Bit 4
B1, Bit 4
G2, Bit 4
R3, Bit 4
D15
-
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
D14
-
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
D13
-
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
D12
-
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
D11
-
-
-
-
-
D10
-
-
-
-
-
D8
0
G1, Bit 5
R2, Bit 5
B2, Bit 5
G3, Bit 5
D7
0
G1, Bit 4
R2, Bit 4
B2, Bit 4
G3, Bit 4
D6
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D5
0
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D4
1
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D3
1
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
D2
0
-
-
-
-
D1
0
-
-
-
-
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
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ST7789S
8.8.18 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
MDT[1:0]=”01b”
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
-
R1, Bit 5
B1, Bit 5
R2, Bit 5
B2, Bit 5
D16
-
R1, Bit 4
B1, Bit 4
R2, Bit 4
B2, Bit 4
D15
-
R1, Bit 3
B1, Bit 3
R2, Bit 3
B2, Bit 3
D14
-
R1, Bit 2
B1, Bit 2
R2, Bit 2
B2, Bit 2
D13
-
R1, Bit 1
B1, Bit 1
R2, Bit 1
B2, Bit 1
D12
-
R1, Bit 0
B1, Bit 0
R2, Bit 0
B2, Bit 0
D11
-
-
-
-
-
D10
-
-
-
-
-
D8
0
G1, Bit 5
-
G2, Bit 5
-
D7
0
G1, Bit 4
-
G2, Bit 4
-
D6
1
G1, Bit 3
-
G2, Bit 3
-
D5
0
G1, Bit 2
-
G2, Bit 2
-
D4
1
G1, Bit 1
-
G2, Bit 1
-
D3
1
G1, Bit 0
-
G2, Bit 0
-
D2
0
-
-
-
-
D1
0
-
-
-
-
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
8.8.19 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
Version 1.5
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ST7789S
MDT[1:0]=”10b”
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
-
R1, Bit 5
B1, Bit 1
R2, Bit 5
B2, Bit 1
D16
-
R1, Bit 4
B1, Bit 0
R2, Bit 4
B2, Bit 0
D15
-
R1, Bit 3
-
R2, Bit 3
-
D14
-
R1, Bit 2
-
R2, Bit 2
-
D13
-
R1, Bit 1
-
R2, Bit 1
-
D12
-
R1, Bit 0
-
R2, Bit 0
-
D11
-
G1, Bit 5
-
G2, Bit 5
-
D10
-
G1, Bit 4
-
G2, Bit 4
-
D8
0
G1, Bit 3
-
G2, Bit 3
-
D7
0
G1, Bit 2
-
G2, Bit 2
-
D6
1
G1, Bit 1
-
G2, Bit 1
-
D5
0
G1, Bit 0
-
G2, Bit 0
-
D4
1
B1, Bit 5
-
B2, Bit 5
-
D3
1
B1, Bit 4
-
B2, Bit 4
-
D2
0
B1, Bit 3
-
B2, Bit 3
-
D1
0
B1, Bit 2
-
B2, Bit2
-
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
Page 83 of 300
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ST7789S
8.8.20 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
MDT[1:0]=”11b”
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
-
-
R1, Bit 3
-
R2, Bit 3
D16
-
-
R1, Bit 2
-
R2, Bit 2
D15
-
-
R1, Bit 1
-
R2, Bit 1
D14
-
-
R1, Bit 0
-
R2, Bit 0
D13
-
-
G1, Bit 5
-
G2, Bit 5
D12
-
-
G1, Bit 4
-
G2, Bit 4
D11
-
-
G1, Bit 3
-
G2, Bit 3
D10
-
-
G1, Bit 2
-
G2, Bit 2
D8
0
-
G1, Bit 1
-
G2, Bit 1
D7
0
-
G1, Bit 0
-
G2, Bit 0
D6
1
-
B1, Bit 5
-
B2, Bit 5
D5
0
-
B1, Bit 4
-
B2, Bit 4
D4
1
-
B1, Bit 3
-
B2, Bit 3
D3
1
-
B1, Bit 2
-
B2, Bit 2
D2
0
R1, Bit 5
B1, Bit 1
R2, Bit 5
B2, Bit 1
D1
0
R1, Bit 4
B1, Bit 0
R2, Bit 4
B2, Bit 0
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
Page 84 of 300
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ST7789S
8.8.21 8080-Ⅰ series 9-Bit Parallel Interface
The 8080-Ⅰ series 9-bit parallel interface of ST7789S can be used by setting IM[3:0]=”0010b”Different
display data formats are available for two colors depth supported by listed below.
-65k colors, RGB 5,6,5-bit input
-262k colors, RGB 6,6,6-bit input
8.8.22 Write 9-bit data for RGB 5-6-5-bit input (65K-Color), 3Ah=”05h”
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 4, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
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ST7789S
8.8.23 Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah=”06h”, MDT[1:0]=”00b”
There is 1 pixel (3 sub-pixels) per 2bytes
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D8
-
R1, Bit 5
G1, Bit 2
R2, Bit 5
G2, Bit 2
D7
0
R1, Bit 4
G1, Bit 1
R2, Bit 4
G2, Bit 1
D6
0
R1, Bit 3
G1, Bit 0
R2, Bit 3
G2, Bit 0
D5
1
R1, Bit 2
B1, Bit 5
R2, Bit 2
B2, Bit 5
D4
0
R1, Bit 1
B1, Bit 4
R2, Bit 1
B2, Bit 4
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-time transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
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ST7789S
8.8.24 Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah=”06h”, MDT[1:0]=”01b”
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D8
-
-
-
-
-
D7
0
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
D6
0
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
D5
1
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
D4
0
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
D3
1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
D2
1
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
Page 87 of 300
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ST7789S
8.8.25 8080-Ⅱ series 9-bit Parallel Interface
The 8080-Ⅱ series 9-bit parallel interface of ST7789S can be used by setting IM[3:0]=”1011b”Different
display data formats are available for two colors depth supported by listed below.
-65k colors, RGB 5,6,5-bit input
-262k colors, RGB 6,6,6-bit input
8.8.26 Write 9-bit data for RGB 5-6-5-bit input (65K-Color), 3Ah=”05h”
Note 1: The data order is as follows, MSB=D16, LSB=D9 and picture data is MSB=Bit 4, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
Page 88 of 300
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ST7789S
8.8.27 Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah=”06h”, MDT[1:0]=”00b”
There is 1 pixel (3 sub-pixels) per 2bytes
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
0
R1, Bit 5
G1, Bit 2
R2, Bit 5
G2, Bit 2
D16
0
R1, Bit 4
G1, Bit 1
R2, Bit 4
G2, Bit 1
D15
1
R1, Bit 3
G1, Bit 0
R2, Bit 3
G2, Bit 0
D14
0
R1, Bit 2
B1, Bit 5
R2, Bit 2
B2, Bit 5
D13
1
R1, Bit 1
B1, Bit 4
R2, Bit 1
B2, Bit 4
D12
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D11
0
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D10
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D9
-
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D17, LSB=D9 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-time transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
Page 89 of 300
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ST7789S
8.8.28 Write 9-bit data for RGB 6-6-6-bit input (262K-Color), 3Ah=”06h”, MDT[1:0]=”01b”
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
0
-
-
-
-
D16
0
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
D15
1
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
D14
0
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
D13
1
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
D12
1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
D11
0
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
D10
0
-
-
-
-
D9
-
-
-
-
Pixel n+1
Pixel n
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D16, LSB=D11 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Version 1.5
Page 90 of 300
2013/04
ST7789S
8.8.29 8080-Ⅰ series 18-Bit Parallel Interface
The 8080-Ⅰ series 18-bit parallel interface of ST7789S can be used by setting IM[3:0]=”0011b”. Different
display data formats are available for three colors depth supported by listed below.
- 4k colors, RGB 4,4,4-bit input
- 65k colors, RGB 5,6,5-bit input
- 262k colors, RGB 6,6,6-bit input.
Version 1.5
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ST7789S
8.8.30 18-bit data bus for 12-bit/pixel (RGB-4-4-4-bit input), 4K-colors, 3Ah=”03h”
There is 1 pixel (3 sub-pixels) per byte
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
-
-
-
-
-
D16
-
-
-
-
-
D15
-
-
-
-
-
D14
-
-
-
-
-
D13
-
-
-
-
-
D12
-
-
-
-
-
D11
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D10
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D9
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D8
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D7
0
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D6
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D5
1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D4
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
12 bits
12 bits
Look-Up Table for 4096 Color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information.
Version 1.5
Page 92 of 300
2013/04
ST7789S
8.8.31 18-bit data bus for 16-bit/pixel (RGB-5-6-5-bit input), 65K-colors, 3Ah=”05h”
There is one pixel (3 sub-pixels) per byte
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2: 1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.
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8.8.32 18-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-colors, 3Ah=”06h”
There is 1 pixel (3 sub-pixels) per byte
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
-
R1, Bit 5
R2, Bit 5
R3, Bit 5
R4, Bit 5
D16
-
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
D15
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D14
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D13
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D12
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D11
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D10
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D9
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D8
-
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D7
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D6
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D5
1
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data.
Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.
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8.8.33 8080-Ⅱ series 18-Bit Parallel Interface
The 8080-Ⅱ series 18-bit parallel interface of ST7789S can be used by setting IM[3:0]=”1010b”. Different
display data formats are available for two colors depth supported by listed below.
- 65k colors, RGB 5,6,5-bit input
- 262k colors, RGB 6,6,6-bit input.
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8.8.34 18-bit data bus for 16-bit/pixel (RGB-5-6-5-bit input), 65K-colors, 3Ah=”05h”
There is one pixel (3 sub-pixels) per byte
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2: 1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.
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8.8.35 18-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-colors, 3Ah=”06h”
There is 1 pixel (3 sub-pixels) per byte
RESX
“1”
CSX
D/CX
WRX
RDX
“1”
8080-series control pins
D17
-
R1, Bit 5
R2, Bit 5
R3, Bit 5
R4, Bit 5
D16
-
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
D15
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D14
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D13
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D12
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D11
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D10
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D9
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D8
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D7
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D6
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D5
0
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
D4
1
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
0
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
-
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data.
Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.
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8.8.36 3-Line Serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input
8.8.37 Write data for 12-bit/pixel (RGB-4-4-4 bit input), 4K-Colors, 3Ah=”03h”
Note 1: Pixel data with the 12-bit color depth information
Note 2: The most significant bits are: Rx3, Gx3 and Bx3
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
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8.8.38 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3Ah=”05h”
Note 1: Pixel data with the 16-bit color depth information
Note 2: The most significant bits are: Rx4, Gx5 and Bx4
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
8.8.39 Write data for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”
RESX
“1”
CSX
SDA
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
R15
R14
R13
R12
R11
R10
-
-
1
G15
G14
G13
G12
G11
G10
-
-
1
B15
B14
B13
B12
B11
B10
-
-
Pixel n
SCL
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: Pixel data with the 18-bit color depth information
Note 2: The most significant bits are: Rx5, Gx5 and Bx5
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
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8.8.40 4-Line Serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input
8.8.41 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah=”03h”
RESX
“1”
CSX
D/CX
“1”
SDA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
R13
R12
R11
R10
G13
G12
G11
G10
B13
B12
B11
B10
R23
R22
R21
R20
G23
G22
G21
G20
B23
B22
B21
B20
Pixel n
Pixel n+1
SCL
12 bits
12 bits
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1. pixel data with the 12-bit color depth information
Note 2. The most significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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8.8.42 Write data for 16-bit/pixel (RGB-5-6-5-bit input), 65K-Colors, 3Ah=”05h”
RESX
“1”
CSX
D/CX
“1”
SDA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
R14
R13
R12
R11
R10
G15
G14
G13
G12
G11
G10
B14
B13
B12
B11
B10
R24
R23
R22
R21
R20
G25
G24
G23
Pixel n
Pixel n+1
SCL
16 bits
16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1. pixel data with the 16-bit color depth information
Note 2. The most significant bits are: Rx4, Gx5 and Bx4
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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8.8.43 Write data for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”
Note 1. pixel data with the 18-bit color depth information
Note 2. The most significant bits are: Rx5, Gx5 and Bx5
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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8.9 RGB Interface
8.9.1
RGB interface Selection
The color format selection of RGB Interface for ST7789S is selected by setting the RIM and command
3Ah, DB[6:4].
RIM
3Ah, DB[6:4]
RGB Interface Mode
Data pins
0
110
18-bit 262K RGB Interface
DB[17:0]
0
101
16-bit 65K RGB Interface
DB[17:13], DB[11:1]
1
110
6-bit 262K RGB Interface
DB[5:0]
1
101
6-bit 65K RGB Interface
DB[5:0]
8.9.2
RGB Color Format
ST7789S supports two kinds of RGB interface, DE mode and HV mode, and 6bit/18bit data format. When DE
mode is selected and the VSYNC, HSYNC, DOTCLK, DE, D[17:0] pins can be used; when HV mode is
selected and the VSYNC, HSYNC, DOTCLK, D[17:0] pins can be used. When using RGB interface, only
serial interface can be selected.
16-bit RGB interface Hardware suggestion, IM[3:0]=0101.
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Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors
D17
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
R5, Bit 4
D16
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
R5, Bit 3
D15
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
R5, Bit 2
D14
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R5, Bit 1
D13
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
R5, Bit 0
D12
-
-
-
-
-
D11
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G5, Bit 5
D10
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
G5, Bit 4
D9
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
G5, Bit 3
D8
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
G5, Bit 2
D7
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
G5, Bit 1
D6
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
G5, Bit 0
D5
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
B5, Bit 4
D4
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
B5, Bit 3
D3
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
B5, Bit 2
D2
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B5, Bit 1
D1
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
B5, Bit 0
-
-
-
-
-
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
Pixel n+4
D0
16 bits
16 bits
Frame memory
R1
Version 1.5
G1
B1
R2
G2
B2
R3
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G3
B3
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18-bit RGB interface hardware suggestion, IM[3:0]=0101.
18-bit RGB Interface
MCU
ST7789S
/RST
/CS
SCL
SDA
VSYNC
HSYNC
DOTCLK
ENABLE
DB[17:0]
RESX
CSX
DCX
SDA
VSYNC
HSYNC
DOTCLK
ENABLE
DB[17:0]
18
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Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors
D17
R1, Bit 5
R2, Bit 5
R3, Bit 5
R4, Bit 5
R5, Bit 5
D16
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
R5, Bit 4
D15
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
R5, Bit 3
D14
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
R5, Bit 2
D13
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R5, Bit 1
D12
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
R5, Bit 0
D11
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G5, Bit 5
D10
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
G5, Bit 4
D9
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
G5, Bit 3
D8
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
G5, Bit 2
D7
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
G5, Bit 1
D6
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
G5, Bit 0
D5
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
B5, Bit 5
D4
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
B5, Bit 4
D3
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
B5, Bit 3
D2
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
B5, Bit 2
D1
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B5, Bit 1
D0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
B5, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
Pixel n+4
18 bits
18 bits
Frame memory
R1
Version 1.5
G1
B1
R2
G2
B2
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R3
G3
B3
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ST7789S
6-bit RGB interface hardware suggestion, IM[3:0]=0101.
Write data for 6-bit/pixel (RGB 5-6-5-bit input), 65K-Colors
D5
R1, Bit 4
G1, Bit 5
B1, Bit 4
R2, Bit 4
G2, Bit 5
D4
R1, Bit 3
G1, Bit 4
B1, Bit 3
R2, Bit 3
G2, Bit 4
D3
R1, Bit 2
G1, Bit 3
B1, Bit 2
R2, Bit 2
G2, Bit 3
D2
R1, Bit 1
G1, Bit 2
B1, Bit 1
R2, Bit 1
G2, Bit 2
D1
R1, Bit 0
G1, Bit 1
B1, Bit 0
R2, Bit 0
G2, Bit 1
D0
-
G1, Bit 0
-
-
G2, Bit 0
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Write data for 6-bit/pixel (RGB 6-6-6-bit input), 262K-Colors
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D5
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
G2, Bit 5
D4
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
G2, Bit 4
D3
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
G2, Bit 3
D2
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
G2, Bit 2
D1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
G2, Bit 1
D0
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
G2, Bit 0
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Figure 23 RGB Interface Data Format
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8.9.3
RGB Interface Definition
The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK
signals. The data can be written only within the specified area with low power consumption by using window
address function. The back porch and front porch are used to set the RGB interface timing.
Figure 24 DRAM Access Area by RGB Interface
Please refer to the following table for the setting limitation of RGB interface signals.
Parameter
Symbol
Min.
Typ.
Horizontal Sync. Width
hpw
2
10
Horizontal Sync. Back Porch
hbp
4
10
Horizontal Sync. Front Porch
hfp
2
38
Vertical Sync. Width
vs
1
4
Vertical Sync. Back Porch
vbp
1
4
Vertical Sync. Front Porch
vfp
1
8
Max.
hpw+hbp=31
Unit
Clock
Clock
vs+vbp=127
Clock
Line
Line
-
Line
Note:
1.
Typical value are related to the setting of dot clock is 7MHz and frame rate is 70Hz..
2.
If the setting of hpw is 10 dot clocks and hbp is 10 dot clocks, the setting of HBP in command B1h is 20 dot clocks
3.
In with ram mode, hpw+hbp+hfp≧22
4.
In without ram mode, hpw+hbp≧20
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8.9.4
RGB Interface Mode Selection
ST7789S supports two kinds of RGB interface, DE mode and HV mode. Each mode also can select with ram
and without ram. The table shown below uses command B1h to select RGB interface mode.
RCM[1:0]
10
WO
0
RGB Mode
0
Shift register (without Ram)
Ram
HV mode
1
8.9.5
Ram
DE mode
1
11
Data Path
Shift register (without Ram)
RGB Interface Timing
The timing chart of RGB interface DE mode is shown as follows.
Note: The setting of front porch and back porch in host must match that in IC as this mode.
Figure 25 Timing Chart of Signals in RGB Interface DE Mode
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The timing chart of RGB interface HV mode is shown as follows.
Figure 26 Timing chart of RGB interface HV mod
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The following are the functions not available in RGB Input Interface mode.
Function
RGB Interface
I80 System Interface
Partial display
Not available
Available
Scroll function
Not available
Available
Interlaced scan
Not available
Available
Graphics operation function
Not available
Available
VSYNC, HSYNC, and DOTCLK signals must be supplied during a display operation period.
In RGB interface mode, the panel controlling signals are generated from DOTCLK, not the internal clock
generated from the internal oscillator.
In 6-bit RGB interface mode, each of RGB dots are transferred in synchronization with DOTCLK signals. In
other words, one pixel data needs to take three DOTCLKs to transfer.
In 6-bit RGB interface mode, the cycles of VSYNC, HSYNC, ENABLE, DOTCLK signals must be set correctly
so that the data transfer is completed in units of pixels.
When switching between the internal operation mode and the external display interface operation mode,
follow the sequences below in setting instruction.
In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing
one frame.
In RGB interface mode, a RAM address is set in the address counter every frame on the falling edge of
VSYNC.
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8.10 VSYNC Interface
8.10.1 18-bit RGB Interface
The ST7789S incorporates VSYNC interface, which enables motion pictures to be displayed with only the
conventional system interface and the frame synchronization signal (VSYNC). This interface requires minimal
changes from the conventional system to display motion pictures.In this interface the internal display
operation is synchronized with VSYNC. Data for display is written to RAM via the system interface with higher
speed than for internal display operation. This method enables tearing-free display of motion pictures with the
conventional interface.
Figure 27 Data transmission through VSYNC interface
VSYNC
Back Porch (VBP)
RAM Write
Display Scan
Display Area (320 Lines)
Front Porch (VFP)
Figure 28 Operation through VSYNC Interface
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Display operation can be achieved by using the internal clock generated by the internal oscillator and the
VSYNC input. Because all the data for display is written to RAM, only the data to be rewritten is transferred.
This method reduces the amount of data transferred during motion picture display operation.
Write Data to
Frame Memory
1 Line
D[17:0]
Gate1
Gate2
Gate320
Source
Figure 29 Timing Diagram of VSYNC Interface
VSYNC interface requires taking the minimum speed for RAM writing via the system interface and the
frequency of the internal clock into consideration. RAM writing should be performed with higher speed than
the result obtained from the calculation shown below. The internal memory writing address counter is reset by
VSYNC. So, insure interval time between VSYNC falling and DRAM data writing.
Note:
1. VSYNC period should always be constant. If not, some degradation of display such as flicker may occur in LCD system.
2. Display data don’t need to be written for every VSYNC period. For example, any system is working under 60Hz frame rate and
30-fps motion picture condition. So being written display data for every other frame would be enough.
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8.10.2 VSYNC Interface Mode
Leading Mode
Figure 30 Operation for Leading Mode of VSYNC Interface
Lagging Mode
Figure 31 Operation for Lagging Mode of VSYNC Interface
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Notes:
1. When RAM writing does not start immediately after the falling edge of VSYNC, the time between the falling edge of VSYNC and
the RAM writing start timing must also be considered.
1. The minimum DRAM write speed must be satisfied and the frequency variation must be taken into consideration.
2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an
entire display.
3. When switching from the internal clock operation mode to the VSYNC interface mode or inversely, the switching starts from the
next VSYNC cycle, i.e. after completing the display of the frame.
4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to
“0” to transfer display data.
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8.11 Display Data RAM
8.11.1 Configuration
The display module has an integrated 240x320x18-bit graphic type static RAM. This 1382400-bit memory
allows storing on-chip a 240xRGBx320 image with an 18-bpp resolution (262K-color). There will be no
abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write
to the same location of the Frame Memory.
TF-LCD panel
(240 x RGB x 320)
MCU
I/F
LUT
Display data RAM
(240 x 320 x 18-bits)
Row
address
counter
Host
interface
Line
address
counter
Scan
address
counter
Column
address
counter
Figure 32 Display data RAM organization
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8.11.2 Memory to display address mapping
RGB alignment
Data control command
Column
(MADCTR) MX=0
(MADCTR) MX=1
Color
0
1
239
239
238
0
R
G
B
R
G
B
R
G
B
0
1
2
3
4
5
717
718
719
Data
Page
(MADCTR)
(MADCTR)
MY=1
MY=0
0
319
1
318
2
317
3
316
4
315
5
314
6
313
7
312
:
:
312
7
313
6
314
5
315
4
316
3
317
2
318
1
319
0
Source output
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8.12 Address Control
The address counter sets the addresses of the display data RAM for writing and reading.
Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected
(RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the “Write
access” is activated on the RAM. The locations of RAM are addressed by the address pointers. The address
ranges are X=0 to X=239 (Efh) and Y=0 to Y=319 (13Fh). Addresses outside these ranges are not allowed.
Before writing to the RAM, a window must be defined that will be written. The window is programmable via
the command registers XS, YS designating the start address and XE, YE designating the end address.
For example the whole display contents will be written, the window is defined by the following values: XS=0
(0h) YS=0 (0h) and XE=239 (Efh), YE=319 (13Fh).
In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address
(Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode
(V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and
Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers
wrap around to address (X=XS and Y=YS).
For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET and
MADCTL”, define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations
of flags are allowed. Section 8.12 show the available combinations of writing to the display RAM. When MX,
MY and MV will be changed the data bust be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as below
Condition
When RAMWR/RAMRD command is accepted
Column Counter
Row Counter
Return to
Return to
“Start Column (XS)”
“Start Row (YS)”
Increment by 1
No change
Complete Pixel Read / Write action
The Column counter value is larger than “End Column (XE)”
Return to
“Start Column (XS)”
Increment by 1
The Column counter value is larger than “End Column (XE)”
Return to
Return to
and the Row counter value is larger than “End Row (YE)”
“Start Column (XS)”
“Start Row (YS)”
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Display
MADCTR
Image in the Host
Image in the Driver
Data
Parameter
(MPU)
(DDRAM)
Direction
MV
MX
MY
Normal
0
0
0
Y-Mirror
0
0
1
X-Mirror
0
1
0
X-Mirror
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Y-Mirror
X-Y
Exchange
X-Y
Exchange
Y-Mirror
X-Y
Exchange
X-Mirror
X-Y
Exchange
X-Mirror
Y-Mirror
Figure 33 Display data RAM organization
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8.13 Normal Display On or Partial Mode On, Vertical Scroll Off
In this mode, contents of the frame memory within an area where column address is 00h to 83h and row address is 00h to
83h is displayed.
To display a dot on leftmost top corner, store the dot data at (column address, row address) = (0,0).
Example1) Normal Display On
Example2) Partial Display On: PSL[15:0] = 0004h, PEL[15:0] = 013Ch, MADCTR (ML)=0
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8.14 Vertical Scroll Mode
8.14.1 Rolling scroll
There is just one types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h)
and “Vertical Scrolling Start Address” (37h).
Figure 34 Rolling Scroll Definition
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) =320. In this case, ‘rolling’ scrolling is applied as shown
below. All the memory contents will be used.
Example1) Panel size=240 x 320, TFA =3, VSA=315, BFA=2, SSA=4, MADCTR ML=0: Rolling Scroll
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Example2) Panel size=132 x 132, TFA =2, VSA=315, BFA=3, SSA=4, MADCTR ML=1: Rolling Scroll (TFA and BFA are
exchanged)
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8.14.2 Vertical Scroll Example
There are 2 types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and
“Vertical Scrolling Start Address” (37h).
Case 1: TFA + VSA + BFA<320
N/A. Do not set TFA + VSA + BFA<320. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA=320 (Rolling Scrolling)
Example1) When MADCTR parameter ML=”0”, TFA=0, VSA=320, BFA=0 and VSCSAD=40.
2
1
1
2
2
1
1
2
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3
2
1
1
1
2
3
3
2
1
3
2
Example2) When MADCTR parameter ML=”1”, TFA=10, VSA=310, BFA=0 and VSCSAD=30.
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8.15 Tearing Effect
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled
or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined
by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize
Frame Memory Writing when displaying video images.
8.15.1 Tearing effect line modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one
V-sync and 320 H-sync pulses per field.
thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
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Note: During Sleep In Mode, the Tearing Output Pin is active Low.
8.15.2 Tearign effect line timings
The Tearing Effect signal is described below:
Symbol
Parameter
min
max
unit
tvdl
Vertical Timing Low Duration
13
-
ms
tvdh
Vertical Timing High Duration
1000
-
µs
thdl
Horizontal Timing Low Duration
33
-
µs
thdh
Horizontal Timing Low Duration
25
500
µs
description
Table 16 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25°C)
Note: The timings in Table 15 apply when MADCTL ML=0 and ML=1
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing
Effect:
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8.15.3 Example 1: MPU Write is faster than panel read
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical
sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan
and each Panel Frame refresh has a complete new image:
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8.15.4 Example 2: MPU write is slower than panel read
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync
pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read
pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the MPU to
Frame memory write position.
B
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8.16 Power ON/OFF Sequence
VDD must be powered on before the VDDI.
VDDI must be powered off before the VDD.
During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec
after RESX has been released.
During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after
RESX has been released.
CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.
Note 1: There will be no damage to the display module if the power sequences are not met.
Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out
command. Also between receiving Sleep In command and Power Off Sequence.
Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to
apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not
guaranteed.
The power on/off sequence is illustrated below
TrPW = +/- no limit
TfPW = +/- no limit
VDD
VDDI
Timing when the latter signal rises up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross
point of 90% of 2.75V, not 90% of 2.6V.
Timing when the latter signal falls up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross
point of 90% of 2.75V, not 90% of 2.6V.
TfPW-CSX = +/- no limit
TrPW-CSX = +/- no limit
CSX
H or L
TrPW-RESX = + no limit
RESX
(Power down in
sleep-out mode)
30%
TfPW-RESX1 = min
120ms
TrPW-RESX = + no limit
RESX
(Power down in
sleep-in mode)
TfPW-RESX2 = min 0ms
30%
TfPW-RESx1 is applied to RESX falling in the Sleep Out Mode.
TfPW-RESx2 is applied to RESX falling in the Sleep In Mode.
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8.16.1 Uncontrolled Power Off
The uncontrolled power-off means a situation which removed a battery without the controlled power off
sequence. It will neither damage the module or the host interface.
If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the display
(blank display) and remains blank until “Power On Sequence” powers it up.
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8.17 Power Level Definition
8.17.1 Power Level
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power
Consumption
1. Normal Mode On (full display), Idle Mode Off, Sleep Out.
In this mode, the display is able to show maximum 262,144 colors.
2. Partial Mode On, Idle Mode Off, Sleep Out.
In this mode part of the display is used with maximum 262,144 colors.
3. Normal Mode On (full display), Idle Mode On, Sleep Out.
In this mode, the full display area is used but with 8 colors.
4. Partial Mode On, Idle Mode On, Sleep Out.
In this mode, part of the display is used but with 8 colors.
5. Sleep In Mode
In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU
interface and memory works with VDDI power supply. Contents of the memory are safe.
Figure 41
Power Off Mode
In this mode, both VDD and VDDI are removed.
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.
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8.18 Power Flow Chart
Normal display mode on = NOR ON
Partial display mode on = PTL ON
Idle mode off = IDM OFF
Idle mode on = IDM ON
Sleep out = SLP OUT
Sleep in = SLP IN
NOR ON
PTL ON
Sleep out
Normal display mode on
Idle mode off
IDM ON
Power on sequence
HW reset
SW reset
SLP IN
Sleep in
Normal display mode on
Idle mode off
SLP OUT
Sleep out
Normal display mode on
Idle mode on
Sleep out
Partial display mode on
Idle mode off
PTL ON
NOR ON
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PTL ON
IDM OFF
IDM ON
IDM ON
NOR ON
SLP IN
Sleep out
Partial display mode on
Idle mode on
Sleep in
Normal display mode on
Idle mode on
SLP OUT
SLP IN
Sleep in
Partial display mode on
Idle mode off
SLP OUT
IDM OFF
IDM OFF
IDM ON
SLP IN
SLP OUT
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IDM OFF
Sleep in
Partial display mode on
Idle mode on
PTL ON
NOR ON
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8.19 Gamma Correction
ST7789S incorporate the gamma correction function to display 262,244 colors for the LCD panel. The
gamma correction is performed with 3 groups of registers, which are gradient adjustment, contrast adjustment
and fine- adjustment registers for positive and negative polarities, and RGB can be adjusted individually.
Figure 35 Gray scale Voltage Generation (Positive)
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Figure 36 Relationship between Source Output and VCOM
Percentage adjustment:
J0P[1:0], J1P[1:0], J0N[1:0], J1N[1:0] these register are used to adjust the voltage level of interpolation point.
The following table is the detail description.
J0P[1:0]/J0N[1:0]:
00h
01h
02h
03h
VP3/VN3
50%
56%
50%
60%
VP5/VN5
50%
44%
50%
42%
VP7/VN7
86%
71%
80%
66%
VP8/VN8
71%
57%
63%
49%
VP9/VN9
57%
40%
49%
34%
VP10/VN10
43%
29%
34%
23%
VP11/VN11
29%
17%
20%
14%
VP12/VN12
14%
6%
9%
6%
00h
01h
02h
03h
VP51/VN51
86%
86%
86%
89%
VP52/VN52
71%
71%
77%
80%
VP53/VN53
57%
60%
63%
69%
VP54/VN54
43%
46%
46%
51%
VP55/VN55
29%
34%
31%
37%
VP56/VN56
14%
17%
14%
20%
VP58/VN58
50%
56%
47%
47%
VP60/VN60
50%
50%
50%
53%
J1P[1:0]/J1N[1:0]:
Table 17 voltage level percentage adjustment description
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Source voltage of positive gamma level
Version 1.5
Gamma level
Related Register
Formula
VP0
V0P[3:0]
(VAP-VBP)*(129R-V0P[3:0]R)/129R+VBP
VP1
V1P[5:0]
(VAP-VBP)*(128R-V1P[5:0]R)/129R+VBP
VP2
V2P[5:0]
(VAP-VBP)*(128R-V2P[5:0]R)/129R+VBP
VP3
J0P[1:0]
(VP2-VP4)*J0P[1:0]+VP4
VP4
V4P[4:0]
(VP2-VP20)*(57R-V4P[4:0])/60R+VP20
VP5
J0P[1:0]
(VP4-VP6)*J0P[1:0]+VP6
VP6
V6P[4:0]
(VP2-VP20)*(47R-V6P[4:0])/60R+VP20
VP7
J0P[1:0]
(VP6-VP13)*J0P[1:0]+VP13
VP8
J0P[1:0]
(VP6-VP13)*J0P[1:0]+VP13
VP9
J0P[1:0]
(VP6-VP13)*J0P[1:0]+VP13
VP10
J0P[1:0]
(VP6-VP13)*J0P[1:0]+VP13
VP11
J0P[1:0]
(VP6-VP13)*J0P[1:0]+VP13
VP12
J0P[1:0]
(VP6-VP13)*J0P[1:0]+VP13
VP13
V13P[3:0]
(VP2-VP20)*(21R-V13P[3:0])/60R+VP20
VP14
--
(VP13-VP20)/(20-13)*(20-14)+VP20
VP15
--
(VP13-VP20)/(20-13)*(20-15)+VP20
VP16
--
(VP13-VP20)/(20-13)*(20-16)+VP20
VP17
--
(VP13-VP20)/(20-13)*(20-17)+VP20
VP18
--
(VP13-VP20)/(20-13)*(20-18)+VP20
VP19
--
(VP13-VP20)/(20-13)*(20-19)+VP20
VP20
V20P[6:0]
(VAP-VBP)*(128R-V20P[6:0]R)/129R+VBP
VP21
--
(VP20-VP27)/(27-20)*(27-21)+VP27
VP22
--
(VP20-VP27)/(27-20)*(27-22)+VP27
VP23
--
(VP20-VP27)/(27-20)*(27-23)+VP27
VP24
--
(VP20-VP27)/(27-20)*(27-24)+VP27
VP25
--
(VP20-VP27)/(27-20)*(27-25)+VP27
VP26
--
(VP20-VP27)/(27-20)*(27-26)+VP27
VP27
V27P[2:0]
(VP20-VP43)*(20R-V27P[2:0])/25R+VP43
VP28
--
(VP27-VP36)/(36-27)*(36-28)+VP36
VP29
--
(VP27-VP36)/(36-27)*(36-29)+VP36
VP30
--
(VP27-VP36)/(36-27)*(36-30)+VP36
VP31
--
(VP27-VP36)/(36-27)*(36-31)+VP36
VP32
--
(VP27-VP36)/(36-27)*(36-32)+VP36
VP33
--
(VP27-VP36)/(36-27)*(36-33)+VP36
VP34
--
(VP27-VP36)/(36-27)*(36-34)+VP36
VP35
--
(VP27-VP36)/(36-27)*(36-35)+VP36
VP36
V36P[2:0]
(VP20-VP43)*(11R-V36P[2:0])/25R+VP43
VP37
--
(VP36-VP43)/(43-36)*(43-37)+VP43
VP38
--
(VP36-VP43)/(43-36)*(43-38)+VP43
VP39
--
(VP36-VP43)/(43-36)*(43-39)+VP43
VP40
--
(VP36-VP43)/(43-36)*(43-40)+VP43
VP41
--
(VP36-VP43)/(43-36)*(43-41)+VP43
VP42
--
(VP36-VP43)/(43-36)*(43-42)+VP43
VP43
V43P[6:0]
(VAP-VBP)*(128R-V43P[6:0]R)/129R+VBP
VP44
--
(VP43-VP50)/(50-43)*(50-44)+VP50
VP45
--
(VP43-VP50)/(50-43)*(50-45)+VP50
VP46
--
(VP43-VP50)/(50-43)*(50-46)+VP50
VP47
--
(VP43-VP50)/(50-43)*(50-47)+VP50
VP48
--
(VP43-VP50)/(50-43)*(50-48)+VP50
VP49
--
(VP43-VP50)/(50-43)*(50-49)+VP50
VP50
V50P[3:0]
(VP43-VP61)*(54R-V50P[3:0])/60R+VP61
VP51
J1P[1:0]
(V5P0-VP57)*J1P[1:0]+VP57
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VP52
J1P[1:0]
(VP50-VP57)*J1P[1:0]+VP57
VP53
J1P[1:0]
(VP50-VP57)*J1P[1:0]+VP57
VP54
J1P[1:0]
(VP50-VP57)*J1P[1:0]+VP57
VP55
J1P[1:0]
(VP50-VP57)*J1P[1:0]+VP57
VP56
J1P[1:0]
(VP50-VP57)*J1P[1:0]+VP57
VP57
V57P[4:0]
(VP43-VP61)*(44R-V57P[4:0])/60R+VP61
VP58
J1P[1:0]
(VP57-VP59)*J1P[1:0]+VP59
VP59
V59P[4:0]
(VP43-VP61)*(34R-V59P[4:0])/60R+VP61
VP60
J1P[1:0]
(VP59-VP61)*J1P[1:0]+VP61
VP61
V61P[5:0]
(VAP-VBP)*(64R-V61P[5:0]R)/129R+VBP
VP62
V62P[5:0]
(VAP-VBP)*(64R-V62P[5:0]R)/129R+VBP
VP63
V63P[3:0]
(VAP-VBP)*(23R-V63P[3:0]R)/129R+VBP
Source voltage of negative gamma level
Version 1.5
Gamma level
Related Register
Formula
VN0
V0N[3:0]
VBN-(VAN-VBN)*(129R-V0N[3:0]R)/129R
VN1
V1N[5:0]
VBN-(VAN-VBN)*(128R-V1N[5:0]R)/129R
VN2
V2N[5:0]
VBN-(VAN-VBN)*(128R-V2N[5:0]R)/129R
VN3
J0N[1:0]
(VN2-VN4)*J0N[1:0]+VN4
VN4
V4N[4:0]
(VN2-VN20)*(57R-V4N[4:0])/60R+VN20
VN5
J0N[1:0]
(VN4-VN6)*J0N[1:0]+VN6
VN6
V6N[4:0]
(VN2-VN20)*(47R-V6N[4:0])/60R+VN20
VN7
J0N[1:0]
(VN6-VN13)*J0N[1:0]+VN13
VN8
J0N[1:0]
(VN6-VN13)*J0N[1:0]+VN13
VN9
J0N[1:0]
(VN6-VN13)*J0N[1:0]+VN13
VN10
J0N[1:0]
(VN6-VN13)*J0N[1:0]+VN13
VN11
J0N[1:0]
(VN6-VN13)*J0N[1:0]+VN13
VN12
J0N[1:0]
(VN6-VN13)*J0N[1:0]+VN13
VN13
V13N[3:0]
(VN2-VN20)*(21R-V13N[3:0])/60R+VN20
VN14
--
(VN13-VN20)/(20-13)*(20-14)+VN20
VN15
--
(VN13-VN20)/(20-13)*(20-15)+VN20
VN16
--
(VN13-VN20)/(20-13)*(20-16)+VN20
VN17
--
(VN13-VN20)/(20-13)*(20-17)+VN20
VN18
--
(VN13-VN20)/(20-13)*(20-18)+VN20
VN19
--
(VN13-VN20)/(20-13)*(20-19)+VN20
VN20
V20N[6:0]
VBN-(VAN-VBN)*(128R-V20N[6:0]R)/129R
VN21
--
(VN20-VN27)/(27-20)*(27-21)+VN27
VN22
--
(VN20-VN27)/(27-20)*(27-22)+VN27
VN23
--
(VN20-VN27)/(27-20)*(27-23)+VN27
VN24
--
(VN20-VN27)/(27-20)*(27-24)+VN27
VN25
--
(VN20-VN27)/(27-20)*(27-25)+VN27
VN26
--
(VN20-VN27)/(27-20)*(27-26)+VN27
VN27
V27N[2:0]
(VN20-VN43)*(20R-V27N[2:0])/25R+VN43
VN28
--
(VN27-VN36)/(36-27)*(36-28)+VN36
VN29
--
(VN27-VN36)/(36-27)*(36-29)+VN36
VN30
--
(VN27-VN36)/(36-27)*(36-30)+VN36
VN31
--
(VN27-VN36)/(36-27)*(36-31)+VN36
VN32
--
(VN27-VN36)/(36-27)*(36-32)+VN36
VN33
--
(VN27-VN36)/(36-27)*(36-33)+VN36
VN34
--
(VN27-VN36)/(36-27)*(36-34)+VN36
VN35
--
(VN27-VN36)/(36-27)*(36-35)+VN36
VN36
V36N[2:0]
(VN20-VN43)*(11R-V36N[2:0])/25R+VN43
VN37
--
(VN36-VN43)/(43-36)*(43-37)+VN43
VN38
--
(VN36-VN43)/(43-36)*(43-38)+VN43
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Version 1.5
VN39
--
(VN36-VN43)/(43-36)*(43-39)+VN43
VN40
--
(VN36-VN43)/(43-36)*(43-40)+VN43
VN41
--
(VN36-VN43)/(43-36)*(43-41)+VN43
VN42
--
(VN36-VN43)/(43-36)*(43-42)+VN43
VN43
V43N[6:0]
VBN-(VAN-VBN)*(128R-V43N[6:0]R)/129R
VN44
--
(VN43-VN50)/(50-43)*(50-44)+VN50
VN45
--
(VN43-VN50)/(50-43)*(50-45)+VN50
VN46
--
(VN43-VN50)/(50-43)*(50-46)+VN50
VN47
--
(VN43-VN50)/(50-43)*(50-47)+VN50
VN48
--
(VN43-VN50)/(50-43)*(50-48)+VN50
VN49
--
(VN43-VN50)/(50-43)*(50-49)+VN50
VN50
V50N[3:0]
(VN43-VN61)*(54R-V50N[3:0])/60R+VN61
VN51
J1N[1:0]
(V5N0-VN57)*J1N[1:0]+VN57
VN52
J1N[1:0]
(VN50-VN57)*J1N[1:0]+VN57
VN53
J1N[1:0]
(VN50-VN57)*J1N[1:0]+VN57
VN54
J1N[1:0]
(VN50-VN57)*J1N[1:0]+VN57
VN55
J1N[1:0]
(VN50-VN57)*J1N[1:0]+VN57
VN56
J1N[1:0]
(VN50-VN57)*J1N[1:0]+VN57
VN57
V57N[4:0]
(VN43-VN61)*(44R-V57N[4:0])/60R+VN61
VN58
J1N[1:0]
(VN57-VN59)*J1N[1:0]+VN59
VN59
V59N[4:0]
(VN43-VN61)*(34R-V59N[4:0])/60R+VN61
VN60
J1N[1:0]
(VN59-VN61)*J1N[1:0]+VN61
VN61
V61N[5:0]
VBN-(VAN-VBN)*(64R-V61N[5:0]R)/129R
VN62
V62N[5:0]
VBN-(VAN-VBN)*(64R-V62N[5:0]R)/129R
VN63
V63N[3:0]
VBN-(VAN-VBN)*(23R-V63N[3:0]R)/129R
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8.20 Gray voltage generator for digital gamma correction
ST7789S digital gamma function can implement the RGB gamma correction independently. ST7789S utilizes
look-up table of digital gamma to change ram data, and then display the changed data from source driver.
The following diagram shows the data flow of digital gamma.
Figure 37 Block diagram of digital gamma
There are 2 registers and each register has 64 bytes to set R, G, B gamma independently. When bit DGMEN
be set to 1, R and B gamma will be mapped via look-up table of digital gamma to gray level voltage.
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8.21 Display Dimming
8.21.1 General Description
A dimming function (how fast to change the brightness from old to new level and what are brightness levels
during the change) is used when changing from one brightness level to another. This dimming function curve
is the same in increment and decrement. The basic idea is described below.
Dimming function can be enable and disable. See “Write CTRL Display (53h)” (bit DD) for more information.
8.21.2 Dimming Requirement
Dimming function in the display module should be implemented so that 400-600ms is used for the transition
between the original brightness value and the target brightness value. The transferring time steps between
these two brightness values are equal making the transition linear.
The dimming function is working similarly in both upward and downward directions.
An upward example is illustrate below
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8.21.3 Definition of brightness transition time
Shorter transition time than 500ms.
There is some stable time between transitions. Below drawing is for transition time: 400ms.
Longer transition time than 500ms
There is no any stable time between transitions. Below drawing is for transition time: 600ms.
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8.22 Content Adaptive Brightness Control (CABC)
8.22.1 Definition of CABC
A Content Adaptive Brightness Control function can be used to reduce the power consumption of the
luminance source. Content adaptation means that content gray level scale can be increased while
simultaneously lowering brightness of the backlight to achieve same perceived brightness. The adjusted gray
level scale and thus the power consumption reduction
Definition of Modes and target power reduction ratio:
Off mode: Content Adaptive Brightness Control functionality is totally off.
UI [User interface] image mode: Optimized for UI image. It is kept image quality as much as possible.
Target power consumption reduction ratio: 10% or less.
Still picture mode: Optimized for still picture. Some image quality degradation would be acceptable.
Target power consumption reduction ratio: more than 30%.
Moving image mode: Optimized for moving image. It is focused on the biggest power reduction with
image quality degradation. Target power consumption reduction ratio: more than 30%.
Note 1: Updating partial area of the image data should be supported by CABC functionality.
Note 2: Processing power consumption of CABC should be minimized.
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The transition time for dimming function is illustrated below.
Content Adaptive Brightness Control
Display brightness is changed, according to the image contents. The following graph mentions the case
of displaying three different images.
Image A: -20% brightness reduction
Image B: -30% brightness reduction
Image C: -30% brightness reduction
Transition time from the previous image to the current displayed image is “transition time A”.
Image A
Brightness
reduction
ratio: -20%
Image B
Brightness
reduction
ratio: -30%
Image C
Brightness
reduction
ratio: -10%
Display brightness
100%
90%
80%
70%
Content Adaptive
Brightness Control
50%
Transition time A
Transition time A
Transition time A
0%
Time
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Manual brightness setting and Dimming function
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Combine Display brightness
Green line in the following graph is for the output brightness of display. It is combined with both display
brightness, which are defined in the above graphs.
Display brightness
Maximum transition time is transition time A+B.
Brightness level calculates with the following formula.
Display Output brightness = Manual Brightness setting * CABC brightness ratio
Manual Brightness
Brightness ratio [CABC]
setting
Display Output
brightness
Case 1
85%
80%
68%
Case 2
60%
70%
42%
Case 3
85%
90%
76.5%
Transition time from the current brightness to target brightness is A+B in the worst case.
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8.22.2 Minimum brightness setting of CABC function
CABC function is automatically reduced backlight brightness based on image contents. In the case of the
combination with the LABC or manual brightness setting, display brightness is too dark. It must affect to
image quality degradation. CABC minimum brightness setting is to avoid too much brightness reduction.
When CABC is active, CABC can not reduce the display brightness to less than CABC minimum brightness
setting. If CABC algorithm works without any abnormal visual effect, image processing function can operate
even when the brightness can not be changed.
This function does not affect to the other function, manual brightness setting. Manual brightness can be set
the display brightness to less than CABC minimum brightness. Smooth transition and dimming function can
be worked as normal.
When display brightness is turned off (BCTRL=0 of “9.1.39 Write CTRL Display (53h)”), CABC minimum
brightness setting is ignored. “9.1.44 Read CABC minimum brightness (5Fh)” always read the setting value of
“9.1.43 Write CABC minimum brightness (5Eh)”.
WRCABC (55h)
Sleep-in
Function
RDCABCMB (5Fh)
NA
WRCABCMB (5Eh)
Image
CABC off
00b
Disable
WRCABCMB (5Eh)
Original
CABC on
01b/10b/11b
Enable
WRCABCMB (5Eh)
CABC modified
Brightness level calculates with the following formula.
Display Output Brightness = Manual brightness setting * CABC brightness ratio
Below drawing is for the explanation of the CABC minimum brightness setting.
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CABC minimum brightness value = 51 (33h: 20% display brightness)
Display Brightness
Brightness ratio
Calculation result of
Display Output
[manual setting]
[CABC]
the display
Brightness
Image
brightness formula
Case 1
50%
70%
35%
35%
CABC modified
Case 2
20%
70%
14%
20%
CABC modified
Case 3
50%
70%
35%
35%
CABC modified
At the case 2, the calculation result of the display brightness is 14%. CABC minimum brightness value is set
to 20% brightness. Actual display brightness is 20% as the CABC minimum brightness setting.
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9 COMMAND
9.1 System Function Command Table 1
Instruction
D/CX WRX RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Function
NOP
0
↑
1
-
0
0
0
0
0
0
0
0
(00h)
No operation
SWRESET
0
↑
1
-
0
0
0
0
0
0
0
1
(01h)
Software reset
0
↑
1
-
0
0
0
0
0
1
0
0
(04h)
Read display ID
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID1 read
1
1
↑
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
ID2 read
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
ID3 read
0
↑
1
-
0
0
0
0
1
0
0
1
RDDID
Read display
(09h)
status
RDDST
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
BSTON
MY
MX
MV
ML
RGB
MH
ST24
-
1
1
↑
-
ST23
IFPF2
IFPF1
IFPF0
1
1
↑
-
ST15
ST14
INVON
ST12
ST11
DISON
TEON
GCS2
-
1
1
↑
-
GCS1
GCS0
TEM
ST4
ST3
ST2
ST1
ST0
-
0
↑
1
-
0
0
0
0
1
0
1
0
IDMON PTLON SLOUT NORON
-
Read display
(0Ah)
power
RDDPM
1
1
↑
-
-
-
1
1
↑
-
BSTON
IDMON
0
↑
1
-
0
0
0
0
1
1
1
↑
-
-
-
-
-
1
1
↑
-
MY
MX
MV
0
↑
1
-
0
0
0
-
-
-
-
-
-
0
0
0
1
1
-
-
-
-
Dummy read
ML
RGB
MH
0
0
-
0
1
1
0
0
PTLON SLPOUT NORON DISON
Dummy read
(0Bh)
Read display
RDD
MADCTL
Read display
(0Ch)
pixel
RDD
COLMOD
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
0
D6
D5
D4
0
D2
D1
D0
-
0
↑
1
-
0
0
0
0
1
1
0
1
Read display
(0Dh)
image
RDDIM
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
VSSON
0
INVON
0
0
GC2
GC1
GC0
-
0
↑
1
-
0
0
0
0
1
1
1
0
Read display
RDDSM
(0Eh)
signal
1
Version 1.5
1
↑
-
-
-
-
-
-
Page 150 of 300
-
-
-
Dummy read
2013/04
ST7789S
Instruction
D/CX WRX RDX
1
1
↑
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
-
TEON
TEM
0
0
0
0
0
0
Hex
Function
Read display
0
↑
1
-
0
0
0
0
1
1
1
1
(0Fh)
self-diagnostic
result
RDDSDR
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
D7
D6
0
0
0
0
0
0
-
SLPIN
0
↑
1
-
0
0
0
1
0
0
0
0
(10h)
Sleep in
SLPOUT
0
↑
1
-
0
0
0
1
0
0
0
1
(11h)
Sleep out
PTLON
0
↑
1
-
0
0
0
1
0
0
1
0
(12h)
Partial mode on
NORON
0
↑
1
-
0
0
0
1
0
0
1
1
(13h)
Partial off
(Normal)
Display inversion
INVOFF
0
↑
1
-
0
0
1
0
0
0
0
0
(20h)
off
Display inversion
INVON
0
↑
1
-
0
0
1
0
0
0
0
1
(21h)
on
0
↑
1
-
0
0
1
0
0
0
0
1
1
↑
1
-
0
0
0
0
GC3
GC2
GC1
GC0
DISPOFF
0
↑
1
-
0
0
1
0
1
0
0
0
(28h)
Display off
DISPON
0
↑
1
-
0
0
1
0
1
0
0
1
(29h)
Display on
0
↑
1
-
0
0
1
0
1
0
1
0
(2Ah)
(26h) Display inversion
GAMSET
on
Column address
set
1
↑
1
1
↑
1
-
XS15
XS14
XS13
XS12
XS11
XS10
XS9
XS8
X address start:
1
XS7
XS6
XS5
XS4
XS3
XS2
XS1
XS0
0≦XS≦X
↑
1
XE15
XE14
XE13
XE12
XE11
XE10
XE9
XE8
X address start:
1
↑
1
XE7
XE6
XE5
XE4
XE3
XE2
XE1
XE0
S≦XE≦X
0
↑
1
-
0
0
1
0
1
0
1
1
1
↑
1
-
YS15
YS14
YS13
YS12
YS11
YS10
YS9
YS8
Y address start:
1
↑
1
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
0≦YS≦Y
1
↑
1
YE15
YE14
YE13
YE12
YE11
YE10
YE9
YE8
Y address start:
1
↑
1
YE7
YE6
YE5
YE4
YE3
YE2
YE1
YE0
S≦YE≦Y
0
↑
1
-
0
0
1
0
1
1
0
0
1
↑
1
D1[17:8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
1
↑
1
Dx[17:8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
1
↑
1
Dn[17:8]
Dn[7]
Dn[6]
Dn[5]
Dn[4]
Dn[3]
Dn[2]
Dn[1]
Dn[0]
0
↑
1
-
0
0
1
0
1
1
1
0
CASET
RASET
(2Bh) Row address set
(2Ch)
Memory write
RAMWR
RAMRD
Version 1.5
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Write data
(2Eh)
Memory read
2013/04
ST7789S
Instruction
D/CX WRX RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
D1[17:8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
1
1
↑
Dx[17:8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
1
1
↑
Dn[17:8]
Dn[7]
Dn[6]
Dn[5]
Dn[4]
Dn[3]
Dn[2]
Dn[1]
Dn[0]
0
↑
1
-
0
0
1
1
0
0
0
0
Hex
Function
Dummy read
Read data
Partial sart/end
(30h)
address set
1
↑
1
-
PSL15
PSL14
PSL13
PSL12
PSL11
PSL10
PSL9
PSL8
1
↑
1
-
PSL7
PSL6
PSL5
PSL4
PSL3
PSL2
PSL1
PSL0
Partial start
address: (0,
PTLAR
1,2, ..P)
1
↑
1
-
PEL15
PEL14
PEL13
PEL12
PEL11
PEL10
PEL9
PEL8
1
↑
1
-
PEL7
PEL6
PEL5
PEL4
PEL3
PEL2
PEL1
PEL0
Partial end
address (0, 1,2,
3, , P)
Vertical scrolling
0
↑
1
-
0
0
1
1
0
0
1
1
(33h)
definition
1
↑
1
-
TFA15
TFA14
TFA13
TFA12
TFA11
TFA10
TFA9
TFA8
1
↑
1
-
TFA7
TFA6
TFA5
TFA4
TFA3
TFA2
TFA1
TFA0
1
↑
1
-
VSA15
VSA14
VSA13
VSA12
VSA11
VSA10
VSA9
VSA8
1
↑
1
-
VSA7
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
1
↑
1
-
BFA15
BFA14
BFA13
BFA12
BFA11
BFA10
BFA9
BFA8
1
↑
1
-
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
0
↑
1
-
0
0
1
1
0
1
0
0
VSCRDEF
Tearing effect
TEOFF
(34h)
line off
Tearing effect
TEON
0
↑
1
-
0
0
1
1
0
1
0
1
(35h)
line on
1
↑
1
-
-
-
-
-
-
-
-
TEM
0
↑
1
-
0
0
1
1
0
1
1
0
Memory data
(36h)
MADCTL
access control
1
↑
1
-
MY
MX
MV
ML
RGB
0
0
0
0
↑
1
-
0
0
1
1
0
1
1
1
Vertical scrolling
(37h)
start address
VSCRSADD
1
↑
1
-
VSP15
VSP14
VSP13
VSP12
VSP11
VSP10
VSP9
VSP8
1
↑
1
-
VSP7
VSP6
VSP5
VSP4
VSP3
VSP2
VSP1
VSP0
IDMOFF
0
↑
1
-
0
0
1
1
1
0
0
0
(38h)
Idle mode off
IDMON
0
↑
1
-
0
0
1
1
1
0
0
1
(39h)
Idle mode on
COLMOD
0
↑
1
-
0
0
1
1
1
0
1
0
(3Ah)
Interface pixel
format
Version 1.5
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ST7789S
Instruction
D/CX WRX RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
1
↑
1
-
0
D6
D5
D4
0
D2
D1
D0
0
↑
1
-
0
0
1
1
1
1
0
0
Hex
Function
Interface format
Memory write
(3Ch)
continue
RAMWRC
1
↑
1
D1[17:8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
1
↑
1
Dx[17:8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
1
↑
1
Dn[17:8]
Dn[7]
Dn[6]
Dn[5]
Dn[4]
Dn[3]
Dn[2]
Dn[1]
Dn[0]
0
↑
1
-
0
0
1
1
1
1
1
0
Write data
Memory read
(3Eh)
continue
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
D1[17:8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
1
1
↑
Dx[17:8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
1
1
↑
Dn[17:8]
Dn[7]
Dn[6]
Dn[5]
Dn[4]
Dn[3]
Dn[2]
Dn[1]
Dn[0]
0
↑
1
-
0
1
0
0
0
1
0
0
1
↑
1
-
N15
N14
N13
N12
N11
N10
N9
N8
1
↑
1
-
N7
N6
N5
N4
N3
N2
N1
N0
0
↑
1
-
0
1
0
0
0
1
0
1
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
-
-
-
-
-
-
N9
N8
1
1
↑
-
N7
N6
N5
N4
N3
N2
N1
N0
0
↑
1
-
0
1
0
1
0
0
0
1
1
↑
1
-
DBV7
DBV6
DBV5
DBV4
DBV3
DBV2
DBV1
DBV0
0
↑
1
-
0
1
0
1
0
0
1
0
Dummy Read
RAMRDC
TESCAN
(44h) Set tear scanline
(45h)
Get scanline
Dummy Read
RDTESCAN
(51h)
Write display
WRDISBV
brightness
Read display
(52h)
brightness value
RDDISBV
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
DBV7
DBV6
DBV5
DBV4
DBV3
DBV2
DBV1
DBV0
0
↑
1
-
0
1
0
1
0
0
1
1
Dummy read
Write CTRL
(53h)
display
WRCTRLD
1
↑
1
-
0
0
BCTRL
0
DD
BL
0
0
0
↑
1
-
0
1
0
1
0
1
0
0
Read CTRL
RDCTRLD
Version 1.5
(54h)
value dsiplay
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
0
0
BCTRL
0
DD
BL
0
0
Page 153 of 300
Dummy read
2013/04
ST7789S
Instruction
D/CX WRX RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Function
Write content
adaptive
0
↑
1
-
0
1
0
1
0
1
0
1
(55h)
brightness
WRCACE
control and Color
enhancemnet
1
↑
1
-
CECTRL
0
CE1
CE0
0
0
C1
C0
Read content
adaptive
0
↑
1
-
0
1
0
1
0
1
1
0
(56h)
brightness
RDCABC
control
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
0
CECTRL
0
0
0
0
C1
C0
Dummy read
Write CABC
0
↑
1
-
0
1
0
1
1
1
1
0
(5Eh)
minimum
WRCABCMB
brightness
1
↑
1
-
CMB7
CMB6
CMB5
CMB4
CMB3
CMB2
CMB1
CMB0
Read CABC
0
↑
1
-
0
1
0
1
1
1
1
1
(5Fh)
brightness
RDCABCMB
RDID1
RDID2
RDID3
minimum
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
CMB7
CMB6
CMB5
CMB4
CMB3
CMB2
CMB1
CMB0
0
↑
1
-
1
1
0
1
1
0
1
0
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
Read parameter
0
↑
1
-
1
1
0
1
1
0
1
1
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
Read parameter
0
↑
1
-
1
1
0
1
1
1
0
0
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
Read parameter
Dummy read
(Dah)
(DBh)
(DCh)
Read ID1
Read ID2
Read ID3
Table 18 System Function Command List
“-”: Don’t care
Version 1.5
Page 154 of 300
2013/04
ST7789S
9.1.1
NOP (00h)
00H
NOP (No Operation)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NOP
0
↑
1
-
0
0
0
0
0
0
0
0
(00h)
Parameter
No Parameter
-
Description
This command is empty command.
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
Availability
Default
Status
Default Value
Power On Sequence
N/A
S/W Reset
N/A
H/W Reset
N/A
Flow Chart
Note: “-“Don’t care
Version 1.5
Page 155 of 300
2013/04
ST7789S
9.1.2
SWRESET (01h): Software Reset
01H
SWRESET (Software Reset)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SWRESET
0
↑
1
-
0
0
0
0
0
0
0
1
(01h)
Parameter
No Parameter
-
“-“ Don’t care
Description
-The display module performs a software reset, registers are written with their SW reset default values.
-Frame memory contents are unaffected by this command.
It will be necessary to wait 5msec before sending new command following software reset.
The display module loads all display suppliers’ factory default values to the registers during this 5msec.
Restriction
If software reset is sent during sleep in mode, it will be necessary to wait 120msec before sending sleep out command.
Software reset command cannot be sent during sleep out sequence.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
Availability
Default
Version 1.5
Status
Default Value
Power On Sequence
N/A
S/W Reset
N/A
H/W Reset
N/A
Page 156 of 300
2013/04
ST7789S
Legend
SWRESET
Command
Parameter
Display whole
blank screen
Display
Flow Chart
Set
Commands
to S/W
Default
Value
Action
Sleep In Mode
Mode
Sequential
transter
Version 1.5
Page 157 of 300
2013/04
ST7789S
9.1.3
RDDID (04h): Read Display ID
04H
RDDID (Read Display ID)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDID
0
↑
1
-
0
0
0
0
0
1
0
0
(04h)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
3rd parameter
1
1
↑
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
st
th
4 parameter
-This read byte returns 24-bit display identification information.
-The 1st parameter is dummy data
-The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID.
-The 3rd parameter (ID26 to ID20): LCD module/driver version ID
Description
-The 4th parameter (ID37 to UD30): LCD module/driver ID.
-Commands RDID1/2/3(Dah, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h,
respectively.
“-“ Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Status
Default Value
ID1
ID2
ID3
Power On Sequence
0x85
0x85
0x52
S/W Reset
0x85
0x85
0x52
H/W Reset
0x85
0x85
0x52
Default
Version 1.5
Page 158 of 300
2013/04
ST7789S
Serial I/F Mode
Parallel I/F Mode
Legend
Read 04h
Read 04h
Host
Display
Dummy
Clock
Dummy
Read
Command
Parameter
Display
Flow Chart
Send 2nd
parameter
Send 2nd
parameter
Action
Send 3rd
parameter
Send 3rd
parameter
Mode
Sequential
transter
Send 4th
parameter
Version 1.5
Send 4th
parameter
Page 159 of 300
2013/04
ST7789S
9.1.4
RDDST (09h): Read Display Status
09H
RDDST (Read Display Status)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDST
0
↑
1
-
0
0
0
0
1
0
0
1
(09h)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
BSTON
MY
MX
MV
ML
RGB
MH
ST24
3rd parameter
1
1
↑
-
ST23
IFPF2
IFPF1
IFPF0
4 parameter
1
1
↑
-
ST15
ST14
INVON
ST12
ST11
DISON
TEON
GCS2
5th parameter
1
1
↑
-
GCS1
GCS0
TEM
ST4
ST3
ST2
ST1
ST0
st
th
IDMON PTLON SLOUT NORON
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
BSTON
Booster Voltage Status
‘1’ =Booster on,
‘0’ =Booster off
MY
Row Address Order (MY)
‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)
‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’)
MX
Column Address Order (MX)
‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)
‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’0’)
MV
Row/Column Exchange (MV)
‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)
‘0’ = Normal, (when MADCTL (36h) D5=’0’
ML
Scan Address Order (ML)
‘0’ =Decrement,
(LCD refresh Top to Bottom, when MADCTL (36h) D4=’0’)
‘1’=Increment,
(LCD refresh Bottom to Top, when MADCTL (36h) D4=’1’)
Description
RGB
RGB/ BGR Order (RGB)
‘1’ =BGR, (When MADCTL (36h) D3=’1’)
‘0’ =RGB, (When MADCTL (36h) D3=’0’)
MH
Horizontal Order
‘0’ =Decrement,
(LCD refresh Left to Right, when MADCTL (36h) D2=’0’)
‘1’ =Increment,
(LCD refresh Right to Left, when MADCTL (36h) D2=’1’)
ST24
For Future Use
‘0’
ST23
For Future Use
‘0’
IFPF2
IFPF1
“011” = 12-bit / pixel,
Interface Color Pixel Format
“101” = 16-bit / pixel,
Definition
“110” = 18-bit / pixel,
IFPF0
Version 1.5
“111” = 16M truncated, others are not defined.
IDMON
Idle Mode On/Off
‘1’ = On, “0” = Off
PTLON
Partial Mode On/Off
‘1’ = On, “0” = Off
SLPOUT
Sleep In/Out
‘1’ = Out, “0” = In
Page 160 of 300
2013/04
ST7789S
NORON
‘1’ = Normal Display,
Display Normal Mode On/Off
‘0’ = Partial Display
ST15
Vertical Scrolling Status (Not Used)
‘1’ = Scroll on,“0” = Scroll off
ST14
Horizontal Scroll Status (Not Used)
‘0’
INVON
Inversion Status
‘1’ = On, “0” = Off
ST12
All Pixels On (Not Used)
‘0’
ST11
All Pixels Off (Not Used)
‘0’
DISON
Display On/Off
‘1’ = On, “0” = Off
TEON
Tearing effect line on/off
‘1’ = On, “0” = Off
GCSEL2
“000” = GC0
GCSEL1
“001” = GC1
Gamma Curve Selection
“010” = GC2
“011” = GC3
GCSEL0
”100” to “111” = Not defined
TEM
Tearing effect line mode
‘0’ = mode1, ‘1’ = mode2
ST4
For Future Use
‘0’
ST3
For Future Use
‘0’
ST2
For Future Use
‘0’
ST1
For Future Use
‘0’
ST0
For Future Use
‘0’
“-“ Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Status
Default Value (ST31 to ST0)
ST[31-24]
ST[23-16]
ST[15-8]
ST[7-0]
Power On Sequence
0000-0000
0110-0001
0000-0000
0000-0000
S/W Reset
0xxx-xx00
0xxx-0001
0000-0000
0000-0000
H/W Reset
0000-0000
0110-0001
0000-0000
0000-0000
Default
Version 1.5
Page 161 of 300
2013/04
ST7789S
Flow Chart
Version 1.5
Page 162 of 300
2013/04
ST7789S
9.1.5
RDDPM (0Ah): Read Display Power Mode
0AH
RDDPM (Read Display Power Mode)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDPM
0
↑
1
-
0
0
0
0
1
0
1
0
(0Ah)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
D1
D0
BSTON IDMON PTLON SLPOUT NORON DISON
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
BSTON
Booster Voltage Status
‘1’ =Booster on,
‘0’ =Booster off
IDMON
Idle mode on/off
‘1’ = Idle Mode On,
‘0’ = Idle Mode Off
PTLON
Partial mode on/off
‘1’ =Partial mode on,
‘0’ =Partial mode off,
Description
SLPOUT
Sleep in/out
‘1’ =Sleep out,
‘0’ =Sleep in,
NORON
Display normal mode on/off
‘1’ = Normal display,
‘0’ = Partial display,
DISON
Display on/off
‘1’ =Display on,
‘0’ =Display off,
D1
Not Used
“0”
D0
Not Used
“0”
“-“ Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Version 1.5
Page 163 of 300
2013/04
ST7789S
Default
Status
Default Value (D7 to D0)
Power On Sequence
0000-1000(08h)
S/W Reset
0000-1000(08h)
H/W Reset
0000-1000(08h)
Flow Chart
Version 1.5
Page 164 of 300
2013/04
ST7789S
9.1.6
RDDMADCTL (0Bh): Read Display MADCTL
0BH
RDDMADCTL (Read Display MADCTL)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDMADCTL
0
↑
1
-
0
0
0
0
1
0
1
1
(0Bh)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
MY
MX
MV
ML
RGB
MH
D1
D0
st
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
MY
Row Address Order (MY)
‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)
‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’)
MX
Column Address Order (MX)
‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)
‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’1’)
MV
Row/Column Exchange (MV)
‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)
‘0’ = Normal, (when MADCTL (36h) D5=’0’
ML
Scan Address Order (ML)
‘0’ =Decrement,
(LCD refresh Top to Bottom, when MADCTL (36h) D4=’0’)
Description
‘1’=Increment,
(LCD refresh Bottom to Top, when MADCTL (36h) D4=’1’)
RGB
RGB/ BGR Order (RGB)
‘1’ =BGR, (When MADCTL (36h) D3=’1’)
‘0’ =RGB, (When MADCTL (36h) D3=’0’)
MH
Horizontal Order
‘0’ =Decrement,
(LCD refresh Left to Right, when MADCTL (36h) D2=’0’)
‘1’ =Increment,
(LCD refresh Right to Left, when MADCTL (36h) D2=’1’)
D1
Not used
‘0’
D0
Not used
‘0’
“-“ Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Version 1.5
Page 165 of 300
2013/04
ST7789S
Default
Status
Default Value (D7 to D0)
Power On Sequence
0000-0000 (00h)
S/W Reset
No change
H/W Reset
0000-0000 (00h)
Flow Chart
Version 1.5
Page 166 of 300
2013/04
ST7789S
9.1.7
RDDCOLMOD (0Ch): Read Display Pixel Format
0CH
RDDCOLMOD (Read Display Pixel Format)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDCOLMOD
0
↑
1
-
0
0
0
0
1
1
0
0
(0Ch)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
0
D6
D5
D4
0
D2
D1
D0
st
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
D7
-
Set to ‘0’
D6
‘101’ = 16 bit/pixel
D5
RGB interface color format
‘110’ = 18 bit/pixel
D4
Description
D3
-
Set to ‘0’
D2
‘101’ = 16 bit/pixel
D1
Control interface color format
‘110’ = 18 bit/pixel
D0
Others are no define and invalid
“-“ Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000-0110 (18 bit/pixel)
S/W Reset
No change
H/W Reset
0000-0110 (18 bit/pixel)
Page 167 of 300
2013/04
ST7789S
Flow Chart
Version 1.5
Page 168 of 300
2013/04
ST7789S
9.1.8
RDDIM (0Dh): Read Display Image Mode
0DH
RDDIM (Read Display Image Mode)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDIM
0
↑
1
-
0
0
0
0
1
1
0
1
(0Dh)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
VSSON
0
INVON
0
0
GC2
GC1
GC0
st
This command indicates the current status of the display as described in the table below:
-VSSON: Vertical scrolling on/off
-INVON: Inversion on/off
Description
Gamma Curve Selection
GC2
GC1
GC0
Gamma set (26h) Parameter
Gamma curve 1
0
0
0
GC0
Gamma curve 2
0
0
1
GC1
Gamma curve 3
0
1
0
GC2
Gamma curve 4
0
1
1
GC3
Not Defined
1
0
0
Not Defined
Not Defined
1
0
1
Not Defined
Not Defined
1
1
0
Not Defined
Not Defined
1
1
1
Not Defined
Others are no define and invalid
“-“ Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000-0000
S/W Reset
0000-0000
H/W Reset
0000-0000
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Flow Chart
Version 1.5
Page 170 of 300
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9.1.9
RDDSM (0Eh): Read Display Signal Mode
0EH
RDDSM (Read Display Signal Status)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDSM
0
↑
1
-
0
0
0
0
1
1
1
0
(0Eh)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
TEON
TEM
0
0
0
0
0
0
-
st
This command indicates the current status of the display as described in the table below:
Bit
Description
TEON
Tearing effect line on/off
Value
‘1’ = ON,
Description
‘0’ = OFF,
‘1’ = mode2,
TEM
Tearing effect line mode
‘0’ = mode1,
“-“ Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000-0000
S/W Reset
0000-0000
H/W Reset
0000-0000
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Flow Chart
Version 1.5
Page 172 of 300
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9.1.10 RDDSDR (0Fh): Read Display Self-Diagnostic Result
09H
RDDSDR (Read Display Self-Diagnostic Result)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDSDR
0
↑
1
-
0
0
0
0
1
1
1
1
(0Fh)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
D7
D6
0
0
0
0
0
0
-
st
This command indicates the current status of the display self-diagnostic result after sleep out command as described
below:
Description
-D7: Register loading detection
-D6: Functionality detection
“-“ Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000-0000
S/W Reset
0000-0000
H/W Reset
0000-0000
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Flow Chart
Version 1.5
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9.1.11 SLPIN (10h): Sleep in
10H
SLPIN (Sleep In)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SLPIN
0
↑
1
-
0
0
0
1
0
0
0
0
(10h)
parameter
No Parameter
-This command causes the LCD module to enter the minimum power consumption mode.
-In this mode the DC/DC converter is stopped, internal oscillator is stopped, and panel scanning is stopped.
Description
-MCU interface and memory are still working and the memory keeps its contents.
“-“ Don’t care
-This command has no effect when module is already in sleep in mode. Sleep in mode can only be left by the sleep out
command (11h).
-It will be necessary to wait 5msec before sending any new commands to a display module following this command to
Restriction
allow time for the supply voltages and clock circuits to stabilize.
-It will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sending an sleep
in command.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Sleep in mode
S/W Reset
Sleep in mode
H/W Reset
Sleep in mode
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ST7789S
Legend
SLPIN
Display whole
blank screen
(Automatic No effect
to DISP ON/OFF
Commands)
Stop
DC-DC
Converter
Command
Parameter
Stop
Internal
Oscillator
Display
Flow Chart
Drain
Charge
From LCD
Panel
Sleep In Mode
Action
Mode
Sequential
transter
Version 1.5
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9.1.12 SLPOUT (11h): Sleep Out
11H
SLPOUT (Sleep Out)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SLPOUT
0
↑
1
-
0
0
0
1
0
0
0
1
(11h)
parameter
No Parameter
-This command turn off sleep mode.
Description
-In this mode the DC/DC converter is enable, internal display oscillator is started, and panel scanning is started.
-This command has no effect when module is already in sleep out mode. Sleep out mode can only be left by the sleep in
command (10h).
-It will be necessary to wait 5msec before sending any new commands to a display module following this command to
Restriction
allow time for the supply voltages and clock circuits to stabilize.
-It will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sending an sleep
in command.
-The display module runs the self-diagnostic functions after this command is received.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Sleep in mode
S/W Reset
Sleep in mode
H/W Reset
Sleep in mode
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Legend
Command
SLPOUT
Start
Internal
Oscillator
Display whole blank
screen for 2 firames
(Automatic No effect
to DISP ON/OFF
Commands)
Parameter
Display
Flow Chart
Start up
DC:DC
Converter
Charge
Offset
voltage for
LCD
Panel
Display Memory
contents In
accordance with
the current
command table
settings
Action
Mode
Sleep Out mode
Sequential
transter
Version 1.5
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9.1.13 PTLON (12h): Partial Display Mode On
12H
PTLON (Partial Display Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PTLON
0
↑
1
-
0
0
0
1
0
0
1
0
(12h)
parameter
No Parameter
-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h)
Description
-To leave Partial mode, the Normal Display Mode On command (13h) should be written.
“-“ Don’t care
Restriction
This command has no effect when partial mode is active.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Flow Chart
Version 1.5
Status
Default Value
Power On Sequence
Normal display mode on
S/W Reset
Normal display mode on
H/W Reset
Normal display mode on
See Partial Area (30h)
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9.1.14 NORON (13h): Normal Display Mode On
12H
NORON (Normal Display Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NORON
0
↑
1
-
0
0
0
1
0
0
1
1
(13h)
parameter
No Parameter
-This command turns the display to normal mode.
-Normal display mode on means partial mode off.
Description
-Exit from NORON by the partial mode on command.
“-“ Don’t care
Restriction
This command has no effect when normal display mode is active.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Flow Chart
Version 1.5
Status
Default Value
Power On Sequence
Normal display mode on
S/W Reset
Normal display mode on
H/W Reset
Normal display mode on
See partial area description for details of when to use this command.
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9.1.15
INVOFF (20h): Display Inversion Off
20H
INVOFF (Display Inversion Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
INVOFF
0
↑
1
-
0
0
1
0
0
0
0
0
(20h)
parameter
No Parameter
-This command is used to recover from display inversion mode.
“-“ Don’t care
(Example)
Top-Left
Description
Memory
Display
(0,0)
Restriction
This command has no effect when module is already in inversion off mode.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Display inversion off
S/W Reset
Display inversion off
H/W Reset
Display inversion off
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Legend
Command
Display
Inversion On
Mode
Parameter
Display
Flow Chart
INVOFF (20h)
Action
Display
Inversion OFF
Mode
Mode
Sequential
transter
Version 1.5
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9.1.16 INVON (21h): Display Inversion On
21H
INVON (Display Inversion On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
INVON
0
↑
1
-
0
0
1
0
0
0
0
1
(21h)
parameter
No Parameter
-This command is used to recover from display inversion mode.
“-“ Don’t care
(Example)
Description
Restriction
Top-Left (0,0)
Memory
Display
This command has no effect when module is already in inversion on mode.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Display inversion off
S/W Reset
Display inversion off
H/W Reset
Display inversion off
Page 183 of 300
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ST7789S
Legend
Command
Display
Inversion OFF
Mode
Parameter
Display
Flow Chart
INVON (21h)
Action
Display
Inversion ON
Mode
Mode
Sequential
transter
Version 1.5
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9.1.17 GAMSET (26h): Gamma Set
26H
GAMSET (Gamma Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
GAMSET
0
↑
1
-
0
0
1
0
0
1
1
0
(26h)
parameter
1
↑
1
-
0
0
0
0
GC3
GC2
GC1
GC0
-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can
be selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table.
GC [7:0]
Parameter
Curve Selected
01h
GC0
Gamma Curve 1 (G2.2)
02h
GC1
Gamma Curve 2 (G1.8)
04h
GC2
Gamma Curve 3 (G2.5)
08h
GC3
Gamma Curve 4 (G1.0)
1. Description
Note: All other values are undefined.
Values of GC[7:0] not shown in table above are invalid and will not change the current selected Gamma curve
Restriction
until valid value is received.
Register availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
0x01
S/W Reset
0x01
H/W Reset
0x01
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Flow Chart
Version 1.5
Page 186 of 300
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9.1.18 DISPOFF (28h): Display Off
28H
DISPOFF (Display Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
DISPOFF
0
↑
1
-
0
0
1
0
1
0
0
0
(28h)
parameter
No Parameter
- This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and
blank page inserted.
- This command makes no change of contents of frame memory.
- This command does not change any other status.
- There will be no abnormal visible effect on the display.
- Exit from this command by Display On (29h)
Description
(Example)
Memory
Restriction
Display
This command has no effect when module is already in display off mode.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Display off
S/W Reset
Display off
H/W Reset
Display off
Page 187 of 300
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Flow Chart
Version 1.5
Page 188 of 300
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9.1.19 DISPON (29h): Display On
29H
DISPON (Display On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
DISPON
0
↑
1
-
0
0
1
0
1
0
0
1
(29h)
parameter
No Parameter
- This command is used to recover from DISPLAY OFF mode.
- Output from the Frame Memory is enabled.
- This command makes no change of contents of frame memory.
- This command does not change any other status.
Description
(Example)
Memory
Restriction
Display
This command has no effect when module is already in display on mode.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Display off
S/W Reset
Display off
H/W Reset
Display off
Page 189 of 300
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Legend
Command
Display Off
Mode
Parameter
Display
Flow Chart
DISPON
Action
Display On
Mode
Mode
Sequential
transter
Version 1.5
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9.1.20 CASET (2Ah): Column Address Set
2AH
CASET (Column Address Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CASET
0
↑
1
-
0
0
1
0
1
0
1
0
(2Ah)
1 parameter
1
↑
1
-
XS15
XS14
XS13
XS12
XS11
XS10
XS9
XS8
2nd parameter
1
↑
1
-
XS7
XS6
XS5
XS4
XS3
XS2
XS1
XS0
3rd parameter
1
↑
1
-
XE15
XE14
XE13
XE12
XE11
XE10
XE9
XE8
1
↑
1
-
XE7
XE6
XE5
XE4
XE3
XE2
XE1
XE0
st
th
4 parameter
-The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes.
-Each value represents one column line in the Frame Memory.
XS[7:0]
XE[7:0]
2. Description
XS [15:0] always must be equal to or less than XE [15:0]
When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored.
Restriction
(Parameter range: 0 < XS [15:0] < XE [15:0] < 239 (00Efh)): MV=”0”)
(Parameter range: 0 < XS [15:0] < XE [15:0] < 319 (013Fh)): MV=”1”)
Register availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
XS[15:0]=0x00
XE[15:0]=0Xef
XS[15:0]=0x00
When MV=0: XE[15:0]=00Efh,
Default
S/W Reset
When MV=1: XE[15:0]=013Fh
H/W Reset
Version 1.5
XS[15:0]=0x00
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XE[15:0]=0Xef
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Flow Chart
Version 1.5
Page 192 of 300
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9.1.21 RASET (2Bh): Row Address Set
2BH
RASET (Row Address Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RASET
0
↑
1
-
0
0
1
0
1
0
1
1
(2Bh)
1 parameter
1
↑
1
-
YS15
YS14
YS13
YS12
YS11
YS10
YS9
YS8
2nd parameter
1
↑
1
-
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
3rd parameter
1
↑
1
-
YE15
YE14
YE13
YE12
YE11
YE10
YE9
YE8
1
↑
1
-
YE7
YE6
YE5
YE4
YE3
YE2
YE1
YE0
st
th
4 parameter
-This command is used to defined area of frame memory where MCU can access.
-The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes.
-Each value represents one page line in the Frame Memory.
YS[15:0]
3. Description
YE[15:0]
YS [15:0] always must be equal to or less than YE [15:0]
When YS [15:0] or YE [15:0] is greater than maximum address like below, data of out of range will be ignored.
Restriction
(Parameter range: 0 < YS [15:0] < YE [15:0] < 239 (00Efh)): MV=”0”)
(Parameter range: 0 < YS [15:0] < YE [15:0] < 319 (013Fh)): MV=”1”)
Register availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
YS[15:0]=0000h
YE[15:0]=013Fh
YS[15:0]=0000h
When MV=0: YE[15:0]=013Fh,
Default
S/W Reset
When MV=1: YE[15:0]=00Efh
H/W Reset
Version 1.5
YS[15:0]=0000h
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YE[15:0]=013Fh
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CASET
Legend
1st parameter XS[15:0]
2nd parameter XE[15:0]
Command
Parameter
PASET
Flow Chart
1st parameter YS[15:0]
2nd parameter YE[15:0]
Display
Action
Mode
RAMWR
Sequential
transter
Image Data
D1[7:0],D2[7:0]
…….Dn[7:0]
Any Command
Version 1.5
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9.1.22 RAMWR (2Ch): Memory Write
2CH
RAMWR (Memory Write)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RAMWR
0
↑
1
-
0
0
1
0
1
1
0
0
(2Ch)
1 parameter
1
↑
1
D1[17]-1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
…
1
↑
1
Dx[17]-x[8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
N parameter
1
↑
1
Dn[17]-n[8]
Dn[7]
Dn[6]
Dn[5]
Dn[4]
Dn[3]
Dn[2]
Dn[1]
Dn[0]
st
-This command is used to transfer data from MCU to frame memory.
-When this command is accepted, the column register and the page register are reset to the start column/start
Description
page positions.
-The start column/start page positions are different in accordance with MADCTL setting.
-Sending any other command can stop frame write.
Restriction
Register availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
Contents of memory is set randomly
S/W Reset
Contents of memory is not cleared
H/W Reset
Contents of memory is not cleared
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Legend
Command
RAMWR
Parameter
Display
Flow Chart
Image Data
D1[17:0],D2[17:0]
…….Dn[17:0]
Action
Mode
Any Command
Version 1.5
Page 196 of 300
Sequential
transter
2013/04
ST7789S
9.1.23 RAMRD (2Eh): Memory Read
2EH
RAMRD (Memory Read)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RAMRD
0
↑
1
-
0
0
1
0
1
1
1
0
(2Eh)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
..
1
1
↑
..
..
..
..
..
..
..
..
..
(N+1) parameter
1
1
↑
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
st
th
-This command is used to transfer data from frame memory to MCU.
-When this command is accepted, the column register and the row register are reset to the Start Column/Start
Row positions.
-The Start Column/Start Row positions are different in accordance with MADCTL setting.
-Then D[17:0] is read back from the frame memory and the column register and the row register incremented
Description
-Frame Read can be cancelled by sending any other command.
-The data color coding is fixed to 18-bit in reading function. Please see section 9.8 “Data color coding” for color
coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data.
Note1: The Command 3Ah should be set to 66h when reading pixel data from frame memory.
Restriction
Register availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
Contents of memory is set randomly
S/W Reset
Contents of memory is not cleared
H/W Reset
Contents of memory is not cleared
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Flow Chart
Version 1.5
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9.1.24 PTLAR (30h): Partial Area
30H
PTLAR (Partial Area)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PTLAR
0
↑
1
-
0
0
1
1
0
0
0
0
(30h)
1 parameter
1
↑
1
-
PSL15
PSL14
PSL13
PSL12
PSL11
PSL10
PSL9
PSL8
2nd parameter
1
↑
1
-
PSL7
PSL6
PSL5
PSL4
PSL3
PSL2
PSL1
PSL0
3rd parameter
1
↑
1
-
PEL15
PEL14
PEL13
PEL12
PEL11
PEL10
PEL9
PEL8
1
↑
1
-
PEL7
PEL6
PEL5
PEL4
PEL3
PEL2
PEL1
PEL0
st
th
4 parameter
-This command defines the partial mode’s display area.
-There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End
Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter.
-If End Row > Start Row, when MADCTL ML=’1’
End row
PEL [15:0]
Non-display area
Partial display area
PSL [15:0]
Start row
Non-display area
-If End Row > Start Row, when MADCTL ML=’0’
Start row
Non-display area
PSL [15:0]
Description
Partial display area
PEL [15:0]
Non-display area
End row
-If End Row < Start Row, when MADCTL ML=’0’
End row
Partial display area
PEL [15:0]
Non-display area
PSL [15:0]
Start row
Partial display area
-If End Row = Start Row then the Partial Area will be one row deep.
Version 1.5
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Restriction
Each detail initial value by the display resolution will be updated.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Status
Default Value
Power On Sequence
PSL[15:0]=0000h, PEL=013Fh
S/W Reset
PSL[15:0]=0000h, PEL=013Fh
H/W Reset
PSL[15:0]=0000h, PEL=013Fh
Flow Chart
Version 1.5
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9.1.25 VSCRDEF (33h): Vertical Scrolling Definition
33H
(Vertical Scrolling Definition)
Inst / Para D/CX WRX RDX D17-8
VSCRDEF
D7
D6
D5
D4
D3
D2
D1
D0
HEX
(33h)
0
↑
1
-
0
0
1
1
0
0
1
1
1
↑
1
-
TFA15
TFA14
TFA13
TFA12
TFA11
TFA10
TFA9
TFA8
1
↑
1
-
TFA7
TFA6
TFA5
TFA4
TFA3
TFA2
TFA1
TFA0
1
↑
1
-
VSA15
VSA14
VSA13
VSA12
VSA11
VSA10
VSA9
VSA8
1
↑
1
-
VSA7
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
1
↑
1
BFA15
BFA14
BFA13
BFA12
BFA11
BFA10
BFA9
BFA8
1
↑
1
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
st
1
parameter
2nd
parameter
3rd
parameter
4th
parameter
5th
parameter
6th
parameter
-This command just defines the Vertical Scrolling Area of the display and not performs vertical scroll
-When MADCTL MV=0
-The 1st & 2nd parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display).
-The 3rd & 4th parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory
[not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the
Top Fixed Area.
-The 4th & 5th parameter BFA [6:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and
Display).
TFA, VSA and BFA refer to the Frame Memory Line Pointer
Description
Restriction The condition is TFA+VSA+BFA = 320, otherwise Scrolling mode is undefined.
Version 1.5
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In Vertical Scrolling Mode, MADCTL parameter MV should be set to ‘0’ – this only affects the Frame Memory write.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
TFA[15:0] = 0000h
VSA[0:15] = 0140h
BFA[15:0] = 0000h
S/W Reset
TFA[15:0] = 0000h
VSA[0:15] = 0140h
BFA[15:0] = 0000h
H/W Reset
TFA[15:0] = 0000h
VSA[0:15] = 0140h
BFA[15:0] = 0000h
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1. TO Enter Vertical Scroll Mode:
Normal Mode
Legend
VSCRDEF
1st parameter TFA[15:0]
Command
2nd parameter VSA[15:0]
Parameter
3rd parameter BFA[15:0]
CASET
Display
1st &2nd parameter XS[15:0]
3rd & 4th parameter XE[15:0]
Flow Chart
RASET
Only required
for non-rolling
scrolling
1st &2nd parameter YS[15:0]
Redefines the
Frame Memory
Window that
the scroll data
will be written
to.
Action
Mode
3rd &4th parameter YE[15:0]
MADCTL
Parameter
RAMWR
Optional - It
may be
necessary to
redefine the
frame memory
write direction.
Sequential
transter
Scroll Image Data
VSCSAD
1st &2nd parameter VSA[15:0]
Scroll Mode
Version 1.5
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9.1.26 TEOFF (34h): Tearing Effect Line OFF
34H
TEOFF (Tearing Effect Line OFF)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
TEOFF
0
↑
1
-
0
0
1
1
0
1
0
0
(34h)
parameter
No Parameter
Description
-This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Restriction
This command has no effect when tearing effect output is already off..
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Off
S/W Reset
Off
H/W Reset
Off
Page 204 of 300
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Legend
Command
TE Line Output
ON
Parameter
TEOFF
Display
Flow Chart
TE Line Output
OFF
Action
Mode
Sequential
transter
Version 1.5
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9.1.27 TEON (35h): Tearing Effect Line On
35H
TEON (Tearing Effect Line On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
TEON
0
↑
1
-
0
0
1
1
0
1
0
1
(35h)
parameter
1
↑
1
-
0
0
0
0
0
0
0
TEM
-This command is used to turn ON the Tearing Effect output signal from the TE signal line.
-This output is not affected by changing MADCTL bit ML.
-The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line:
-When TEM =’0’: The Tearing Effect output line consists of V-Blanking information only
Tvdl
Description
Tvdh
Vertical time scale
-When TEM =’1’: The Tearing Effect output Line consists of both V-Blanking and H-Blanking information
Tvdl
Tvdh
Vertical time scale
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Restriction
This command has no effect when tearing effect output is already on.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Off
S/W Reset
Off
H/W Reset
Off
Page 206 of 300
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Legend
TE Line Output
OFF
Command
Parameter
TEON
Display
Flow Chart
TELOM
Action
TE Line Output
ON
Mode
Sequential
transter
Version 1.5
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9.1.28 MADCTL (36h): Memory Data Access Control
36H
MADCTL (Memory Data Access Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
MADCTL
0
↑
1
-
0
0
1
1
0
1
1
0
(36h)
parameter
1
↑
1
-
MY
MX
MV
ML
RGB
-
-
-
-This command defines read/ write scanning direction of frame memory.
Bit
NAME
MY
Row Address Order
MX
Column Address Order
MV
Row/Column Exchange
DESCRIPTION
These 3bits controls MCU to memory
write/read direction.
LCD vertical refresh direction control
ML
Vertical Refresh Order
‘0’ = LCD vertical refresh Top to Bottom
‘1’ = LCD vertical refresh Bottom to Top
Color selector switch control
RGB
RGB-BGR ORDER
‘0’ =RGB color filter panel,
‘1’ =BGR color filter panel)
-Bit Assignment
Description Top-left (0, 0)
Top-left (0, 0)
Memory
Display
Send first
Send 2nd
Send 3rd
ML="0"
Send last
Top-left (0, 0)
Top-left (0, 0)
Memory
Display
Send last
ML="1"
Send 3rd
Send 2nd
Send first
Version 1.5
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R
G
B
R
SIG1
RGB="0"
RGB="1"
Driver IC
Driver IC
G
B
R
SIG2
SIG1
SIG2
R
G
B
R
R
G
B
R
G
B
R
SIG240
G
B
R
SIG1
SIG240
SIG1
B
R
G
B
B
G
R
B
G
B
R
G
B
B
G
R
B
Top-left (0, 0)
B
R
G
B
SIG240
SIG2
G
LCD panel
G
SIG2
SIG240
G
R
B
G
R
G
R
B
G
R
LCD panel
Top-left (0, 0)
Memory
Memory
ML="0"
ML="1"
Send first
Send 3rd
Send 2nd
Send last
Send last
Send 3rd
Send 2nd
Send first
Top-left (0, 0)
Top-left (0, 0)
Display
Display
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Version 1.5
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Default
Status
Default Value
Power On Sequence
0000h
S/W Reset
No change
H/W Reset
0000h
Legend
Command
MADCTL
Parameter
Display
Flow Chart
1st parameter
B[7:0]
Action
Mode
Sequential
transter
Version 1.5
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9.1.29 VSCSAD (37h): Vertical Scroll Start Address of RAM
37H
Inst / Para
VSCSAD (Vertical Scroll Start Address of RAM)
D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
(37h)
0
↑
1
-
0
0
1
1
0
1
1
1
parameter
1
↑
1
-
VSP15
VSP14
VSP13
VSP12
VSP11
VSP10
VSP9
VSP8
2ND parameter
1
↑
1
-
VSP7
VSP6
VSP5
VSP4
VSP3
VSP2
VSP1
VSP0
VSCSAD
ST
1
-This command is used together with Vertical Scrolling Definition (33h).
-These two commands describe the scrolling area and the scrolling mode.
-The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory
will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below:
When ML=0
Example:
When Top Fixed Area = Bottom Fixed Area = 00, vertical Scrolling Area = 320 and VSP = ‘3’
Description
When ML=1
Example:
When Top Fixed Area = Bottom Fixed Area = 00, vertical Scrolling Area = 320 and VSP = ‘3’
NOTE: When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel
Scan to avoid tearing effect.
VSP refers to the Frame Memory line Pointer
Since the value of the vertical scrolling start address is absolute (with reference to the frame memory), it must not
Restriction
enter the fixed area (defined by Vertical Scrolling Definition (33h)- otherwise undesirable image will be displayed on
the panel)
Register
availability
Version 1.5
Page 211 of 300
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Default
Flow Chart
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
See Vertical Scrolling Definition (33h) description
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9.1.30 IDMOFF (38h): Idle Mode Off
38H
IDMOFF (Idle Mode Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
IDMOFF
0
↑
1
-
0
0
1
1
1
0
0
0
(38h)
parameter
No Parameter
-This command is used to recover from Idle mode on.
-In the idle off mode,
Description
1. LCD can display 4096, 65k or 262k colors.
2. Normal frame frequency is applied.
Restriction
This command has no effect when module is already in idle off mode
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
Idle mode off
S/W Reset
Idle mode off
H/W Reset
Idle mode off
Page 213 of 300
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Flow Chart
Version 1.5
Page 214 of 300
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9.1.31 IDMON (39h): Idle mode on
39H
IDMON (Idle Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
IDMON
0
↑
1
-
0
0
1
1
1
0
0
1
(39h)
parameter
No Parameter
-This command is used to enter into Idle mode on.
-There will be no abnormal visible effect on the display mode change transition.
-In the idle on mode,
1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame
Memory, 8 color depth data is displayed.
2. 8-Color mode frame frequency is applied.
3. Exit from IDMON by Idle Mode Off (38h) command
Top-Left (0,0)
(Example) Memory
Display
Description
Restriction
Color
R5 R4 R3 R2 R1 R0
G5 G4 G3 G2 G1 G0
B5 B4 B3 B4 B1 B0
Black
0xxxxx
0xxxxx
0xxxxx
Blue
0xxxxx
0xxxxx
1xxxxx
Red
1xxxxx
0xxxxx
0xxxxx
Magenta
1xxxxx
0xxxxx
1xxxxx
Green
0xxxxx
1xxxxx
0xxxxx
Cyan
0xxxxx
1xxxxx
1xxxxx
Yellow
1xxxxx
1xxxxx
0xxxxx
White
1xxxxx
1xxxxx
1xxxxx
This command has no effect when module is already in idle off mode
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Version 1.5
Page 215 of 300
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Default
Status
Default Value
Power On Sequence
Idle mode off
S/W Reset
Idle mode off
H/W Reset
Idle mode off
Legend
Command
Idle off mode
Parameter
IDMON
Display
Idle on mode
Action
Flow Chart
Mode
Sequential
transter
Version 1.5
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9.1.32 COLMOD (3Ah): Interface Pixel Format
3AH
Inst / Para
COLMOD
1st
Parameter
COLMOD (Interface Pixel Format)
D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
(3Ah)
0
↑
1
-
0
0
1
1
1
0
1
0
1
↑
1
-
0
D6
D5
D4
0
D2
D1
D0
This command is used to define the format of RGB picture data, which is to be transferred via the
MCU interface. The formats are shown in the table:
1st parameter:
Bit
Description
D7
-
Set to ‘0’
D6
RGB interface color format
D5
Description
‘101’ = 65K of RGB interface
‘110’ = 262K of RGB interface
D4
D3
-
D2
Set to ‘0’
‘011’ = 12bit/pixel
D1
Control interface color format
‘101’ = 16bit/pixel
‘110’ = 18bit/pixel
D0
‘111’ = 16M truncated
Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory.
Note2: The Command 3Ah should be set at 55h when writing 16-bit/pixel data into frame memory, but 3Ah should be
re-set to 66h when reading pixel data from frame memory.
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Flow Chart
Version 1.5
Status
Default Value
Power On Sequence
18bit/pixel
S/W Reset
No change
H/W Reset
18bit/pixel
See Vertical Scrolling Definition (33h) description
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9.1.33 WRMEMC (3Ch): Write Memory Continue
3CH
Inst / Para
WRMEMC (Write Memory Continue)
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
(3Ch)
WRMEMC
0
↑
1
-
0
0
1
1
1
1
0
0
ST
1
↑
1
D1[17]-D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
…
D/CX WRX RDX
1
↑
1
Dx[17]-Dx[8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
Nth parameter
1
↑
1
Dn[17]-Dn[8]
Dn[7]
Dn[6]
Dn[5]
Dn[4]
Dn[3]
Dn[2]
Dn[1]
Dn[0]
1
parameter
-This command transfers image data from the host processor to the display module’s frame memory continuing from
the pixel location following the previous write memory continue or memory write command.
-If MV=0:
Data is written continuing from the pixel location after the write range of the previous memory write or write memory
continue. The column register is then incremented and pixels are written to the frame memory until the column register
equals the end column (XE) value. The column register is then reset to XS and the page register is incremented. Pixels
are written to the frame memory until the page register equals the end page (YE) value and the column register equals
the XE value, or the host processor sends another command. If the number of pixels exceeds (XE-XS+1)*(YE-YS+1)
Description the extra pixels are ignored.
If MV=1:
Data is written continuing from the pixel location after the write range of the previous memory write or write memory
continue. The page register is then incremented and pixels are written to the frame memory until the page register
equals the end page (YE) value. The page register is then reset to YS and the column register is incremented. Pixels
are written to the frame memory until the column register equals the end column (XE) value and the page register
equals the YE value, or the host processor sends another command. If the number of pixels exceeds
(XE-XS+1)*(YE-YS+1) the extra pixels are ignored.
A memory write should follow a column address set or page address set to define the write address. Otherwise, data
Restriction
written with write memory continue is written to undefined addresses.
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Version 1.5
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Default
Status
Default Value
Power On Sequence
Contents of memory is set randomly
S/W Reset
Contents of memory is not cleared
H/W Reset
Contents of memory is not cleared
Legend
Command
WRMEMC
Parameter
Display
Flow Chart
Image Data
D1[17:0],D2[17:0]
…….Dn[17:0]
Action
Mode
Any Command
Version 1.5
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9.1.34 RDMEMC (3Eh): Read Memory Continue
3EH
D/CX WRX RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
-
0
0
1
1
1
1
1
0
(3Eh)
parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
D1[17]-D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
…
Inst / Para
RDMEMC (Read Memory Continue)
1
1
↑
Dx[17]-Dx[8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
Nth parameter
1
1
↑
Dn[17]-Dn[8]
Dn[7]
Dn[6]
Dn[5]
Dn[4]
Dn[3]
Dn[2]
Dn[1]
Dn[0]
RDMEMC
ST
1
-This command transfers image data from the host processor to the display module’s frame memory continuing from
the pixel location following the previous read memory continue or memory read command.
-If MV=0:
Pixels are read continuing from the pixel location after the read range of the previous memory read or read memory
continue. The column register is then incremented and pixels are read from the frame memory until the column register
equals the end column (XE) value. The column register is then reset to XS and the page register is incremented. Pixels
are read from the frame memory until the page register equals the end page (YE) value and the column register equals
Description the XE value, or the host processor sends another command.
If MV=1:
Pixels are read continuing from the pixel location after the read range of the previous memory read or read memory
continue. The page register is then incremented and pixels are read from the frame memory until the page register
equals the end page (YE) value. The page register is then reset to YS and the column register is incremented. Pixels
are read from the frame memory until the column register equals the end column (XE) value and the page register
equals the YE value, or the host processor sends another command.
Regardless of the color mode set in interface pixel format, the pixel format returned by read memory continue is always
Restriction
18-bit so there is no restriction on the length of data
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Status
Default Value
Power On Sequence
Contents of memory is set randomly
S/W Reset
Contents of memory is not cleared
Default
Version 1.5
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H/W Reset
Contents of memory is not cleared
Flow Chart
Version 1.5
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9.1.35
STE (44h): Set Tear Scanline
44H
STE (Set Tear ScanLine )
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
STE
0
↑
1
-
0
1
0
0
0
1
0
0
(44h)
1st parameter
1
↑
1
-
N15
N14
N13
N12
N11
N10
N9
N8
2nd parameter
1
↑
1
-
N7
N6
N5
N4
N3
N2
N1
N0
-This command turns on the display module’s Tearing Effect output signal on the TE signal line when the display
module reaches line N. The TE signal is not affected by changing MV.
-The tearing effect line on has one parameter that describes the tearing effect output line mode.
-The tearing effect output line consist of V-blanking information only.
Tvdl
Description
Tvdh
Vertical time scale
Note that set tear scanline with N=0 is equivalent to tearing effect line on with TEM=0.
The tearing effect output line shall be active low when the display module is in sleep mode
This command takes affect on the frame following the current frame. Therefore, if the tear effect (TE) output is already
Restriction
on, the TE output shall continue to operate as programmed by the previous tearing effect line on or set tear scanline
command until the end of the frame
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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Legend
Command
TE Output On or OFF
Parameter
Set Tear on
Display
Flow Chart
Line N (LSB)
Action
Line N (MSB)
Mode
TE Output ON
Sequential
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9.1.36
GSCAN (45h): Get Scanline
45H
GSCAN (Get ScanLine )
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
GSCAN
0
↑
1
-
0
1
0
0
0
1
0
1
(45h)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
N15
N14
N13
N12
N11
N10
N9
N8
3rd parameter
1
1
↑
-
N7
N6
N5
N4
N3
N2
N1
N0
st
-The display module returns the current scanline ,N, used to update the display device. The total number of scanlines
on a display device is defined as VSYNC+VBP+VACT+VFP. The first scanline is defined as the first line of V Sync and
Description
is denoted as Line 0.
-When in sleep in mode, the value returned by get scanline is undefined.
Restriction
-
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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Legend
Get scanline
Command
Dummy read
Parameter
Line N (MSB)
Display
Flow Chart
Line N (LSB)
Action
Mode
Sequential
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9.1.37 WRDISBV (51h): Write Display Brightness
51H
WRDISBV (Write Display Brightness)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
WRDISBV
0
↑
1
-
0
1
0
1
0
0
0
1
(51h)
Parameter
1
↑
1
-
DBV7
DBV6
DBV5
DBV4
DBV3
DBV2
DBV1
DBV0
-This command is used to adjust the brightness value of the display.
-It should be checked what the relationship between this written value and output brightness of the display is. This
Description
relationship is defined on the display module specification.
-In principle relationship is that 00h value means the lowest brightness and FFh value means the highest brightness.
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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Legend
Command
Parameter
WRDISBV
Display
Flow Chart
DBV[7:0]
Action
New Display
Luminance
Value Loaded
Mode
Sequential
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9.1.38 RDDISBV (52h): Read Display Brightness Value
52H
RDDISBV (Read Display Brightness Value )
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDISBV
0
↑
1
-
0
1
0
1
0
0
1
0
(52h)
st
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
DBV7
DBV6
DBV5
DBV4
DBV3
DBV2
DBV1
DBV0
-This command returns the brightness value of the display.
-It should be checked what the relationship between this returned value and output brightness of the display. This
relationship is defined on the display module specification is.
Description
-In principle the relationship is that 00h value means the lowest brightness and FFh value means the highest brightness.
-DBV[7:0] is reset when display is in sleep in mode.
-DBV[7:0] is ‘0’ when bit BCTRL of write CTRL display command (53h) is ‘0’
-DBV[7:0] IS manual set brightness specified with write CTRL display command (53h) when bit BCTRL is ‘1’
Restriction
-
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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Flow Chart
Version 1.5
Page 229 of 300
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9.1.39 WRCTRLD (53h): Write CTRL Display
53H
WRCTRLD (Write CTRL Display )
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
WRCTRLD
0
↑
1
-
0
1
0
1
0
0
1
1
(53h)
Parameter
1
↑
1
-
0
0
BCTRL
0
DD
BL
0
0
-This command is used to control display brightness.
-BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
0 = Off (Brightness register are 00h, DBV[7:0])
1 = On (Brightness register are active, according to the other parameters.)
-DD: Display Dimming (Only for manual brightness setting)
DD = 0: Display Dimming is off.
DD = 1: Display Dimming is on.
Description
-BL: Backlight Control On/Off
0 = Off (Completely turn off backlight circuit. Control lines must be low.)
1 = On
-Dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=1.
-When BL bit changed from ‘on’ to ‘off’, backlight is turned off without gradual dimming, even if dimming-on (DD=1) are
selected.
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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ST7789S
Legend
Command
Parameter
WRCTRLD
Display
Flow Chart
BCTRL, DD, BL
Action
New control
Value loaded
Mode
Sequential
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Version 1.5
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9.1.40 RDCTRLD (54h): Read CTRL Value Display
54H
RDCTRLD (Read CTRL value Display )
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDCTRLD
0
↑
1
-
0
1
0
1
0
1
0
0
(54h)
st
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
0
0
BCTRL
0
DD
BL
0
0
-This command returns ambient light and brightness control values..
-BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
0 = Off
1 = On
-DD: Display Dimming (Only for manual brightness setting)
Description
DD = 0
DD = 1
-BL: Backlight Control On/Off
0 = Off
1 = On
Restriction
-
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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Flow Chart
Version 1.5
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9.1.41 WRCACE (55h): Write Content Adaptive Brightness Control and Color Enhancement
55H
WRCACE (Write Content Adaptive Brightness Control and Color Enhancement)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
WRCACE
0
↑
1
-
0
1
0
1
0
1
0
1
(55h)
Parameter
1
↑
1
-
CECTRL
0
CE1
CE0
0
0
C1
C0
-This command is used to set parameters for image content based adaptive brightness control functionality and Color
Enhancement function.
-There is possible to used 4 different modes for content adaptive image functionality, which are defined on a table
below.
C1
C0
Function
0
0
Off
0
1
User Interface Mode
1
0
Still Picture
1
1
Moving Image
Description
-CECTRL: Color Enhancement Control Bit:
CECTRL=0: Color Enhancement Off.
CECTRL=1: Color Enhancement On.
-There are three color enhancement levels can be set.
CE1
CE0
Color enhancement level
0
0
Low enhancement
0
1
Medium enhancement
1
1
High enhancement
‘-’: Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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Legend
Command
Parameter
WRCACE
Display
st
Flow Chart
1 parameter:
C[1:0]
Action
New Adaptive
Image Mode
Mode
Sequential
transter
Version 1.5
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9.1.42 RDCABC (56h): Read Content Adaptive Brightness Control
56H
RDCABC (Read Content Adaptive Brightness Control )
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDCABC
0
↑
1
-
0
1
0
1
0
1
1
0
(56h)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
0
0
0
0
0
0
C1
C0
st
-This command is used to read the settings for image content based adaptive brightness control functionality.
-There is possible to used 4 different modes for content adaptive image functionality, which are defined on a table
below.
Description
C1
C0
Function
0
0
Off
0
1
User Interface Mode
1
0
Still Picture
1
1
Moving Image
‘-’: Don’t care
Restriction
-
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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Flow Chart
Version 1.5
Page 237 of 300
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9.1.43 WRCABCMB (5Eh): Write CABC Minimum Brightness
5EH
WRCABCMB (Write CABC Minimum Brightness )
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
WRCABCMB
0
↑
1
-
0
1
0
1
1
1
1
0
(5Eh)
Parameter
1
↑
1
-
CMB7
CMB6
CMB5
CMB4
CMB3
CMB2
CMB1
CMB0
-This command is used to set the minimum brightness value of the display for CABC function.
-In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the brightness
Description
for CABC.
‘-’: Don’t care
Restriction
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Version 1.5
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
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Legend
Command
Parameter
WRCABCMB
Display
Flow Chart
CMB[7:0]
Action
New Display
Luminance
Value Loaded
Mode
Sequential
transter
Version 1.5
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9.1.44 RDCABCMB (5Fh): Read CABC Minimum Brightness
5FH
RDCABCMB (Read CABC Minimum Brightness)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDCABCMB
0
↑
1
-
0
1
0
1
1
1
1
1
(5Fh)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
CMB7
CMB6
CMB5
CMB4
CMB3
CMB2
CMB1
CMB0
st
-This command returns the minimum brightness value of CABC function.
-In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the brightness for
Description
CABC.
‘-’: Don’t care
Restriction
-
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Status
Default Value
Power On Sequence
0000h
S/W Reset
0000h
H/W Reset
0000h
Flow Chart
Version 1.5
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9.1.45 RDID1 (Dah): Read ID1
DAH
RDID1 (Read ID1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDID1
0
↑
1
-
1
1
0
1
1
0
1
0
(Dah)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
st
Description
-This read byte identifies the LCD module’s manufacturer.
Restriction
-
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Status
Default Value
Power On Sequence
85h
S/W Reset
85h
H/W Reset
85h
Flow Chart
Version 1.5
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9.1.46 RDID2 (DBh): Read ID2
DBH
RDID2 (Read ID2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDID2
0
↑
1
-
1
1
0
1
1
0
1
1
(DBh)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
This read byte is used to track the LCD module/driver IC version.
Description
‘-’: Don’t care.
Restriction
-
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Status
Default Value
Power On Sequence
85h
S/W Reset
85h
H/W Reset
85h
Flow Chart
Version 1.5
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9.1.47 RDID3 (DCh): Read ID3
DCH
RDID3 (Read ID3)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDID3
0
↑
1
-
1
1
0
1
1
1
0
0
(DCh)
1 parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
st
Description
This read byte identifies the LCD module/driver.
Restriction
-
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Register
availability
Default
Status
Default Value
Power On Sequence
52h
S/W Reset
52h
H/W Reset
52h
Flow Chart
Version 1.5
Page 243 of 300
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ST7789S
9.2 System Function Command Table 2
Instruction
D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
(B0h)
Function
0
↑
1
-
1
0
1
1
0
0
0
0
1
↑
1
-
0
0
0
RM
0
0
DM1
DM0
1
↑
1
-
1
1
EPF1
EPF0
ENDIAN
RIM
MDT1
MDT0
0
↑
1
-
1
0
1
1
0
0
0
1
1
↑
1
-
WO
RCM1
RCM0
0
VSPL
HSPL
DPL
EPL
RGB
1
↑
1
-
0
VBP6
VBP5
VBP4
VBP3
VBP2
VBP1
VBP0
Control
1
↑
1
-
0
0
0
HBP4
HBP3
HBP2
HBP1
HBP0
0
↑
1
-
1
0
1
1
0
0
1
0
1
↑
1
-
0
BPA6
BPA5
BPA4
BPA3
BPA2
BPA1
BPA0
1
↑
1
-
0
FPA6
FPA5
FPA4
FPA3
FPA2
FPA1
FPA0
Porch
1
↑
1
-
0
0
0
0
0
0
0
PSEN
control
1
↑
1
BPB3
BPB2
BPB1
BPB0
FPB3
FPB2
FPB1
FPB0
1
↑
1
BPC3
BPC2
BPC1
BPC0
FPC3
FPC2
FPC1
FPC0
0
↑
1
-
1
0
1
1
0
0
1
1
1
↑
1
-
0
0
0
FRSEN
0
0
DIV1
DIV0
1
↑
1
-
NLB2
NLB1
NLB0
RTNB4
RTNB3
RTNB2
RTNB1
RTNB0
1
↑
1
-
NLC2
NLC1
NLC0
RTNC4
RTNC3
RTNC2
RTNC1
RTNC0
0
↑
1
-
1
0
1
1
0
1
1
1
1
↑
1
-
0
VGHS2
VGHS1
VGHS0
0
VGLS2
VGLS1
VGLS0
0
↑
1
-
1
0
1
1
1
0
1
0
1
↑
1
-
0
0
0
0
0
DGMEN
0
0
RAM
RAMCTRL
Control
(B1h)
RGBCTRL
(B2h)
PORCTRL
(B3h)
Frame
FRCTRL1
Rate
Control 1
(B7h)
Gate
GCTRL
control
(Bah)
DGMEN
Digital
Gamma
Enable
0
↑
1
-
1
0
1
1
1
0
1
1
1
↑
1
-
0
0
VCOMS5
VCOMS4
VCOMS3
VCOMS2
VCOMS1
VCOMS0
0
↑
1
-
1
1
0
0
0
0
0
0
1
↑
1
-
MX
MY
BGR
REV
SS
MH
MV
GS
0
↑
1
-
1
1
0
0
0
0
0
1
1
↑
1
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
1
↑
1
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
1
↑
1
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
0
↑
1
-
1
1
0
0
0
0
1
0
1
↑
1
-
0
0
0
0
0
0
0
CMDEN
1
↑
1
-
1
1
1
1
1
1
1
1
(BBh)
VCOM
VCOMS
Setting
LCM
(C0h)
LCMCTRL
IDSET
Control
(C1h)
ID Setting
(C2h) VDV and
VRH
VDVVRHEN
Command
Enable
Version 1.5
Page 244 of 300
2013/04
ST7789S
Instruction
D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
(C3h)
0
↑
1
1
1
0
0
0
0
1
1
1
↑
1
0
0
VRHS5
VRHS4
VRHS3
VRHS2
VRHS1
VRHS0
0
↑
1
-
1
1
0
0
0
1
0
0
1
↑
1
-
0
0
VDVS5
VDVS4
VDVS3
VDVS2
VDVS1
VDVS0
0
↑
1
-
1
1
0
0
0
1
0
1
1
↑
1
-
0
0
VCMOFS5
VCMOFS4
VCMOFS3
VCMOFS2
VCMOFS1
VCMOFS0
0
↑
1
1
1
0
0
0
1
1
0
1
↑
1
NLA2
NLA1
NLA0
RTNA4
RTNA3
RTNA2
RTNA1
RTNA0
0
↑
1
-
1
1
0
0
0
1
1
1
1
↑
1
-
0
0
0
0
PWMFIX
PWMPOL
0
↑
1
-
1
1
0
0
1
0
0
0
1
↑
1
-
0
0
0
0
1
0
0
0
VRHS
Function
VRH Set
VDV
(C4h)
VDVSET
Setting
(C5h)
VCOM
VCMOFSET
Offset Set
FR
(C6h)
FRCTR2
Control 2
(C7h)
CABC
CABCCTRL
LEDONREV DPOFPWM
Control
(C8h)
Register
REGSEL1
value
selection1
0
↑
1
-
1
1
0
0
1
0
1
0
1
↑
1
-
0
0
0
0
1
1
1
1
(Cah)
Register
REGSEL2
value
selection2
0
↑
1
-
1
1
0
1
0
0
0
0
1
↑
1
-
1
0
1
0
0
1
0
0
1
↑
1
-
AVDD1
AVDD0
AVCL1
AVCL0
0
0
VDS1
VDS0
0
↑
1
-
1
1
0
1
0
0
1
0
(D0h)
Power
PWCTRL1
Control 1
Enable
(D2h)
VAP/VAN
VAPVANEN
1
↑
1
-
0
1
0
0
1
1
0
signal
0
output
PVGAMCTRL
0
↑
1
-
1
1
1
0
0
0
0
0
1
↑
1
-
V63P3
V63P2
V63P1
V63P0
V0P3
V0P2
V0P1
V0P0
1
↑
1
-
0
0
V1P5
V1P4
V1P3
V1P2
V1P1
V1P0
1
↑
1
-
0
0
V2P5
V2P4
V2P3
V2P2
V2P1
V2P0
1
↑
1
-
0
0
0
V4P4
V4P3
V4P2
V4P1
V4P0
1
↑
1
-
0
0
0
V6P4
V6P3
V6P2
V6P1
V6P0
1
↑
1
-
0
0
J0P1
J0P0
V13P3
V13P2
V13P1
V13P0
1
↑
1
-
0
V20P6
V20P5
V20P4
V20P3
V20P2
V20P1
V20P0
1
↑
1
-
0
V36P2
V36P1
V36P0
0
V27P2
V27P1
V27P0
1
↑
1
-
0
V43P6
V43P5
V43P4
V43P3
V43P2
V43P1
V43P0
Positive
(E0h)
Voltage
Gamma
Control
Version 1.5
Page 245 of 300
2013/04
ST7789S
Instruction
D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
1
↑
1
-
0
0
J1P1
J1P0
V50P3
V50P2
V50P1
V50P0
1
↑
1
-
0
0
0
V57P4
V57P3
V57P2
V57P1
V57P0
1
↑
1
-
0
0
0
V59P4
V59P3
V59P2
V59P1
V59P0
1
↑
1
-
0
0
V61P5
V61P4
V61P3
V61P2
V61P1
V61P0
1
↑
1
-
0
0
V62P5
V62P4
V62P3
V62P2
V62P1
V62P0
0
↑
1
-
1
1
1
0
0
0
0
1
1
↑
1
-
V63N3
V63N2
V63N1
V63N0
V0N3
V0N2
V0N1
V0N0
1
↑
1
-
0
0
V1N5
V1N4
V1N3
V1N2
V1N1
V1N0
1
↑
1
-
0
0
V2N5
V2N4
V2N3
V2N2
V2N1
V2N0
1
↑
1
-
0
0
0
V4N4
V4N3
V4N2
V4N1
V4N0
1
↑
1
-
0
0
0
V6N4
V6N3
V6N2
V6N1
V6N0
1
↑
1
-
0
0
J0N1
J0N0
V13N3
V13N2
V13N1
V13N0
1
↑
1
0
V20N6
V20N5
V20N4
V20N3
V20N2
V20N1
V20N0
Hex
Function
(E1h)
Negative
Voltage
NVGAMCTRL
Gamma
1
↑
1
0
V36N2
V36N1
V36N0
0
V27N2
V27N1
V27N0
1
↑
1
0
V43N6
V43N5
V43N4
V43N3
V43N2
V43N1
V43N0
1
↑
1
0
0
J1N1
J1N0
V50N3
V50N2
V50N1
V50N0
1
↑
1
0
0
0
V57N4
V57N3
V57N2
V57N1
V57N0
1
↑
1
0
0
0
V59N4
V59N3
V59N2
V59N1
V59N0
1
↑
1
0
0
V61N5
V61N4
V61N3
V61N2
V61N1
V61N0
1
↑
1
0
0
V62N5
V62N4
V62N3
V62N2
V62N1
V62N0
0
↑
1
-
1
1
1
0
0
0
1
0
1
↑
1
-
DGM_LUT_R00[7:0]
1
↑
1
-
DGM_LUT_R01[7:0]
Control
(E2h)
Digital
↑
1
-
…
1
↑
1
-
DGM_LUT_R30[7:0]
1
↑
1
-
DGM_LUT_R31[7:0]
1
↑
1
-
…
DGMLUTR
1
1
↑
1
-
DGM_LUT_R62[7:0]
1
↑
1
-
DGM_LUT_R63[7:0]
0
↑
1
-
Gamma
Look-up
Table for
Red
DGMLUTB
Version 1.5
1
1
1
0
Page 246 of 300
0
0
1
1
(E3h)
2013/04
Digital
ST7789S
Instruction
D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Function
↑
1
-
DGM_LUT_B00[7:0]
1
↑
1
-
DGM_LUT_B01[7:0]
1
↑
1
-
1
↑
1
-
DGM_LUT_B30[7:0]
1
↑
1
-
DGM_LUT_B31[7:0]
1
↑
1
-
…
Gamma
1
1
↑
1
-
DGM_LUT_B62[7:0]
1
↑
1
-
DGM_LUT_B63[7:0]
0
↑
1
-
1
1
1
0
0
1
0
0
1
↑
1
-
0
0
NL5
NL4
NL3
NL2
NL1
NL0
Gate
1
↑
1
-
0
0
SCN5
SCN4
SCN3
SCN2
SCN1
SCN0
control
1
↑
1
-
0
0
1
0
0
SM
0
GS
0
↑
1
-
1
1
1
0
1
0
0
0
1
↑
1
-
1
0
SBCLK1
SBCLK0
0
0
0
↑
1
-
1
1
1
0
1
0
0
1
1
↑
1
-
0
0
0
SEQ4
SEQ3
SEQ2
SEQ1
SEQ0
1
↑
1
-
0
0
0
SPRET4
SPRET3
SPRET2
SPRET1
SPRET0
Look-up
Table for
…
Blue
(E4h)
GATECTRL
(E8h)
Power
PWCTRL2
Control 2
STP14CK1 STP14CK0
(E9h)
Equalize
Time
EQCTRL
Control
1
↑
1
-
0
0
0
0
GEQ3
GEQ2
GEQ1
GEQ0
0
↑
1
-
1
1
1
0
1
1
0
0
1
↑
1
-
0
0
0
0
0
0
0
1
0
↑
1
-
1
1
1
1
1
0
1
0
1
↑
1
-
0
1
0
1
1
0
1
0
Program
1
↑
1
-
0
1
1
0
1
0
0
1
Mode
1
↑
1
-
1
1
1
0
1
1
1
0
1
↑
1
-
0
0
0
0
0
PROMEN
0
0
0
↑
1
-
1
1
1
1
1
1
0
0
1
↑
1
-
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
1
↑
1
-
D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
-
1
1
1
1
1
1
1
0
1
↑
1
-
0
0
0
1
1
0
0
1
(Ech)
Program
PROMCTRL
PROMEN
Control
(Fah)
Enable
(FCh)
NVM
NVMSET
Setting
PROMACT
Version 1.5
Page 247 of 300
(Feh)
Program
Action
2013/04
ST7789S
Instruction
D/CX WRX RDX D17-8
1
↑
Version 1.5
1
-
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
1
0
1
Page 248 of 300
Hex
Function
2013/04
ST7789S
9.2.1
RAMCTRL (B0h): RAM Control
B0H
RAMCTR (RAM Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RAMCTRL
0
↑
1
-
1
0
1
1
0
0
0
0
(B0h)
st
1 Parameter
1
↑
1
-
0
0
0
RM
0
0
DM1
DM0
2nd Parameter
1
↑
1
-
1
1
EPF1
EPF0
ENDIAN
RIM
MDT1
MDT0
RM : ram access selection.
RM=”0” : Ram access from MCU interface
RM=”1” : Ram access from RGB interface
DM[1:0] : Display operation selection.
DM[1:0]
Mode
00h
MCU interface
01h
RGB interface
10h
VSYNC interface
11h
Reserved
ENDIAN :
ENDIAN
Mode
0
Normal (MSB first)
1
Little Endian (LSB first)
Description
Note: Little Endian only can be supported in 65K 8-bit and 9-bit interface.
MDT[1:0] : Method of pixel data transfer.
Please refer to section 8.8 Data Color Coding
Version 1.5
Page 249 of 300
2013/04
ST7789S
RIM: Specify RGB interface bus width.
RIM=”0”: 18 bit bus width.
RIM=”1”: 6 bit bus width
EPF[1:0] : Data translate of 65k and 4k to frame data.
65K data formate:
Data Bus
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R4
R3
R2
R1
0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
Read Data
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data Bus
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R4
R3
R2
R1
1
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
Read Data
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data Bus
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
Read Data
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data Bus
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
EPF=00
Frame
Data
R5
0
EPF=01
R5
1
EPF=10
R5
B0
EPF=11
R5
Read Data
Register
Availability
Version 1.5
Status
Page 250 of 300
Availability
2013/04
B0
ST7789S
Default
Version 1.5
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h/F0h
S/W Reset
00h/F0h
H/W Reset
00h/F0h
Page 251 of 300
2013/04
ST7789S
9.2.2
RGBCTRL (B1h): RGB Interface Control
B1H
RGBCTRL (RGB Interface Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RGBCTRL
0
↑
1
-
1
0
1
1
0
0
0
1
(B1h)
st
1 parameter
1
↑
1
-
WO
RCM1
RCM0
0
VSPL
HSPL
DPL
EPL
2nd parameter
1
↑
1
-
0
VBP6
VBP5
VBP4
VBP3
VBP2
VBP1
VBP0
3rd parameter
1
↑
1
-
0
0
0
HBP4
HBP3
HBP2
HBP1
HBP0
WO: Direct RGB mode.
WO
Mode
0
Memory
1
Shift register
RCM[1:0]: RGB I/F enable mode selection.
RCM[1:0]
Mode
00
MCU interface
01
10
RGB DE mode
11
RGB HV mode
VSPL : Sets the signal polarity of the VSYNC pin.
Description
VSPL=”0”, Low active
VSPL=”1”, High active
HSPL : Sets the signal polarity of the HSYNC pin.
HSPL=”0”, Low active
HSPL=”1”, High active
DPL : Sets the signal polarity of the DOTCLK pin.
DPL = “0” The data is input on the positive edge of DOTCLK
DPL = “1” The data is input on the negative edge of DOTCLK
EPL : Sets the signal polarity of the ENABLE pin.
EPL = “0” The data DB17-0 is written when ENABLE = “1”. Disable data write operation when ENABLE =
“0”.
EPL = “1” The data DB17-0 is written when ENABLE = “0”. Disable data write operation when ENABLE =
“1”.
VBP[6:0]: RGB interface Vsync back porch setting. Minimum setting is 0x02.
HBP[4:0]: RGB interface Hsync back porch setting. Please refer to the section 8.9.3 for minimum setting.
Register
Availability
Version 1.5
Status
Availability
Page 252 of 300
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ST7789S
Default
Version 1.5
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
40h/02h/14h
S/W Reset
40h/02h/14h
H/W Reset
40h/02h/14h
Page 253 of 300
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ST7789S
9.2.3
PORCTRL (B2h): Porch Setting
B2H
PORCTRL (Porch Setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PORCTRL
0
↑
1
-
1
0
1
1
0
0
1
0
(B2h)
st
1 parameter
1
↑
1
-
0
BPA6
BPA5
BPA4
BPA3
BPA2
BPA1
BPA0
2nd parameter
1
↑
1
-
0
FPA6
FPA5
FPA4
FPA3
FPA2
FPA1
FPA0
3rd parameter
1
↑
1
-
0
0
0
0
0
0
0
PSEN
4 parameter
1
↑
1
-
BPB3
BPB2
BPB1
BPB0
FPB3
FPB2
FPB1
FPB0
5th parameter
1
↑
1
-
BPC3
BPC2
BPC1
BPC0
FPC3
FPC2
FPC1
FPC0
th
BPA[6:0]: Back porch setting in normal mode. The minimum setting is 0x01.
FPA[6:0]: Front porch setting in normal mode. The minimum setting is 0x01.
PSEN: Enable separate porch control.
PSEN
Mode
0
Disable separate porch control
1
Enable separate porch control
Description
BPB[3:0]: Back porch setting in idle mode. The minimum setting is 0x01.
FPB[3:0]: Front porch setting in idle mode. The minimum setting is 0x01.
BPC[3:0]: Back porch setting in partial mode. The minimum setting is 0x01.
FPC[3:0]: Front porch setting in partial mode. The minimum setting is 0x01.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
08h/08h/00h/22h/22h
S/W Reset
08h/08h/00h/22h/22h
H/W Reset
08h/08h/00h/22h/22h
Page 254 of 300
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ST7789S
9.2.4
FRCTRL1 (B3h): Frame Rate Control 1 (In partial mode/ idle colors)
B3H
FRCTRL1 (Frame rate control 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
FRCTRL1
0
↑
1
-
1
0
1
1
0
0
1
1
(B3h)
st
1 parameter
1
↑
1
-
0
0
0
FRSEN
0
0
DIV1
DIV0
2nd parameter
1
↑
1
-
NLB2
NLB1
NLB0
RTNB4
RTNB3
RTNB2
RTNB1
RTNB0
3rd parameter
1
↑
1
-
NLC2
NLC1
NLC0
RTNC4
RTNC3
RTNC2
RTNC1
RTNC0
FRSEN: Enable separate frame rate control.
When FRSEN=0, Frame rate of idle and partial mode are determined by C6h
When FRSEN=1, Frame rate of idle and partial mode are determined by B3h
FRSEN
Mode
0
Disable separate FR control
1
Enable separate FR control
DIV[1:0]: Frame rate divided control
DIV[1:0]
Mode
00
Divide by 1
01
Divide by 2
10
Divide by 4
11
Divide by 8
NLB[2:0]: Inversion selection in idle mode.
Description
0x00: dot inversion.
0x07: column inversion.
RTNB[4:0]: Frame rate control in idle mode.
RTNB[4:0]
Version 1.5
FR in idle mode (Hz)
RTNB[4:0]
FR in idle mode (Hz)
00h
119
10h
58
01h
111
11h
57
02h
105
12h
55
03h
99
13h
53
04h
94
14h
52
05h
90
15h
50
06h
86
16h
49
07h
82
17h
48
08h
78
18h
46
09h
75
19h
45
0Ah
72
1Ah
44
Page 255 of 300
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ST7789S
0Bh
69
1Bh
43
0Ch
67
1Ch
42
0Dh
64
1Dh
41
0Eh
62
1Eh
40
0Fh
60
1Fh
39
NLC[2:0]: Inversion setting in partial mode.
0x00: dot inversion.
0x07: column inversion.
RTNC[4:0]: Frame rate control in partial mode. This setting is equal to RTNB.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h/0Fh/0Fh
S/W Reset
00h/0Fh/0Fh
H/W Reset
00h/0Fh/0Fh
Page 256 of 300
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ST7789S
9.2.5
GCTRL (B7h): Gate Control
B7H
GCTRL (Gate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
GCTRL
0
↑
1
-
1
0
1
1
0
1
1
1
(B7h)
Parameter
1
↑
1
-
0
VGHS2
VGHS1
VGHS0
0
VGLS2
VGLS1
VGLS0
VGHS[2:0]: VGH Setting.
VGHS[2:0]
VGH (V)
00h
12.2
01h
12.54
02h
12.89
03h
13.26
04h
13.65
05h
14.06
06h
14.5
07h
14.97
Description
VGLS[2:0]: VGL Setting.
Register
Availability
Version 1.5
VGLS[2:0]
VGL (V)
00h
-7.16
01h
-7.67
02h
-8.23
03h
-8.87
04h
-9.6
05h
-10.43
06h
-11.38
07h
-12.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Page 257 of 300
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ST7789S
Default
Version 1.5
Status
Default Value
Power On Sequence
35h
S/W Reset
35h
H/W Reset
35h
Page 258 of 300
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9.2.6
DGMEN (Bah): Digital Gamma Enable
BAH
DGMEN (Digital Gamma Enable)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
DGMEN
0
↑
1
-
1
0
1
1
1
0
1
0
(Bah)
Parameter
1
↑
1
-
0
0
0
0
0
DGMEN
0
0
DGMEN:
Description
“0”: disable digital gamma.
“1”: enable digital gamma.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
Page 259 of 300
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ST7789S
9.2.7
VCOMS (BBh): VCOM Setting
BBH
VCOMS (VCOM Setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
VCOMS
0
↑
1
-
1
0
1
1
1
0
1
1
(BBh)
Parameter
1
↑
1
-
0
0
VCOM5
VCOM4
VCOM1
VCOM0
VCOM3 VCOM2
VCOMS[5:0]:
VCOMS[5:0]
VCOM (V)
VCOMS[5:0]
VCOM (V)
00h
0.1
20h
0.9
01h
0.125
21h
0.925
02h
0.15
22h
0.95
03h
0.175
23h
0.975
04h
0.2
24h
1.0
05h
0.225
25h
1.025
06h
0.25
26h
1.05
07h
0.275
27h
1.075
08h
0.3
28h
1.1
09h
0.325
29h
1.125
0Ah
0.35
2Ah
1.15
0Bh
0.375
2Bh
1.175
0Ch
0.4
2Ch
1.2
0Dh
0.425
2Dh
1.225
0Eh
0.45
2Eh
1.25
0Fh
0.475
2Fh
1.275
10h
0.5
30h
1.3
11h
0.525
31h
1.325
12h
0.55
32h
1.35
13h
0.575
33h
1.375
14h
0.6
34h
1.4
15h
0.625
35h
1.425
16h
0.65
36h
1.45
17h
0.675
37h
1.475
18h
0.7
38h
1.5
19h
0.725
39h
1.525
1Ah
0.75
3Ah
1.55
1Bh
0.775
3Bh
1.575
1Ch
0.8
3Ch
1.6
1Dh
0.825
3Dh
1.625
Description
Version 1.5
Page 260 of 300
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ST7789S
Register
Availability
Default
Version 1.5
1Eh
0.85
3Eh
1.65
1Fh
0.875
3Fh
1.675
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
20h
S/W Reset
20h
H/W Reset
20h
Page 261 of 300
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ST7789S
9.2.8
LCMCTRL (C0h): LCM Control
C0H
LCMCTRL (LCM Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
LCMCTRL
0
↑
1
-
1
1
0
0
0
0
0
0
(C0h)
st
1
↑
1
-
0
XMY
XBGR
XINV
XMX
XMH
XMV
GS
1 parameter
XMY: XOR MY setting in command 36h.
XBGR: XOR RGB setting in command 36h.
XREV: XOR inverse setting in command 21h
Description
XMH: XOR MH setting in command 36h, only support RGB interface.
XMV: XOR MV setting in command 36h
XMX: XOR MX setting in command 36h.
GS: Gate scan inversion enable: 1: enable, 0: disable.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
2Ch
S/W Reset
2Ch
H/W Reset
2Ch
Page 262 of 300
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ST7789S
9.2.9
IDSET (C1h): ID Code Setting
C1H
IDSET (ID Code Setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
(C1h)
0
↑
1
-
1
1
0
0
0
0
0
1
st
Parameter 1
1
↑
1
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
Parameter 2nd
1
↑
1
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
Parameter 3rd
1
↑
1
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
IDSET
ID1[7:0]: ID1 Setting.
Description
ID2[7:0]: ID2 Setting.
ID3[7:0]: ID3 Setting.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
85h/85h/52h
S/W Reset
85h/85h/52h
H/W Reset
85h/85h/52h
Page 263 of 300
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ST7789S
9.2.10 VDVVRHEN (C2h): VDV and VRH Command Enable
C2H
VDVVRHEN (VDV and VRH Command Enable)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
VDVVRHEN
0
↑
1
-
1
1
0
0
0
0
1
0
(C2h)
1 Parameter
1
↑
1
-
0
0
0
0
0
0
0
CMDEN
2nd Parameter
1
↑
1
-
1
1
1
1
1
1
1
1
st
CMDEN: VDV and VRH command write enable.
Description
CMDEN=”0”: VDV and VRH register value comes from NVM.
CMDEN=”1”, VDV and VRH register value comes from command write.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
01h/FFh
S/W Reset
01h/FFh
H/W Reset
01h/FFh
Page 264 of 300
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ST7789S
9.2.11 VRHS (C3h): VRH Set
C3H
VRHS (VRH Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
VRHS
0
↑
1
-
1
1
0
0
0
0
1
1
(C3h)
1 Parameter
1
↑
1
-
0
0
VRHS5
VRHS4
VRHS3
VRHS2
VRHS1
VRHS0
st
VRHS[5:0]: VRH Set.
VRHS[5:0]
VAP(GVDD) (V)
VRHS[5:0]
VAP(GVDD) (V)
00h
3.55+(vcom+vcom offset+0.5vdv)
15h
4.6+( vcom+vcom offset+0.5vdv)
01h
3.6+( vcom+vcom offset+0.5vdv)
16h
4.65+( vcom+vcom offset+0.5vdv)
02h
3.65+( vcom+vcom offset+0.5vdv)
17h
4.7+( vcom+vcom offset+0.5vdv)
03h
3.7+( vcom+vcom offset+0.5vdv)
18h
4.75+( vcom+vcom offset+0.5vdv)
04h
3.75+( vcom+vcom offset+0.5vdv)
19h
4.8+( vcom+vcom offset+0.5vdv)
05h
3.8+( vcom+vcom offset+0.5vdv)
1Ah
4.85+( vcom+vcom offset+0.5vdv)
06h
3.85+( vcom+vcom offset+0.5vdv)
1Bh
4.9+( vcom+vcom offset+0.5vdv)
07h
3.9+( vcom+vcom offset+0.5vdv)
1Ch
4.95+( vcom+vcom offset+0.5vdv)
08h
3.95+( vcom+vcom offset+0.5vdv)
1Dh
5+( vcom+vcom offset+0.5vdv)
09h
4+( vcom+vcom offset+0.5vdv)
1Eh
5.05+( vcom+vcom offset+0.5vdv)
0Ah
4.05+( vcom+vcom offset+0.5vdv)
1Fh
5.1+( vcom+vcom offset+0.5vdv)
0Bh
4.1+( vcom+vcom offset+0.5vdv)
20h
5.15+( vcom+vcom offset+0.5vdv)
0Ch
4.15+( vcom+vcom offset+0.5vdv)
21h
5.2+( vcom+vcom offset+0.5vdv)
0Dh
4.2+( vcom+vcom offset+0.5vdv)
22h
5.25+( vcom+vcom offset+0.5vdv)
0Eh
4.25+( vcom+vcom offset+0.5vdv)
23h
5.3+( vcom+vcom offset+0.5vdv)
0Fh
4.3+( vcom+vcom offset+0.5vdv)
24h
5.35+( vcom+vcom offset+0.5vdv)
10h
4.35+( vcom+vcom offset+0.5vdv)
25h
5.4+( vcom+vcom offset+0.5vdv)
11h
4.4+( vcom+vcom offset+0.5vdv)
26h
5.45+( vcom+vcom offset+0.5vdv)
12h
4.45+( vcom+vcom offset+0.5vdv)
27h
5.5+( vcom+vcom offset+0.5vdv)
13h
4.5+( vcom+vcom offset+0.5vdv)
28h~3Fh
Reserved
14h
4.55+( vcom+vcom offset+0.5vdv)
--
--
VRHS[5:0]
VAN(GVCL) (V)
VRHS[5:0]
VAN(GVCL) (V)
00h
-3.55+(vcom+vcom offset-0.5vdv)
15h
-4.6+( vcom+vcom offset-0.5vdv)
01h
-3.6+( vcom+vcom offset-0.5vdv)
16h
-4.65+( vcom+vcom offset-0.5vdv)
02h
-3.65+( vcom+vcom offset-0.5vdv)
17h
-4.7+( vcom+vcom offset-0.5vdv)
03h
-3.7+( vcom+vcom offset-0.5vdv)
18h
-4.75+( vcom+vcom offset-0.5vdv)
04h
-3.75+( vcom+vcom offset-0.5vdv)
19h
-4.8+( vcom+vcom offset-0.5vdv)
05h
-3.8+( vcom+vcom offset-0.5vdv)
1Ah
-4.85+( vcom+vcom offset-0.5vdv)
06h
-3.85+( vcom+vcom offset-0.5vdv)
1Bh
-4.9+( vcom+vcom offset-0.5vdv)
Description
Version 1.5
Page 265 of 300
2013/04
ST7789S
07h
-3.9+( vcom+vcom offset-0.5vdv)
1Ch
-4.95+( vcom+vcom offset-0.5vdv)
08h
-3.95+( vcom+vcom offset-0.5vdv)
1Dh
-5+( vcom+vcom offset-0.5vdv)
09h
-4+( vcom+vcom offset-0.5vdv)
1Eh
-5.05+( vcom+vcom offset-0.5vdv)
0Ah
-4.05+( vcom+vcom offset-0.5vdv)
1Fh
-5.1+( vcom+vcom offset-0.5vdv)
0Bh
-4.1+( vcom+vcom offset-0.5vdv)
20h
-5.15+( vcom+vcom offset-0.5vdv)
0Ch
-4.15+( vcom+vcom offset-0.5vdv)
21h
-5.2+( vcom+vcom offset-0.5vdv)
0Dh
-4.2+( vcom+vcom offset-0.5vdv)
22h
-5.25+( vcom+vcom offset-0.5vdv)
0Eh
-4.25+( vcom+vcom offset-0.5vdv)
23h
-5.3+( vcom+vcom offset-0.5vdv)
0Fh
-4.3+( vcom+vcom offset-0.5vdv)
24h
-5.35+( vcom+vcom offset-0.5vdv)
10h
-4.35+( vcom+vcom offset-0.5vdv)
25h
-5.4+( vcom+vcom offset-0.5vdv)
11h
-4.4+( vcom+vcom offset-0.5vdv)
26h
-5.45+( vcom+vcom offset-0.5vdv)
12h
-4.45+( vcom+vcom offset-0.5vdv)
27h
-5.5+( vcom+vcom offset-0.5vdv)
13h
-4.5+( vcom+vcom offset-0.5vdv)
28h~3Fh
Reserved
14h
-4.55+( vcom+vcom offset-0.5vdv)
--
--
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
0Bh
S/W Reset
0Bh
H/W Reset
0Bh
Page 266 of 300
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ST7789S
9.2.12 VDVS (C4h): VDV Set
C4H
VDVS (VDV Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
VDVS
0
↑
1
-
1
1
0
0
0
1
0
0
(C4h)
1 Parameter
1
↑
1
-
0
0
VDVS5
VDVS4
VDVS3
VDVS2
VDVS1
VDVS0
st
VDVS[5:0]: VDV Set.
VDVS[5:0]
VDV (V)
VDVS[5:0]
VDV (V)
00h
-0.8
20h
0
01h
-0.775
21h
0.025
02h
-0.75
22h
0.05
03h
-0.725
23h
0.075
04h
-0.7
24h
0.1
05h
-0.675
25h
0.125
06h
-0.65
26h
0.15
07h
-0.625
27h
0.175
08h
-0.6
28h
0.2
09h
-0.575
29h
0.225
0Ah
-0.55
2Ah
0.25
0Bh
-0.525
2Bh
0.275
0Ch
-0.5
2Ch
0.3
0Dh
-0.475
2Dh
0.325
0Eh
-0.45
2Eh
0.35
0Fh
-0.425
2Fh
0.375
10h
-0.4
30h
0.4
11h
-0.375
31h
0.425
12h
-0.35
32h
0.45
13h
-0.325
33h
0.475
14h
-0.3
34h
0.5
15h
-0.275
35h
0.525
16h
-0.25
36h
0.55
17h
-0.225
37h
0.575
18h
-0.2
38h
0.6
19h
-0.175
39h
0.625
1Ah
-0.15
3Ah
0.65
1Bh
-0.125
3Bh
0.675
1Ch
-0.1
3Ch
0.7
1Dh
-0.075
3Dh
0.725
Description
Version 1.5
Page 267 of 300
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ST7789S
Register
Availability
Default
Version 1.5
1Eh
-0.05
3Eh
0.75
1Fh
-0.025
3Fh
0.775
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
20h
S/W Reset
20h
H/W Reset
20h
Page 268 of 300
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9.2.13 VCMOFSET (C5h): VCOM Offset Set
C5H
Inst / Para
VCMOFSET
st
1 Parameter
VCMOFSET (VCOM Offset Set)
D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
0
0
1
0
1
(C5h)
0
↑
1
-
1
1
1
↑
1
-
0
0
VCMOFS5 VCMOFS4 VCMOFS3 VCMOFS2 VCMOFS1 VCMOFS0
VCOM offset setting:
VCMOFS[5:0]
VCOM OFFSET (V)
VCMOFS[5:0]
VCOM OFFSET(V)
00h
-0.8
20h
0
01h
-0.775
21h
0.025
02h
-0.75
22h
0.05
03h
-0.725
23h
0.075
04h
-0.7
24h
0.1
05h
-0.675
25h
0.125
06h
-0.65
26h
0.15
07h
-0.625
27h
0.175
08h
-0.6
28h
0.2
09h
-0.575
29h
0.225
0Ah
-0.55
2Ah
0.25
0Bh
-0.525
2Bh
0.275
0Ch
-0.5
2Ch
0.3
0Dh
-0.475
2Dh
0.325
0Eh
-0.45
2Eh
0.35
0Fh
-0.425
2Fh
0.375
10h
-0.4
30h
0.4
11h
-0.375
31h
0.425
12h
-0.35
32h
0.45
13h
-0.325
33h
0.475
14h
-0.3
34h
0.5
15h
-0.275
35h
0.525
16h
-0.25
36h
0.55
17h
-0.225
37h
0.575
18h
-0.2
38h
0.6
19h
-0.175
39h
0.625
1Ah
-0.15
3Ah
0.65
1Bh
-0.125
3Bh
0.675
1Ch
-0.1
3Ch
0.7
1Dh
-0.075
3Dh
0.725
Description
Version 1.5
Page 269 of 300
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ST7789S
Register
Availability
Default
Version 1.5
1Eh
-0.05
3Eh
0.75
1Fh
-0.025
3Fh
0.775
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
20h
S/W Reset
20h
H/W Reset
20h
Page 270 of 300
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ST7789S
9.2.14 FRCTRL2 (C6h): Frame Rate Control in Normal Mode
C6H
FRCTRL2 (Frame Rate Control in Normal Mode)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
FRCTRL2
0
↑
1
-
1
1
0
0
0
1
1
0
(C6h)
1
↑
1
-
NLA2
NLA1
NLA0
RTNA4
RTNA3
RTNA2
RTNA1
RTNA0
st
1 Parameter
NLA[2 :0] : Inversion selection in normal mode.
0x00 : dot inversion.
0x07: column inversion.
RTNA[4:0]:
Description
Register
Availability
Version 1.5
RTNA[4:0]
FR in normal mode (Hz)
RTNA[4:0]
FR in normal mode (Hz)
00h
119
10h
58
01h
111
11h
57
02h
105
12h
55
03h
99
13h
53
04h
94
14h
52
05h
90
15h
50
06h
86
16h
49
07h
82
17h
48
08h
78
18h
46
09h
75
19h
45
0Ah
72
1Ah
44
0Bh
69
1Bh
43
0Ch
67
1Ch
42
0Dh
64
1Dh
41
0Eh
62
1Eh
40
0Fh
60
1Fh
39
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Page 271 of 300
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ST7789S
Default
Version 1.5
Status
Default Value
Power On Sequence
0Fh
S/W Reset
0Fh
H/W Reset
0Fh
Page 272 of 300
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ST7789S
9.2.15 CABCCTRL (C7h): CABC Control
C7H
CABCCTRL (CABC Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CABCCTRL
0
↑
1
-
1
1
0
0
0
1
1
1
(C7h)
1
↑
1
-
0
0
0
0
st
1 Parameter
LEDONREV DPOFPWM PWMFIX PWMPOL
LEDONREV: Reverse the status of LED_ON:
“0”: keep the status of LED_ON.
“1”: reverse the status of LED_ON.
DPOFPWM: initial state control of LEDPWM.
“0”: The initial state of LEDPWM is low.
“1”: The initial state of LEDPWM is high.
Description
PWMFIX: LEDPWM fix control.
“0”: LEDPWM control by CABC.
“1”: fix LEDPWM in “ON” status.
PWMPOL: LEDPWM polarity control.
“0”: polarity high.
“1”: polarity low.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
Page 273 of 300
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ST7789S
9.2.16 REGSEL1 (C8h): Register Value Selection 1
C8H
REGSEL1 (Register Value Selection 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
REGSEL1
0
↑
1
-
1
1
0
0
1
0
0
0
(C8h)
Parameter
1
↑
1
-
0
0
0
0
1
0
0
0
Description
Reserved for testing
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
08h
S/W Reset
08h
H/W Reset
08h
Page 274 of 300
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ST7789S
9.2.17 REGSEL2 (Cah): Register Value Selection 2
CAH
REGSEL2 (Register Value Selection 2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
REGSEL2
0
↑
1
-
1
1
0
0
1
0
1
0
(Cah)
Parameter
1
↑
1
-
0
0
0
0
1
1
1
1
Description
Reserved for testing
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
0Fh
S/W Reset
0Fh
H/W Reset
0Fh
Page 275 of 300
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ST7789S
9.2.18 PWCTRL1 (D0h): Power Control 1
D0H
PWCTRL (Power Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PWCTRL
0
↑
1
-
1
1
0
1
0
0
0
0
(D0h)
1 Parameter
1
↑
1
-
1
0
1
0
0
1
0
0
2nd Parameter
1
↑
1
-
AVCL0
0
0
VDS1
VDS0
st
AVDD1 AVDD0 AVCL1
AVDD[1:0]:
AVDD[1:0]
AVDD (V)
00h
6.2
01h
6.4
02h
6.6
03h
6.8
AVCL[1:0]:
AVCL[1:0]
AVCL (V)
00h
-4.4
01h
-4.6
02h
-4.8
03h
-5.0
Description
VDS[1:0]:
VDS[1:0]
VDDS (V)
00h
2.19
01h
2.3
02h
2.4
03h
2.51
VDDS: Power of source OP
Register
Availability
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Page 276 of 300
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ST7789S
Default
Version 1.5
Status
Default Value
Power On Sequence
A4h/A1h
S/W Reset
A4h/A1h
H/W Reset
A4h/A1h
Page 277 of 300
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ST7789S
9.2.19 VAPVANEN (D2h): Enable VAP/VAN signal output
D2H
VAPVANEN (Enable VAP/VAN signal output)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
VAPVANEN
0
↑
1
-
1
1
0
1
0
0
1
0
(D2h)
Parameter
1
↑
1
-
0
1
0
0
1
1
0
0
Description
Enable VAP/VAN signal output
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
Page 278 of 300
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ST7789S
9.2.20 PVGAMCTRL (E0h): Positive Voltage Gamma Control
E0H
PVGAMCTRL (Positive Voltage Gamma Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PVGAMCTRL
0
↑
1
-
1
1
1
0
0
0
0
0
(E0h)
1 Parameter
1
↑
1
-
V63P3
V63P2
V63P1
V63P0
V0P3
V0P2
V0P1
V0P0
2nd Parameter
1
↑
1
-
0
0
V1P5
V1P4
V1P3
V1P2
V1P1
V1P0
3rd Parameter
1
↑
1
-
0
0
V2P5
V2P4
V2P3
V2P2
V2P1
V2P0
4 Parameter
1
↑
1
-
0
0
0
V4P4
V4P3
V4P2
V4P1
V4P0
5th Parameter
1
↑
1
-
0
0
0
V6P4
V6P3
V6P2
V6P1
V6P0
6th Parameter
1
↑
1
-
0
0
J0P1
J0P0
V13P3
V13P2
V13P1
V13P0
7th Parameter
1
↑
1
-
0
V20P6
V20P5
V20P4
V20P3
V20P2
V20P1
V20P0
8 Parameter
1
↑
1
-
0
V36P2
V36P1
V36P0
0
V27P2
V27P1
V27P0
9th Parameter
1
↑
1
-
0
V43P6
V43P5
V43P4
V43P3
V43P2
V43P1
V43P0
10th Parameter
1
↑
1
-
0
0
J1P1
J1P0
V50P3
V50P2
V50P1
V50P0
11 Parameter
1
↑
1
-
0
0
0
V57P4
V57P3
V57P2
V57P1
V57P0
12th Parameter
1
↑
1
-
0
0
0
V59P4
V59P3
V59P2
V59P1
V59P0
13th Parameter
1
↑
1
-
0
0
V61P5
V61P4
V61P3
V61P2
V61P1
V61P0
1
↑
1
-
0
0
V62P5
V62P4
V62P3
V62P2
V62P1
V62P0
st
th
th
th
th
14 Parameter
Please refer to 8.19.
Default value:
Value(hex)
VP0[3:0]
0
VP1[5:0]
2C
VP2[5:0]
2E
VP4[4:0]
15
VP6[4:0]
10
VP13[3:0]
9
VP20[6:0]
48
VP27[2:0]
3
VP36[2:0]
3
VP43[6:0]
53
VP50[3:0]
B
VP57[4:0]
19
VP59[4:0]
18
VP61[5:0]
20
Description
Version 1.5
Page 279 of 300
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VP63[3:0]
7
JP0[1:0]
0
JP1[1:0]
0
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
Refer to description
S/W Reset
Refer to description
H/W Reset
Refer to description
Page 280 of 300
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ST7789S
9.2.21 NVGAMCTRL (E1h): Negative Voltage Gamma Control
E1H
NVGAMCTRL (Negative Voltage Gamma Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NVGAMCTRL
0
↑
1
-
1
1
1
0
0
0
0
1
(E1h)
1 Parameter
1
↑
1
-
V63N3
V63N2
V63N1
V63N0
V0N3
V0N2
V0N1
V0N0
2nd Parameter
1
↑
1
-
0
0
V1N5
V1N4
V1N3
V1N2
V1N1
V1N0
3rd Parameter
1
↑
1
-
0
0
V2N5
V2N4
V2N3
V2N2
V2N1
V2N0
4 Parameter
1
↑
1
-
0
0
0
V4N4
V4N3
V4N2
V4N1
V4N0
5th Parameter
1
↑
1
-
0
0
0
V6N4
V6N3
V6N2
V6N1
V6N0
6th Parameter
1
↑
1
-
0
0
J0N1
J0N0
V13N3
V13N2
V13N1
V13N0
7th Parameter
1
↑
1
-
0
V20N6
V20N5
V20N4
V20N3
V20N2
V20N1
V20N0
8 Parameter
1
↑
1
-
0
V36N2
V36N1
V36N0
0
V27N2
V27N1
V27N0
9th Parameter
1
↑
1
-
0
V43N6
V43N5
V43N4
V43N3
V43N2
V43N1
V43N0
10th Parameter
1
↑
1
-
0
0
J1N1
J1N0
V50N3
V50N2
V50N1
V50N0
11 Parameter
1
↑
1
-
0
0
0
V57N4
V57N3
V57N2
V57N1
V57N0
12th Parameter
1
↑
1
-
0
0
0
V59N4
V59N3
V59N2
V59N1
V59N0
13th Parameter
1
↑
1
-
0
0
V61N5
V61N4
V61N3
V61N2
V61N1
V61N0
1
↑
1
-
0
0
V62N5
V62N4
V62N3
V62N2
V62N1
V62N0
st
th
th
th
th
14 Parameter
Please refer to 8.19.
Default value:
Value(hex)
VN0[3:0]
0
VN1[5:0]
2C
VN2[5:0]
2E
VN4[4:0]
15
VN6[4:0]
10
VN13[3:0]
9
VN20[6:0]
48
VN27[2:0]
3
VN36[2:0]
3
VN43[6:0]
53
VN50[3:0]
B
VN57[4:0]
19
VN59[4:0]
18
VN61[5:0]
20
Description
Version 1.5
Page 281 of 300
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ST7789S
VN63[3:0]
7
JN0[1:0]
0
JN1[1:0]
0
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
Refer to description
S/W Reset
Refer to description
H/W Reset
Refer to description
Page 282 of 300
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ST7789S
9.2.22 DGMLUTR (E2h): Digital Gamma Look-up Table for Red
E2H
DGMLUTR (Digital Gamma Look-up Table for Red)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
DGMLUTR
0
↑
1
-
1
1
1
0
0
0
1
0
(E2h)
st
1 Parameter
1
↑
1
-
DGM_LUT_R00[7:0]
2nd Parameter
1
↑
1
-
DGM_LUT_R01[7:0]
…
1
↑
1
-
…
31 Parameter
1
↑
1
-
DGM_LUT_R30[7:0]
32th Parameter
1
↑
1
-
DGM_LUT_R31[7:0]
…
1
↑
1
-
…
63th Parameter
1
↑
1
-
DGM_LUT_R62[7:0]
1
↑
1
-
DGM_LUT_R63[7:0]
th
th
64 Parameter
Please refer to 8.20.
Default value:
Value(hex)
00h
DGM_LUT_R01[7:0]
04h
…
…
Description
DGM_LUT_R00[7:0]
DGM_LUT_R30[7:0]
78h
DGM_LUT_R31[7:0]
7Ch
…
…
DGM_LUT_R62[7:0]
F8h
DGM_LUT_R63[7:0]
FCh
Register
Availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
Refer to description
S/W Reset
Refer to description
Default
Version 1.5
Page 283 of 300
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ST7789S
H/W Reset
Version 1.5
Refer to description
Page 284 of 300
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ST7789S
9.2.23 DGMLUTB (E3h): Digital Gamma Look-up Table for Blue
E3H
DGMLUTB (Digital Gamma Look-up Table for Blue)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
DGMLUTB
0
↑
1
-
1
1
1
0
0
0
1
1
(E3h)
st
1 Parameter
1
↑
1
-
DGM_LUT_B00[7:0]
2nd Parameter
1
↑
1
-
DGM_LUT_B01[7:0]
…
1
↑
1
-
…
31 Parameter
1
↑
1
-
DGM_LUT_B30[7:0]
32th Parameter
1
↑
1
-
DGM_LUT_B31[7:0]
…
1
↑
1
-
…
63th Parameter
1
↑
1
-
DGM_LUT_B62[7:0]
1
↑
1
-
DGM_LUT_B63[7:0]
th
th
64 Parameter
Please refer to 8.20.
Default value:
Value(hex)
00h
DGM_LUT_B01[7:0]
04h
…
…
Description
DGM_LUT_B00[7:0]
DGM_LUT_B30[7:0]
78h
DGM_LUT_B31[7:0]
7Ch
…
…
DGM_LUT_B62[7:0]
F8h
DGM_LUT_B63[7:0]
FCh
Register
Availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
Refer to description
S/W Reset
Refer to description
Default
Version 1.5
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ST7789S
H/W Reset
Version 1.5
Refer to description
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ST7789S
9.2.24 GATECTRL (E4h): Gate Control
E4H
GATECTRL (Gate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
GATECTRL
0
↑
1
-
1
1
1
0
0
1
0
0
(E4h)
1 Parameter
1
↑
1
-
0
0
NL5
NL4
NL3
NL2
NL1
NL0
2nd Parameter
1
↑
1
-
0
0
SCN5
SCN4
SCN3
SCN2
SCN1
SCN0
3rd Parameter
1
↑
1
-
0
0
0
1
0
SM
0
GS
st
NL[5:0]: Set the number of gate line.
0x00
8 gate line
0x01
16 gate line
0x02
24 gate line
…
The number of gate line
…
NL[5:0]
0x27
320 gate line
SCN[5:0]: set the first scan line
0x00
Gate 0
0x01
Gate 1
…
The first scan line
…
Description
SCN[5:0]
0x3F
Gate 319
SM: Gate interlace mode selection
SM=”0”: Gate scan using interlace mode.
SM=”1”: Gate scan using non-interlace mode.
GS: Gate scan direction
GS=”0”: Gate scan direction is 0319
GS=”1”: Gate scan direction is 3190
Register
Availability
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
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ST7789S
Default
Version 1.5
Status
Default Value
Power On Sequence
27h/00h/10h
S/W Reset
27h/00h/10h
H/W Reset
27h/00h/10h
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ST7789S
9.2.25 SPI2EN (E7h): SPI2 Enable
E7H
SPI2EN (SPI2 Enable)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SPI2EN
0
↑
1
-
1
1
1
0
0
1
1
1
(E7h)
Parameter
1
↑
1
-
0
0
0
SPI2EN
0
0
0
0
SPI2EN: 2 data lane enable control.
Description
“0”: disable 2 data lane mode.
“1”: enable 2 data lane mode
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
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ST7789S
9.2.26 PWCTRL2 (E8h): Power Control 2
E8H
PWCTRL2 (Power Control 2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PWCTRL2
0
↑
1
-
1
1
1
0
1
0
0
0
(E8h)
Parameter
1
↑
1
-
1
0
0
0
SBCLK1 SBCLK0
STP14CK1 STP14CK0
SBCLK[1:0]:Source booster clock selection
SBCLK[1:0]
00h
SBCLK DIV 2
01h
SBCLK DIV 3
02h
SBCLK DIV 4
03h
SBCLK DIV 6
Description
STP14CK[1:0]:STP14(AVDD/AVCL) booster clock selection
STP14CK[1:0]
00h
BCLK DIV 2
01h
BCLK DIV 3
02h
BCLK DIV 4
03h
BCLK DIV 6
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
93h
S/W Reset
93h
H/W Reset
93h
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9.2.27 EQCTRL (E9h): Equalize time control
E9H
EQCTRL (Equalize time Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
EQCTRL
0
↑
1
-
1
1
1
0
1
0
0
1
(E9h)
1 Parameter
1
↑
1
-
0
0
0
SEQ4
SEQ3
SEQ2
SEQ1
SEQ0
2nd Parameter
1
↑
1
-
0
0
0
3rd Parameter
1
↑
1
-
0
0
0
st
SPRET4 SPRET3 SPRET2 SPRET1 SPRET0
0
GEQ3
GEQ2
GEQ1
GEQ0
SEQ[4:0]:Source Equalize Time
Source equalize time: SEQ[4:0]*400ns, SEQ[4:0]=0x01~0x1f
SPRET[4:0]: Source Pre-drive Time
Description
Source pre-drive time: SPRET[4:0]*400ns, SPRET[4:0]=0x01~0x1f
GEQ[3:0]: Gate Equalize Time
Gate equalize time: GEQ[3:0]*400ns, GEQ[3:0]=0x00~0x0f
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
11h/11h/08h
S/W Reset
11h/11h/08h
H/W Reset
11h/11h/08h
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ST7789S
9.2.28 PROMCTRL (ECh): Program Mode Control
ECH
PROMCTRL (Program Mode Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PROMCTRL
0
↑
1
-
1
1
1
0
1
1
0
0
(Ech)
Parameter
1
↑
1
-
0
0
0
0
0
0
0
1
Description
When program mode enable, this command need be set.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
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ST7789S
9.2.29 PROMEN (FAh): Program Mode Enable
FAH
PROMEN (Program Mode Enable)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PROMEN
0
↑
1
-
1
1
1
1
1
0
1
0
(Fah)
1 Parameter
1
↑
1
-
0
1
0
1
1
0
1
0
(5Ah)
2nd Parameter
1
↑
1
-
0
1
1
0
1
0
0
1
(69h)
3rd Parameter
1
↑
1
-
1
1
1
0
1
1
1
0
(Eeh)
1
↑
1
-
0
0
0
0
0
PROMEN
0
0
st
th
4 Parameter
PROMEN:
Description
“0”: Program mode disable
“1”: Program mode enable
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
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9.2.30 NVMSET (FCh): NVM Setting
FCH
NVMSET (NVM Setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NVMSET
0
↑
1
-
1
1
1
1
1
1
0
0
(FCh)
1 Parameter
1
↑
1
-
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
2nd Parameter
1
↑
1
-
D7
D6
D5
D4
D3
D2
D1
D0
st
ADD[7:0]: NVM address setting
Description
D[7:0]: Data setting of NVM address
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h/00h
S/W Reset
00h/00h
H/W Reset
00h/00h
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9.2.31 PROMACT (FEh): Program action
FEH
PROMACT (Program action)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PROMACT
0
↑
1
-
1
1
1
1
1
1
1
0
(Feh)
st
1 Parameter
1
↑
1
-
0
0
1
0
1
0
0
1
(29h)
2nd Parameter
1
↑
1
-
1
0
1
0
0
1
0
1
(A5h)
Description
When program mode enable, this command need be set.
Register
Availability
Default
Version 1.5
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
Yes
Partial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In
Yes
Status
Default Value
Power On Sequence
00h/00h
S/W Reset
00h/00h
H/W Reset
00h/00h
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ST7789S
10 APPLICATION
10.1 Configuration of Power Supply Circuit
FPC
VCOM
<10ohm
DUMMY
DUMMY
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
DUMMY
VAG
VAG
VDDS
VDDS
VDDGX
VDDGX
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
G1
G3
G5
G7
G9
G 11
G 13
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VGL
VGL
VGL
VGL
VGL
VGL
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVCL
AVCL
G303
G305
G307
G309
G311
G313
G315
G317
G319
AVCL
AVCL
AVCL
AVCL
AVCL
VAN
VAN
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VAP
VAP
V20
V20
V20
V20
V20
V20
V20
DUMMY
DUMMY
DUMMY
DUMMY
VDD
<10ohm
<10ohm
<10ohm
IM3
IM1
RESX
DCX
RDX
EXTC
IM2
IM0
CSX
WRX
VSYNC
HSYNC
DOTCLK
ENABLE
DB0
DB2
SDA
DB1
DB3
DB4
DB6
DB9
DB11
DB13
DB15
DB17
TE
LED_PWM
DB5
DB7
DB8
DB10
DB12
DB14
DB16
SDO
LED_EN
VDDI_LED
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
DB12
DB13
DB14
DB15
DUMMY
DB16
DB17
TEST0
TE
SDO
<10ohm
<10ohm
Version 1.5
IM2
IM1
IM0
RESX
CSX
DCX
WRX
RDX
TEST2
VSYNC
HSYNC
ENABLE
DOTCLK
DUMMY
SDA
DB0
DB1
DB2
DB3
TEST1
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
VPP
<10ohm
S353
S354
S355
S356
S357
S358
S359
S360
DGND
DGND
DGND
DGND
DGND
TEST3
DUMMY
DUMMY
EXTC
IM3
DB4
DB5
DB6
DB7
DUMMY
DB8
DB9
DB10
DB11
TEST0
<10ohm
VCOM
DUMMY
DUMMY
DUMMY
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
VDDI
S1
S2
S3
S4
S5
S6
Y
S361
S362
S363
S364
S365
S366
S367
S368
X
LED_PWM
LED_EN
VDDI_LED
VDDI_LED
TE2
TESTO1
TESTO2
TESTO3
TESTO4
TESTO5
TESTO6
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DUMMY
VPP
VPP
VPP
VPP
DUMMY
DUMMY
VGH
S712
S713
S714
S715
S716
S717
S718
S719
S720
G320
G318
G316
G314
G312
G310
G308
G306
VGH
VGH
VGH
VGH
VGH
VGH
VGH
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DUMMYR1
DUMMYR2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
G12
G10
G8
G6
G4
G2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
DUMMY
DUMMY
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ST7789S
10.2 Voltage Generation
The following is the ST7789S analog voltage pattern diagram:
Figure 38 Power Booster Level
Version 1.5
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ST7789S
10.3 Relationship about source voltage
The relationship about source voltage is shown as below:
VAP
VAP
VP0
VP0
VP1
VAP
VP1
VP0
VP1
VP62
VP63
VP62
VBP
VP63
VP62
VBP
VP63
VBP
VBN
VN63
VBN
VN63
VN62
VN62
VBN
VN63
VN62
VN1
VN0
VN1
VAN
VN0
VN1
VAN
VN0
VAN
Figure 39 Relationship about source voltage
Note: if VDV=0V, VBP=VBN=VCOM+VCOM OFFSET.
Version 1.5
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ST7789S
10.4 Applied Voltage to the TFT panel
Figure 40 Voltage Output to TFT LCD Panel
Version 1.5
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ST7789S
11 REVISION HISTORY
Version
Date
Description
V1.0
2012/11
First issue
V1.1
2012/12
1. Modified pin20~24, 26~31, 190~197 pin definition.
2. Fix type error in command 3Ah.
V1.2
2013/01
1. Specify pin description for TE2
2. Modify TEST3~0 connect level from GND to open
V1.3
2013/02
1. Specify pin description for V20
2. Specify connect pin for AVDD/AVCL/VAP/VAN/VGH/VGL
3. Correct type error for DUMMYR1 and DUMMYR2.
4. Fix type error about description of RGB 16bit data bus.
5. Specify command E8h and E9h
V1.4
2013/03
1. Specify command D0h and D2h
2. Correct type error in command 2Ch
3. Specify minimum setting of hpw and hbp in RGB interface.
V1.5
Version 1.5
2013/04
Specify 2 data lane serial interface.
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