SITRONIX ST7715

ST
Sitronix
ST7715
262K Color Single-Chip TFT Controller/Driver
1
Introduction
The ST7715 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 132
gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial
Peripheral Interface (SPI), 8-bit/9-bit/16-bit/18-bit parallel interface. Display data can be stored in the on-chip display data
RAM of 132 x 132 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to
minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal,
it is possible to make a display system with fewer components.
2
Features
Single chip TFT-LCD Controller/Driver with RAM
On-chip Display Data RAM (i.e. Frame Memory)
- 132 (H) x RGB x 132 (V) bits
LCD Driver Output Circuits:
- Source Outputs: 132 RGB channels
Built-in Circuits
- DC/DC converter
- Gate Outputs: 132 channels
Display Resolution
- 132 (RGB) x 132
-
Adjustable VCOM
-
Non-volatile (NV) memory to store initial register setting
-
Oscillator for display clock generation
-
Factory default value (module ID, module version, etc)
are stored in NV memory
(GM[2:0]= ”001”, DDRAM: 132 x 18-bits x 132)
Display Colors (Color Mode)
- Full Color: 262K, RGB=(666) max., Idle Mode OFF
- Timing controller
Built-in NV Memory for LCD Initial Register Setting
- 7-bits for ID2
- Color Reduce: 8-color, RGB=(111), Idle Mode ON
Programmable Pixel Color Format (Color Depth) for
Various Display Data input Format
- 12-bit/pixel: RGB=(444) using the 384k-bit frame
-
- 7-bits for VCOM adjustment
Wide Supply Voltage Range
- I/O Voltage (VDDI to DGND): 1.65V~VDD
memory and LUT
-
(VDDI ≤ VDD)
16-bit/pixel: RGB=(565) using the 384k-bit frame
- Analog Voltage (VDD to AGND): 2.6V~3.3V
On-Chip Power System
- Source Voltage (GVDD to AGND): 3.0V~5.0V
memory and LUT
-
18-bit/pixel: RGB=(666) using the 384k-bit frame
memory and LUT
Various Interfaces
- Parallel 8080-series MCU Interface
-
VCOM HIGH level (VCOMH to AGND): 2.5V to 5.0V
-
VCOM LOW level (VCOML to AGND): -2.4V to 0.0V
-
Gate driver HIGH level (VGH to AGND):
-
Gate driver LOW level (VGL to AGND):
(8-bit, 9-bit, 16-bit & 18-bit)
-
+10.0V to 15V
3-line serial interface
- 4-line serial interface
Display Features
- Programmable partial display duty
-
Line inversion, frame inversion
-
Support both normal-black & normal-white LC
-
Software programmable color depth mode
ST7715
8-bits for ID3
-12.4V to –7.5V
Operating Temperature: -30°C to +85°C
Parallel Interface: 8-bit/9-bit/16-bit/18-bit
Serial Interface: 3-line/4-line
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
V1.5
1
2009-12-04
ST7715
3
Pad arrangement
3.1 Output Bump Dimension
Boundary (Include scribe Lane)
C
L
K
H
J
A
V1.5
Item
Symbol
Size
Bump pitch
A
16 um
Bump width
C
16 um
Bump height
H
98 um
Bump gap1 (Vertical)
J
19 um
Bump gap2 (Horizontal)
K
16 um
Bump area
CxH
1568 um2
Chip Boundary (include scribe Lane)
L
59 um
2
2009-12-04
ST7715
3.2 Input Bump Dimension
C2
C2
A1
A2
C1
H
K
K2
K1
K1
L
Boundary (Include scribe Lane)
V1.5
Item
Symbol
Size
Bump pitch 1
A1
67 um
Bump pitch 2
A2
50 um
Bump width 1
C1
35 um
Bump width 2
C2
40 um
Bump height
H
90 um
Bump gap
K
20 um
Bump gap1
K1
15 um
Bump gap2
K2
32 um
Bump area 1
C1 X H
3150 um2
Bump area 2
C2 X H
3690 um2
Chip Boundary(include scribe Lane)
L
59 um
3
2009-12-04
ST7715
3.3 Alignment Mark Dimension
10 5
5 10
80
15 15
15 15
20
20
15 15
15 15
80
15 15
20
15 15
15 15
80
20
15 15
80
3.4 Chip Information
Chip size (um x um): 9900 x 670
PAD coordinate: pad center
Coordinate origin: chip center
Chip thickness (um): 300 (TYP)
Bump height (um): 15 (TYP)
Bump hardness (HV): 75 (TYP)
V1.5
4
2009-12-04
ST7715
4
Pad Center Coordinates
No.
PAD Name
X
Y
No.
PAD Name
X
Y
No.
PAD Name
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DUMMY
VDDIO
EXTC
DGNDO
IM0
VDDIO
IM1
DGNDO
DUMMY
VDDIO
TPI[1]
DGNDO
TPI[2]
VDDIO
SRGB
DGNDO
SMX
VDDIO
SMY
DGNDO
DUMMY
VDDIO
DUMMY
DGNDO
DUMMY
VDDIO
DUMMY
DGNDO
DUMMY
VDDIO
LCM
DGNDO
DUMMY
VDDIO
GM2
DGNDO
GM1
VDDIO
GM0
DGNDO
DUMMY
GS
SPI4W
VDDIO
TPO[8]
TPO[7]
TPO[6]
TPO[5]
TPO[4]
OSC
-4750
-4700
-4650
-4600
-4550
-4500
-4450
-4400
-4350
-4300
-4250
-4200
-4150
-4100
-4050
-4000
-3950
-3900
-3850
-3800
-3750
-3700
-3650
-3600
-3550
-3500
-3450
-3400
-3350
-3300
-3250
-3200
-3150
-3100
-3050
-3000
-2950
-2900
-2850
-2800
-2750
-2700
-2650
-2600
-2550
-2500
-2450
-2400
-2350
-2300
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VDD
VDD
VDD
VDD
VDD
VDD
AGND
AGND
AGND
AGND
AGND
AGND
RDX
D/CX
TESEL
DGNDO
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D1
D3
D5
D7
TE
RESX
CSX
D6
D4
D2
IM2
D0
WRX
DUMMY
DUMMY
DUMMY
DUMMY
TPO[3]
TPO[2]
TPO[1]
DGND
DGND
DGND
DGND
-2250
-2200
-2150
-2100
-2050
-2000
-1950
-1900
-1850
-1800
-1750
-1700
-1630
-1570
-1510
-1450
-1390
-1330
-1270
-1210
-1150
-1090
-1030
-970
-910
-850
-790
-730
-670
-610
-550
-490
-430
-370
-310
-250
-190
-130
-70
0
50
100
150
200
250
300
350
400
450
500
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
DGND
DGND
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VCC
VCC
VCCO
VCI1
VCI1
VCI1
VREF
VREF
VREF
DUMMY
DUMMY
AVDD
AVDD
AVDD
AVDDO
AVDDO
GVDD
GVDD
GVDD
DUMMY
DUMMY
C11P
C11P
C11P
C11P
C11N
C11N
C11N
C11N
C12P
C12P
C12P
C12P
C12N
C12N
C12N
C12N
AGND
AGND
AGND
VCL
VCL
550
600
650
700
750
800
850
900
950
1000
1050
1100
1150
1200
1250
1300
1350
1400
1450
1500
1550
1600
1650
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
2250
2300
2350
2400
2450
2500
2550
2600
2650
2700
2750
2800
2850
2900
2950
3000
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
V1.5
5
2009-12-04
ST7715
No.
PAD Name
X
Y
No.
PAD Name
X
Y
No.
PAD Name
X
Y
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
VCL
C41P
C41P
C41P
C41N
C41N
C41N
C22P
C22P
C22P
C22N
C22N
C22N
C23P
C23P
C23P
C23N
C23N
C23N
VGL
VGL
VGL
VGH
VGH
VGHO
VCOMH
VCOMH
VCOMH
VCOML
VCOML
VCOML
VCOM
VCOM
VCOM
DUMMY2
DUMMY3
DUMMY4
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
3050
3100
3150
3200
3250
3300
3350
3400
3450
3500
3550
3600
3650
3700
3750
3800
3850
3900
3950
4000
4050
4100
4150
4200
4250
4300
4350
4400
4450
4500
4550
4600
4650
4700
4750
4772
4756
4740
4724
4708
4692
4676
4660
4644
4628
4612
4596
4580
4564
4548
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
-231
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
DUMMYG
DUMMYG
G132
G130
G128
G126
G124
G122
G120
G118
G116
G114
G112
G110
G108
G106
G104
G102
G100
G98
G96
G94
G92
G90
G88
G86
G84
G82
G80
G78
G76
G74
G72
G70
G68
G66
G64
G62
G60
G58
G56
G54
G52
G50
G48
G46
G44
G42
G40
G38
4532
4516
4500
4484
4468
4452
4436
4420
4404
4388
4372
4356
4340
4324
4308
4292
4276
4260
4244
4228
4212
4196
4180
4164
4148
4132
4116
4100
4084
4068
4052
4036
4020
4004
3988
3972
3956
3940
3924
3908
3892
3876
3860
3844
3828
3812
3796
3780
3764
3748
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
G36
G34
G32
G30
G28
G26
G24
G22
G20
G18
G16
G14
G12
G10
G8
G6
G4
G2
DUMMY
DUMMY
DUMMY
DUMMY
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369
3732
3716
3700
3684
3668
3652
3636
3620
3604
3588
3572
3556
3540
3524
3508
3492
3476
3460
3444
3428
3412
3396
3380
3364
3348
3332
3316
3300
3284
3268
3252
3236
3220
3204
3188
3172
3156
3140
3124
3108
3092
3076
3060
3044
3028
3012
2996
2980
2964
2948
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
V1.5
6
2009-12-04
ST7715
No.
PAD Name
X
Y
No.
PAD Name
X
Y
No.
PAD Name
X
Y
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
S368
S367
S366
S365
S364
S363
S362
S361
S360
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
2932
2916
2900
2884
2868
2852
2836
2820
2804
2788
2772
2756
2740
2724
2708
2692
2676
2660
2644
2628
2612
2596
2580
2564
2548
2532
2516
2500
2484
2468
2452
2436
2420
2404
2388
2372
2356
2340
2324
2308
2292
2276
2260
2244
2228
2212
2196
2180
2164
2148
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
S318
S317
S316
S315
S314
S313
S312
S311
S310
S309
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269
2132
2116
2100
2084
2068
2052
2036
2020
2004
1988
1972
1956
1940
1924
1908
1892
1876
1860
1844
1828
1812
1796
1780
1764
1748
1732
1716
1700
1684
1668
1652
1636
1620
1604
1588
1572
1556
1540
1524
1508
1492
1476
1460
1444
1428
1412
1396
1380
1364
1348
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219
1332
1316
1300
1284
1268
1252
1236
1220
1204
1188
1172
1156
1140
1124
1108
1092
1076
1060
1044
1028
1012
996
980
964
948
932
916
900
884
868
852
836
820
804
788
772
756
740
724
708
692
676
660
644
628
612
596
580
564
548
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
V1.5
7
2009-12-04
ST7715
No.
PAD Name
X
Y
No.
PAD Name
X
Y
No.
PAD Name
X
Y
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
S218
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
DUMMY
DUMMY
DUMMY
DUMMY
S198
S197
S196
S195
S194
S193
S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
532
516
500
484
468
452
436
420
404
388
372
356
340
324
308
292
276
260
244
228
212
196
-196
-212
-228
-244
-260
-276
-292
-308
-324
-340
-356
-372
-388
-404
-420
-436
-452
-468
-484
-500
-516
-532
-548
-564
-580
-596
-612
-628
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
-644
-660
-676
-692
-708
-724
-740
-756
-772
-788
-804
-820
-836
-852
-868
-884
-900
-916
-932
-948
-964
-980
-996
-1012
-1028
-1044
-1060
-1076
-1092
-1108
-1124
-1140
-1156
-1172
-1188
-1204
-1220
-1236
-1252
-1268
-1284
-1300
-1316
-1332
-1348
-1364
-1380
-1396
-1412
-1428
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
-1444
-1460
-1476
-1492
-1508
-1524
-1540
-1556
-1572
-1588
-1604
-1620
-1636
-1652
-1668
-1684
-1700
-1716
-1732
-1748
-1764
-1780
-1796
-1812
-1828
-1844
-1860
-1876
-1892
-1908
-1924
-1940
-1956
-1972
-1988
-2004
-2020
-2036
-2052
-2068
-2084
-2100
-2116
-2132
-2148
-2164
-2180
-2196
-2212
-2228
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
V1.5
8
2009-12-04
ST7715
No.
PAD Name
X
Y
No.
PAD Name
X
Y
No.
PAD Name
X
Y
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
-2244
-2260
-2276
-2292
-2308
-2324
-2340
-2356
-2372
-2388
-2404
-2420
-2436
-2452
-2468
-2484
-2500
-2516
-2532
-2548
-2564
-2580
-2596
-2612
-2628
-2644
-2660
-2676
-2692
-2708
-2724
-2740
-2756
-2772
-2788
-2804
-2820
-2836
-2852
-2868
-2884
-2900
-2916
-2932
-2948
-2964
-2980
-2996
-3012
-3028
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
DUMMY
DUMMY
DUMMY
DUMMY
G1
G3
G5
G7
G9
G11
G13
G15
G17
G19
G21
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
-3044
-3060
-3076
-3092
-3108
-3124
-3140
-3156
-3172
-3188
-3204
-3220
-3236
-3252
-3268
-3284
-3300
-3316
-3332
-3348
-3364
-3380
-3396
-3412
-3428
-3444
-3460
-3476
-3492
-3508
-3524
-3540
-3556
-3572
-3588
-3604
-3620
-3636
-3652
-3668
-3684
-3700
-3716
-3732
-3748
-3764
-3780
-3796
-3812
-3828
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
G49
G51
G53
G55
G57
G59
G61
G63
G65
G67
G69
G71
G73
G75
G77
G79
G81
G83
G85
G87
G89
G91
G93
G95
G97
G99
G101
G103
G105
G107
G109
G111
G113
G115
G117
G119
G121
G123
G125
G127
G129
G131
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
DUMMYG
-3844
-3860
-3876
-3892
-3908
-3924
-3940
-3956
-3972
-3988
-4004
-4020
-4036
-4052
-4068
-4084
-4100
-4116
-4132
-4148
-4164
-4180
-4196
-4212
-4228
-4244
-4260
-4276
-4292
-4308
-4324
-4340
-4356
-4372
-4388
-4404
-4420
-4436
-4452
-4468
-4484
-4500
-4516
-4532
-4548
-4564
-4580
-4596
-4612
-4628
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
110
227
V1.5
9
2009-12-04
ST7715
No.
PAD Name
X
Y
751
752
753
754
755
756
757
758
759
DummyG
DummyG
DummyG
DummyG
DummyG
DummyG
DummyG
DUMMY
DUMMY
-4644
-4660
-4676
-4692
-4708
-4724
-4740
-4756
-4772
110
227
110
227
110
227
110
227
110
ALK-R
ALK-L
4841
-4841
-220
-220
V1.5
10
2009-12-04
ST7715
5
V1.5
Block diagram
11
2009-12-04
ST7715
6
Driver IC Pin Description
6.1 Power Supply Pin
Name
I/O
Description
Connect pin
VDD
I
Power supply for analog, digital system and booster circuit.
VDD
VDDI
I
Power supply for I/O system.
VDDI
AGND
I
System ground for analog system and booster circuit.
GND
DGND
I
System ground for I/O system and digital system.
GND
Description
Connect pin
6.2 Interface logic pin
Name
I/O
MCU Parallel interface bus and Serial interface select
IM2
I
IM2=’1’, Parallel interface
DGND/VDDI
IM2=’0’, Serial interface
- MCU parallel interface type selection
-If not used, please fix this pin at VDDI or DGND level.
IM1,IM0
I
IM1
IM0
Parallel interface
0
0
MCU 8-bit parallel
0
1
MCU 16-bit parallel
1
0
MCU 9-bit parallel
1
1
MCU 18-bit parallel
DGND/VDDI
- SPI4W=’0’, 3-line SPI enable.
SPI4W
I
- SPI4W=’1’, 4-line SPI enable.
DGND/VDDI
-If not used, please fix this pin at DGND level.
-This signal will reset the device and it must be applied to properly
RESX
I
initialize the chip.
MCU
-Signal is active low.
CSX
I
-Chip selection pin
MCU
-Low enable.
-Display data/command selection pin in MCU interface.
D/CX
(SCL)
-D/CX=’1’: display data or parameter.
I
-D/CX=’0’: command data.
MCU
-In serial interface, this is used as SCL.
-If not used, please fix this pin at VDDI or DGND level.
RDX
WRX
(D/CX)
D[17:0]
V1.5
I
-Read enable in 8080 MCU parallel interface.
-If not used, please fix this pin at VDDI or DGND level.
MCU
-Write enable in MCU parallel interface.
I
-In 4-line SPI, this pin is used as D/CX (data/ command selection).
MCU
-If not used, please fix this pin at VDDI or DGND level.
I/O
-D[17:0] are used as MCU parallel interface data bus.
12
MCU
2009-12-04
ST7715
-D0 is the serial input/output signal in serial interface mode.
-In serial interface, D[17:1] are not used and should be fixed at VDDI or
DGND level.
-Tearing effect output pin to synchronies MCU to frame rate, activated
TE
O
by S/W command.
MCU
-If not used, please open this pin.
-Monitoring pin of internal oscillator clock and is turned ON/OFF by
OSC
O
S/W command.
-When this pin is inactive (function OFF), this pin is DGND level.
-
-If not used, please open this pin.
Note1. When in parallel mode, no use data pin must be connected to “1” or “0”.
Note2. When CSX=”1”, there is no influence to the parallel and serial interface.
V1.5
13
2009-12-04
ST7715
6.3 Mode selection pin
Name
I/O
Description
Connect pin
-To use extended command set, please connect this pin to VDDI.
-During normal operation, please open this pin (internal
Rpull-down=2MΩ).
EXTC
I
EXTC
Enable/disable modification of extend command
0
System function command list can be used.
1
All command list can be used.
Open
-Panel resolution selection pins.
GM2,
GM1,
GM0
I
G
G
G
M
M
M
2
1
0
0
0
1
Selection of panel resolution
VDDI/DGND
132RGB x 132 (S1~S396 & G1~G132 output)
-RGB direction select H/W pin for color filter setting.
SRGB
I
SRGB
RGB arrangement
0
S1, S2, S3 filter order = ’R’, ’G’, ’B’
1
S1, S2, S3 filter order = ‘B’, ‘G’, ‘R’
VDDI/DGND
-Module source output direction H/W selection pin.
SMX
SMX
Scanning direction of source output
GM= ‘001’
I
0
S1 -> S396
1
S396 -> S1
VDDI/DGND
-Module Gate output direction H/W selection pin.
SMY
SMY
Scanning direction of gate output
GM= ‘001’
I
0
G1 -> G132
1
G132 -> G1
VDDI/DGND
-Liquid crystal (LC) type selection pins.
LCM
V1.5
I
LCM
Selection of LC type
0
Normally white LC type
1
Normally black LC type
14
VDDI/DGND
2009-12-04
ST7715
-Gamma curve selection pin.
GS
I
GS
Selection of gamma curve
0
GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8
1
GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0
VDDI/DGND
Input pin to select horizontal line number in TE signal.
TESEL
V1.5
I
DGND
Connect this pin to DGND
15
2009-12-04
ST7715
6.4 Driver output pins
Name
I/O
Description
S1 to S396
O
- Source driver output pins.
-
G1 to G132
O
- Gate driver output pins.
-
VCI1
I/O
- Hi-Z
-
AVDD
I
AVDDO
O
VCL
O
VGH
I
VGHO
O
- Power input pin for analog circuits.
- In normal usage, connect it to AVDDO.
- Output of step-up circuit 1
- Connect a capacitor for stabilization.
Connect pin
AVDDO
Capacitor
- A power supply pin for generating VCOML.
- Connect a capacitor for stabilization.
- Power input pin for gate driver circuit.
- In normal usage, connect it to VGHO.
- Positive output pin of the step-up circuit 2.
- Connect a capacitor for stabilization.
Capacitor
VGHO
Capacitor
- Power input pin for gate driver circuit.
VGL
I
- Negative output of the step-up circuit 2 is connected inside the
driver.
Capacitor
- Connect a capacitor for stabilization.
VREF
O
- A reference voltage for power system.
-
- A power output of grayscale voltage generator.
GVDD
O
- When internal GVDD generator is not used, connect an external
-
power supply (AVDD-0.5V) to this pin.
- Positive voltage output of VCOM.
VCOMH
O
VCOML
O
VCOM
O
- A power supply for the TFT-LCD common electrode.
C11P, C11N
O
- Capacitor connecting pins for step-up circuit 1 (for AVDDO)
C22P, C22N
C23P, C23N
O
C41P, C41N
VDDIO
V1.5
O
- Connect a capacitor for stabilization.
- Negative voltage output of VCOM.
- Connect a capacitor for stabilization.
- Capacitor connecting pins for step-up circuit 2 and 4 (for VGHO,
VGL, VCL)
Capacitor
Capacitor
Common
electrode
Step-up
Capacitor
Step-up
Capacitor
-VDDI voltage output level for monitoring.
16
-
2009-12-04
ST7715
DGNDO
O
VCC
O
VCCO
O
-DGND voltage output level for monitoring.
-Power input pin for internal digital reference voltage.
-In normal usage, connect it to VCCO.
-Monitoring pin of internal digital reference voltage.
-Connect a capacitor for stabilization.
VCCO
Capacitor
6.5 Test pins
Name
TPI[2]
TPI[1]
I/O
Description
Connect pin
-These test pins for Driver vender test used.
I
-Please connect these pins to DGND.
DGND
TPO[8]
TPO[7]
TPO[6]
TPO[5]
TPO[4]
-These test pins for Driver vender test used.
O
Open
-Please open these pins.
TPO[3]
TPO[2]
TPO[1]
Dummy
DummyG
V1.5
-
-These pins are dummy (have no function inside).
-Can allow signal traces pass through these pads on TFT glass.
- Vendor function
Open
Open
17
2009-12-04
ST7715
7
Driver electrical characteristics
7.1 Absolute operation range
Item
Symbol
Rating
Unit
Supply voltage
VDD
-0.3 ~ +4.6
V
Supply voltage (Logic)
VDDI
-0.3 ~ +4.6
V
Supply voltage (Digital)
VCC
-0.3 ~ +1.95
V
Driver supply voltage
VGH-VGL
-0.3 ~ +30.0
V
Logic input voltage range
VIN
0.3 ~ VDDI +0.3
V
Logic output voltage range
VO
0.3 ~ VDDI +0.3
V
Operating temperature range
TOPR
-30 ~ +85
℃
Storage temperature range
TSTG
-40 ~ +125
℃
Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute
maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the recommend range.
7.2 DC characteristic
Parameter
Symbol
Specification
Condition
Min
Unit
Typ
Max
Related
Pins
Power & operation voltage
System voltage
Interface operation
voltage
Gate driver high
voltage
Gate driver low
voltage
VDD
Operating voltage
2.6
2.75
3.3
V
VDDI
I/O supply voltage
1.65
1.9
3.3
V
VGH
10
15
V
VGL
-12.4
-7.5
V
17.5
27.5
V
VIH
0.7VDDI
VDDI
V
Note 1
VIL
VSS
0.3VDDI
V
Note 1
Gate driver supply
| VGH-VGL |
voltage
Input / Output
Logic-high input
voltage
Logic-low input
voltage
Logic-high output
voltage
Logic-low output
voltage
Logic-high input
current
V1.5
VOH
IOH = -1.0mA
0.8VDDI
VDDI
V
Note 1
VOL
IOL = +1.0mA
VSS
0.2VDDI
V
Note 1
IIH
VIN = VDDI
1
uA
Note 1
18
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Logic-low input
IIL
VIN = VSS
-1
IIL
IOH = -1.0mA
-0.1
VCOM high voltage
VCOMH
Ccom=12nF
VCOM low voltage
VCOML
VCOMAC
current
Input leakage
current
uA
Note 1
+0.1
uA
Note 1
2.5
5.0
V
Ccom=12nF
-2.4
0.0
V
|VCOMH-VCOML|
4.0
6.0
V
Vsout
0.1
AVDD-0.1
V
GVDD
3.0
5.0
V
20
us
Note 2
35
mV
Note 3
VCOM voltage
VCOM amplitude
Source driver
Source output range
Gamma reference
voltage
Source output
settling time
Output offset voltage
Tr
Below with 99%
precision
Voffset
Notes:
1. VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, TA= -30 to 85℃
2. Source channel loading= 2KΩ+12pF/channel, Gate channel loading=5KΩ+40pF/channel.
3. The Max. value is between measured point of source output and gamma setting value.
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7.3 Power consumption
VDD=2.8V, VDDI=1.8V, Ta=25℃, Frame rate = 60Hz, the registers setting are IC default setting.
Current consumption
Operation mode
Normal mode
Partial + Idle mode (40 lines)
Sleep-in mode
Inversion
mode
One Line
One Line
N/A
Typical
Image
Maximum
IDDI
IDD
IDDI
IDD
(mA)
(mA)
(mA)
(mA)
Note 1
0.01
0.5
0.02
0.7
Note 2
0.01
0.5
0.02
0.7
Note 1
0.01
0.3
0.02
0.5
Note 2
0.01
0.3
0.02
0.5
N/A
0.005
0.015
0.01
0.03
Notes:
1. All pixels black.
2. All pixels white.
3. The Current Consumption is DC characteristics. .
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8
Timing chart
8.1 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (8080 series MCU interface)
Fig. 8.1.1 Parallel interface timing characteristics (8080 series MCU interface)
Signal
D/CX
CSX
WRX
RDX (ID)
Symbol
Parameter
Min
Max
Unit
TAST
Address setup time
10
ns
TAHT
Address hold time (Write/Read)
10
ns
TCHW
Chip select “H” pulse width
0
ns
TCS
Chip select setup time (Write)
15
ns
TRCS
Chip select setup time (Read ID)
45
ns
TRCSFM
Chip select setup time (Read FM)
350
ns
TCSF
Chip select wait time (Write/Read)
10
ns
TCSH
Chip select hold time
10
ns
TWC
Write cycle
100
ns
TWRH
Control pulse “H” duration
30
ns
TWRL
Control pulse “L” duration
30
ns
TRC
Read cycle (ID)
160
ns
TRDH
Control pulse “H” duration (ID)
90
ns
TRDL
Control pulse “L” duration (ID)
45
ns
TRCFM
Read cycle (FM)
450
ns
TRDHFM
Control pulse “H” duration (FM)
150
ns
TRDLFM
Control pulse “L” duration (FM)
150
ns
RDX
(FM)
V1.5
Description
-
-
When read ID data
When read from frame
21
memory
2009-12-04
ST7715
D[17:0]
TDST
Data setup time
10
ns
TDHT
Data hold time
10
ns
TRAT
Read access time (ID)
40
ns
TRATFM
Read access time (FM)
40
ns
TODH
Output disable time
80
ns
For CL=30pF
Table 8.1.1 Parallel Interface Characteristics
Note: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃
TR
TF
TR
TF
VIH=0.7 x VDDI
VOH=0.8 x VDDI
VIL=0.3 x VDDI
VOL=0.2 x VDDI
TR=TF<=15ns
TR=TF<=15ns
Fig. 8.1.2 Rising and falling timing for input and output signal
Fig. 8.1.3 Chip selection (CSX) timing
Fig. 8.1.4 Write-to-read and read-to-write timing
Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%
and 70% of VDDI for Input signals.
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8.2 Serial interface characteristics (3-line serial)
CSX
VIH
TCHW
VIL
TSCYCW/TSCYCR
TCSH
TCSS
TSLW/TSLR
SCL
TSHW/TSHR
TSDS
SDA
TSCC
VIH
VIL
TSDH
VIH
VIL
TACC
TOH
VIH
VIL
VIH
SDA
(DOUT)
VIL
Fig. 8.2.1 3-line serial interface timing
Signal
CSX
SCL
SDA
Symbol
Parameter
Min
Max
Unit
TCSS
Chip select setup time (write)
15
ns
TCSH
Chip select hold time (write)
15
ns
TCSS
Chip select setup time (read)
60
ns
TSCC
Chip select hold time (read)
65
ns
TCHW
Chip select “H” pulse width
40
ns
TSCYCW
Serial clock cycle (Write)
66
ns
TSHW
SCL “H” pulse width (Write)
30
ns
TSLW
SCL “L” pulse width (Write)
30
ns
TSCYCR
Serial clock cycle (Read)
150
ns
TSHR
SCL “H” pulse width (Read)
60
ns
TSLR
SCL “L” pulse width (Read)
60
ns
TSDS
Data setup time
10
ns
TSDH
Data hold time
10
ns
For maximum CL=30pF
TACC
Access time
10
50
ns
For minimum CL=8pF
TOH
Output disable time
50
ns
(DIN)
(DOUT)
Description
Table 8.2.1 3-line Serial Interface Characteristics
Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃
Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%
and 70% of VDDI for Input signals.
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8.3 Serial interface characteristics (4-line serial)
Fig. 8.3.1 4-line serial interface timing
Signal
CSX
Symbol
Parameter
MIN
MAX
Unit
TCSS
Chip select setup time (write)
15
ns
TCSH
Chip select hold time (write)
15
ns
TCSS
Chip select setup time (read)
60
ns
TSCC
Chip select hold time (read)
65
ns
TCHW
Chip select “H” pulse width
40
ns
TSCYCW
Serial clock cycle (Write)
66
ns
TSHW
SCL “H” pulse width (Write)
30
ns
TSLW
SCL “L” pulse width (Write)
30
ns
TSCYCR
Serial clock cycle (Read)
150
ns
TSHR
SCL “H” pulse width (Read)
60
ns
TSLR
SCL “L” pulse width (Read)
60
ns
TDCS
D/CX setup time
TDCH
D/CX hold time
10
ns
TSDS
Data setup time
10
ns
TSDH
Data hold time
10
ns
TACC
Access time
10
TOH
Output disable time
Description
-write command & data
SCL
ram
-read command & data
D/CX
SDA
(DIN)
(DOUT)
0
ram
ns
50
ns
For maximum CL=30pF
50
ns
For minimum CL=8pF
Table 8.3.1 4-line Serial Interface Characteristics
Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃
Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%
and 70% of VDDI for Input signals.
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9
Function description
9.1 Interface type selection
The selection of given interfaces are done by setting IM2, IM1, and IM0 pins as shown in following table.
IM2
IM1
IM0
Interface
Read back selection
0
-
-
3-line serial interface
Via the read instruction
1
0
0
8080 MCU 8-bit parallel
RDX strobe (8-bit read data and 8-bit read parameter)
1
0
1
8080 MCU 16-bit parallel
RDX strobe (16-bit read data and 8-bit read parameter)
1
1
0
8080 MCU 9-bit parallel
RDX strobe (9-bit read data and 8-bit read parameter)
1
1
1
8080 MCU 18-bit parallel
RDX strobe (18-bit read data and 8-bit read parameter)
Table 9.1.1 Selection of MCU interface
IM2
IM1
IM0
0
-
-
1
0
1
Interface
RDX
WRX
D/CX
Read back selection
3-line serial
Note1
Note1
SCL
D[17:1]: unused, D0: SDA
0
8080 8-bit parallel
RDX
WRX
D/CX
D[17:8]: unused, D7-D0: 8-bit data
0
1
8080 16-bit parallel
RDX
WRX
D/CX
D[17:16]: unused, D15-D0: 16-bit data
1
1
0
8080 9-bit parallel
RDX
WRX
D/CX
D[17:9]: unused, D8-D0: 9-bit data
1
1
1
8080 18-bit parallel
RDX
WRX
D/CX
D17-D0: 18-bit data
Table 9.1.2 Pin connection according to various MCU interface
Note1 Unused pins can be open, or connected to DGND or VDDI.
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9.2 8080-series MCU parallel interface
The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface,
19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low)
enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write enable,
RDX is the parallel data read enable and D[17:0] is parallel data bus.
The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=’1’,
D[17:0] bits is either display data or command parameter. When D/C=’0’, D[17:0] bits is command.
The interface functions of 8080-series parallel interface are given in following table.
IM2
1
1
1
1
IM1
0
0
1
1
IM0
0
1
0
1
Interface
8-bit
parallel
16-bit
parallel
9-bit
parallel
18-bit
parallel
D/CX
RDX
WRX
Read back selection
0
1
↑
Write 8-bit command (D7 to D0)
1
1
↑
Write 8-bit display data or 8-bit parameter (D7 to D0)
1
↑
1
Read 8-bit display data (D7 to D0)
1
↑
1
Read 8-bit parameter or status (D7 to D0)
0
1
↑
Write 8-bit command (D7 to D0)
1
1
↑
Write 16-bit display data or 8-bit parameter (D15 to D0)
1
↑
1
Read 16-bit display data (D15 to D0)
1
↑
1
Read 8-bit parameter or status (D7 to D0)
0
1
↑
Write 8-bit command (D7 to D0)
1
1
↑
Write 9-bit display data or 8-bit parameter (D8 to D0)
1
↑
1
Read 9-bit display data (D8 to D0)
1
↑
1
Read 8-bit parameter or status (D7 to D0)
0
1
↑
Write 8-bit command (D7 to D0)
1
1
↑
Write 18-bit display data or 8-bit parameter (D17 to D0)
1
↑
1
Read 18-bit display data (D17 to D0)
1
↑
1
Read 8-bit parameter or status (D7 to D0)
Table 9.2.1 the function of 8080-series parallel interface
Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh
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9.2.1
Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write
cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit
is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is
low (=’0’) and vice versa it is data (=’1’).
WRX
D[17:0]
The host starts to control D[17:0]
lines when there is a falling edge
of the WRX.
The display writes D[17:0] lines
when there is a rising edge of
WRX.
The host stops to
control D[17:0] lines.
Fig. 9.2.1 8080-series WRX protocol
Note: WRX is an unsynchronized signal (It can be stopped).
1-byte
command
D[17:0]
S
2-byte
command
N-byte
command
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
RESX “1”
CSX
D/CX
RDX
“1”
WRX
D[17:0]
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Host D[17:0]
Host to LCD
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Hi-Z
Driver D[17:0]
LCD to Host
Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.
CMD: write command code
PA: parameter or display data
Fig. 9.2.2 8080-series parallel bus protocol, write to register or display RAM
9.2.2
Read cycle sequence
The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The
driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising
edge of RDX.
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Fig. 9.2.3 8080-series RDX protocol
Note: RDX is an unsynchronized signal (It can be stopped).
Read parameter
D[17:0]
Read display data
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
D[17:0]
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
Host D[17:0]
Host to LCD
S
CMD
Driver D[17:0]
LCD to Host
S
RESX “1”
CSX
D/CX
RDX
WRX
Hi-Z
Hi-Z
DM
CMD
PA1
Hi-Z
Hi-Z
P
DM & data
PAN-2
PAN-1
P
Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.
CMD: write command code
PA: parameter or display data
Fig. 9.2.4 8080-series parallel bus protocol, read data from register or display RAM
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9.3 Serial interface
The selection of this interface is done by IM2. See the Table 9.3.1.
IM2
SPI4W
Interface
Read back selection
0
0
3-line serial interface
Via the read instruction (8-bit, 24-bit and 32-bit read parameter)
0
1
4-line serial interface
Via the read instruction (8-bit, 24-bit and 32-bit read parameter)
Table 9.3.1 Selection of serial interface
The serial interface is either 3-line/9-bit or 4-line/8-bit bi-directional interface for communication between the micro
controller and the LCD driver. The 3-line serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data
input/output), and the 4-line serial interface use: CSX (chip enable), D/CX (data/ command flag), SCL (serial clock) and
SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no
communication is necessary.
9.3.1
Command Write Mode
The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-line serial data
packet contains a control bit D/CX and a transmission byte. In 4-line serial interface, data packet contains just transmission
byte and control bit D/CX is transferred by the D/CX pin. If D/CX is “low”, the transmission byte is interpreted as a
command byte. If D/CX is “high”, the transmission byte is stored in the display data RAM (memory write command), or
command register as parameter.
Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when
CSX is high. In this state, SCL clock pulse or SDA data have no effect.
A falling edge on CSX enables the serial interface and indicates the start of data transmission.
Fig. 9.3.1 Serial interface data stream format
When CSX is “high”, SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling
edge of CSX, SCL can be high or low (see Fig 9.3.2). SDA is sampled at the rising edge of SCL. D/CX indicates whether
the byte is command (D/CX=’0’) or parameter/RAM data (D/CX=’1’). D/CX is sampled when first rising edge of SCL (3-line
serial interface) or 8th rising edge of SCL (4-line serial interface). If CSX stays low after the last bit of command/data byte,
the serial interface expects the D/CX bit (3-line serial interface) or D7 (4-line serial interface) of the next byte at the next
rising edge of SCL.
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Fig. 9.3.2 3-line serial interface write protocol (write to register with control bit in transmission)
Fig. 9.3.3 4-line serial interface write protocol (write to register with control bit in transmission)
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9.3.2
Read Functions
The read mode of the interface means that the micro controller reads register value from the driver. To achieve read
function, the micro controller first has to send a command (read ID or register command) and then the following byte is
transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below
figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of
SCL. Thus the micro controller is supported to read at the rising edge of SCL.
After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL
of the last bit.
9.3.3
3-line serial protocol
3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
3-line serial protocol (for RDDID command: 24-bit read)
3-line Serial Protocol (for RDDST command: 32-bit read)
Fig. 9.3.4 3-line serial interface read protocol
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9.3.4
4-line serial protocol
4-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
4-line serial protocol (for RDDID command: 24-bit read)
4-line Serial Protocol (for RDDST command: 32-bit read)
Host
Driver
Fig. 9.3.5 4-line serial interface read protocol
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9.4 Data Transfer Break and Recovery
If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple
parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have
reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next
activated after RESX have been HIGH state. See the following example
Host
(MCU to driver)
Fig. 9.4.1 Serial bus protocol, write mode – interrupted by RESX
If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple
parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have
reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next
activated. See the following example
Fig. 9.4.2 Serial bus protocol, write mode – interrupted by CSX
If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one
and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the
parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is
ready to receive next byte as shown below.
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Fig. 9.4.3 Write interrupts recovery (serial interface)
If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent,
then the parameters that were successfully sent are stored and the other parameter of that command remains previous
value.
Fig. 9.4.4 Write interrupts recovery (both serial and parallel Interface)
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9.5 Data transfer pause
It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the
data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data
has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the
point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then
the display module will receive either the command‘s parameters (if appropriate) or a new command when the chip select
line is next enabled as shown below.
This applies to the following 4 conditions:
1) Command-Pause-Command
2) Command-Pause-Parameter
3) Parameter-Pause-Command
4) Parameter-Pause-Parameter
9.5.1
Serial interface pause
Fig. 9.5.1 Serial interface pause protocol (pause by CSX)
9.5.2
Parallel interface pause
Fig. 9.5.2 Parallel bus pause protocol (paused by CSX)
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9.6 Data Transfer Modes
The module has three kinds color modes for transferring data to the display RAM. These are 12-bit color per pixel, 16-bit
color per pixel and 18-bit color per pixel. The data format is described for each interface. Data can be downloaded to the
frame memory by 2 methods.
9.6.1
Method 1
The image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame
memory pointer is reset to the start point and the next frame is written.
9.6.2
Method 2
The image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write.
Then start memory write command is sent, and a new frame is downloaded.
Note 1: These apply to all data transfer Color modes on both serial and parallel interfaces.
Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in
the frame memory.
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9.7 Data Color Coding
9.7.1
8-bit Parallel Interface (IM2, IM1, IM0= “100”)
Different display data formats are available for three Colors depth supported by listed below.
- 4k colors, RGB 4,4,4-bit input.
- 65k colors, RGB 5,6,5-bit input.
- 262k colors, RGB 6,6,6-bit input.
9.7.2
8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h”
RESX
IM[2:0]
“
1”
“100”
”
CSX
D/CX
WRX
RDX
“1”
”
8080-series control pins
D7
0
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
D6
0
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
D5
1
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
D4
0
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
D3
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D2
1
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D1
0
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D0
0
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
Pixel n
Pixel n+1
12 bits
12 bits
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'
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9.7.3
8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h”
There is 1 pixel (3 sub-pixels) per 2-byte
RESX
“1”
”
“ 100”
”
IM[2:0]
CSX
D/CX
WRX
RDX
“1”
”
8080-series control pins
D7
0
R1, Bit 4
G1, Bit 2
R2, Bit 4
G2, Bit 2
D6
0
R1, Bit 3
G1, Bit 1
R2, Bit 3
G2, Bit 1
D5
1
R1, Bit 2
G1, Bit 0
R2, Bit 2
G2, Bit 0
D4
0
R1, Bit 1
B1, Bit 4
R2, Bit 1
B2, Bit 4
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n
Pixel n+1
16 bits
16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for
Red and Blue data.
Note 2:2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'
V1.5
38
2009-12-04
ST7715
9.7.4
8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h”
There is 1 pixel (3 sub-pixels) per 3-bytes.
RESX
IM[2:0]
“
1”
”
“
100”
”
CSX
D/CX
WRX
RDX
“
1”
”
8080-series control pins
D7
0
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
D6
0
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
D5
1
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
D4
0
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
D3
1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
D2
1
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
-
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2:3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'
V1.5
39
2009-12-04
ST7715
9.7.5
16-Bit Parallel Interface (IM2,IM1, IM0= “101”)
Different display data formats are available for three colors depth supported by listed below.
- 4k colors, RGB 4,4,4-bit input
- 65k colors, RGB 5,6,5-bit input
- 262k colors, RGB 6,6,6-bit input
9.7.6
16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h”
There is 1 pixel (3 sub-pixels) per 1 byte
RESX
“1”
”
“101”
”
IM[2:0]
CSX
D/CX
WRX
RDX
“1”
”
8080-series control pins
D15
-
-
-
-
-
D14
-
-
-
-
-
D13
-
-
-
-
-
D12
-
-
-
-
-
D11
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D10
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D9
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D8
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D7
0
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D6
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D5
1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D4
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
12 bits
12 bits
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2:1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.
V1.5
40
2009-12-04
ST7715
9.7.7
16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h”
There is 1 pixel (3 sub-pixels) per 1 byte
RESX
“ 1”
”
“101”
”
IM[2:0]
CSX
D/CX
WRX
RDX
“ 1”
”
8080-series control pins
D15
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
D14
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D13
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D12
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D11
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D10
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D9
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D8
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D7
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D6
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D5
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
16 bits
16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2:1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'
V1.5
41
2009-12-04
ST7715
9.7.8
16-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h”
There are 2 pixels (6 sub-pixels) per 3 bytes
RESX
“1”
”
“ 101”
”
IM[2:0]
CSX
D/CX
WRX
RDX
“1”
”
8080-series control pins
D15
-
R1, Bit 5
B1, Bit 5
G2, Bit 5
R3, Bit 5
D14
-
R1, Bit 4
B1, Bit 4
G2, Bit 4
R3, Bit 4
D13
-
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
D12
-
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
D11
-
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
D10
-
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
D9
-
-
-
-
-
D8
-
-
-
-
-
D7
0
G1, Bit 5
R2, Bit 5
B2, Bit 5
G3, Bit 5
D6
0
G1, Bit 4
R2, Bit 4
B2, Bit 4
G3, Bit 4
D5
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D4
0
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D3
1
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D2
1
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
-
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2:3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'
V1.5
42
2009-12-04
ST7715
9.7.9
9-Bit Parallel Interface (IM2, IM1, IM0=“110”)
Different display data formats are available for three colors depth supported by listed below.
-262k colors, RGB 6,6,6-bit input
9.7.10 Write 9-bit data for RGB 6-6-6-bit input (262k-color)
There is 1 pixel (6 sub-pixels) per 3 bytes
RESX
“1”
”
“ 110”
”
IM[2:0]
CSX
D/CX
WRX
RDX
“1”
”
8080-series control
pins
D8
-
R1, Bit 5
G1, Bit 2
R2, Bit 5
G2, Bit 2
D7
0
R1, Bit 4
G1, Bit 1
R2, Bit 4
G2, Bit 1
D6
0
R1, Bit 3
G1, Bit 0
R2, Bit 3
G2, Bit 0
D5
1
R1, Bit 2
B1, Bit 5
R2, Bit 2
B2, Bit 5
D4
0
R1, Bit 1
B1, Bit 4
R2, Bit 1
B2, Bit 4
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2:3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'
V1.5
43
2009-12-04
ST7715
9.7.11 18-Bit Parallel Interface (IM2, IM1, IM0=“111”)
Different display data formats are available for three colors depth supported by listed below.
- 4k colors, RGB 4,4,4-bit input
- 65k colors, RGB 5,6,5-bit input
- 262k colors, RGB 6,6,6-bit input.
9.7.12 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”
There is 1 pixel (3 sub-pixels) per 1 byte
RESX
IM [2:0]
“ 1”
“ 111 ”
C SX
D /CX
W RX
R DX
“ 1”
8080-series control pins
D17
-
-
-
-
-
D16
-
-
-
-
-
D15
-
-
-
-
-
D14
-
-
-
-
-
D13
-
-
-
-
-
D12
-
-
-
-
-
D11
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D10
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D9
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D8
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D7
0
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D6
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D5
1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D4
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
12 bits
12 bits
Look-Up Table for 4096 Color data m apping (12 bits to 18 bits)
18 bits
Fram e m em ory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2:1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information.
V1.5
44
2009-12-04
ST7715
9.7.13 18-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”
There is 1 pixel (3 sub-pixels) per 1 byte
RESX
“1”
”
“111”
”
IM[2:0]
CSX
D/CX
WRX
RDX
“1”
”
8080-series control pins
D17
-
-
-
-
-
D16
-
-
-
-
-
D15
-
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
D14
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D13
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D12
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D11
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D10
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D9
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D8
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D7
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D6
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D5
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
16 bits
16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2:1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.
V1.5
45
2009-12-04
ST7715
9.7.14 18-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”
There is 1 pixel (3 sub-pixels) per 1 byte
RESX
“1”
”
“ 111”
”
IM[2:0]
CSX
D/CX
WRX
RDX
“1”
”
8080-series control pins
D17
-
R1, Bit 5
R2, Bit 5
R3, Bit 5
R4, Bit 5
D16
-
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
D15
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D14
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D13
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D12
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D11
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D10
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D9
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D8
-
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D7
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D6
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D5
1
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data.
Note 2:1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.
V1.5
46
2009-12-04
ST7715
9.7.15 3-line serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input
9.7.16 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”
Note 1: pixel data with the 12-bit color depth information
Note 2: The most significant bits are: Rx3, Gx3 and Bx3
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
V1.5
47
2009-12-04
ST7715
9.7.17 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”
Note 1: pixel data with the 16-bit color depth information
Note 2: The most significant bits are: Rx4, Gx5 and Bx4
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
V1.5
48
2009-12-04
ST7715
9.7.18 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”
Note 1: pixel data with the 18-bit color depth information
Note 2: The most significant bits are: Rx5, Gx5 and Bx5
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
V1.5
49
2009-12-04
ST7715
9.7.19 4-line serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input
9.7.20 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”
Note 1: pixel data with the 12-bit color depth information
Note 2: The most significant bits are: Rx3, Gx3 and Bx3
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
V1.5
50
2009-12-04
ST7715
9.7.21 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”
Note 1: pixel data with the 16-bit color depth information
Note 2: The most significant bits are: Rx4, Gx5 and Bx4
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
V1.5
51
2009-12-04
ST7715
9.7.22 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”
Note 1: pixel data with the 18-bit color depth information
Note 2: The most significant bits are: Rx5, Gx5 and Bx5
Note 3: The least significant bits are: Rx0, Gx0 and Bx0
V1.5
52
2009-12-04
ST7715
9.8 Display Data RAM
9.8.1
Configuration (GM[2:0] = “001”)
The display module has an integrated 132x132x18-bit graphic type static RAM. This 313,632-bit memory allows storing
on-chip a 132xRGBx132 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the
display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory.
Fig. 9.8.1 Display data RAM organization
V1.5
53
2009-12-04
ST7715
9.8.2
Memory to Display Address Mapping
9.8.3
When using 132RGB x 132 resolution (GM[2:0] = “001”, SMX=SMY=SRGB= ‘0’)
1
2
3
4
5
6
7
8
|
|
|
|
|
125
126
127
128
129
130
131
132
G0
B0
R1
G1
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0
131
S6 -------- S391 S392 S393 S394 S395 S396
1
130
RGB
Order
RGB=1
S5
RGB=0
S4
Pixel 132
RGB=1
RA
MY=' 0 ' MY=' 1 '
0
131
R0
1
130
2
129
3
128
4
127
5
126
6
125
7
124
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
124
7
125
6
126
5
127
4
128
3
129
2
130
1
131
0
MX='0'
CA
MX='1'
S3
Pixel 131
--------
RGB=0
S2
RGB=0
S1
RGB=1
Source Out
RGB=0
Gate Out
Pixel 2
RGB=1
Pixel 1
SA
ML=' 0 ' ML=' 1 '
B1 -------- R130 G130 B130 R131 G131 B131
0
131
-------1
130
-------2
129
-------3
128
-------4
127
-------5
126
-------6
125
-------7
124
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-------124
7
-------125
6
-------126
5
-------127
4
-------128
3
-------129
2
-------130
1
-------131
0
130
131
-------1
0
--------
Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
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9.8.4
Normal Display On or Partial Mode On
9.8.5
When using 132RGB x 132 resolution (GM[2:0] = “001”)
In this mode, contents of the frame memory within an area where column pointer is 00h to 83h and page pointer is 00h to
83h is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0)
1). Example for Normal Display On (MX=MY=ML=’0’, SMX=SMY=’0’)
Scan
Order
132 Columns
01h
01
11
21
31
41
51
---- ---- ---- ---- ---- 82h
02 03
0W 0X 0Y
12 13
1W 1X 1Y
22
2X 2Y
32
3X 3Y
42
4X 4Y
5Y
83h
0Z
1Z
2Z
3Z
4Z
5Z
6Z
132 x 132 x18 bit
Fram e RAM
U1
V1
W1
X1
Y1
Z1
V2
W2
X2
Y2 Y3
Z2 Z3
VX
WX
XX
YW YX
ZW ZX
UY
VY
WY
XY
YY
ZY
SZ
UZ
VZ
WZ
XZ
YZ
ZZ
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
81h
82h
83h
1
2
3
|
|
|
|
|
|
|
|
|
|
|
|
130
131
132
00h
00
10
20
30
40
50
60
S0
U0
V0
W0
X0
Y0
Z0
01h
01
11
21
31
41
51
U1
V1
W1
X1
Y1
Z1
---- ---- ---- ---- ---- 82h 83h
02 03
0W 0X 0Y 0Z G1
12 13
1W 1X 1Y 1Z G2
22
2X 2Y 2Z G3
32
3X 3Y 3Z |
42
4X 4Y 4Z |
5Y 5Z |
6Z |
|
|
132RGB x 132
LCD Panel
|
|
SZ |
UY UZ |
V2
VX VY VZ |
W2
WX WY WZ |
X2
XX XY XZ G130
Y2 Y3
YW YX YY YZ G131
Z2 Z3
ZW ZX ZY ZZ G132
Display area =132 lines
132 Lines
00h
00h 00
01h 10
02h 20
| 30
| 40
| 50
| 60
|
|
|
|
| S0
| U0
| V0
| W0
81h X0
82h Y0
83h Z0
132 Columns
2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=7Ch, MX=MV=ML=’0’ ,SMX=SMY=’0’)
Scan
Order
132 Columns
132 Lines
V1.5
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
81h
82h
83h
00h
00
10
20
30
40
50
60
01h
01
11
21
31
41
51
---- ---- ---- ---- ---- 82h
02 03
0W 0X 0Y
12 13
1W 1X 1Y
22
2X 2Y
32
3X 3Y
42
4X 4Y
5Y
132RGB x 132
LCD Panel
S0
U0
V0
W0
X0
Y0
Z0
U1
V1
W1
X1
Y1
Z1
V2
W2
X2
Y2 Y3
Z2 Z3
VX
WX
XX
YW YX
ZW ZX
UY
VY
WY
XY
YY
ZY
83h
0Z G1
1Z G2
2Z G3
3Z
|
4Z
|
5Z
|
6Z
|
|
|
|
|
SZ
|
UZ
|
VZ
|
WZ
|
XZ G130
YZ G131
ZZ G132
132 Columns
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
81h
82h
83h
55
00h
00
10
20
30
40
50
60
01h
01
11
21
31
41
51
---- ---- ---- ---- ---- 82h
02 03
0W 0X 0Y
12 13
1W 1X 1Y
22
2X 2Y
32
3X 3Y
42
4X 4Y
5Y
132RGB x 132
LCD Panel
S0
U0
V0
W0
X0
Y0
Z0
U1
V1
W1
X1
Y1
Z1
V2
W2
X2
Y2 Y3
Z2 Z3
VX
WX
XX
YW YX
ZW ZX
UY
VY
WY
XY
YY
ZY
83h
0Z G1
1Z G2
2Z G3
3Z
|
4Z
|
5Z
|
6Z
|
|
|
|
|
SZ
|
UZ
|
VZ
|
WZ
|
XZ G130
YZ G131
ZZ G132
Non-Displa
y area =4
lines
Display
area
=124
lines
Non-Displa
y area
=4lines
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9.9 Address Counter
The address counter sets the addresses of the display data RAM for writing and reading.
Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit),
according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM.
The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to
Y=131 (83h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that
will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE
designating the end address.
For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h)
and XE=127 (83h), YE=131 (83h).
In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps
around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address
increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next
row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS).
For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET and MADCTL” (see
section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All
combinations of flags are allowed. Section 9.10 show the available combinations of writing to the display RAM. When MX,
MY and MV will be changed the data bust be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as section 9.10 below
Condition
Column Counter
Row Counter
When RAMWR/RAMRD command is accepted
Return to
“Start Column (XS)”
Return to
“Start Row (YS)”
Complete Pixel Read / Write action
Increment by 1
No change
The Column counter value is larger than “End Column (XE)”
Return to
“Start Column (XS)”
Increment by 1
The Column counter value is larger than “End Column (XE)” and the Row
counter value is larger than “End Row (YE)”
Return to
“Start Column (XS)”
Return to
“Start Row (YS)”
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9.10 Memory Data Write/ Read Direction
The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be
written is controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.
Panel
Fig. 9.10.1 Data streaming order
9.10.1 When 132RGBx132 (GM= “001”)
MV
MX
MY
CASET
RASET
0
0
0
Direct to Physical Column Pointer
Direct to Physical Row Pointer
0
0
1
Direct to Physical Column Pointer
Direct to (131-Physical Row Pointer)
0
1
0
Direct to (131-Physical Column Pointer)
Direct to Physical Row Pointer
0
1
1
Direct to (131-Physical Column Pointer)
Direct to (131-Physical Row Pointer)
1
0
0
Direct to Physical Row Pointer
Direct to Physical Column Pointer
1
0
1
Direct to (131-Physical Row Pointer)
Direct to Physical Column Pointer
1
1
0
Direct to Physical Row Pointer
Direct to (131-Physical Column Pointer)
1
1
1
Direct to (131-Physical Row Pointer)
Direct to (131-Physical Column Pointer)
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7
(MY), B6 (MX), B5 (MV). The write order for each pixel unit is
One pixel unit represents 1 column and 1page counter value on the Frame Memory.
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9.10.2 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY)
Normal
MADCTL
Parameter
MV MX
0
0
MY
0
Y-Mirror
0
0
1
X-Mirror
0
1
0
X-Mirror
Y-Mirror
0
1
1
X-Y Exchange
1
0
0
X-Y Exchange
Y-Mirror
1
0
1
X-Y Exchange
X-Mirror
1
1
0
X-Y Exchange
X-Mirror
Y-Mirror
1
1
1
Display Data
Direction
V1.5
Image in the Host
(MPU)
Image in the Driver
(DDRAM)
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9.11 Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled
by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the
Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when
displaying video images.
9.11.1 Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 132
H-sync pulses per field.
thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
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9.11.2 Tearing Effect Line Timings
The Tearing Effect signal is described below:
Table 9.11.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25°C)
Symbol
Parameter
min
max
unit
tvdl
Vertical Timing Low Duration
13
-
ms
tvdh
Vertical Timing High Duration
1000
-
µs
thdl
Horizontal Timing Low Duration
33
-
µs
thdh
Horizontal Timing Low Duration
25
500
µs
description
NOTE: The timings in Table 9.11.1 apply when MADCTL ML=0 and ML=1
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:
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9.11.3 Example 1: MPU Write is faster than panel read
MCU to memory
1st
132nd
time
TE output signal
time
Memory to LCD
1st
132nd
time
Image on LCD
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of
the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame
refresh has a complete new image:
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9.11.4 Example 2: MPU write is slower than panel read
MCU to memory
1st
132nd
time
TE output signal
time
Memory to LCD
1st
time
132nd
Image on LCD
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the
Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing
download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position.
B
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9.12 Power ON/OFF Sequence
VDDI and VDD can be applied in any order.
VDDI and VDD can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX
has been released.
During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has
been released.
CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.
Note 1: There will be no damage to the display module if the power sequences are not met.
Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out
command. Also between receiving Sleep In command and Power Off Sequence.
Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to
apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not
guaranteed.
The power on/off sequence is illustrated below
TrPW ≧ 0ns
TfPW ≧ 0ns
VDD
VDDI
Timing when the latter signal rises up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross point of
90% of 2.75V, not 90% of 2.6V.
Timing when the latter signal falls up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross point of
90% of 2.75V, not 90% of 2.6V.
TfPW-CSX = +/- no limit
TrPW-CSX = +/- no limit
CSX
H or L
TrPW-RESX = + no limit
RESX
(Power down in
sleep-out mode)
TfPW-RESX1 = min 120ms
30%
TrPW-RESX = + no limit
RESX
(Power down in
sleep-in mode)
TfPW-RESX2 = min 0ms
30%
TfPW-RESx1 is applied to RESX falling in the Sleep Out Mode.
TfPW-RESx2 is applied to RESX falling in the Sleep In Mode.
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9.12.1 Uncontrolled Power Off
The uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. It will
neither damage the module or the host interface.
If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the display (blank
display) and remains blank until “Power On Sequence” powers it up.
9.13 Power Level Definition
9.13.1 Power Level
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption
1. Normal Mode On (full display), Idle Mode Off, Sleep Out.
In this mode, the display is able to show maximum 262,144 colors.
2. Partial Mode On, Idle Mode Off, Sleep Out.
In this mode part of the display is used with maximum 262,144 colors.
3. Normal Mode On (full display), Idle Mode On, Sleep Out.
In this mode, the full display area is used but with 8 colors.
4. Partial Mode On, Idle Mode On, Sleep Out.
In this mode, part of the display is used but with 8 colors.
5. Sleep In Mode
In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and
memory works with VDDI power supply. Contents of the memory are safe.
6. Power Off Mode
In this mode, both VDD and VDDI are removed.
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.
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9.13.2 Power Flow Chart
Normal display mode on = NOR ON
Partial display mode on = PTL ON
Idle mode off = IDM OFF
Idle mode on = IDM ON
Sleep out = SLP OUT
Sleep in = SLP IN
NOR ON
PTL ON
Sleep out
Normal display mode on
Idle mode off
IDM ON
Power on sequence
HW reset
SW reset
SLP IN
SLP OUT
Sleep in
Normal display mode on
Idle mode off
Sleep out
Normal display mode on
Idle mode on
Sleep out
Partial display mode on
Idle mode off
PTL ON
NOR ON
V1.5
PTL ON
IDM OFF
IDM ON
IDM ON
NOR ON
SLP IN
SLP OUT
SLP IN
SLP OUT
IDM OFF
Sleep out
Partial display mode on
Idle mode on
Sleep in
Normal display mode on
Idle mode on
Sleep in
Partial display mode on
Idle mode off
IDM ON
SLP IN
SLP OUT
65
IDM OFF
IDM OFF
Sleep in
Partial display mode on
Idle mode on
PTL ON
NOR ON
2009-12-04
ST7715
9.14 Reset Table
9.14.1 Reset Table (GM[2:0]= “001”, 132RGB x 132)
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
After Power On
Random
In
Off
Normal
Off
Off
0000h
After H/W Reset
No Change
In
Off
Normal
Off
Off
0000h
Column: End Address (XE)
0083h
0083h
Row: Start Address (YS)
0000h
0000h
Row: End Address (YE)
0083h
0083h
Gamma setting
RGB for 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Tearing: On/Off
Tearing Effect Mode (*1)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
RDDPM
RDDMADCTL
RDDCOLMOD
RDDIM
RDDSM
ID2
ID3
GC0
See Section 9.17
0000h
0083h
Off
0 (Mode1)
GC0
See Section 9.17
0000h
0083h
Off
0 (Mode1)
After S/W Reset
No Change
In
Off
Normal
Off
Off
0000h
0083h (131d) (when
MV=0)
0083h (131d) (when
MV=1)
0000h
0083h (131d) (when
MV=0)
0083h (131d) (when
MV=1)
GC0
No Change
0000h
0083h
Off
0 (Mode1)
0/0/0/0/0
0/0/0/0/0
No Change
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
NV value
NV value
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
NV value
NV value
No Change
08h
No Change
No Change
00h
00h
NV value
NV value
Note 1: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
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9.15 Module Input/Output Pins
9.15.1 Output or Bi-directional (I/O) Pins
Output or Bi-directional pins
TE
D7 to D0 (Output driver)
Input pins
RESX
CSX
D/CX
WRX
RDX
D7 to D0
During Power
On Process
See 9.15
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
After Power On
Low
High-Z (Inactive)
After Power On
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
After Hardware Reset
Low
High-Z (Inactive)
After Hardware
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
After Software Reset
Low
High-Z (Inactive)
After Software
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
During Power
Off Process
See 9.15
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
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9.16 Reset Timing
Table 9.16.1 Reset timing
Related
Pins
RESX
Symbol
Parameter
tRESW
Reset pulse duration
tREST
Reset cancel
MIN
10
-
Unit
MAX
5
120
us
ms
ms
Notes:
1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from EEPROM (or
similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a
rising edge of RESX.
2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below:
RESX Pulse
Action
Shorter than 5us
Reset Rejected
Longer than 9us
Reset
Between 5us and 9us
Reset starts
3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum
time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In -mode.) and then
return to Default condition for Hardware Reset.
4. Spike Rejection also applies during a valid reset pulse as shown below:
5. When Reset applied during Sleep In Mode.
6. When Reset applied during Sleep Out Mode.
7. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent
for 120msec.
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9.17 Color Depth Conversion Look Up Tables
9.17.1 65536 Color to 262,144 Color
Color
RED
Color
GREEN
V1.5
Look Up Table Output
Frame Memory Data (6-bits)
R005 R004 R003 R002 R001 R000
R015 R014 R013 R012 R011 R010
R025 R024 R023 R022 R021 R020
R035 R034 R033 R032 R031 R030
R045 R044 R043 R042 R041 R040
R055 R054 R053 R052 R051 R050
R065 R064 R063 R062 R061 R060
R075 R074 R073 R072 R071 R070
R085 R084 R083 R082 R081 R080
R095 R094 R093 R092 R091 R090
R105 R104 R103 R102 R101 R100
R115 R114 R113 R112 R111 R110
R125 R124 R123 R122 R121 R120
R135 R134 R133 R132 R131 R130
R145 R144 R143 R142 R141 R140
R155 R154 R153 R152 R151 R150
R165 R164 R163 R162 R161 R160
R175 R174 R173 R172 R171 R170
R185 R184 R183 R182 R181 R180
R195 R194 R193 R192 R191 R190
R205 R204 R203 R202 R201 R200
R215 R214 R213 R212 R211 R210
R225 R224 R223 R222 R221 R220
R235 R234 R233 R232 R231 R230
R245 R244 R243 R242 R241 R240
R255 R254 R253 R252 R251 R250
R265 R264 R263 R262 R261 R260
R275 R274 R273 R272 R271 R270
R285 R284 R283 R282 R281 R280
R295 R294 R293 R292 R291 R290
R305 R304 R303 R302 R301 R300
R315 R314 R313 R312 R311 R310
Look Up Table Output
Frame Memory Data (6-bits)
G005 G004 G003 G002 G001 G000
G015 G014 G013 G012 G011 G010
G025 G024 G023 G022 G021 G020
G035 G034 G033 G032 G031 G030
G045 G044 G043 G042 G041 G040
G055 G054 G053 G052 G051 G050
G065 G064 G063 G062 G061 G060
G075 G074 G073 G072 G071 G070
G085 G084 G083 G082 G081 G080
G095 G094 G093 G092 G091 G090
G105 G104 G103 G102 G101 G100
G115 G114 G113 G112 G111 G110
G125 G124 G123 G122 G121 G120
G135 G134 G133 G132 G131 G130
G145 G144 G143 G142 G141 G140
G155 G154 G153 G152 G151 G150
G165 G164 G163 G162 G161 G160
G175 G174 G173 G172 G171 G170
G185 G184 G183 G182 G181 G180
G195 G194 G193 G192 G191 G190
G205 G204 G203 G202 G201 G200
Default value
after H/W Reset
000000
000010
000100
000110
001000
001010
001100
001110
010000
010010
010100
010110
011000
011010
011100
011110
100001
100011
100101
100111
101001
101011
101101
101111
110001
110011
110101
110111
111001
111011
111101
111111
Default value
after H/W Reset
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
69
RGBSET
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RGBSET
Parameter
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Look Up Table Input Data
65k Color (5-bits)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Look Up Table Input Data
65k Color (5-bits)
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
2009-12-04
ST7715
G215 G214 G213 G212 G211 G210
G225 G224 G223 G222 G221 G220
G235 G234 G233 G232 G231 G230
G245 G244 G243 G242 G241 G240
G255 G254 G253 G252 G251 G250
G265 G264 G263 G262 G261 G260
G275 G 274 G273 G272 G271 G270
G285 G 284 G283 G282 G281 G280
G295 G 294 G293 G292 G291 G290
G305 G 304 G303 G302 G301 G300
G315 G 314 G313 G312 G311 G310
G325 G324 G323 G322 G321 G320
G335 G334 G333 G332 G331 G330
G345 G344 G343 G342 G341 G340
G355 G354 G353 G352 G351 G350
G365 G364 G363 G362 G361 G360
G375 G374 G373 G372 G371 G370
G385 G384 G383 G382 G381 G380
G395 G394 G393 G392 G391 G390
G405 G404 G403 G402 G401 G400
G415 G414 G413 G412 G411 G410
G425 G424 G423 G422 G421 G420
G435 G434 G433 G432 G431 G430
G445 G444 G443 G442 G441 G440
G455 G454 G453 G452 G451 G450
G465 G464 G463 G462 G461 G460
G475 G474 G473 G472 G471 G470
G485 G484 G483 G482 G481 G480
G495 G494 G493 G492 G491 G490
G505 G504 G503 G502 G501 G500
G515 G514 G513 G512 G511 G510
G525 G524 G523 G522 G521 G520
G535 G534 G533 G532 G531 G530
G545 G544 G543 G542 G541 G540
G555 G554 G553 G552 G551 G550
G565 G564 G563 G562 G561 G560
G575 G574 G573 G572 G571 G570
G585 G584 G583 G582 G581 G580
G595 G594 G593 G592 G591 G590
G605 G604 G603 G602 G601 G600
G615 G614 G613 G612 G611 G610
G625 G624 G623 G622 G621 G620
G635 G634 G633 G632 G631 G630
Color
BLUE
V1.5
Look Up Table Output
Frame Memory Data (6-bits)
B005 B004 B003 B002 B001 B000
B015 B014 B013 B012 B011 B010
B025 B024 B023 B022 B021 B020
B035 B034 B033 B032 B031 B030
B045 B044 B043 B042 B041 B040
B055 B054 B053 B052 B051 B050
B065 B064 B063 B062 B061 B060
B075 B074 B073 B072 B071 B070
B085 B084 B083 B082 B081 B080
B095 B094 B093 B092 B091 B090
B105 B104 B103 B102 B101 B100
B115 B114 B113 B112 B111 B110
B125 B124 B123 B122 B121 B120
B135 B134 B133 B132 B131 B130
B145 B144 B143 B142 B141 B140
B155 B154 B153 B152 B151 B150
B165 B164 B163 B162 B161 B160
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Default value
after H/W Reset
000000
000010
000100
000110
001000
001010
001100
001110
010000
010010
010100
010110
011000
011010
011100
011110
100001
70
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
RGBSET
Parameter
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Look Up Table Input Data
65k Color (5-bits)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
2009-12-04
ST7715
B175 B174 B173 B172 B171 B170
B185 B184 B183 B182 B181 B180
B195 B194 B193 B192 B191 B190
B205 B204 B203 B202 B201 B200
B215 B214 B213 B212 B211 B210
B225 B224 B223 B222 B221 B220
B235 B234 B233 B232 B231 B230
B245 B244 B243 B242 B241 B240
B255 B254 B253 B252 B251 B250
B265 B264 B263 B262 B261 B260
B275 B274 B273 B272 B271 B270
B285 B284 B283 B282 B281 B280
B295 B294 B293 B292 B291 B290
B305 B304 B303 B302 B301 B300
B315 B314 B313 B312 B311 B310
V1.5
100011
100101
100111
101001
101011
101101
101111
110001
110011
110101
110111
111001
111011
111101
111111
71
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
2009-12-04
ST7715
9.17.2 4096 Color to 262,144 Color
Color
RED
GREEN
BLUE
V1.5
Look Up Table Output
Frame Memory Data (6-bits)
R005 R004 R003 R002 R001 R000
R015 R014 R013 R012 R011 R010
R025 R024 R023 R022 R021 R020
R035 R034 R033 R032 R031 R030
R045 R044 R043 R042 R041 R040
R055 R054 R053 R052 R051 R050
R065 R064 R063 R062 R061 R060
R075 R074 R073 R072 R071 R070
R085 R084 R083 R082 R081 R080
R095 R094 R093 R092 R091 R090
R105 R104 R103 R102 R101 R100
R115 R114 R113 R112 R111 R110
R125 R124 R123 R122 R121 R120
R135 R134 R133 R132 R131 R130
R145 R144 R143 R142 R141 R140
R155 R154 R153 R152 R151 R150
R165 R164 R163 R162 R161 R160
|
R315 R314 R313 R312 R311 R310
G005 G004 G003 G002 G001 G000
G015 G014 G013 G012 G011 G010
G025 G024 G023 G022 G021 G020
G035 G034 G033 G032 G031 G030
G045 G044 G043 G042 G041 G040
G055 G054 G053 G052 G051 G050
G065 G064 G063 G062 G061 G060
G075 G074 G073 G072 G071 G070
G085 G084 G083 G082 G081 G080
G095 G094 G093 G092 G091 G090
G105 G104 G103 G102 G101 G100
G115 G114 G113 G112 G111 G110
G125 G124 G123 G122 G121 G120
G135 G134 G133 G132 G131 G130
G145 G144 G143 G142 G141 G140
G155 G154 G153 G152 G151 G150
G165 G164 G163 G162 G161 G160
|
G635 G634 G633 G632 G631 G630
B005 B004 B003 B002 B001 B000
B015 B014 B013 B012 B011 B010
B025 B024 B023 B022 B021 B020
B035 B034 B033 B032 B031 B030
B045 B044 B043 B042 B041 B040
B055 B054 B053 B052 B051 B050
B065 B064 B063 B062 B061 B060
B075 B074 B073 B072 B071 B070
B085 B084 B083 B082 B081 B080
B095 B094 B093 B092 B091 B090
B105 B104 B103 B102 B101 B100
B115 B114 B113 B112 B111 B110
B125 B124 B123 B122 B121 B120
B135 B134 B133 B132 B131 B130
B145 B144 B143 B142 B141 B140
B155 B154 B153 B152 B151 B150
B165 B164 B163 B162 B161 B160
|
B315 B314 B313 B312 B311 B310
Default value
after H/W Reset
000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
-----|
-----000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
-----|
-----000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
-----|
------
72
RGBSET
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
|
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
|
128
Look Up Table Input Data
4k Color (4-bits)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not used
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not used
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not used
2009-12-04
ST7715
10 Command
10.1 System function Command List and Description
Table 10.1.1 System Function command List (1)
Instruction Refer D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Function
10.1.1
0
↑
1
-
0
0
0
0
0
0
0
0
(00h)
No Operation
SWRESET 10.1.2
0
↑
1
-
0
0
0
0
0
0
0
1
(01h)
Software reset
0
↑
1
-
0
0
0
0
0
1
0
0
(04h)
Read Display ID
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID1 read
1
1
↑
-
1
ID26
ID25
ID24
ID23
ID22
ID21
ID20
ID2 read
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
0
↑
1
-
0
0
0
0
1
0
0
1
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
BSTON
MY
MX
MV
ML
RGB
0
ST24
-
1
1
↑
-
1
1
↑
-
1
1
↑
-
NOP
RDDID 10.1.3
RDDST 10.1.4
RDDPM 10.1.5
RDD
10.1.6
MADCTL
RDD
10.1.7
COLMOD
RDDIM 10.1.8
RDDSM 10.1.9
ST23 IFPF2 IFPF1
IFPF0 IDMON PTLON SLOUT NORON
VSSON ST14 INVON ST12
GCS1 GCS0 TELON
ID3 read
(09h)
ST4
-
ST11 DISON TEON GCS2
ST3
0
↑
1
-
1
1
↑
-
1
1
↑
-
0
↑
1
-
0
0
0
0
1
1
1
↑
-
-
-
-
-
-
1
1
↑
-
MY
MX
MV
ML
RGB
ST2
ST1
Read Display Status
-
ST0
Read Display Power
(0Ah)
Mode
0
0
0
0
1
0
1
0
-
-
-
-
-
-
-
-
Dummy read
-
-
-
0
1
1
-
-
-
0
-
-
Read Display Pixel
Format
BSTON IDMON PTLON SLPOUT NORON DISON
0
↑
1
-
0
0
0
0
1
1
0
0
1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
0
0
0
0
-
0
↑
1
-
1
1
↑
-
-
-
-
-
-
1
1
↑
-
VSSON
D6
INVON
-
-
0
0
0
0
1
IFPF2 IFPF1 IFPF0
1
0
1
-
-
-
GCS2 GCS1 GCS0
(0Bh) Read Display MADCTL
Dummy read
(0Ch)
Dummy read
Read Display Image
(0Dh)
Mode
Dummy read
Read Display Signal
(0Eh)
Mode
0
↑
1
-
0
0
0
0
1
1
1
0
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
-
-
-
-
-
-
-
TEON TELON
“-“: Don’t care
V1.5
73
2009-12-04
ST7715
Table 10.1.2 System Function command List (2)
Instruction
Refer
D/C
X
WR
D17RDX
X
8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Function
SLPIN
10.1.10
0
↑
1
-
0
0
0
1
0
0
0
0
(10h)
Sleep in & booster off
SLPOUT
10.1.11
0
↑
1
-
0
0
0
1
0
0
0
1
(11h)
Sleep out & booster on
PTLON
10.1.12
0
↑
1
-
0
0
0
1
0
0
1
0
(12h)
Partial mode on
NORON
10.1.13
0
↑
1
-
0
0
0
1
0
0
1
1
(13h)
Partial off (Normal)
INVOFF
10.1.14
0
↑
1
-
0
0
1
0
0
0
0
0
(20h)
Display inversion off
(normal)
INVON
10.1.15
0
↑
1
-
0
0
1
0
0
0
0
1
(21h)
Display inversion on
0
↑
1
-
0
0
1
0
0
1
1
0
(26h)
Gamma curve select
1
↑
1
-
-
-
-
-
DISPOFF 10.1.17
0
↑
1
-
0
0
1
0
1
0
0
0
(28h)
DISPON
0
↑
1
-
0
0
1
0
1
0
0
1
(29h)
Display on
0
↑
1
-
0
0
1
0
1
0
1
0
(2Ah)
Column address set
1
↑
1
-
-
-
-
-
-
-
-
-
1
↑
1
-
XS7
XS
XS5
XS4
XS3
XS2
XS1
XS0
1
↑
1
-
-
-
-
-
-
-
-
-
1
↑
1
-
XE7
XE6
XE5
XE4
XE3
XE2
XE1
XE0
0
↑
1
-
0
0
1
0
1
0
1
1
1
↑
1
-
-
-
-
-
-
-
-
-
1
↑
1
-
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
1
↑
1
-
-
-
-
-
-
-
-
-
GAMSET 10.1.16
CASET
RASET
10.1.18
10.1.19
GC3 GC2 GC1 GC0
Display off
X address start: 0≦S≦X
X address end: XS≦XE≦
X
(2Bh)
Row address set
Y address start: 0≦YS≦Y
10.1.20
Y address end:S≦YE≦Y
RAMWR
RAMRD
10.1.21
10.1.22
1
↑
1
-
0
↑
1
-
0
0
1
0
1
1
0
0
1
↑
1
-
D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
-
0
0
1
0
1
1
1
0
1
1
↑
-
-
-
-
-
-
-
-
-
Dummy read
1
1
↑
-
D7
D6
D5
D4
D3
D2
D1
D0
Read data
YE7
YE6
YE5
YE4
YE3
YE2
YE1
YE0
(2Ch)
Memory write
(2Eh)
Memory read
Write data
“-“: Don’t care
V1.5
74
2009-12-04
ST7715
Table 10.1.3 System Function command List (3)
Instruction Refer D/CX WRXRDX D17-8 D7
D6
D5
D4
D3
D2
D1
D0
Hex
Function
(30h)
Partial start/end address set
0
↑
1
-
0
0
1
1
0
0
0
0
1
↑
1
-
-
-
-
-
-
-
-
-
PTLAR 10.1.23 1
↑
1
-
1
↑
1
-
1
↑
1
-
TEOFF 10.1.24 0
↑
1
-
0
0
1
1
0
1
0
0
(34h)
0
↑
1
-
0
0
1
1
0
1
0
1
(35h) Tearing effect mode set & on
1
↑
1
-
-
-
-
-
-
-
-
TELOM
0
↑
1
-
0
0
1
1
0
1
1
0
1
↑
1
-
MY
MX
MV
0
-
-
IDMOFF 10.1.27 0
↑
1
-
0
0
1
1
1
0
0
0
(38h)
IDMON 10.1.28 0
↑
1
-
0
0
1
1
1
0
0
1
(39h)
Idle mode on
0
↑
1
-
0
0
1
1
1
0
1
0
(3Ah)
Interface pixel format
1
↑
1
-
-
-
-
-
-
0
↑
1
-
1
1
0
1
1
0
1
0
RDID1 10.1.30 1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
0
↑
1
-
1
1
0
1
1
0
1
1
RDID2 10.1.31 1
1
↑
-
-
-
-
-
-
-
-
-
1
1
↑
-
1
0
↑
1
-
1
1
0
1
1
1
0
RDID3 10.1.32 1
1
↑
-
-
-
-
-
-
-
-
1
1
↑
-
TEON 10.1.25
MADCTL 10.1.26
COLMOD 10.1.29
Partial start address (0,1,2, ..P)
PSL7PSL6 PSL5 PSL4PSL3 PSL2 PSL1 PSL0
-
-
-
-
-
-
-
-
Partial end address (0,1,2, .., P)
PEL7PEL6 PEL5 PEL4PEL3 PEL2 PEL1 PEL0
ML RGB
Mode1: TELOM=”0”
Mode2: TELOM=”1”
(36h)
ID26 ID25 ID24 ID23 ID22 ID21
ID37 ID36 ID35 ID34 ID33 ID32 ID31
Idle mode off
Interface format
(DAh)
Read ID1
Dummy read
ID10
Read parameter
(DBh)
Read ID2
Dummy read
ID20
0
Memory data access control
-
IFPF2IFPF1 IFPF0
ID17 ID16 ID15 ID14 ID13 ID12 ID11
Tearing effect line off
Read parameter
(DCh)
Read ID3
-
Dummy read
ID30
Read parameter
“-“: Don’t care
Note 1: After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer
“RESET TABLE” section)
Note 2: Undefined commands are treated as NOP (00 h) command.
Note 3: B0 to D9 and DA to F are for factory use of driver supplier.
Note 4: Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 36h (ML parameter only), 38h and 39h are updated during V-sync when
Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately.
Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch), Read
Display Image Mode (0Dh), Read Display Signal Mode (0Eh) and Read Display Self Diagnostic Result (0Fh) of these commands
are updated immediately both in Sleep In mode and Sleep Out mode.
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10.1.1 NOP (00h)
00H
NOP (No Operation)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NOP
0
↑
1
-
0
0
0
0
0
0
0
0
(00h)
Parameter
No Parameter
Description
This command is empty command.
-
“-“ Don’t care
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10.1.2 SWRESET (01h): Software Reset
01H
SWRESET (Software Reset)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SWRESET
0
↑
1
-
0
0
0
0
0
0
0
1
(01h)
Parameter
No Parameter
-
“-“ Don’t care
-If Software Reset is applied during Sleep In mode, it will be necessary to wait 120msec before sending next
command.
Description -The display module loads all default values to the registers during 120msec.
-If Software Reset is applied during Sleep Out or Display On Mode, it will be necessary to wait 120msec before sending
next command.
Legend
SWRESET
Command
Parameter
Display whole
blank screen
Display
Flow Chart
Set
Commands
to S/W
Default
Value
Action
Sleep In Mode
Mode
Sequential
transter
V1.5
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10.1.3 RDDID (04h): Read Display ID
04H
RDDID (Read Display ID)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDID
0
↑
1
-
0
0
0
0
0
1
0
0
(04h)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
3rd parameter
1
1
↑
-
1
ID26
ID25
ID24
ID23
ID22
ID21
ID20
4th parameter
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
-This read byte returns 24-bit display identification information.
-The 1st parameter is dummy data
-The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID.
-The 3rd parameter (ID26 to ID20): LCD module/driver version ID
Description
-The 4th parameter (ID37 to UD30): LCD module/driver ID.
- Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h,
respectively.
“-“ Don’t care
Default Value
Status
Default
Power On Sequence
ID1
ID2
ID3
-
8xh
00h
S/W Reset
-
8xh
00h
H/W Reset
-
8xh
00h
Flow Chart
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10.1.4 RDDST (09h): Read Display Status
09H
RDDST (Read Display Status)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDST
0
↑
1
-
0
0
0
0
1
0
0
1
(09h)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
BSTON
MY
MX
MV
ML
RGB
0
ST24
3rd parameter
1
1
↑
-
ST23
IFPF2
IFPF1
IFPF0
4th parameter
1
1
↑
-
VSSON
ST14
INVON
ST12
ST11
DISON
TEON
GCS2
1
1
↑
-
GCS1
GCS0
TELOM
ST4
ST3
ST2
ST1
ST0
th
5 parameter
IDMON PTLON SLOUT NORON
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
BSTON
Booster Voltage Status
‘1’ =Booster on,
‘0’ =Booster off
MY
Row Address Order (MY)
‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)
‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’)
MX
Column Address Order (MX)
‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)
‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’1’)
MV
Row/Column Exchange (MV)
‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)
‘0’ = Normal, (when MADCTL (36h) D5=’0’)
ML
Scan Address Order (ML)
‘1’=Increment,
(LCD refresh Bottom to Top, when MADCTL (36h) D4=’1’)
‘0’ =Decrement,
(LCD refresh Top to Bottom, when MADCTL (36h) D4=’0’)
RGB
RGB/ BGR Order (RGB)
‘1’ =BGR, (When MADCTL (36h) D3=’1’)
‘0’ =RGB, (When MADCTL (36h) D3=’0’)
Description
ST24
For Future Use
‘0’
ST23
For Future Use
‘0’
IFPF2
“011” = 12-bit / pixel,
Interface Color Pixel Format
“101” = 16-bit / pixel,
IFPF1
Definition
“110” = 18-bit / pixel, others are no define
IFPF0
IDMON
Idle Mode On/Off
‘1’ = On, “0” = Off
PTLON
Partial Mode On/Off
‘1’ = On, “0” = Off
SLPOUT
Sleep In/Out
‘1’ = Out, “0” = In
NORON
‘1’ = Normal Display,
Display Normal Mode On/Off
‘0’ = Partial Display
V1.5
VSSON
Reversed
“0”
ST14
Reversed
‘0’
INVON
Inversion Status
‘1’ = On, “0” = Off
ST12
All Pixels On (Not Used)
‘0’
ST11
All Pixels Off (Not Used)
‘0’
DISON
Display On/Off
‘1’ = On, “0” = Off
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TEON
Tearing effect line on/off
‘1’ = On, “0” = Off
GCSEL2
“000” = GC0
GCSEL1
“001” = GC1
Gamma Curve Selection
“010” = GC2
“011” = GC3
GCSEL0
”100” to “111” = Not defined
TELOM
Tearing effect line mode
‘0’ = mode1, ‘1’ = mode2
ST4
For Future Use
‘0’
ST3
For Future Use
‘0’
ST2
For Future Use
‘0’
ST1
For Future Use
‘0’
ST0
For Future Use
‘0’
“-“ Don’t care
Status
Default
V1.5
Default Value (ST31 to ST0)
ST[31-24]
ST[23-16]
ST[15-8]
ST[7-0]
Power On Sequence
0000-0000
0110-0001
0000-0000
0000-0000
S/W Reset
0xxx0xx00
0xxx-0001
0000-0000
0000-0000
H/W Reset
0000-0000
0110-0001
0000-0000
0000-0000
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Serial I/F Mode
RDDST 09h
Parallel I/F Mode
RDDST 09h
Legend
Command
Dummy
Clock
Dummy
Read
Send 2nd
parameter
Send 2nd
parameter
Parameter
Display
Flow Chart
Action
Send 3rd
parameter
Send 3rd
parameter
Mode
V1.5
Send 4th
parameter
Send 4th
parameter
Send 5th
parameter
Sendth
parameter
81
Sequential
transter
2009-12-04
ST7715
10.1.5 RDDPM (0Ah): Read Display Power Mode
0AH
RDDPM (Read Display Power Mode)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDPM
0
↑
1
-
0
0
0
0
1
0
1
0
(0Ah)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
D1
D0
BSTON IDMON PTLON SLPOUT NORON DISON
This command indicates the current status of the display as described in the table below:
“-“ Don’t care
Bit
Description
BSTON
Booster Voltage Status
Value
‘1’ =Booster on,
‘0’ =Booster off
‘1’ = Idle Mode On,
IDMON
Idle Mode On/Off
‘0’ = Idle Mode Off
‘1’ = Partial Mode On,
PTLON
Partial Mode On/Off
‘0’ = Partial Mode Off
Description
‘1’ = Sleep Out,
SLPON
Sleep In/Out
‘0’ = Sleep In
‘1’ = Normal Display,
NORON
Display Normal ModemOn/Off
‘0’ = Partial Display
‘1’ = Display On,
DISON
Display On/Off
‘0’ = Display Off
D1
Not Used
‘0’
D0
Not Used
‘0’
Status
Default Value (D7 to D0)
Power On Sequence
0000_1000(08h)
S/W Reset
0000_1000(08h)
H/W Reset
0000_1000(08h)
Default
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Legend
Serial I/F Mode
Parallel I/F Mode
Command
RDDPM 0Ah
RDDPM 0Ah
Parameter
Send 2nd
parameter
Dummy
Read
Display
Flow Chart
Action
Send 2nd
parameter
Mode
Sequential
transter
V1.5
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ST7715
10.1.6 RDDMADCTL (0Bh): Read Display MADCTL
0BH
RDDMADCTL (Read Display MADCTL)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDMADCTL
0
↑
1
-
0
0
0
0
1
0
1
1
(0Bh)
1st parameter
1
1
↑
-
-
2nd parameter
1
1
↑
-
-
-
-
-
-
-
-
MY
MX
MV
ML
RGB
0
D1
D0
This command indicates the current status of the display as described in the table below:
“-“ Don’t care
Bit
Description
MX
Column Address Order
Value
‘1’ = Right to Left (When MADCTL B6=’1’)
‘0’ = Left to Right (When MADCTL B6=’0’)
‘1’ = Bottom to Top (When MADCTL B7=’1’)
MY
Row Address Order
‘0’ = Top to Bottom (When MADCTL B7=’0’)
Description
‘1’ = Row/column exchange (MV=1)
MV
Row/Column Order (MV)
‘0’ = Normal (MV=0)
‘1’ =LCD Refresh Bottom to Top
ML
Vertical Refresh Order
‘0’ =LCD Refresh Top to Bottom
RGB
RGB/BGR Order
‘1’ =BGR, “0”=RGB
D1
Not Used
‘0’
D0
Not Used
‘0’
Status
Default Value (D7 to D0)
Power On Sequence
0000_0000 (00h)
S/W Reset
No change
H/W Reset
0000_0000 (00h)
Default
Flow Chart
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10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format
0CH
RDDCOLMOD (Read Display Pixel Format)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDCOLMOD
0
↑
1
-
0
0
0
0
1
1
0
0
(0Ch)
-
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
0
0
0
0
-
IFPF2
IFPF1
IFPF0
This command indicates the current status of the display as described in the table below:
IFPF[2:0]
MCU Interface Color Format
011
12-bit/pixel
101
16-bit/pixel
110
18-bit/pixel
111
No used
Description
Others are no define and invalid
“-“ Don’t care
Status
Default Value
IFPF[2:0]
Default
Power On Sequence
0110 (18 bits/pixel)
S/W Reset
No Change
H/W Reset
0110 (18 bits/pixel)
Flow Chart
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10.1.8 RDDIM (0Dh): Read Display Image Mode
0DH
RDDIM (0Dh): Read Display Image Mode
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDIM
0
↑
1
-
0
0
0
0
1
1
0
1
(0Dh)
-
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
VSSON
D6
INVON
D4
D3
GCS2
GCS1
GCS0
This command indicates the current status of the display as described in the table below:
“-“ Don’t care
Bit
Description
VSSON
Reversed
D6
Reversed
INVON
Inversion On/Off
Value
“0”
“0”
“1” = Inversion is On,
“0” = Inversion is Off
Description
D4
All Pixels On
“0” (Not used)
D3
All Pixels Off
“0” (Not used)
“000” = GC0,
GCS2
“001” = GC1,
GCS1
Gamma Curve Selection
“010” = GC2,
GCS0
“011” = GC3, ”100” to “111” = Not defined
Status
Default Value(D7 to D0)
Power On Sequence
0000_0000 (00h)
S/W Reset
0000_0000 (00h)
H/W Reset
0000_0000 (00h)
Default
Flow Chart
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10.1.9 RDDSM (0Eh): Read Display Signal Mode
0EH
RDDSM (0Eh): Read Display Signal Mode
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDDSM
0
↑
1
-
0
0
0
0
1
1
1
0
(0Eh)
-
-
-
1st parameter
1
1
↑
-
2nd parameter
1
1
↑
-
TEON TELOM
-
-
-
-
-
-
D5
D4
D3
D2
D1
D0
This command indicates the current status of the display as described in the table below:
“-“ Don’t care
Bit
Description
Value
TEON
Tearing Effect Line On/Off
“1” = On,
“0” = Off
TELOM
Tearing effect line mode
“1” = mode2,
“0” = mode1
D5
Not Used
“1” = On,
“0” = Off
Description
D4
Not Used
“1” = On,
“0” = Off
D3
Not Used
“1” = On,
“0” = Off
D2
Not Used
“1” = On,
“0” = Off
D1
Not Used
“1” = On,
“0” = Off
D0
Not Used
“1” = On,
“0” = Off
Status
Default Value(D7~D0)
Power On Sequence
0000_0000 (00h)
S/W Reset
0000_0000 (00h)
H/W Reset
0000_0000 (00h)
Default
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Serial I/F Mode
Parallel I/F Mode
Read RDDSM
Command
Read RDDSM
Host
Display
Send 2nd
parameter
Legend
Parameter
Dummy
Read
Display
Flow Chart
Send 2nd
parameter
Action
Mode
Sequential
transter
V1.5
88
2009-12-04
ST7715
10.1.10 SLPIN (10h): Sleep In
10H
SLPIN (Sleep In)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SLPIN
0
↑
1
-
0
0
0
1
0
0
0
0
(10h)
Parameter
No Parameter
-
-This command causes the LCD module to enter the minimum power consumption mode.
Description
-In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
-This command has no effect when module is already in Sleep In mode. Sleep In Mode can only be exit by the Sleep Out
Command (11h).
Restriction
-When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command because of
the stabilization timing for the supply voltages and clock circuits.
Status
Default Value
Power On Sequence
Sleep in mode
S/W Reset
Sleep in mode
H/W Reset
Sleep in mode
Default
Legend
Stop
DC-DC
Converte
r
SLPIN
Command
Parameter
Display whole blank
screen (Automatic
No effect to DISP
ON/OFF
Commands)
Stop
Internal
Oscillator
Display
Flow Chart
Sleep In Mode
Drain
Charge
From LCD
Panel
Action
Mode
Sequential
transter
V1.5
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ST7715
10.1.11 SLPOUT (11h): Sleep Out
11H
SLPOUT (Sleep Out)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
SLPOUT
0
↑
1
-
0
0
0
1
0
0
0
1
(11h)
Parameter
No Parameter
-
-This command turns off sleep mode.
Description
-In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
-This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In
Command (10h).
-When IC is in Sleep In mode, it is necessary to wait 120msec before sending next command because of the stabilization
Restriction
timing for the supply voltages and clock circuits.
-When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command due to the
download of default value of registers and the execution of self-diagnostic function.
Status
Default Value
Power On Sequence
Sleep in mode
S/W Reset
Sleep in mode
H/W Reset
Sleep in mode
Default
Legend
Command
SLPOUT
Display whole blank
screen for 2 firames
(Automatic No effect
to DISP ON/OFF
Commands)
Start
Internal
Oscillator
Parameter
Display
Flow Chart
Start up
DC:DC
Converter
Display Memory
contents In
accordance with
the current
command table
settings
Charge
Offset
voltage for
LCD
Panel
Action
Mode
Sleep Out mode
Sequential
transter
V1.5
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2009-12-04
ST7715
10.1.12 PTLON (12h): Partial Display Mode On
12H
PTLON (12h): Partial Display Mode On
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PTLON
0
↑
1
-
0
0
0
1
0
0
1
0
(12h)
Parameter
No Parameter
-
-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h)
Description
-To leave Partial mode, the Normal Display Mode On command (13h) should be written.
“-“ Don’t care
Default
Flow Chart
V1.5
Status
Default Value
Power On Sequence
Normal Mode On
S/W Reset
Normal Mode On
H/W Reset
Normal Mode On
See Partial Area (30h)
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10.1.13 NORON (13h): Normal Display Mode On
13H
NORON (Normal Display Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NORON
0
↑
1
-
0
0
0
1
0
0
1
1
(13h)
Parameter
No Parameter
-
-This command returns the display to normal mode.
-Normal display mode on means Partial mode off.
Description
-Exit from NORON by the Partial mode On command (12h)
“-“ Don’t care
Default
Flow Chart
V1.5
Status
Default Value
Power On Sequence
Normal Mode On
S/W Reset
Normal Mode On
H/W Reset
Normal Mode On
See Partial Area Definition Descriptions for details of when to use this command
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2009-12-04
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10.1.14 INVOFF (20h): Display Inversion Off
20H
IVNOFF (Normal Display Mode Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
INVOFF
0
↑
1
-
0
0
1
0
0
0
0
0
(20h)
Parameter
No Parameter
-
-This command is used to recover from display inversion mode.
(Example)
“-“ Don’t care
Memory
Description
Display
Top-Left
(0,0)
Status
Default
Default Value
Power On Sequence
Display Inversion off
S/W Reset
Display Inversion off
H/W Reset
Display Inversion off
Legend
Command
Display
Inversion On
Mode
Parameter
Display
Flow Chart
INVOFF (20h)
Action
Display
Inversion OFF
Mode
Mode
Sequential
transter
V1.5
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2009-12-04
ST7715
10.1.15 INVON (21h): Display Inversion On
21H
IVNOFF (Display Inversion On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
INVON
0
↑
1
-
0
0
1
0
0
0
0
1
(21h)
Parameter
No Parameter
-
-This command is used to enter into display inversion mode
-To exit from Display Inversion On, the Display Inversion Off command (20h) should be written.
(Example)
Memory
“-“ Don’t care
Description
Default
Display
Top-Left (0,0)
Status
Default Value
Power On Sequence
Display Inversion off
S/W Reset
Display Inversion off
H/W Reset
Display Inversion off
Legend
Command
Display
Inversion OFF
Mode
Parameter
Display
Flow Chart
INVON (21h)
Action
Display
Inversion ON
Mode
Mode
Sequential
transter
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10.1.16 GAMSET (26h): Gamma Set
26H
GAMSET (Gamma Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
GAMSET
0
↑
1
-
0
0
1
0
0
1
1
0
(26h)
Parameter
1
↑
1
-
-
-
-
-
GC3
GC2
GC1
GC0
-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be
selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table.
GC [7:0]
Description
Parameter
Curve Selected
GS=1
GS=0
01h
GC0
Gamma Curve 1 (G2.2)
Gamma Curve 1 (G1.0)
02h
GC1
Gamma Curve 2 (G1.8)
Gamma Curve 2 (G2.5)
04h
GC2
Gamma Curve 3 (G2.5)
Gamma Curve 3 (G2.2)
08h
GC3
Gamma Curve 4 (G1.0)
Gamma Curve 4 (G1.8)
Note: All other values are undefined.
Default
Status
Default Value
Power On Sequence
01h
S/W Reset
01h
H/W Reset
01h
Flow Chart
V1.5
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2009-12-04
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10.1.17 DISPOFF (28h): Display Off
28H
DISPOFF (Display Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
DISPOFF
0
↑
1
-
0
0
1
0
1
0
0
0
(28h)
Parameter
No Parameter
-
- This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is
disabled and blank page inserted.
- This command makes no change of contents of frame memory.
- This command does not change any other status.
- There will be no abnormal visible effect on the display.
- Exit from this command by Display On (29h)
- The delay time between DISPON and DISPOFF needs 120ms at least.
Description
(Example)
Memory
Display
Note1: Complete 1 frame display (ex: continue 2-falling edges of VS)
Note2: Please use command 28h (display off) combined with command 10h (sleep in) to make module into display
off status. Please check the application note of ST7715 when using display off function.
Status
Default
Default Value
Power On Sequence
Display off
S/W Reset
Display off
H/W Reset
Display off
Legend
Command
Display On
Mode
Parameter
Display
Flow Chart
DISPOFF
Action
Display Off
Mode
Mode
Sequential
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10.1.18 DISPON (29h): Display On
29H
DISPON
DISPON (Display On)
0
↑
1
-
0
Parameter
0
1
0
1
0
0
1
No Parameter
(29h)
-
- This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled.
- This command makes no change of contents of frame memory.
- This command does not change any other status.
- The delay time between DISPON and DISPOFF needs 120ms at least.
Description
Default
(Example)
Memory
Display
Status
Default Value
Power On Sequence
Display off
S/W Reset
Display off
H/W Reset
Display off
Legend
Command
Display Off
Mode
Parameter
Display
Flow Chart
DISPON
Action
Display On
Mode
Mode
Sequential
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10.1.19 CASET (2Ah): Column Address Set
2AH
CASET(Colume Address Set)_
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CASET(2Ah)
0
↑
1
-
0
0
1
0
1
0
1
0
(2Ah)
1st parameter
1
↑
1
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
↑
1
-
XS7
XS6
XS5
XS4
XS3
XS2
XS1
XS0
3rd parameter
1
↑
1
-
-
-
-
-
-
-
-
-
4th parameter
1
↑
1
-
XE7
XE6
XE5
XE4
XE3
XE2
XE1
XE0
-The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes.
-Each value represents one column line in the Frame Memory.
XS[7:0]
XE[7:0]
Description
XS [15:0] always must be equal to or less than XE [15:0]
When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored.
Restriction
1. 132X132 memory base (GM = ’001’)
(Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV=”0”)
(Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV=”1”)
Default
V1.5
Default Value
GM Status
Status
GM=’001’
(132x132
memory base)
Power On
Sequence
0000h
0083h (131)
S/W Reset
0000h
0083h (131)
H/W Reset
0000h
0083h (131)
XS [7:0]
98
XE [7:0] (MV=’0 ’)
XE [7:0] (MV=’1’)
2009-12-04
ST7715
CASET
Legend
1st parameter XS[15:0]
2nd parameter XE[15:0]
Command
Parameter
PASET
Display
Flow Chart
1st parameter YS[15:0]
2nd parameter YE[15:0]
Action
Mode
RAMWR
Sequential
transter
Image Data
D1[7:0],D2[7:0]
… … .Dn[7:0]
Any Command
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10.1.20 RASET (2Bh): Row Address Set
2BH
RASET (Row Address Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RASET (2Bh)
0
↑
1
-
0
0
1
0
1
0
1
1
(2Bh)
1st parameter
1
↑
1
-
-
-
-
-
-
-
-
-
2nd parameter
1
↑
1
-
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
3rd parameter
1
↑
1
-
-
-
-
-
-
-
-
-
4th parameter
1
↑
1
-
YE7
YE6
YE5
YE4
YE3
YE2
YE1
YE0
The value of YS [7:0] and YE [7:0] are referred when RAMWR command comes.
Each value represents one column line in the Frame Memory.
YS[7:0]
Description
YE[7:0]
YS [15:0] always must be equal to or less than YE [15:0]
When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored.
Restriction
1. 132X132 memory base (GM = ’001’)
(Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (0083h)): MV=”0”
(Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (0083h)): MV=”1”
Default
V1.5
Default Value
GM status
Status
GM=’001’
(132x132
memory base)
Power On
Sequence
0000h
0083h (131)
S/W Reset
0000h
0083h (131)
H/W Reset
0000h
0083h (131)
YS [15:0]
100
YE [15:0] (MV=’0 ’)
YE [15:0] (MV=’1’)
2009-12-04
ST7715
CASET
Legend
1st parameter XS[15:0]
2nd parameter XE[15:0]
Command
Parameter
PASET
Flow Chart
Display
1st parameter YS[15:0]
2nd parameter YE[15:0]
Action
Mode
RAMWR
Sequential
transter
Image Data
D1[7:0],D2[7:0]
… … .Dn[7:0]
Any Command
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10.1.21 RAMWR (2Ch): Memory Write
2CH
RAMWR (Memory Write)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RAMWR
0
↑
1
-
0
0
1
0
1
1
0
0
(2Ch)
1st parameter
1
↑
1
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
∣
1
↑
1
∣
∣
∣
∣
∣
∣
∣
∣
∣
Nth parameter
1
↑
1
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
In all color modes, there is no restriction on length of parameters.
1. 132x132 memory base (GM = ‘001’)
Description
132x132x18-bit memory can be written on this command.
Memory range: (0000h, 0000h) -> (0083h, 0083h)
Default
Status
Default Value
Power On Sequence
Contents of memory is set randomly
S/W Reset
Contents of memory is not cleared
H/W Reset
Contents of memory is not cleared
Legend
Command
RAMWR
Parameter
Display
Flow Chart
Image Data
D1[7:0],D2[7:0]
… … .Dn[7:0]
Action
Mode
Any Command
V1.5
102
Sequential
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ST7715
10.1.22 RAMRD (2Eh): Memory Read
2EH
RAMHD (Memory Read)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RAMHD
0
↑
1
-
0
0
1
0
1
1
1
0
(2Eh)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
∣
1
1
↑
∣
∣
∣
∣
∣
∣
∣
∣
∣
(N+1)th parameter
1
1
↑
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
-This command is used to transfer data from frame memory to MCU.
-When this command is accepted, the column register and the row register are reset to the Start Column/Start
Row positions.
-The Start Column/Start Row positions are different in accordance with MADCTL setting.
-Then D[17:0] is read back from the frame memory and the column register and the row register incremented as
section 9.10
Description
-Frame Read can be cancelled by sending any other command.
-The data color coding is fixed to 18-bit in reading function. Please see section 9.8 “Data color coding” for color
coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data.
Note1: The Command 3Ah should be set to 66h when reading pixel data from frame memory.Please check the
LUT in chapter 9.17 when using memory read function.
Default
Status
Default Value
Power On Sequence
Contents of memory is set randomly
S/W Reset
Contents of memory is not cleared
H/W Reset
Contents of memory is not cleared
Flow Chart
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10.1.23 PTLAR (30h): Partial Area
30H
PTLAR (Partial Area)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PTLAR
0
↑
1
-
0
0
1
1
0
0
0
0
(30h)
1st
parameter
1
↑
1
-
PSL15
PSL14
PSL13
PSL12
PSL11
PSL10
PSL9
PSL8
2nd
parameter
1
↑
1
-
PSL7
PSL6
PSL5
PSL4
PSL3
PSL2
PSL1
PSL0
3rd
parameter
1
↑
1
-
PEL15
PEL14
PEL13
PEL12
PEL11
PEL10
PEL9
PEL8
4th
parameter
1
↑
1
-
PEL7
PEL6
PEL5
PEL4
PEL3
PEL2
PEL1
PEL0
-This command defines the partial mode’s display area.
-There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row
(PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter.
-If End Row > Start Row, when MADCTL ML=’0’
End row
Non-display area
PEL [7:0]
Partial display area
PSL [7:0]
Non-display area
Start row
Start row
Non-display area
PSL [7:0]
-If End Row > Start Row, when MADCTL ML=’1’
Partial display area
Description
PEL [7:0]
Non-display area
End row
-If End Row < Start Row, when MADCTL ML=’0’
Partial display area
End row
PEL [7:0]
Non-display area
PSL [7:0]
Start row
Partial display area
-If End Row = Start Row then the Partial Area will be one row deep.
Status
Default
V1.5
Default Value
PSL [15:0]
PEL [15:0]
GM[2:0]
“xxx”
GM[2:0]=”001”
Power On Sequence
0000h
0083h
S/W Reset
0000h
0083h
H/W Reset
0000h
0083h
104
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Flow Chart
V1.5
105
2009-12-04
ST7715
10.1.24 TEOFF (34h): Tearing Effect Line OFF
34H
TEOFF (Tearing Effect Line OFF)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
TEOFF
0
↑
1
-
0
0
1
1
0
1
0
0
(34h)
Parameter
Description
No Parameter
-
-This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Status
Default
Default Value
Power On Sequence
OFF
S/W Reset
OFF
H/W Reset
OFF
Legend
Command
TE Line Output
ON
Parameter
TEOFF
Display
Flow Chart
TE Line Output
OFF
Action
Mode
Sequential
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10.1.25 TEON (35h): Tearing Effect Line ON
35H
TEON (Tearing Effect Line ON)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
TEON
0
↑
1
-
0
0
1
1
0
1
0
1
(35h)
1
↑
1
-
0
0
0
0
0
0
0
TELOM
Parameter
-This command is used to turn ON the Tearing Effect output signal from the TE signal line.
-This output is not affected by changing MADCTL bit ML.
-The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output
Line:
-When TELOM =’0’: The Tearing Effect output line consists of V-Blanking information only
Tvdl
Tvdh
Vertical time scale
Description
-When TELOM =’1’: The Tearing Effect output Line consists of both V-Blanking and H-Blanking
information
Tvdl
Tvdh
Vertical time scale
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Default
Status
Default Value
Power On Sequence
Tearing effect off & TELOM=0
S/W Reset
Tearing effect off & TELOM=0
H/W Reset
Tearing effect off & TELOM=0
Legend
TE Line Output
OFF
Command
Parameter
TEON
Display
Flow Chart
TELOM
Action
TE Line Output
ON
Mode
Sequential
transter
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10.1.26 MADCTL (36h): Memory Data Access Control
36H
MADCTL (Memory Data Access Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
MADCTL
0
↑
1
-
0
0
1
1
0
1
1
0
(36h)
Parameter
1
↑
1
-
MY
MX
MV
ML
RGB
0
-
-
-This command defines read/ write scanning direction of frame memory.
Bit
NAME
DESCRIPTION
MY
Row Address Order
MX
Column Address Order
MV
Row/Column Exchange
ML
Vertical Refresh Order
LCD vertical refresh direction control
‘0’ = LCD vertical refresh Top to Bottom
‘1’ = LCD vertical refresh Bottom to Top
RGB
RGB-BGR ORDER
Color selector switch control
‘0’ =RGB color filter panel,
‘1’ =BGR color filter panel)
These 3bits controls MCU to memory
write/read direction.
-Bit Assignment
Top-left (0, 0)
Top-left (0, 0)
Memory
Display
Send first
Send 2nd
Send 3rd
ML="0"
Send last
Description
Top-left (0, 0)
Top-left (0, 0)
Memory
Display
Send last
ML="1"
Send 3rd
Send 2nd
Send first
R
G
B
R
SIG1
RGB="0"
RGB="1"
Driver IC
Driver IC
G
B
R
SIG2
SIG1
G
B
SIG2
G
B
R
SIG1
SIG132
G
B
R
SIG2
SIG1
G
B
SIG132
SIG2
SIG132
R
G
B
R
G
B
R
G
B
B
G
R
B
G
R
B
G
R
R
G
B
R
G
B
R
G
B
B
G
R
B
G
R
B
G
R
LCD panel
V1.5
R
SIG132
LCD panel
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Top-left (0, 0)
Top-left (0, 0)
Memory
Memory
ML="0"
ML="1"
Send first
Send 3rd
Top-left (0, 0)
Display
Default
Send 2nd
Send last
Send last
Send 3rd
Send 2nd
Send first
Top-left (0, 0)
Display
Status
Default Value
Power On Sequence
MY=0,MX=0,MV=0,ML=0,RGB=0
S/W Reset
No Change
H/W Reset
MY=0,MX=0,MV=0,ML=0,RGB=0
Legend
Command
MADCTL
Parameter
Display
Flow Chart
1st parameter
B[7:0]
Action
Mode
Sequential
transter
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10.1.27 IDMOFF (38h): Idle Mode Off
38H
IDMOFF (Idle Mode Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
IDMOFF
0
↑
1
-
0
0
1
1
1
0
0
0
(38h)
Parameter
No Parameter
-
-This command is used to recover from Idle mode on.
-In the idle off mode,
Description
1. LCD can display 4096, 65k or 262k colors.
2. Normal frame frequency is applied.
Default
Status
Default Value
Power On Sequence
Idle Mode Off
S/W Reset
Idle Mode Off
H/W Reset
Idle Mode Off
Legend
Command
Idle on mode
Parameter
IDMOFF
Display
Flow Chart
Idle off mode
Action
Mode
Sequential
transter
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10.1.28 IDMON (39h): Idle Mode On
39H
IDMON (Idle Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
IDMOFF
0
↑
1
-
0
0
1
1
1
0
0
1
(39h)
Parameter
No Parameter
-
-This command is used to enter into Idle mode on.
-There will be no abnormal visible effect on the display mode change transition.
-In the idle on mode,
1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame
Memory, 8 color depth data is displayed.
2. 8-Color mode frame frequency is applied.
3. Exit from IDMON by Idle Mode Off (38h) command
(Example) Memory
Top-Left (0,0)
Display
Description
Register
Availability
Default
V1.5
Color
R5 R4 R3 R2 R1 R0
G5 G4 G3 G2 G1 G0
B5 B4 B3 B4 B1 B0
Black
0xxxxx
0xxxxx
0xxxxx
Blue
0xxxxx
0xxxxx
1xxxxx
Red
1xxxxx
0xxxxx
0xxxxx
Magenta
1xxxxx
0xxxxx
1xxxxx
Green
0xxxxx
1xxxxx
0xxxxx
Cyan
0xxxxx
1xxxxx
1xxxxx
Yellow
1xxxxx
1xxxxx
0xxxxx
White
1xxxxx
1xxxxx
1xxxxx
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
No
Partial Mode On, Idle Mode On, Sleep Out
No
Sleep In
Yes
Status
Default Value
Power On Sequence
Idle Mode Off
S/W Reset
Idle Mode Off
H/W Reset
Idle Mode Off
111
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ST7715
Legend
Command
Idle off mode
Parameter
IDMON
Display
Idle on mode
Action
Flow Chart
Mode
Sequential
transter
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10.1.29 COLMOD (3Ah): Interface Pixel Format
3AH
COLMOD (3Ah): Interface Pixel Format
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
COLMOD
0
↑
1
-
0
0
1
1
1
0
1
0
(3Ah)
Parameter
1
↑
1
-
-
-
-
-
-
IFPF2
IFPF1
IFPF0
This command is used to define the format of RGB picture data, which is to be transferred via the
MCU interface. The formats are shown in the table:
IFPF[2:0]
Description
MCU Interface Color Format
011
3
101
5
12-bit/pixel
16-bit/pixel
110
6
18-bit/pixel
111
7
No used
Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory.
Note2: The Command 3Ah should be set at 55h when writing 16-bit/pixel data into frame memory, but 3Ah should be
re-set to 66h when reading pixel data from frame memory. Please check the LUT in chapter 9.17 when using
memory read function.
Register
Availability
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
No
Partial Mode On, Idle Mode On, Sleep Out
No
Sleep In
Yes
Status
Default
V1.5
Power On Sequence
Default Value
IFPF[2:0]
VIPF[3:0]
0110(18-bit/Pixel)
0110(18-bit/Pixel)
S/W Reset
No Change
No Change
H/W Reset
0110(18-bit/Pixel)
0110(18-bit/Pixel)
113
2009-12-04
ST7715
Flow Chart
V1.5
114
2009-12-04
ST7715
10.1.30 RDID1 (DAh): Read ID1 Value
DAH
RDID1 (Read ID1 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDID1
0
↑
1
-
1
1
0
1
1
0
1
0
(DAh)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
-This read byte returns 8-bit LCD module’s manufacturer ID
-The 1st parameter is dummy data
Description
-The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID.
NOTE: See command RDDID (04h), 2nd parameter.
Register
Availability
Default
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
No
Partial Mode On, Idle Mode On, Sleep Out
No
Sleep In
Yes
Status
Default Value
Power On Sequence
-
S/W Reset
-
H/W Reset
-
Legend
Serial I/F Mode
Parallel I/F Mode
Read ID1
Command
Read ID1
Parameter
Send 2nd
parameter
Dummy
Read
Display
Flow Chart
Action
Send 2nd
parameter
Mode
Sequential
transter
V1.5
115
2009-12-04
ST7715
10.1.31 RDID2 (DBh): Read ID2 Value
DBH
RDID2 (Read ID2 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDID2
0
↑
1
-
1
1
0
1
1
0
1
1
(DBh)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
1
ID26
ID25
ID24
ID23
ID22
ID21
ID20
-This read byte returns 8-bit LCD module/driver version ID
-The 1st parameter is dummy data
-The 2nd parameter (ID26 to ID20): LCD module/driver version ID
-Parameter Range: ID=80h to FFh
Description
ID26 to ID20
Version
Changes
80h
81h
82h
83h
NOTE: See command RDDID (04h), 3rd parameter.
Register
Availability
Default
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
No
Partial Mode On, Idle Mode On, Sleep Out
No
Sleep In
Yes
Status
Default Value
Power On Sequence
NV value
S/W Reset
NV value
H/W Reset
NV value
Legend
Serial I/F Mode
Parallel I/F Mode
Command
Read ID2
Parameter
Read ID2
Host
Display
Display
Flow Chart
Send 2nd
parameter
Dummy
Read
Action
Send 2nd
parameter
Mode
Sequential
transter
V1.5
116
2009-12-04
ST7715
10.1.32 RDID3 (DCh): Read ID3 Value
DCH
RDID3 (Read ID2 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
RDID3
0
↑
1
-
1
1
0
1
1
1
0
0
(DCh)
1st parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
2nd parameter
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
-This read byte returns 8-bit LCD module/driver ID.
-The 1st parameter is dummy data
Description
-The 2nd parameter (ID37 to ID30): LCD module/driver ID.
NOTE: See command RDDID (04h), 4th parameter.
Register
Availability
Default
Status
Availability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
Yes
Partial Mode On, Idle Mode Off, Sleep Out
No
Partial Mode On, Idle Mode On, Sleep Out
No
Sleep In
Yes
Status
Default Value
Power On Sequence
NV value
S/W Reset
NV value
H/W Reset
NV value
Legend
Serial I/F Mode
Read ID3
Parallel I/F Mode
Command
Read ID3
Parameter
Host
Display
Display
Flow Chart
Send 2nd
parameter
Dummy
Read
Action
Send 2nd
parameter
Mode
Sequential
transter
V1.5
117
2009-12-04
ST7715
10.2 Panel Function Command List and Description
Table 10.2.1 Panel Function Command List (1)
Instruction
Refer D/CX WRX RDX D23-8 D7
FRMCTR1 10.2.1
FRMCTR2 10.2.2
FRMCTR3 10.2.3
INVCTR
DISSET5
V1.5
D6
D5
D4
D3
D2
D1
D0
Hex
Function
0
1
1
0
0
0
1
(B1h)
In normal mode
(Full colors)
0
↑
1
-
1
↑
1
-
1
↑
1
-
FPA5 FPA4 FPA3
FPA2
FPA1
FPA0
1
↑
1
-
BPA5 BPA4 BPA3
BPA2
BPA1
BPA0
0
↑
1
-
0
1
0
1
↑
1
-
1
↑
1
-
FPB5 FPB4 FPB3
FPB2
FPB1
FPB0
1
↑
1
-
BPB5 BPB4 BPB3
BPB2
BPB1
BPB0
0
↑
1
-
0
1
1
1
↑
1
-
1
↑
1
-
FPC5 FPC4 FPC3
FPC2
FPC1
FPC0
1
↑
1
-
BPC5 BPC4 BPC3
BPC2
BPC1
BPC0
1
↑
1
-
1
↑
1
-
FPD5 FPD4 FPD3
FPD2
FPD1
FPD0
1
↑
1
-
BPD5 BPD4 BPD3
BPD2
BPD1
BPD0
0
↑
1
-
1
0
1
1
0
1
0
0
1
↑
1
-
0
0
0
0
0
NLA
NLB
NLC
0
↑
1
-
1
0
1
1
0
1
1
0
1
↑
1
-
0
0
NO1
NO0
SDT1
SDT0
EQ1
EQ0
1
↑
1
-
0
0
0
0
PTG1
PTG0
PT1
PT0
1
RTNA3 RTNA2 RTNA1 RTNA0
1
0
1
1
0
RTNA set 1-line
period
FPA: front porch
BPA: back porch
(B2h)
RTNB3 RTNB2 RTNB1 RTNB0
1
0
1
1
0
In Idle mode
(8-colors)
RTNB: set 1-line
period
FPB: front porch
BPB: back porch
(B3h)
In partial mode +
Full colors
RTNC3 RTNC2 RTNC1 RTNC0
RTNC,RTND: set
1-line period
FPC,FPD: front
porch
BPC,BPD: back
porch
RTND3 RTND2 RTND1 RTND0
(B4h)
Display inversion
control
10.2.4
10.2.5
118
NLA,NLB,NLC set
inversion
(B6h)
Display function
setting
SDT: set amount of
source delay
EQ: set EQ period
PT: No display area
source/VCOM/Gate
output control
2009-12-04
ST7715
Table 10.2.2 Panel Function Command List (2)
Instruction Refer D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Function
0
0
0
0
0
(C0h)
Power control setting
0
↑
1
-
1
1
0
1
↑
1
-
0
0
0
VRH4 VRH3 VRH2 VRH1 VRH0
VRH: Set the GVDD
voltage
VC: Set the VCI1
voltage
PWCTR1 10.2.6
IBIBSEL1 SEL0
1
↑
1
-
0
1
0
↑
1
-
1
1
0
1
↑
1
-
0
0
0
↑
1
-
1
1
↑
1
0
0
0
0
0
0
0
0
1
0
0
0
BT2
BT1
BT0
1
0
0
0
0
1
0
0
0
0
0
0
-
0
0
0
0
0
-
0
0
0
0
0
-
0
0
0
0
0
0
0
0
-
1
1
0
0
0
0
1
1
-
0
0
0
0
0
-
0
0
0
0
0
-
0
0
0
0
0
-
0
0
0
0
0
0
0
0
1
0
0
(C1h)
PWCTR2 10.2.7
PWCTR3 10.2.8
1
↑
↑
1
1
↑
1
PWCTR4 10.2.9
1
↑
BT: set VGH/ VGL
voltage
(C2h)
0
0
APA: adjust the
operational amplifier
DCA: adjust the booster
Voltage
0
DCA2 DCA1 DCA0
(C3h) In Idle mode (8-colors)
APB2 APB1 APB0
0
0
APB: adjust the
operational amplifier
DCB: adjust the booster
Voltage
0
DCB2 DCB1 DCB0
1
0
↑
1
-
1
1
0
0
0
1
↑
1
-
0
0
0
0
0
APC2 APC1 APC0
1
↑
1
-
0
0
0
0
0
DCC2 DCC1 DCC0
0
↑
1
-
1
1
0
0
0
1
↑
1
-
-
VMH6 VMH5 VMH4 VMH3 VMH2 VMH1 VMH0
1
↑
1
-
-
VML6 VML5 VML4 VML3 VML2 VML1 VML0
0
↑
1
-
1
1
0
1
↑
1
-
-
-
-
0
↑
1
-
1
1
0
1
↑
1
-
-
(C4h)
In partial mode + Full
colors
APC: adjust the
operational amplifier
DCC: adjust the booster
circuit for Idle mode
(C5h)
VCOM control 1
PWCTR5 10.2.10
1
0
1
VMCTR1 10.2.11
0
0
In normal mode (Full
colors)
APA2 APA1 APA0
1
0
Power control setting
1
1
1
VMH: VCOMH voltage
control
VML: VCOML voltage
control
(C7h) Set VCOM offset control
VMOFCTR 10.2.12
WRID2
VMF4 VMF3 VMF2 VMF1 VMF0
1
0
0
0
1
(D1h) Set LCM version code
10.2.13
ID2[6] ID2[5] ID2[4] ID2[3] ID2[2] ID2[1] ID2[0]
“-“: Don’t care
Note 1: C0h to C7h are fixed for about power controller
V1.5
119
2009-12-04
ST7715
Table 10.2.3 Panel Function Command List (3)
Instruction
WRID3
Refer D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
-
1
1
0
1
0
0
1
0
1
↑
1
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
Function
Customer Project
(D2h) code
Set the project code
at ID3
0
↑
1
-
1
1
1
1
1
1
0
0
(FCh) In partial mode + Idle
1
↑
1
-
-
Sapa Sapa Sapa
--[2]
[1]
[0]
Sapb Sapb Sapb
[2]
[1]
[0]
1
↑
1
-
-
Sapc Sapc Sapc
--[2]
[1]
[0]
DCD DCD DCD
[2]
[1]
[0]
0
↑
1
-
1
0
0
0
VMF ID2
0
_EN _EN
10.2.14
PWCTR6 10.2.15
1
NVCTR1 10.2.16
0
1
1
0
0
1
0
(D9h)
EEPROM control
status
0
1
↑
1
-
0
↑
1
-
1
↑
1
-
0
↑
1
-
1
1
↑
1
-
EE_
IB7
1
↑
1
-
EE_ EE_ EE_ EE_ EE_ EE_ EE_
EE_
CMD CMD CMD CMD CMD CMD CMD
CMD7
6
5
4
3
2
1
0
1
↑
1
-
1
1
1
0
1
1
1
1
0
NVCTR2 10.2.17
NVCTR3 10.2.18
1
0
1
1
0
0
0
1
EE_ EE_ EE_
IB6 IB5 IB4
0
1
0
1
1
0
1
Hex
1
1
EEPROM Read
(DEh) Command
A5
1
Action code
EEPROM Write
(DFh) Command
EE_ EE_ EE_ EE_
IB3 IB2 IB1 IB0
0
1
0
1
A5
“-“: Don’t care
Note 1: The D1h to D2h registers are fixed for about ID code setting.
Note 2: The D9h, DEh and DFh registers are used for NV Memory function controller. (Ex: write, clear, etc.)
V1.5
120
2009-12-04
ST7715
Table 10.2.4 Panel Function Command List (4)
Instruction
Refer D/CX WRX RDX D17-8 D7
0
GAMCTRP1 10.2.19
GAMCTRN1 10.2.20
↑
1
-
1
D6
D5
D4
D3
D2
D1
D0
Hex
1
1
0
0
0
0
0
(E0h)
1
↑
1
-
---
---
VRFP[5]
VRFP[4]
VRFP[3]
VRFP[2]
VRFP[1]
VRF0P[0]
1
↑
1
-
---
---
VOS0P[5]
VOS0P[4]
VOS0P[3]
VOS0P[2]
VOS0P[1]
VOS0P[0]
1
↑
1
-
---
---
PKP0[5]
PKP0[4]
PKP0[3]
PKP0[2]
PKP0[1]
PKP0[0]
1
↑
1
-
---
---
PKP1[5]
PKP1[4]
PKP1[3]
PKP1[2]
PKP1[1]
PKP1[0]
1
↑
1
-
---
---
PKP2[5]
PKP2[4]
PKP2[3]
PKP2[2]
PKP2[1]
PKP2[0]
1
↑
1
-
---
---
PKP3[5]
PKP3[4]
PKP3[3]
PKP3[2]
PKP3[1]
PKP3[0]
1
↑
1
-
---
---
PKP4[5]
PKP4[4]
PKP4[3]
PKP4[2]
PKP4[1]
PKP4[0]
1
↑
1
-
---
---
PKP5[5]
PKP5[4]
PKP5[3]
PKP5[2]
PKP5[1]
PKP5[0]
1
↑
1
-
---
---
PKP6[5]
PKP6[4]
PKP6[3]
PKP6[2]
PKP6[1]
PKP6[0]
1
↑
1
-
---
---
PKP7[5]
PKP7[4]
PKP7[3]
PKP7[2]
PKP7[1]
PKP7[0]
1
↑
1
-
---
---
PKP8[5]
PKP8[4]
PKP8[3]
PKP8[2]
PKP8[1]
PKP8[0]
1
↑
1
---
---
PKP9[5]
PKP9[4]
PKP9[3]
PKP9[2]
PKP9[1]
PKP9[0]
1
↑
1
-
---
---
SELV0P[5] SELV0P[4] SELV0P[3] SELV0P[2] SELV0P[1] SELV0P[0]
1
↑
1
-
---
---
SELV1P[5] SELV1P[4] SELV1P[3] SELV1P[2] SELV1P[1] SELV1P[0]
1
↑
1
---
---
SELV62P[5] SELV62P[4] SELV62P[3] SELV62P[2] SELV62P[1] SELV62P[0]
1
↑
1
-
---
---
SELV63P[5] SELV63P[4] SELV63P[3] SELV63P[2] SELV63P[1] SELV63P[0]
0
↑
1
-
1
1
1
0
0
0
0
1
1
↑
1
-
---
---
VRF0N[5]
VRF0N[4]
VRF0N[3]
VRF0N[2]
VRF0N[1]
VRF0N[0]
1
↑
1
-
---
---
VOS0N[5]
VOS0N[4]
VOS0N[3]
VOS0N[2]
VOS0N[1]
VOS0N[0]
1
↑
1
-
---
---
PKN0[5]
PKN0[4]
PKN0[3]
PKN0[2]
PKN0[1]
PKN0[0]
1
↑
1
-
---
---
PKN1[5]
PKN1[4]
PKN1[3]
PKN1[2]
PKN1[1]
PKN1[0]
1
↑
1
-
---
---
PKN2[5]
PKN2[4]
PKN2[3]
PKN2[2]
PKN2[1]
PKN2[0]
1
↑
1
-
---
---
PKN3[5]
PKN3[4]
PKN3[3]
PKN3[2]
PKN3[1]
PKN3[0]
1
↑
1
-
---
---
PKN4[5]
PKN4[4]
PKN4[3]
PKN4[2]
PKN4[1]
PKN4[0]
1
↑
1
-
---
---
PKN5[5]
PKN5[4]
PKN5[3]
PKN5[2]
PKN5[1]
PKN5[0]
1
↑
1
-
---
---
PKN6[5]
PKN6[4]
PKN6[3]
PKN6[2]
PKN6[1]
PKN6[0]
1
↑
1
-
---
---
PKN7[5]
PKN7[4]
PKN7[3]
PKN7[2]
PKN7[1]
PKN7[0]
1
↑
1
-
---
---
PKN8[5]
PKN8[4]
PKN8[3]
PKN8[2]
PKN8[1]
PKN8[0]
1
↑
1
-
---
---
PKN9[5]
PKN9[4]
PKN9[3]
PKN9[2]
PKN9[1]
PKN9[0]
1
↑
1
-
---
---
SELV0N[5] SELV0N[4] SELV0N[3] SELV0N[2] SELV0N[1] SELV0N[0]
1
↑
1
-
---
---
SELV1N[5] SELV1N[4] SELV1N[3] SELV1N[2] SELV1N[1] SELV1N[0]
1
↑
1
-
---
---
SELV62N[5] SELV62N[4] SELV62N[3] SELV62N[2] SELV62N[1] SELV62N[0]
1
↑
1
-
---
---
SELV63N[5] SELV63N[4] SELV63N[3] SELV63N[2] SELV63N[1] SELV63N[0]
0
↑
1
-
1
1
1
1
0
0
0
0
Function
Set
Gamma
adjustment
(+ polarity)
Set
(E1h)
Gamma
adjustment
(- polarity)
Extension
(F0h) Command
EXTCTRL 10.2.21
Control
1
↑
1
-
0
0
0
0
0
0
0
1
0
↑
1
-
1
1
1
1
1
1
1
0
01
Vcom 4
(FFh) Level
Control
VCOM4L 10.2.22
1
↑
1
-
1
↑
1
-
-
1
↑
1
-
0
TC2[3] TC2[2]
TC2[1]
TC2[0]
TC1[3]
TC1[2]
TC1[1]
TC1[0]
-
-
-
TC3[3]
TC3[2]
TC3[1]
TC3[0]
0
0
1
1
0
1
0
“-“: Don’t care
Note 1: E0-E1 registers are fixed for adjusting Gamma
V1.5
121
2009-12-04
ST7715
10.2.1 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)
B1H
FRMCTR1 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
FRMCTR1
0
↑
1
-
1
0
1
1
0
0
0
1
(B1h)
1st parameter
1
↑
1
-
-
-
-
-
RTNA
RTNA
RTNA
RTNA
2 parameter
1
↑
1
-
-
-
FPA5
FPA4
FPA3
FPA2
FPA1
FPA0
3rd parameter
1
↑
1
-
-
-
BPA5
BPA4
BPA3
BPA2
BPA1
BPA0
nd
-Set the frame frequency of the full colors normal mode.
Description
- Frame rate=fosc/((RTNA + 20) x (LINE + FPA + BPA))
- 1 < FPA(front porch) + BPA(back porch) ; Back porch ≠ 0
Default
Status
Default Value
Power On Sequence
08h/22h/23h
S/W Reset
08h/22h/23h
H/W Reset
08h/22h/23h
Flow Chart
V1.5
122
2009-12-04
ST7715
10.2.2 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)
B2H
FRMCTR2 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
FRMCTR2
0
↑
1
-
1
0
1
1
0
0
1
0
(B2h)
1st parameter
1
↑
1
-
-
-
-
-
RTNB
RTNB
RTNB
RTNB
-
FPB5
FPB4
FPB3
FPB2
FPB1
FPB0
-
BPB5
BPB4
BPB3
BPB2
BPB1
BPB0
2nd parameter
rd
3 parameter
1
↑
1
-
-
1
↑
1
-
-
-Set the frame frequency of the Idle mode.
Description
- Frame rate=fosc/((RTNB + 20) x (LINE + FPB + BPB))
- 1 < FPB(front porch) + BPB(back porch) ; Back porch ≠ 0
Default
Status
Default Value
Power On Sequence
08h/22h/23h
S/W Reset
08h/22h/23h
H/W Reset
08h/22h/23h
Flow Chart
V1.5
123
2009-12-04
ST7715
10.2.3 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)
B3H
FRMCTR3 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
FRMCTR3
0
↑
1
-
1
0
1
1
0
0
1
1
(B3h)
1st parameter
1
↑
1
-
-
-
-
-
RTNC
RTNC
RTNC
RTNC
2 parameter
1
↑
1
-
-
-
FPC5
FPC4
FPC3
FPC2
FPC1
FPC0
3rd parameter
1
↑
1
-
-
-
BPC5
BPC4
BPC3
BPC2
BPC1
BPC0
4th parameter
nd
1
↑
1
-
-
-
-
-
RTND
RTND
RTND
RTND
th
1
↑
1
-
-
-
FPD5
FPD4
FPD3
FPD2
FPD1
FPD0
th
1
↑
1
-
-
-
BPD5
BPD4
BPD3
BPD2
BPD1
BPD0
5 parameter
6 parameter
-Set the frame frequency of the Partial mode/ full colors.
- 1st parameter to 3rd parameter are used in line inversion mode.
Description
- 4th parameter to 6th parameter are used in frame inversion mode.
- Frame rate=fosc/((RTNC + 20) x (LINE + FPC + BPC))
- 1 < FPC(front porch) + BPC(back porch) ; Back porch ≠ 0
Default
Status
Default Value
Power On Sequence
08h/22h/23h /08h/22h/23h
S/W Reset
08h/22h/23h /08h/22h/23h
H/W Reset
08h/22h/23h /08h/22h/23h
Flow Chart
V1.5
124
2009-12-04
ST7715
10.2.4 INVCTR (B4h): Display Inversion Control
B4H
INVCTR (Display Inversion Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
INVCTR
0
↑
1
-
1
0
1
1
0
1
0
0
(B4h)
Parameter
1
↑
1
-
0
0
0
0
0
NLA
NLB
NLC
-Display Inversion mode control
-NLA: Inversion setting in full colors normal mode (Normal mode on)
NLA
Inversion setting in full Colors normal mode
0
Line Inversion
1
Frame Inversion
-NLB: Inversion setting in Idle mode (Idle mode on)
Description
NLB
Inversion setting in Idle mode
0
Line Inversion
1
Frame Inversion
-NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off)
NLC
Inversion setting in full Colors partial mode
0
Line Inversion
1
Frame Inversion
Status
Default
Default Value
NLA
NLB
NLC
Power On Sequence
1d
1d
1d
B4h
03h
S/W Reset
1d
1d
1d
03h
H/W Reset
1d
1d
1d
03h
Flow Chart
V1.5
125
2009-12-04
ST7715
10.2.5 DISSET5 (B6h): Display Function set 5
B6H
DISSET (Display Function set 5)
Inst / Para
D/CX
WRX
RDX
D17-
D7
D6
D5
D4
D3
D2
D1
D0
HEX
DISSET5
0
↑
1
-
1
0
1
1
0
1
1
0
(B6h)
1st parameter
1
↑
1
-
0
0
NO1
NO0
SDT1
SDT0
EQ1
EQ0
1
↑
1
-
0
0
0
0
PTG1
PTG0
PT1
PT0
nd
2 parameter
1st parameter: Set output waveform relation.
-NO[1:0]: Set the amount of non-overlap of the gate output
Amount of non-overlap of the gate
NO[1:0]
output
Refer the Internal oscillator
00
0
1 clock cycle
01
1
2 clock cycle
10
2
4 clock cycle
11
3
6 clock cycle
-SDT[1:0]: Set delay amount from gate signal falling edge of the source output.
Amount of non-overlap of the gate
SDT[1:0]
output
Refer the Internal oscillator
00
0
0 clock cycle
01
1
1 clock cycle
10
2
2 clock cycle
11
3
3 clock cycle
-EQ[1:0]: Set the Equalizing period
Amount of non-overlap of the gate
EQ[1:0]
output
Refer the Internal oscillator
00
0
No EQ
01
1
3 clock cycle
10
2
5 clock cycle
11
3
7 clock cycle
-2nd parameter: Set the output waveform in non-display area.
-PTG[1:0]: Determine gate output in a non-display area in the partial mode
-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode
Description
PTG[1:0]
00
01
10
11
PT[1:0]
00
01
10
11
V1.5
0
1
2
3
0
1
2
3
Gate output in a non-display area
Normal scan
Fix on VGL
Fix on VGL
Fix on VGL
Source output on non-display area
VCOM output on non-display area
Positive
Negative
Positive
Negative
V63
V0
VCOML
VCOMH
V0
V63
VCOML
VCOMH
AGND
AGND
AGND
AGND
Hi-z
Hi-z
AGND
AGND
126
2009-12-04
ST7715
Status
Default Value
B6h
Default
Power On Sequence
15h/00h
S/W Reset
15h/00h
H/W Reset
15h/00h
Flow Chart
V1.5
127
2009-12-04
ST7715
10.2.6 PWCTR1 (C0h): Power Control 1
C0H
PWCTR1 (Power Control 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PWCTR1
0
↑
1
-
1
1
0
0
0
0
0
0
(C0h)
1st paramete
1
↑
1
-
0
0
0
VRH4
VRH3
VRH2
VRH1
VRH0
2nd parameter
1
↑
1
-
0
1
IB_
SEL1
IB_
SEL0
-
0
0
0
- Set the GVDD voltage
Description
Restriction
Register
Availability
V1.5
VRH[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GVDD
5.00
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
3.75
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
3.25
3.00
IB_SEL[1:0]
00
01
10
11
0
1
2
3
AVDD
2.5uA
2.0uA
1.5uA
1.0uA
-If this register not using the register need be reserved.
-The deviation value of GVDD between with Measurement and Specification : Max <= 50mV
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
128
2009-12-04
ST7715
Status
Default
Power On Sequence
S/W Reset
H/W Reset
Default Value
C0h
02h/70h
02h/70h
02h/70h
Flow Chart
V1.5
129
2009-12-04
ST7715
10.2.7 PWCTR2 (C1h): Power Control 2
C1H
PWCTR2 (Power Control 2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PWCTR2
0
↑
1
-
1
1
0
0
0
0
0
1
(C1h)
1st parameter
1
↑
1
0
0
0
0
0
BT2
BT1
BT0
-Set the VGH and VGL supply power level
Description
Restriction
Register
Availability
BT[2:0]
VGH
000
4X
9.8
001
4X
9.8
-4X
-9.8
010
5X
12.25
-3X
-7.35
011
5X
12.25
-4X
-9.8
100
5X
12.25
-5X
-12.25
101
6X
14.7
-3X
-7.35
110
6X
14.7
-4X
-9.8
111
6X
14.7
-5X
-12.25
V1.5
-7.35
-If this register not using the register need be reserved.
-The deviation value of VGH/ VGL between with Measurement and Specification: Maxmum <= 1V
-VGH-VGL <= 32V
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default
VGL
-3X
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
C1h
05h
05h
05h
130
2009-12-04
ST7715
Flow Chart
V1.5
131
2009-12-04
ST7715
10.2.8 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors)
C2H
PWCTR3 (Power Control 3)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PWCTR3
0
↑
1
-
1
1
0
0
0
0
1
0
(C2h)
1st parameter
1
↑
1
-
0
0
0
0
0
APA2
APA1
APA0
1
↑
1
-
0
0
0
0
0
DCA2
DCA1
DCA0
nd
2 parameter
-Set the amount of current in Operational amplifier in normal mode/full colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source
driver.
AP[2:0]
Amount of Current in Operational Amplifier
Description
000
0
Operation of the operational amplifier stops
001
1
Small
010
2
Medium Low
011
3
Medium
100
4
Medium High
101
5
Large
110
6
Reserved
111
7
Reserved
-Set the Booster circuit Step-up cycle in Normal mode/ full colors.
DC[2:0]
Step-up cycle in Booster circuit 1
Step-up cycle in Booster circuit 2,4
000
0
BCLK / 1
BCLK / 1
001
1
BCLK / 1
BCLK / 2
010
2
BCLK / 1
BCLK / 4
011
3
BCLK / 2
BCLK / 2
100
4
BCLK / 2
BCLK / 4
101
5
BCLK / 4
BCLK / 4
110
6
BCLK / 4
BCLK / 8
111
7
BCLK / 4
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
-If this register not using the register need be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default
V1.5
BCLK / 16
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
C2h
01h/01h
01h/01h
01h/01h
132
2009-12-04
ST7715
Flow Chart
V1.5
133
2009-12-04
ST7715
10.2.9 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors)
C3H
PWCTR4 (Power Control 4)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PWCTR4
0
↑
1
-
1
1
0
0
0
0
1
1
(C3h)
1st parameter
1
↑
1
-
0
0
0
0
0
APB2
APB1
APB0
1
↑
1
-
0
0
0
0
0
DCB2
DCB1
DCB0
nd
2 parameter
-Set the amount of current in Operational amplifier in Idle mode/8 colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source
driver.
AP[2:0]
Amount of Current in Operational Amplifier
Description
000
0
Operation of the operational amplifier stops
001
1
Small
010
2
Medium Low
011
3
Medium
100
4
Medium High
101
5
Large
110
6
Reserved
111
7
Reserved
-Set the Booster circuit Step-up cycle in Idle mode/8 colors.
DC[2:0]
Step-up cycle in Booster circuit 1
0
BCLK / 1
BCLK / 1
001
1
BCLK / 1
BCLK / 2
010
2
BCLK / 1
BCLK / 4
011
3
BCLK / 2
BCLK / 2
100
4
BCLK / 2
BCLK / 4
101
5
BCLK / 4
BCLK / 4
110
6
BCLK / 4
BCLK / 8
111
7
BCLK / 4
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
V1.5
BCLK / 16
-If this register not using the register need be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default
Step-up cycle in Booster circuit 2,4
000
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
C3h
02h/07h
02h/07h
02h/07h
134
2009-12-04
ST7715
Flow Chart
V1.5
135
2009-12-04
ST7715
10.2.10 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors)
C4H
PWCTR5 (Power Control 5)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PWCTR5
0
↑
1
-
1
1
0
0
0
1
0
0
(C4h)
1st parameter
1
↑
1
-
0
0
0
0
0
APC2
APC1
APC0
1
↑
1
-
0
0
0
0
0
DCC2
DCC1
DCC0
nd
2 parameter
-Set the amount of current in Operational amplifier in Partial mode/ full-colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source
driver.
AP[2:0]
Amount of Current in Operational Amplifier
Description
000
0
Operation of the operational amplifier stops
001
1
Small
010
2
Medium Low
011
3
Medium
100
4
Medium High
101
5
Large
110
6
Reserved
111
7
Reserved
-Set the Booster circuit Step-up cycle in Partial mode/ full-colors.
DC[2:0]
Step-up cycle in Booster circuit 1
Step-up cycle in Booster circuit 2,4
000
0
BCLK / 1
BCLK / 1
001
1
BCLK / 1
BCLK / 2
010
2
BCLK / 1
BCLK / 4
011
3
BCLK / 2
BCLK / 2
100
4
BCLK / 2
BCLK / 4
101
5
BCLK / 4
BCLK / 4
110
6
BCLK / 4
BCLK / 8
111
7
BCLK / 4
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
-If this register not using the register need be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default
V1.5
BCLK / 16
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
C4h
02h/04h
02h/04h
02h/04h
136
2009-12-04
ST7715
Flow Chart
V1.5
137
2009-12-04
ST7715
10.2.11 VMCTR1 (C5h): VCOM Control 1
C5H
VMCTR1 (VCOM Control 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
VMCTR1
0
↑
1
-
1
1
0
0
0
1
0
1
(C5h)
1st parameter
1
↑
1
-
-
VMH6
VMH5
VMH 4
VMH 3
VMH 2
VMH 1
VMH 0
2nd parameter
1
↑
1
-
-
VML6
VML5
VML4
VML3
VML2
VML1
VML0
-Set VCOMH Voltage
VMH[6:0]
Description
V1.5
VCOMH
VMH[6:0]
VCOMH
VMH[6:0]
VCOMH
VMH[6:0]
VCOMH
0000000
0
2.500
0011011
27
3.175
0110110
54
3.850
1010001
81
4.525
0000001
1
2.525
0011100
28
3.200
0110111
55
3.875
1010010
82
4.550
0000010
2
2.550
0011101
29
3.225
0111000
56
3.900
1010011
83
4.575
0000011
3
2.575
0011110
30
3.250
0111001
57
3.925
1010100
84
4.600
0000100
4
2.600
0011111
31
3.275
0111010
58
3.950
1010101
85
4.625
0000101
5
2.625
0100000
32
3.300
0111011
59
3.975
1010110
86
4.650
0000110
6
2.650
0100001
33
3.325
0111100
60
4.000
1010111
87
4.675
0000111
7
2.675
0100010
34
3.350
0111101
61
4.025
1011000
88
4.700
0001000
8
2.700
0100011
35
3.375
0111110
62
4.050
1011001
89
4.725
0001001
9
2.725
0100100
36
3.400
0111111
63
4.075
1011010
90
4.750
0001010
10
2.750
0100101
37
3.425
1000000
64
4.100
1011011
91
4.775
0001011
11
2.775
0100110
38
3.450
1000001
65
4.125
1011100
92
4.800
0001100
12
2.800
0100111
39
3.475
1000010
66
4.150
1011101
93
4.825
0001101
13
2.825
0101000
40
3.500
1000011
67
4.175
1011110
94
4.850
0001110
14
2.850
0101001
41
3.525
1000100
68
4.200
1011111
95
4.875
0001111
15
2.875
0101010
42
3.550
1000101
69
4.225
1100000
96
4.900
0010000
16
2.900
0101011
43
3.575
1000110
70
4.250
1100001
97
4.925
0010001
17
2.925
0101100
44
3.600
1000111
71
4.275
1100010
98
4.950
0010010
18
2.950
0101101
45
3.625
1001000
72
4.300
1100011
99
4.975
0010011
19
2.975
0101110
46
3.650
1001001
73
4.325
1100100
100
5.000
0010100
20
3.000
0101111
47
3.675
1001010
74
4.350
1100101
101
0010101
21
3.025
0110000
48
3.700
1001011
75
4.375
0010110
22
3.050
0110001
49
3.725
1001100
76
4.400
0010111
23
3.075
0110010
50
3.750
1001101
77
4.425
0011000
24
3.100
0110011
51
3.775
1001110
78
4.450
0011001
25
3.125
0110100
52
3.800
1001111
79
4.475
0011010
26
3.150
0110101
53
3.825
1010000
80
4.500
138
|
1111111
Not
Permitted
127
2009-12-04
ST7715
-Set VCOML Voltage
VML[6:0]
Restriction
Register
Availability
VCOML
0000000
0
0000001
1
0000010
2
0000011
3
0000100
4
0000101
V1.5
VCOML
VML[6:0]
VCOML
VML[6:0]
VCOML
0011011
27
-1.825
0110110
54
-1.150
1010001
81
-0.475
0011100
28
-1.800
0110111
55
-1.125
1010010
82
-0.450
0011101
29
-1.775
0111000
56
-1.100
1010011
83
-0.425
0011110
30
-1.750
0111001
57
-1.075
1010100
84
-0.400
-2.400
0011111
31
-1.725
0111010
58
-1.050
1010101
85
-0.375
5
-2.375
0100000
32
-1.700
0111011
59
-1.025
1010110
86
-0.350
0000110
6
-2.350
0100001
33
-1.675
0111100
60
-1.000
1010111
87
-0.325
0000111
7
-2.325
0100010
34
-1.650
0111101
61
-0.975
1011000
88
-0.300
0001000
8
-2.300
0100011
35
-1.625
0111110
62
-0.950
1011001
89
-0.275
0001001
9
-2.275
0100100
36
-1.600
0111111
63
-0.925
1011010
90
-0.250
0001010
10
-2.250
0100101
37
-1.575
1000000
64
-0.900
1011011
91
-0.225
0001011
11
-2.225
0100110
38
-1.550
1000001
65
-0.875
1011100
92
-0.200
0001100
12
-2.200
0100111
39
-1.525
1000010
66
-0.850
1011101
93
-0.175
0001101
13
-2.175
0101000
40
-1.500
1000011
67
-0.825
1011110
94
-0.150
0001110
14
-2.150
0101001
41
-1.475
1000100
68
-0.800
1011111
95
-0.125
0001111
15
-2.125
0101010
42
-1.450
1000101
69
-0.775
1100000
96
-0.100
0010000
16
-2.100
0101011
43
-1.425
1000110
70
-0.750
1100001
97
-0.075
0010001
17
-2.075
0101100
44
-1.400
1000111
71
-0.725
1100010
98
-0.050
0010010
18
-2.050
0101101
45
-1.375
1001000
72
-0.700
1100011
99
-0.025
0010011
19
-2.025
0101110
46
-1.350
1001001
73
-0.675
1100100
100
0.000
0010100
20
-2.000
0101111
47
-1.325
1001010
74
-0.650
1100101
101
0010101
21
-1.975
0110000
48
-1.300
1001011
75
-0.625
0010110
22
-1.950
0110001
49
-1.275
1001100
76
-0.600
0010111
23
-1.925
0110010
50
-1.250
1001101
77
-0.575
0011000
24
-1.900
0110011
51
-1.225
1001110
78
-0.550
0011001
25
-1.875
0110100
52
-1.200
1001111
79
-0.525
0011010
26
-1.850
0110101
53
-1.175
1010000
80
-0.500
Not
Permitted
|
1111111
Not
Permitted
127
-If this register not using the register need be reserved.
-The VcomAC = VCOMH – VCOML
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default
VML[6:0]
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
C5h
51h/4Dh
51h/4Dh
51h/4Dh
139
2009-12-04
ST7715
Flow Chart
V1.5
140
2009-12-04
ST7715
10.2.12 VMOFCTR (C7h): VCOM Offset Control
C7H
VMOFCTR (VCOM Offset Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
VMOFCTR
0
↑
1
-
1
1
0
0
0
1
1
1
(C7h)
Parameter
1
↑
1
-
-
-
-
VMF4
VMF3
VMF2
VMF1
VMF0
-Set VCOM Voltage level for reduce the flicker issue
VMF
0
1
2
Description
VMF[4:0]
VCOMH,VCOML
Output Level
00000
“VMH”
-16d,”VML”-16d
00001
“VMH”-15d,
“VML”-15d
00010
“VMH”-14d,
“VML”-14d
|
|
|
14
01110
“VMH”-2d, “VML”-2d
15
01111
“VMH”-1d, “VML”-1d
16
10000
“VMH”, “VML”
17
10001
“VMH”+1d, “VML”+1d
18
10010
“VMH”+2d, “VML”+2d
|
|
|
11110
“VMH”+14d,
“VML”+14d
11111
“VMH”+15d,
“VML”+15d
30
31
- 1d=25mV, 2d=50mV 3d=75mv....
- 2.5V <= VMH ± nd <= 5.0V; -2. 5V <= VML ± nd<= 0V (n=0~15,16)
Restriction
Register
Availability
-If this register not using the register need be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default
V1.5
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
C7h
F0h
F0h
F0h
141
2009-12-04
ST7715
Flow Chart
V1.5
142
2009-12-04
ST7715
10.2.13 WRID2 (D1h): Write ID2 Value
D1H
WRID2 (Write ID2 Value)
Inst / Para
D/CX
WRX
RDX
D17
D7
D6
D5
D4
D3
D2
D1
D0
HEX
WRID2
0
↑
1
-
1
1
0
1
0
0
0
1
(D1h)
Parameter
1
↑
1
-
-
ID26
ID25
ID24
ID23
ID22
ID21
ID20
-
-Write 7-bit data of LCD module version to save it to EEPROM.
Description
-The parameter ID2[6:0] is LCD Module version ID.
Flow Chart
V1.5
143
2009-12-04
ST7715
10.2.14 WRID3 (D2h): Write ID3 Value
D2H
WRID3 (Write ID3 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
WRID3
0
↑
1
-
1
1
0
1
0
0
1
0
(D2h)
Parameter
1
↑
1
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
-
Description
-Write 8-bit data of project code module to save it to EEPROM.
-The parameter ID3[7:0] is product project ID.
Flow Chart
V1.5
144
2009-12-04
ST7715
10.2.15 PWCTR6 (FCh): Power Control 5 (in Idle mode + Partial mode)
FCH
PWCTR6 (Gamma control adjust)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
PWCTR6
0
↑
1
-
1
1
1
1
1
1
0
0
(FCh)
1st parameter
1
↑
1
-
-
Sapa2
Sapa1
Sapa0
-
Sapb2
Sapb1
Sapb0
1
↑
1
-
-
Sapc2
Sapc1
Sapc0
-
DCD2
DCD1
DCD0
2nd parameter
Description
-Set the amount of current in Operational amplifier in Idle mode + Partial mode.
Status
Default Value
Power On Sequence
11h/15h
S/W Reset
11h/15h
H/W Reset
11h/15h
FCh
Default
Flow Chart
V1.5
145
2009-12-04
ST7715
10.2.16 NVFCTR1 (D9h): EEPROM Control Status
D9H
NVFCTR1 (NV Memory Function Controller 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NVFCTR1
0
↑
1
-
1
1
0
0
1
0
0
1
(D9h)
parameter
1
1
↑
-
0
0
0
0
0
0
VMF_EN ID2_EN
-EEPROM control status
Description
Bit
Value
VMF_EN
“1” = Command C7h enable ; “0” = Command C7h disable
ID2_EN
“1” = Command D1h enable ; “0” = Command D1h disable
Status
Default Value
Power On Sequence
00h
S/W Reset
00h
H/W Reset
00h
D9h
Default
Flow Chart
V1.5
146
2009-12-04
ST7715
10.2.17 NVFCTR2 (DEh): EEPROM Read Command
DEH
NVFCTR1 (NV Memory Function Controller 2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NVFCTR2
0
↑
1
-
1
1
0
1
1
1
1
0
(DEh)
parameter
1
↑
1
1
0
1
0
0
1
0
1
A5
EEPROM Read Command
Description
NOTE: “-“ Don’t care
Flow Chart
V1.5
147
2009-12-04
ST7715
10.2.18 NVFCTR3 (DFh): EEPROM Write Command
DFH
NVFCTR1 (NV Memory Function Controller 3
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
NVFCTR1
0
↑
1
-
1
1
0
1
1
1
1
1
(DFh)
1st parameter
1
↑
1
EE_IB7 EE_IB6 EE_IB5 EE_IB4 EE_IB3 EE_IB2 EE_IB1 EE_IB0
EE_CM EE_CM EE_CM EE_CM EE_CM EE_CM EE_CM EE_CM
D7
D6
D5
D4
D3
D2
D1
D0
2nd parameter
1
↑
1
3rd parameter
1
↑
1
1
0
1
0
0
1
0
1
A5
-EEPROM Write Command
-EE_IB[7:0] : Select Command. ; ADDR: C7h, D1h, D2h ; Select all: AAh
Description
-EE_CMD[7:0] : Select to Program/Erase ; Program command : 3Ah ; Erase command : C5h
NOTE: “-“ Don’t care
Flow Chart
V1.5
148
2009-12-04
ST7715
10.2.19 GMCTRP1 (E0h): Gamma (‘+’polarity) Correction Characteristics Setting
E0H
Inst / Para
GMCTRP0 (Gamma ‘+’polarity Correction Characteristics Setting)
D6
D5
D4
D3
D2
D1
D0
HEX
GMCTRP1
0
↑
1
-
1
1
1
0
0
0
0
0
(E0h)
1st parameter
1
↑
1
-
-
-
VRF0P[5]
VRF0P[4]
VF0P[3]
VRF0P[2]
VRF0P[1]
VRF0P[0]
2 parameter
1
↑
1
-
-
-
VOS0P[5]
VOS0P[4]
VOS0P[3]
VOS0P[2]
VOS0P[1]
VOS0P[0]
3rd parameter
1
↑
1
-
-
-
PK0P[5]
PK0P[4]
PK0P[3]
PK0P[2]
PK0P[1]
PK0P[0]
4 parameter
1
↑
1
-
-
-
PK1P[5]
PK1P[4]
PK1P[3]
PK1P[2]
PK1P[1]
PK1P[0]
5th parameter
1
↑
1
-
-
-
PK2P[5]
PK2P[4]
PK2P[3]
PK2P[2]
PK2P[1]
PK2P[0]
6 parameter
1
↑
1
-
-
-
PK3P[5]
PK3P[4]
PK3P[3]
PK3P[2]
PK3P[1]
PK3P[0]
7th parameter
1
↑
1
-
-
-
PK4P[5]
PK4P[4]
PK4P[3]
PK4P[2]
PK4P[1]
PK4P[0]
8 parameter
1
↑
1
-
-
-
PK5P[5]
PK5P[4]
PK5P[3]
PK5P[2]
PK5P[1]
PK5P[0]
9th parameter
1
↑
1
-
-
-
PK6P[5]
PK6P[4]
PK6P[3]
PK6P[2]
PK6P[1]
PK6P[0]
th
1
↑
1
-
-
-
PK7P[5]
PK7P[4]
PK7P[3]
PK7P[2]
PK7P[1]
PK7P[0]
th
11 parameter
1
↑
1
-
-
-
PK8P[5]
PK8P[4]
PK8P[3]
PK8P[2]
PK8P[1]
PK8P[0]
12th parameter
1
↑
1
-
-
-
PK9P[5]
PK9P[4]
PK9P[3]
PK9P[2]
PK9P[1]
PK9P[0]
13 parameter
1
↑
1
-
-
-
SELV0P[5] SELV0P[4] SELV0P[3] SELV0P[2] SELV0P[1] SELV0P[0]
14th parameter
1
↑
1
-
-
-
SELV1P[5] SELV1P[4] SELV1P[3] SELV1P[2] SELV1P[1] SELV1P[0]
15 parameter
1
↑
1
-
-
-
SELV62P[5] SELV62P[4] SELV62P[3] SELV62P[2] SELV62P[1] SELV62P[0]
16th parameter
1
↑
1
-
-
-
SELV63P[5] SELV63P[4] SELV63P[3] SELV63P[2] SELV63P[1] SELV63P[0]
nd
th
th
th
10 parameter
th
th
Description
D/CX WRX RDX D17-8 D7
Register Group
Positive Polarity
Set-up Contents
High level adjustment
VRF0P[5:0]
Variable resistor VRHP
SELV0P[5:0]
The voltage of V0 grayscale is selected by the 64 to 1 selector
SELV1P[5:0]
The voltage of V1 grayscale is selected by the 64 to 1 selector
PK0P[5:0]
The voltage of V3 grayscale is selected by the 64 to 1 selector
PK1P[5:0]
The voltage of V6 grayscale is selected by the 64 to 1 selector
PK2P[5:0]
The voltage of V11 grayscale is selected by the 64 to 1 selector
PK3P[5:0]
The voltage of V19 grayscale is selected by the 64 to 1 selector
PK4P[5:0]
The voltage of V27 grayscale is selected by the 64 to 1 selector
PK5P[5:0]
The voltage of V36 grayscale is selected by the 64 to 1 selector
PK6P[5:0]
The voltage of V44 grayscale is selected by the 64 to 1 selector
PK7P[5:0]
The voltage of V52 grayscale is selected by the 64 to 1 selector
PK8P[5:0]
The voltage of V57 grayscale is selected by the 64 to 1 selector
PK9P[5:0]
The voltage of V60 grayscale is selected by the 64 to 1 selector
SELV62P[5:0]
The voltage of V62 grayscale is selected by the 64 to 1 selector
SELV63P[5:0]
The voltage of V63 grayscale is selected by the 64 to 1 selector
VOS0P[5:0]
Variable resistor VRLP
Mid level adjustment
Low level adjustment
V1.5
149
2009-12-04
ST7715
Flow Chart
V1.5
150
2009-12-04
ST7715
10.2.20 GMCTRN1 (E1h): Gamma ‘-’polarity Correction Characteristics Setting
E1H
Inst / Para
GMCTRP0 (Gamma ‘+’polarity Correction Characteristics Setting)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
GMCTRP1
0
↑
1
-
1
1
1
0
0
0
0
1
(E1h)
1st parameter
1
↑
1
-
-
-
VRF0N[5]
VRF0N[4]
VF0N[3]
VRF0N[2]
VRF0N[1]
VRF0N[0]
2 parameter
1
↑
1
-
-
-
VOS0N[5]
VOS0N[4]
VOS0N[3]
VOS0N[2]
VOS0N[1]
VOS0N[0]
3rd parameter
1
↑
1
-
-
-
PK0N[5]
PK0N[4]
PK0N[3]
PK0N[2]
PK0N[1]
PK0N[0]
4 parameter
1
↑
1
-
-
-
PK1N[5]
PK1N[4]
PK1N[3]
PK1N[2]
PK1N[1]
PK1N[0]
5th parameter
1
↑
1
-
-
-
PK2N[5]
PK2N[4]
PK2N[3]
PK2N[2]
PK2N[1]
PK2N[0]
6 parameter
1
↑
1
-
-
-
PK3N[5]
PK3N[4]
PK3N[3]
PK3N[2]
PK3N[1]
PK3N[0]
7th parameter
1
↑
1
-
-
-
PK4N[5]
PK4N[4]
PK4N[3]
PK4N[2]
PK4N[1]
PK4N[0]
8 parameter
1
↑
1
-
-
-
PK5N[5]
PK5N[4]
PK5N[3]
PK5N[2]
PK5N[1]
PK5N[0]
9th parameter
1
↑
1
-
-
-
PK6N[5]
PK6N[4]
PK6N[3]
PK6N[2]
PK6N[1]
PK6N[0]
th
1
↑
1
-
-
-
PK7N[5]
PK7N[4]
PK7N[3]
PK7N[2]
PK7N[1]
PK7N[0]
th
11 parameter
1
↑
1
-
-
-
PK8N[5]
PK8N[4]
PK8N[3]
PK8N[2]
PK8N[1]
PK8N[0]
12th parameter
1
↑
1
-
-
-
PK9[5]
PK9N[4]
PK9N[3]
PK9N[2]
PK9N[1]
PK9N[0]
13 parameter
1
↑
1
-
-
-
SELV0N[5] SELV0N[4] SELV0N[3] SELV0N[2] SELV0N[1] SELV0N[0]
14th parameter
1
↑
1
-
-
-
SELV1N[5] SELV1N[4] SELV1N[3] SELV1N[2] SELV1N[1] SELV1N[0]
15 parameter
1
↑
1
-
-
-
SELV62N[5] SELV62N[4] SELV62N[3] SELV62N[2] SELV62N[1] SELV62N[0]
16th parameter
1
↑
1
-
-
-
SELV63N[5] SELV63N[4] SELV63N[3] SELV63N[2] SELV63N[1] SELV63N[0]
nd
th
th
th
10 parameter
th
th
Description
D/CX WRX RDX D17-8
Register Group
Negative Polarity
Set-up Contents
High level adjustment
VRF0N[5:0]
Variable resistor VRHN
SELV0N[5:0]
The voltage of V0 grayscale is selected by the 64 to 1 selector
SELV1N[5:0]
The voltage of V1 grayscale is selected by the 64 to 1 selector
PK0N[5:0]
The voltage of V3 grayscale is selected by the 64 to 1 selector
PK1N[5:0]
The voltage of V6 grayscale is selected by the 64 to 1 selector
PK2N[5:0]
The voltage of V11 grayscale is selected by the 64 to 1 selector
PK3N[5:0]
The voltage of V19 grayscale is selected by the 64 to 1 selector
PK4N[5:0]
The voltage of V27 grayscale is selected by the 64 to 1 selector
PK5N[5:0]
The voltage of V36 grayscale is selected by the 64 to 1 selector
PK6N[5:0]
The voltage of V44 grayscale is selected by the 64 to 1 selector
PK7N[5:0]
The voltage of V52 grayscale is selected by the 64 to 1 selector
PK8N[5:0]
The voltage of V57 grayscale is selected by the 64 to 1 selector
PK9N[5:0]
The voltage of V60 grayscale is selected by the 64 to 1 selector
SELV62N[5:0]
The voltage of V62 grayscale is selected by the 64 to 1 selector
SELV63N[5:0]
The voltage of V63 grayscale is selected by the 64 to 1 selector
VOS0N[5:0]
Variable resistor VRLN
Mid level adjustment
Low level adjustment
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Flow Chart
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10.2.21 EXTCTRL (F0h): Extension Command Control
F0H
EXTCTRL (Extension command control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
EXTCTRL
0
↑
1
-
1
1
1
1
0
0
0
0
(F0h)
parameter
1
↑
1
0
0
0
0
0
0
0
1
(01h)
When EXTC PIN =”L”, this command will enable extension command.
Description
NOTE: “-“ Don’t care
Flow Chart
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10.2.22 VCOM4L (FFh): Vcom 4 Level Control
FFH
VCOM4L (Vcom 4 level control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
HEX
VCOM4L
0
↑
1
-
1
1
1
1
0
0
0
0
(FFh)
Parameter1
1
↑
1
-
Parameter2
1
↑
1
-
-
-
-
-
Parameter3
1
↑
1
-
0
0
0
1
Description
TC2[3] TC2[2] TC2[1] TC2[0] TC1[3] TC1[2] TC1[1] TC1[0]
TC3[3] TC3[2] TC3[1] TC3[0]
1
0
TC1[3:0]
Delay time
TC2[3:0]
Delay time
TC3[3:0]
Delay time
0000
0 clock
0000
0 clock
0000
0 clock
0001
1 clock
0001
1 clock
0001
1 clock
0010
2 clock
0010
2 clock
0010
2 clock
0011
3 clock
0011
3 clock
0011
3 clock
0100
4 clock
0100
4 clock
0100
4 clock
0101
5 clock
0101
5 clock
0101
5 clock
0110
6 clock
0110
6 clock
0110
6 clock
0111
7 clock
0111
7 clock
0111
7 clock
1000
8 clock
1000
8 clock
1000
8 clock
1001
9 clock
1001
9 clock
1001
9 clock
1010
10 clock
1010
10 clock
1010
10 clock
1011
11 clock
1011
11 clock
1011
11 clock
1100
12 clock
1100
12 clock
1100
12 clock
1101
13 clock
1101
13 clock
1101
13 clock
1110
14 clock
1110
14 clock
1110
14 clock
1111
15 clock
1111
15 clock
1111
15 clock
1
0
(1Ah)
NOTE: “-“ Don’t care
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Flow Chart
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11 Power structure
11.1 Driver IC Operating Voltage Specification
Fig 11.1.1 Power Booster Level
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11.2 Power Booster Circuit
11.2.1 Power Booster Circuit
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11.2.2 EXTERNAL COMPONENTS CONNECTION
Pad Name
Rated (Min)
Typical
Voltage
capacitance value
Connection
VDDI
VDDI (Logic Power)
6.3V
1.0 uF
VDD
VDD (Analog Power)
6.3V
1.0 uF
VCC
Connect to Capacitor: VCC -------||-------- GND
6.3V
1.0 uF
C41P, C41N
Connect to Capacitor: C41P -------||--- -----C41N
6.3V
1.0 uF
C22P, C22N
Connect to Capacitor: C22P -------||--------C22N
25.0V; 16.0V*
0.1 uF
C23P, C23N
Connect to Capacitor: C23P -------||--- -----C23N
25.0V; 16.0V*
0.1 uF
C11P, C11N
Connect to Capacitor: C11P -------||--------C11N
6.3V
1.0 uF
AVDD
Connect to Capacitor: AVDD -------||-------- GND
6.3V
1.0 uF
VGH
Connect to Capacitor: VGH -------||-------- GND
25.0V; 16.0V*
0.1 uF
VGL
Connect to Capacitor: VGL -------||-------- GND
25.0V; 16.0V*
0.1 uF
VCL
Connect to Capacitor: VCL -------||-------- GND
6.3V
1.0 uF
VCOMH
Connect to Capacitor: VCOMH-------||--------- GND
6.3V
1.0 uF
VCOML
Connect to Capacitor: VCOML -------||-------- GND
6.3V
1.0 uF
Note: For the typical specification of capacitor, the surge voltage is 125% of rated voltage. The capacitor of rated voltage of 16V can be
only used for the case of VGH < 12.8V and VGL > -12.8V to prevent from stability issue. For normal usage, please use the
capacitor of 25V rating.
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12 Gamma structure
12.1 TRUCTURE OF GRAYSCALE AMPLIFIER
The structure of grayscale amplifier is shown as below. 16 voltage levels (VIN0-VIN15) between GVDD and VGS are
determined by the high/ mid/ low level adjustment registers. Each mid-adjustment level is split into 64 levels again by the
internal ladder resistor network. As a result, grayscale amplifier generates 64 voltage levels ranging from V0 to V63 and
outputs one of 64 levels.
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12.2 Gamma Voltage Formula (Positive/ Negative Polarity)
Gray Level
Voltage Formula (Positive)
Voltage Formula (Negative)
0
VINP0
VINN0
1
VINP1
VINN1
2
VINP2
VINN2
3
VINP3
VINN3
4
V3-(V3-V6)*(11/30)
V3-(V3-V6)*(11/30)
5
V3-(V3-V6)*(21/30)
V3-(V3-V6)*(21/30)
6
VINP4
VINN4
7
V6-(V6-V11)*(7/30)
V6-(V6-V11)*(7/30)
8
V6-(V6-V11)*(14/30)
V6-(V6-V11)*(14/30)
9
V6-(V6-V11)*(20/30)
V6-(V6-V11)*(20/30)
10
V6-(V6-V11)*(25/30)
V6-(V6-V11)*(25/30)
11
VINP5
VINN5
12
V11-(V11-V19)*(4/32)
V11-(V11-V19)*(4/32)
13
V11-(V11-V19)*(8/32)
V11-(V11-V19)*(8/32)
14
V11-(V11-V19)*(12/32)
V11-(V11-V19)*(12/32)
15
V11-(V11-V19)*(16/32)
V11-(V11-V19)*(16/32)
16
V11-(V11-V19)*(20/32)
V11-(V11-V19)*(20/32)
17
V11-(V11-V19)*(24/32)
V11-(V11-V19)*(24/32)
18
V11-(V11-V19)*(28/32)
V11-(V11-V19)*(28/32)
19
VINP6
VINN6
20
V19-(V19-V27)*(4/32)
V19-(V19-V27)*(4/32)
21
V19-(V19-V27)*(8/32)
V19-(V19-V27)*(8/32)
22
V19-(V19-V27)* (12/32)
V19-(V19-V27)* (12/32)
23
V19-(V19-V27)* (1632/)
V19-(V19-V27)* (1632/)
24
V19-(V19-V27)* (20/32)
V19-(V19-V27)* (20/32)
25
V19-(V19-V27)* (24/32)
V19-(V19-V27)* (24/32)
26
V19-(V19-V27)* (28/32)
V19-(V19-V27)* (28/32)
27
VINP7
VINN7
28
V27-(V27-V36)* (4/36)
V27-(V27-V36)* (4/36)
29
V27-(V27-V36)* (8/36)
V27-(V27-V36)* (8/36)
30
V27-(V27-V36)* (12/36)
V27-(V27-V36)* (12/36)
31
V27-(V27-V36)* (16/36)
V27-(V27-V36)* (16/36)
32
V27-(V27-V36)* (20/36)
V27-(V27-V36)* (20/36)
33
V27-(V27-V36)* (24/36)
V27-(V27-V36)* (24/36)
34
V27-(V27-V36)* (28/36)
V27-(V27-V36)* (28/36)
35
V27-(V27-V36)* (32/36)
V27-(V27-V36)* (32/36)
36
VINP8
VINN8
37
V36-(V36-V44)*(4/32)
V36-(V36-V44)*(4/32)
38
V36-(V36-V44)*(8/32)
V36-(V36-V44)*(8/32)
39
V36-(V36-V44)*(12/32)
V36-(V36-V44)*(12/32)
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40
V36-(V36-V44)*(16/32)
V36-(V36-V44)*(16/32)
41
V36-(V36-V44)*(20/32)
V36-(V36-V44)*(20/32)
42
V36-(V36-V44)*(24/32)
V36-(V36-V44)*(24/32)
43
V36-(V36-V44)*(28/32)
V36-(V36-V44)*(28/32)
44
VINP9
VINN9
45
V44-(V44-V52)*(4/32)
V44-(V44-V52)*(4/32)
46
V44-(V44-V52)*(8/32)
V44-(V44-V52)*(8/32)
47
V44-(V44-V52)*(12/32)
V44-(V44-V52)*(12/32)
48
V44-(V44-V52)*(16/32)
V44-(V44-V52)*(16/32)
49
V44-(V44-V52)*(20/32)
V44-(V44-V52)*(20/32)
50
V44-(V44-V52)*(24/32)
V44-(V44-V52)*(24/32)
51
V44-(V44-V52)*(28/32)
V44-(V44-V52)*(28/32)
52
VINP10
VINN10
53
V52-(V52-V57)*(5/30)
V52-(V52-V57)*(5/30)
54
V52-(V52-V57)*(11/30)
V52-(V52-V57)*(11/30)
55
V52-(V52-V57)*(17/30)
V52-(V52-V57)*(17/30)
56
V52-(V52-V57)*(23/30)
V52-(V52-V57)*(23/30)
57
VINP11
VINN11
58
V57-(V57-V60)*(8/30)
V57-(V57-V60)*(8/30)
59
V57-(V57-V60)*(18/30)
V57-(V57-V60)*(18/30)
60
VINP12
VINN12
61
VINP13
VINN13
62
VINP14
VINN14
63
VINP15
VINN15
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13 Example Connection with Panel direction
13.1 Application of connection with panel direction
Case 1:
- 1st Pixel is at Left Top of the panel
- RGB filter order = RGB
IC (Bump down)
LCD Front side
CF Glass
TFT Glass
Case 2:
- 1st Pixel is at Left Top of the panel
- RGB filter order = BGR
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Case 3:
- 1st Pixel is at Righ Bottom of the panel
- RGB filter order = RGB
IC (Bump down)
LCD Front side
CF Glass
TFT Glass
Case 4:
- 1st Pixel is at Righ Bottom of the panel
- RGB filter order = BGR
IC (Bump down)
LCD Front side
CF Glass
TFT Glass
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13.2 Application of connection with 132RGB x 132 Resolution (GM[2:0] = “001”)
RAM size=132 x 132 x 18-bit
Display size = 132RGB x 132
1). Example for SMX=SMY=’0’
2). Example for SMX=SMY=’1’
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13.3 MicroProcessor Interface applications
8080-Seriers MCU + SPI Interface ( IM2=’1’)
13.3.1 8080-Series MCU Interface for 8-bit data bus (IM1, IM0=”00”)
Driver IC
Host
RESX
TE
RESX
TE
SCL
SDA
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
D/CX (SCL)
WRX
RDX
D7 to D1
D0
“0”
“0”
D/CX
WRX
RDX
D7 to D1
D0
D15 to D8
D17 to D16
”00”
IM2
IM1,IM0
IM2
Fig 13.3.1 8080 Series MCU Interface for 8-bit data bus
13.3.2 8080-Series MCU Interface for 16-bit data bus (IM1, IM0=”01”)
Driver IC
Host
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
RESX
TE
RESX
TE
SCL
SDA
D/CX (SCL)
WRX
RDX
D7 to D1
D0
“0”
“0”
D/CX
WRX
RDX
D7 to D1
D0
D15 to D8
D17 to D16
”01”
IM1,IM0
IM2
IM2
Fig 13.3.2 8080 Series MCU Interface for 16-bit data bus
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13.3.3 8080-Series MCU Interface for 9-bit data bus (IM1, IM0=”10”)
Driver IC
Host
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
RESX
TE
RESX
TE
SCL
SDA
D/CX (SCL)
WRX
RDX
D8 o D1
D0
“0”
“0”
D/CX
WRX
RDX
D8 o D1
D0
D15 to D9
D17 to D16
“10”
IM2
IM1,IM0
IM2
Fig 13.3.3 8080 Series MCU Interface for 9-bit data bus
13.3.4 8080-Series MCU Interface for 18-bit data bus (IM1, IM0=”11”)
Driver IC
Host
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
RESX
TE
RESX
TE
SCL
SDA
D/CX (SCL)
WRX
RDX
D7 to D1
D0
D17 to D8
D/CX
WRX
RDX
D7 to D1
D0
D17 to D8
”11”
IM2
IM1,IM0
IM2
Fig. 13.3.4 8080 Series MCU Interface for 18-bit data bus
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14 Revision History
ST7715 Specification Revision History
Version
Date
1.0
2008/11/27
Description
First issue.
Modify features description (P1)
Modify TESEL description (P15)
Modify address counter sections reference (P56)
Modify reset table sections reference (P66)
1.1
2009/01/05
Modify DISPOFF(28h) and DISPON(29h) command description (P96~97)
Modify frame rate control (B1~B3h) description (P122~124)
Modify ROM code default value (P122~145)
Modify external components table, AVDD capacitance value change and schottky diode remove.
(P157~158)
Modify VCC maximum absolute operating voltage (P18)
1.2
2009/03/09
Modify power consumption condition (P20)
Modify VMCTR1(C5h) command restriction (P139)
V1.5
1.3
2009/8/5
1.4
2009/09/23
Modify EXTC description.(P14)
Modify VCI1 description to Hi-Z.(P16)
1.5
2009/12/04
Modify DISSET5 (B6h) command (P126)
Modify the parameter of command 0xDF.(P148)
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