ILI9163 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Datasheet Version: V0.18 Document No.: ILI9163DS_V0.18.pdf ILI TECHNOLOGY CORP. 8F, No.38, Taiyuan St., Jhubei City, Hsinchu County, Taiwan 302, R.O.C. Tel.886-3-5600099; Fax.886-3-56--00585 http://www.ilitek.com http://www.ilitek.com a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 1. Introduction ................................................................................................................................................ 6 2. Features..................................................................................................................................................... 6 3. Block Diagram............................................................................................................................................ 8 4. Pin Descriptions ......................................................................................................................................... 9 5. Pad Arrangement and Coordination ........................................................................................................ 14 6. Function Description ................................................................................................................................ 20 6.1. MCU Interface Type Selection........................................................................................................... 20 6.2. Serial Interface .................................................................................................................................. 20 6.2.1 Command Write ............................................................................................................................... 20 6.2.2 Read Function .................................................................................................................................. 21 6.3. 8080-Series Parallel Interface (P68=’0’) ........................................................................................... 24 6.3.1 Write Cycle/Sequence...................................................................................................................... 24 6.3.2 Read Cycle/Sequence ..................................................................................................................... 25 6.4. 6800-Series Parallel Interface (P68=’1’) ........................................................................................... 27 6.4.1 Write Cycle/Sequence...................................................................................................................... 28 6.4.2 Read Cycle/Sequence ..................................................................................................................... 29 6.5. Display Data Transfer Recovery........................................................................................................ 30 6.6. Display Data Transfer Pause............................................................................................................. 31 6.6.1 Serial Interface Pause...................................................................................................................... 32 6.7. Display Data Transfer Mode.............................................................................................................. 32 6.8. Display Data Color Coding ................................................................................................................ 34 6.8.1 Serial Interface ................................................................................................................................. 34 6.8.3 16-bit Parallel Interface (IM2=’1’, IM1, IM0=”01”) ............................................................................ 41 6.8.4 9-bit Parallel Interface (IM2=’2’, IM1, IM0=”10”) .............................................................................. 44 6.8.5 18-bit Parallel Interface (IM2=’1’, IM1, IM0=”11”)............................................................................. 45 7. Display Data RAM.................................................................................................................................... 48 7.1. Configuration ..................................................................................................................................... 48 7.2. Memory to Display Address Mapping................................................................................................ 49 7.2.1 132RGB x 132 resolution (GM[2:0] = “101”, SMX=SMY=SRGB=’0’) .............................................. 49 7.2.2 130RGB x 130 resolution(GM[2:0] = “100”, SMX=SMY=SRGB=’0’) ............................................... 50 7.2.3 128RGB x 160 resolution (GM[2:0] = “011”, SMX=SMY=SRGB=’0’) .............................................. 51 7.2.4 120RGB x 160 resolution (GM[2:0] = “010”, SMX=SMY=SRGB=’0’) .............................................. 52 7.2.5 128RGB x 128 resolution (GM[2:0] = “001”, SMX=SMY=SRGB=’0’) .............................................. 53 7.2.6 132RGB x 162 resolution (GM[2:0] = “000”, SMX=SMY=SRGB=’0’) .............................................. 54 7.3. 8. MCU to memory write/read direction (Address Counter) .................................................................. 55 Tearing Effect Output Line ....................................................................................................................... 57 8.1. Tearing Effect Line Modes................................................................................................................. 57 8.2. Tearing Effect Line Timing ................................................................................................................. 58 8.2.1 Example 1 MCU Write is Faster than Panel Read........................................................................... 59 8.2.2 Example 2 MCU Write is slower than Panel Read........................................................................... 59 Page 2 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color 9. ILI9163 Power ON/OFF Sequence....................................................................................................................... 61 9.1. Case 1 – RESX line is held high or Unstable by Host at Power –On ............................................... 61 9.2. Case 2 – RESX line is held Low by Host at Power On ..................................................................... 61 9.3. Uncontrolled Power Off ..................................................................................................................... 62 10. Power Level Definition ............................................................................................................................. 62 10.1. Power Levels ..................................................................................................................................... 62 10.2. Power Flow Chart.............................................................................................................................. 64 11. Gamma Curves........................................................................................................................................ 65 12. Reset........................................................................................................................................................ 66 12.1. Registers ........................................................................................................................................... 66 12.2. Input/Output Pins............................................................................................................................... 71 12.2.1 Output Pins, I/O Pins...................................................................................................................... 71 12.2.2 Input Pins ....................................................................................................................................... 72 12.3. 13. Reset Timing...................................................................................................................................... 72 SleepOut – Command and Self-Diagnostic Functions of Display ........................................................... 73 13.1. Register loading Detection ................................................................................................................ 73 13.2. Functionality Detection ...................................................................................................................... 74 14. Command ................................................................................................................................................ 76 14.1. Command List ................................................................................................................................... 76 14.2. Command Description....................................................................................................................... 78 14.2.1 NOP (00h) ...................................................................................................................................... 78 14.2.2 Software Reset (01h) ..................................................................................................................... 79 14.2.3 Read Display Identification Information (04h) ................................................................................ 80 14.2.4 Read Display Status (09h) ............................................................................................................. 81 14.2.5 Read Display Power Mode (0Ah)................................................................................................... 84 14.2.6 Read Display MADCTL (0Bh) ........................................................................................................ 85 14.2.7 Read Display Pixel Format (0Ch)................................................................................................... 86 14.2.8 Read Display Image Mode (0Dh)................................................................................................... 87 14.2.9 Read Display Signal Mode (0Eh) ................................................................................................... 88 14.2.10 Read Display Signal Mode (0Fh) ................................................................................................. 89 14.2.11 Sleep In (10h) ............................................................................................................................... 90 14.2.12 Sleep Out (11h) ............................................................................................................................ 91 14.2.13 Partial Mode On (12h).................................................................................................................. 93 14.2.14 Normal Display Mode On (13h).................................................................................................... 94 14.2.15 Display Inversion Off (20h)........................................................................................................... 95 14.2.16 Display Inversion On (21h)........................................................................................................... 96 14.2.17 Gamma Set (26h)......................................................................................................................... 97 14.2.18 Display Off (28h) .......................................................................................................................... 98 14.2.19 Display On (29h) ........................................................................................................................ 100 14.2.20 Column Address Set (2Ah)......................................................................................................... 102 Page 3 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.21 Page Address Set (2Bh)............................................................................................................. 105 14.2.22 Memory Write (2Ch) ................................................................................................................... 108 14.2.23 Color Setting fro 4K, 65K and 262K (2Dh)................................................................................. 110 14.2.24 Memory Read (2Eh)....................................................................................................................111 14.2.25 Partial Area (30h) ....................................................................................................................... 112 14.2.26 Vertical Scrolling Definition (33h) ............................................................................................... 114 14.2.27 Tearing Effect Line Off (34h) ...................................................................................................... 119 14.2.28 Tearing Effect Line On (35h) ...................................................................................................... 120 14.2.29 Memory Access Control (36h).................................................................................................... 122 14.2.30 Vertical Scrolling Start Address (37h)......................................................................................... 124 14.2.31 Idle Mode Off (38h) .................................................................................................................... 126 14.2.32 Idle Mode On (39h) .................................................................................................................... 127 14.2.33 Interface Pixel Format (3Ah) ...................................................................................................... 129 14.2.34 Read ID1 (DAh).......................................................................................................................... 130 14.2.35 Read ID2 (DBh).......................................................................................................................... 131 14.2.36 Read ID3 (DCh).......................................................................................................................... 132 14.2.38 Frame Rate Control(In normal mode/Full colors) (B1h)............................................................. 133 14.2.39 Frame Rate Control(In Idle mode/8-colors) (B2h)...................................................................... 134 14.2.40 Frame Rate Control(In Partial mode/full colors) (B3h)............................................................... 136 14.2.41 Display Inversion Control (B4h) ................................................................................................. 138 14.2.44 Source Driver Direction Control (B7h) ....................................................................................... 139 14.2.45 Gate Driver Direction Control (B8h) ........................................................................................... 140 14.2.46 Power_Control1 (C0h) ............................................................................................................... 141 14.2.47 Power_Control2 (C1h) ............................................................................................................... 143 14.2.48 Power_Control3 (C2h) ............................................................................................................... 144 14.2.49 Power_Control4 (C3h) ............................................................................................................... 146 14.2.50 Power_Control 5 (C4h) .............................................................................................................. 148 14.2.51 VCOM_Control 1 (C5h).............................................................................................................. 150 14.2.52 VCOM_Control 2 (C6h).............................................................................................................. 151 14.2.53 VCOM Offset Control (C7h) ....................................................................................................... 152 14.2.54 Write ID4 Value (D3h) ................................................................................................................ 154 14.2.55 NV Memory Function Controller (D7h)....................................................................................... 156 14.2.56 NV Memory Function Controller 2(DEh) .................................................................................... 157 14.2.57 Positive Gamma Correction Setting (E0h) ................................................................................. 158 14.2.58 Negative Gamma Correction Setting (E1h) ............................................................................... 160 14.2.59 GAM_R_SEL (F2h) .................................................................................................................... 162 15. Example Connection with Panel direction and Different Resolution...................................................... 163 15.1. Application of connect with panel direction (when GM=’011’)......................................................... 163 15.2. Application of connection with Different resolution.......................................................................... 166 16. OTP Programming Flow ........................................................................................................................ 175 Page 4 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color 17. ILI9163 Electrical Characteristics........................................................................................................................ 176 17.1. Absolute Maximum Ratings............................................................................................................. 176 17.2. DC Characteristics .......................................................................................................................... 177 17.3. AC Characteristics........................................................................................................................... 178 17.4. Display Module Parallel 18/16/9/8-bit Bus ...................................................................................... 178 17.5. Display Serial Interface ................................................................................................................... 179 17.5.1 3-pin Serial Interface .................................................................................................................... 179 17.5.2 4-pin Serial Interface .................................................................................................................... 180 17.6. 18. Reset Timing Characteristics........................................................................................................... 182 Revision History ..................................................................................................................................... 183 Page 5 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 1. Introduction ILI9163 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 132RGBx162 dots, comprising a 396-channel source driver, a 162-channel gate driver, 48,114bytes GRAM for graphic data of 132RGBx162 dots, and power supply circuit. The ILI9163 supports 18-/16-/9-/8-bit data bus interface and serial peripheral interfaces (SPI). The moving picture area can be specified in internal GRAM by window address function. The specified window area can be updated selectively, so that moving picture can be displayed simultaneously independent of still picture area. ILI9163 can operate with 1.65V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD. The ILI9163 also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the ILI9163 an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, MP3 and PMP where long battery life is a major concern. 2. Features Display resolution: [132xRGB](H) x 162(V) Output: ¾ 396 source outputs ¾ 162 gate outputs ¾ Common electrode output AM-LCD driver with on-chip full display RAM: 48,114 bytes MCU Interface ¾ 8-bits, 9-bits, 16-bits, 18-bits interface with 8080-series MCU ¾ 8-bits, 9-bits, 16-bits, 18-bits interface with 6800-series MCU ¾ 3-pin/4-pin serial interface Display mode: ¾ Full color mode (idle mode off): 262K-colors ¾ Reduced color mode (idle mode on): 8-colors (3-bits MSB bits mode) On chip functions: ¾ VCOM generator and adjustment ¾ Timing generator ¾ Oscillator ¾ DC/DC converter ¾ 8 preset gamma curve selectable ¾ Line/frame inversion ¾ MTP to store initialization register setting ¾ Factory default value(Contrast, Module ID, Module version, etc) are stored on the display module MTP: ¾ 7-bits for ID2 Page 6 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 ¾ 8-bits for ID3 ¾ 7-bits for VCOM adjustment Low –power consumption architecture ¾ Low operating power supplies: VDDI = 1.65V ~ 3.3 V (interface I/O) VDD = 2.6V ~ 3.3 V (analog) LCD Voltage drive: ¾ Source/VCOM power supply voltage AVDD – GND = 4.5V ~ 6.0 VCL – GND = -1.0V ~ -3.0V VDD – VCL ≦ 6.0V ¾ Gate driver output voltage VGH – GND = 10V ~ 16V VGL – GND = -9V ~ -16V VGH – VGL ≦ 32V ¾ VCOM driver output voltage VCOMH = 2.5V ~5V VCOML = -2.5V ~ 0V VCOMH-VCOML ≦ 6.0V Operate temperature range: -40℃ to 85℃ Page 7 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 3. Block Diagram GS RCM[1:0] REV LCM[1:0] TESEL SMY SMX SRGB EXTC RCM[1:0] IDM GM[2:0] P68 Register Address IM[2:0] SPI4W RESX 8 CSX MPU I/F 18-bit 16-bit 9-bit 8-bit D/CX(SCL) RDX(E) WRX(R/WX) D[0]/SDIO 8 Control Register Address Counter LCD Source Driver S[396:1] D[17:1] SPI I/F 18 SDA VDDI 18 Look-Up Table VSYNC I/F V63 ~ 0 GND 18 Read Latch Write Latch 72 Regulator LCD Gate Driver Timing Controller VDD VCOM Generator VGH C23- VGL C23+ C22- C21- C22+ VCL C12+ AVDD C11- VCI1 C11+ C21+ Charge-pump Power Circuit GND Page 8 of 183 VCOMH OSC. C12- OSC 72 GVDD Graphics RAM (GRAM) VCC VREF Grayscale Reference Voltage G[162:1] VCOM VCOML TE Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 4. Pin Descriptions Pin Name P68 IM2 I/O I I Descriptions 8080/6800 MCU Interface mode selection. P68=’1’: select 6800-MCU parallel interface P68=’0’: select 8080-MCU parallel interface If not used, please fix this pin at GND level. MCU Parallel interface bus and Serial interface select - IM2=’1’;Parallel Interface - IM2=’0’;Serial Interface MCU parallel interface type selection IM1, IM0 I IM1 IM0 Parallel interface 0 0 MCU 8-bit Parallel 0 1 MCU 16-bit Parallel 1 0 MCU 9-bit Parallel 1 1 MCU 18-bit Parallel SPI interface selection pin SPI4W I SPI4W=’0’: 3-wire SPI. (default) SPI4W=’1’: 4-wire SPI. This pin is internal pull low. Chip reset pin (“Low Active”). RESX I This signal low will reset the device and must be applied to properly initialize the chip. CSX I Chip select input pin (“Low” enable). This pin can be permanently fixed “Low” in MCU interface mode only. Display data / Command selection pin in parallel and SCL in 3-pin SPI interface. D/CX (SCL) I D/CX=’1’: Display data. D/CX=’0’: Command data. If not used, please connect this pin to GND. Read enable in 8080-parallel interface and Read/ Write operation enable pin in RDX (E) I 6800-parallel interface. If not used, please connect this pin to GND. Write enable in parallel interface. WRX: for 8080 MCU WRX (R/Wx)(D/CX) I R/WX: for 6800 MCU D/CX: for 4-wire SPI If not used, please connect to ground or VDDI this pin. When– RCM=’0’ (MCU I/F), D[17:0] are used to MCU parallel interface data bus, D[17:1] D[0]/SDIO I/O and D0 is also the serial input/ output signal in SPI interface mode. In serial interface, D[17:1] are not used and should be connected to ground. TE O Tearing effect output pin to synchronies MCU to frame writing, activated by S/W command. When this pin is not activated, this pin is low. Page 9 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Pin Name I/O ILI9163 Descriptions If not used, please open this pin. SDA I/O OSC O When RCM[1:0]= ’0X’ (MCU I/F), This pin is not used, and fix at GND level. -If it’s not used, please fix this pin at GND level. Oscillator output or test purpose. To use extended command set, please connect this pin to VDDI. During normal operation, please open this pin. (It has an internal pull low resistor.) EXTC I EXTC=’1’, all the command can be used. EXTC=’0’, only Command (00h~3Ah, Dah~DCh) can be used Normal mode and Idle mode control pin IDM IDM 0 1 I Idle mode H/W controller Normal display (can be changed to Idle mode by S/W) Into Idle mode Panel Resolution selection pins GM2,GM1,GM0 I GM2 GM1 GM0 Resolution selection 0 0 0 132RGB x 162(S1~396 and G1~ G162 output) 0 0 1 128RGB x 128(S7~390 and G2~ G129 output) 0 1 0 120RGB x 160(S7~366 and G2~ G161 output) 0 1 1 128RGB x 160(S7~390 and G2~ G161 output) 1 0 0 130RGB x 130(S7~396 and G2~ G131 output) 1 0 1 132RGB x 132(S1~396 and G2~ G133 output) MCU interface mode selection pin RCM[1:0] RCM1 0 0 1 1 I RCM0 0 1 0 1 Resolution selection MCU interface mode MCU interface mode Setting prohibited Setting prohibited RGB direction select H/W pin for Color filter default setting. SRGB I SRGB 0 1 Color mapping selection S1, S2, S3 filter order = ’R’, ‘G’, ‘B’ S1, S2, S3 filter order = ’B’, ‘G’, ‘R’ If the register is not changed, this H/W pin is always valid. If the register be changed, should be following registers setting. When Power On or H/W reset, this function follow H/W pins setting first. Source output direction H/W select pin SMX I SMX 0 1 GM=’101’ S1 Æ S396 S396 Æ S1 GM=’100’ S7 Æ S396 S396 Æ S7 Source Output Direction GM=’011’ GM=’010’ S7 Æ S390 S7 Æ S366 S390 Æ S7 S366 Æ S7 GM=’001’ S7 Æ S390 S390 Æ S7 GM=’000’ S1 Æ S396 S396 Æ S1 If the register is not changed, this H/W pin is always valid. If the register be Page 10 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Pin Name I/O ILI9163 Descriptions changed, should be following registers setting. When Power On or H/W reset, Gate output direction H/W select pin Gate Output Direction SMY SMY I 0 1 GM=’101’ G2 Æ G133 GM=’100’ G2 Æ G131 GM=’011’,’010’ G2 Æ G161 GM=’001’ G2 Æ G129 GM=’000’ G1 Æ G162 G133 Æ G2 G131 Æ G2 G161 Æ G2 G129 Æ G2 G162 Æ G1 If the register is not changed, this H/W pin is always valid. If the register be changed, should be following registers setting. When Power On or H/W reset, this function follow H/W pins setting first. Source output data polarity select H/W pin. REV I REV 0 1 Source output data polarity Data not reverse Data reverse If the register is not changed, this H/W pin is always valid. If the register be changed, should be following registers setting. When Power On or H/W reset, this function follow H/W pins setting first. Different Liquid Crystal type selection pins. There is a pull-low resistor only in LCM1 pin LCM[1:0] I LCM1 LCM0 LC Type Selection 0 0 TR (Transflective) LC Type 0 1 TM (Transmission) LC Type1 1 0 TM (Transmission) LC Type2 1 1 MVA-TM/TR LC type Input pin to select the gamma curve order GS I Connect to VDDI for GC0(2,0), GC1(1.8), GC2(2.5), GC3(1.0) Connect to GND for GC0(1,0), GC1(2.5), GC2(2.2), GC3(1.8) There is a pull-high resistor in the pin. TESEL I This pin is only for GM[2:0]=’000’ mode Connect to VDDI (Disable scroll function) Connect to GND (Enable scroll function) S1 ~ S396 O Source driver output pins. G1 ~ G162 O Gate driver output pins. VDD P VDDI P VDDI voltage level for interface control pins. VCC P Power supply for internal logic regulator. GND P GND voltage output level for control pins. Power supply to liquid crystal power supply analog circuit. Connect to external power supply (VDD=2.5~3.3V). Page 11 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Pin Name I/O Descriptions VDDIO P VDDI voltage output level for control pins using. GNDO P GND voltage output level for control pins using. VCI1 I/O ILI9163 A reference voltage in step-up circuit 1 Connect a capacitor for stabilization A power output pin for source driver block that is generated from power block. AVDD P Output of booster 1 circuit (output of 2-times output of VCI1) Connect a capacitor for stabilization. VCL P VREF - GVDD P VGH P VGL P VCL P C11+, C11-, C12+, C12- O C21+, C21-, C22+, C22-, A power supply pin for generating VCOML Connect a capacitor for stabilization Floating pin. Leave this pin as open. A standard level for grayscale voltage generator. Connect a capacitor for stabilization. Positive voltage of the Booster circuit Connect a capacitor for stabilization Negative voltage of the Booster circuit 3 Connect a capacitor for stabilization Power supply to drive VCOML. Connect a capacitor for stabilization Make sure to connect to capacitor that is used in internal step-up circuit 1. Make sure to connect to capacitor that is used in internal step-up circuit 2. O Connect to capacitors according to the step-up factors in use. C23+, C23TFT display common electrode power supply. Alternates between voltage levels VCOM O between VCOMH-VCOML. Registers set the alternating cycle. Registers set the alternating cycle and operate or halt VCOM. VCOMH O VCOML O DUMMY_TEST DUMMY_TESTOSC I DUMMY_TESTDA[6:0] DUMMY_VPRER_OUT O DUMMYR1-DUMMYR2 - DUMMY1-DUMMY18 - Positive voltage output of VCOM Connect a capacitor for stabilization Negative voltage output of VCOM Connect a capacitor for stabilization These test pins for Driver vender test used. Please open these pins or fix to GND. These test pins for Driver vendor test used. Please open these pins. DUMMYR1 and DUMMYR2 are short-circuited within the chip for COG contact resistance measurement. Please leave them open when not used. -These pins are dummy (not have any function inside) -Can have signal traces pass through on TFT glass under the PAD Page 12 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Liquid crystal power supply specifications Table 1 No. 1 2 3 4 5 6 7 Item TFT Source Driver TFT Gate Driver TFT Display’s Capacitor Structure S1 ~ S396 Liquid Crystal Drive Output G1 ~ G162 VCOM VDDI Input Voltage VDD AVDD VGH VGL Liquid Crystal Drive Voltages VCL VGH – VGL VDD – VCL AVDD VGH Internal Step-up Circuits VGL VCL Description 396 pins (132 x RGB) 162 pins Cst structure only (Common VCOM) V0 ~ V63 grayscales VGH – VGL VCOMH – VCOML: Amplitude = electronic volumes 1.65 ~ 3.30V 2.60 ~ 3.30V 4.5V ~ 6.0V 10V ~ 16V -9V ~ -16V -1.7V ~ -2.7V Max. 32V Max. 6.0V VCI1 x2 VCI1 x4, x5, x6 VCI1 x-3, x-4, x-5 VCI1 x-1 Page 13 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 5. Pad Arrangement and Coordination 7 5 9 Chip Size: 9900um x 670um 15um 15um 20um 15um 15um ………………………. ………………………. 1 8 0 1 8 5 1 8 6 Page 14 of 183 ………………………. 15um 1 7 0 (4841, -220) Face Up (Bump View) 1 6 0 15um ………………………. 20um S389 S390 S391 S392 S393 S394 S395 S396 DUMMY8 DUMMY7 DUMMY6 DUMMY5 G2 G4 G6 G8 1 5 0 80um 15um ………………………. 10um ………………………. 15um 1 4 0 10um 1 3 0 80um 1 2 0 Alignment Mark-Right Y 20um 15um 15um X 15um 15um 15um 1 1 0 (-4841, -220) DUMMY10 DUMMY9 S199 S200 S201 S202 S203 S204 S205 S206 S207 S208 1 0 0 15um 392um 20um 9 0 80um Chip Center 15um S189 S190 S191 S192 S193 S194 S195 S196 S197 S198 DUMMY12 DUMMY11 8 0 41 19 10um ………………………. 19 15um 7 0 80um 10um 6 0 41 5 0 32 Alignment Mark-Left G7 G5 G3 G1 DUMMY16 DUMMY15 Dummy14 DUMMY13 S1 S2 S3 S4 S5 S6 S7 S8 4 0 15 35 15 35 3 0 75 2 0 Au bump height: 15 +-3 um ………………………. Coordinate Origin: Chip Center 1 0 Pad Location: Pad Center. DUMMY18 DUMMY17 G161 G159 G157 G155 G153 G151 G149 G147 1 Chip thickness : 300 um (typ.)/400um Dummy1 VDDIO EXTC GNDO IM0 VDDIO IM1 GNDO P68 VDDIO RCM0 GNDO RCM1 VDDIO SRGB GNDO SMX VDDIO SMY GNDO IDM VDDIO REV GNDO RL VDDIO TB GNDO SHUT VDDIO LCM0 GNDO LCM1 VDDIO GM2 GNDO GM1 VDDIO GM0 GNDO SDA GS SPI4W VDDIO TESTDA[6] TESTDA[5] TESTDA[4] TESTDA[3] TESTOSC OSC VDD VDD VDD VDD VDD VDD AGND AGND AGND AGND AGND AGND RDX D/CX TESEL GNDO D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D1 D3 D5 D7 TE RESX CSX D6 D4 D2 IM2 D0 WRX PCLK DE HS VS TESTDA[2] TESTDA[1] TESTDA[0] GND GND GND GND GND GND VDDI VDDI VDDI VDDI VDDI VDDI VCC VCC VCC VCI1 VCI1 VCI1 VREF VREF VREF TEST VPRER_OUT AVDD AVDD AVDD AVDD AVDD GVDD GVDD GVDD DUMMYR1 DUMMYR2 C11A C11A C11A C11A C11B C11B C11B C11B C12A C12A C12A C12A C12B C12B C12B C12B AGND AGND AGND VCL VCL VCL C21A C21A C21A C21B C21B C21B C22A C22A C22A C22B C22B C22B C23A C23A C23A C23B C23B C23B VGL VGL VGL VGH VGH VGH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOM VCOM VCOM DUMMY2 G148 G150 G152 G154 G156 G158 G160 G162 DUMMY4 DUMMY3 Version: 0.18 4 0 5 0 … … … … … … … … … . … … … … … … … … … . 6 0 7 0 8 0 Y 392um Chip Center 9 0 1 0 0 X 1 1 0 … … … … … … … … … . 3 0 1 2 0 … … … … … … … … … . … … … … … … … … … . … … … … … … … … … . 2 0 1 3 0 1 4 0 1 5 0 1 6 0 … … … … … … … … … . 1 0 1 7 0 … … … … … … … … … . 7 5 9 1 1 8 0 1 8 5 1 8 6 Version: 0.18 Page 15 of 183 ILI9163 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color No. Name X Y X Y No. Name No. Name No. Name 1 Dummy1 -4750 -238.5 61 AGND -1750 -238.5 121 AVDD 1550 -238.5 181 VCOML 4550 -238.5 241 G56 3892 227 2 VDDIO -4700 -238.5 62 AGND -1700 -238.5 122 AVDD 1600 -238.5 182 VCOM 4600 -238.5 242 G54 3876 110 3 EXTC -4650 -238.5 63 RDX -1630 -238.5 123 AVDD 1650 -238.5 183 VCOM 4650 -238.5 243 G52 3860 227 4 GNDO -4600 -238.5 64 D/CX -1570 -238.5 124 AVDD 1700 -238.5 184 VCOM 4700 -238.5 244 G50 3844 110 5 IM0 -4550 -238.5 65 TESEL -1510 -238.5 125 GVDD 1750 -238.5 185 DUMMY2 4750 -238.5 245 G48 3828 227 6 VDDIO -4500 -238.5 66 GNDO -1450 -238.5 126 GVDD 1800 -238.5 186 DUMMY3 4772 110 246 G46 3812 110 7 IM1 -4450 -238.5 67 D17 -1390 -238.5 127 GVDD 1850 -238.5 187 DUMMY4 4756 227 247 G44 3796 227 8 GNDO -4400 -238.5 68 D16 -1330 -238.5 128 DUMMYR1 1900 -238.5 188 G162 4740 110 248 G42 3780 110 9 P68 -4350 -238.5 69 D15 -1270 -238.5 129 DUMMYR2 1950 -238.5 189 G160 4724 227 249 G40 3764 227 10 VDDIO -4300 -238.5 70 D14 -1210 -238.5 130 190 G158 4708 110 250 G38 3748 110 C11+ X Y 2000 -238.5 No. Name ILI9163 X Y X Y 11 RCM0 -4250 -238.5 71 D13 -1150 -238.5 131 C11+ 2050 -238.5 191 G156 4692 227 251 G36 3732 227 12 GNDO -4200 -238.5 72 D12 -1090 -238.5 132 C11+ 2100 -238.5 192 G154 4676 110 252 G34 3716 110 13 RCM1 -4150 -238.5 73 D11 -1030 -238.5 133 C11+ 2150 -238.5 193 G152 4660 227 253 G32 3700 227 14 VDDIO -4100 -238.5 74 D10 -970 -238.5 134 C11- 2200 -238.5 194 G150 4644 110 254 G30 3684 110 15 SRGB -4050 -238.5 75 D9 -910 -238.5 135 C11- 2250 -238.5 195 G148 4628 227 255 G28 3668 227 16 GNDO -4000 -238.5 76 D8 -850 -238.5 136 C11- 2300 -238.5 196 G146 4612 110 256 G26 3652 110 17 SMX -3950 -238.5 77 D1 -790 -238.5 137 C11- 2350 -238.5 197 G144 4596 227 257 G24 3636 227 18 VDDIO -3900 -238.5 78 D3 -730 -238.5 138 C12+ 2400 -238.5 198 G142 4580 110 258 G22 3620 110 19 SMY -3850 -238.5 79 D5 -670 -238.5 139 C12+ 2450 -238.5 199 G140 4564 227 259 G20 3604 227 20 GNDO -3800 -238.5 80 D7 -610 -238.5 140 C12+ 2500 -238.5 200 G138 4548 110 260 G18 3588 110 21 IDM -3750 -238.5 81 TE -550 -238.5 141 C12+ 2550 -238.5 201 G136 4532 227 261 G16 3572 227 22 VDDIO -3700 -238.5 82 RESX -490 -238.5 142 C12- 2600 -238.5 202 G134 4516 110 262 G14 3556 110 23 REV -3650 -238.5 83 CSX -430 -238.5 143 C12- 2650 -238.5 203 G132 4500 227 263 G12 3540 227 24 GNDO -3600 -238.5 84 D6 -370 -238.5 144 C12- 2700 -238.5 204 G130 4484 110 264 G10 3524 110 25 RL -3550 -238.5 85 D4 -310 -238.5 145 C12- 2750 -238.5 205 G128 4468 227 265 G8 3508 227 26 VDDIO -3500 -238.5 86 D2 -250 -238.5 146 AGND 2800 -238.5 206 G126 4452 110 266 G6 3492 110 27 TB -3450 -238.5 87 IM2 -190 -238.5 147 AGND 2850 -238.5 207 G124 4436 227 267 G4 3476 227 28 GNDO -3400 -238.5 88 D0 -130 -238.5 148 AGND 2900 -238.5 208 G122 4420 110 268 G2 3460 110 29 SHUT -3350 -238.5 89 WRX -70 -238.5 149 VCL 2950 -238.5 209 G120 4404 227 269 DUMMY5 3444 227 30 VDDIO -3300 -238.5 90 PCLK 0 -238.5 150 VCL 3000 -238.5 210 G118 4388 110 270 DUMMY6 3428 110 31 LCM0 -3250 -238.5 91 DE 50 -238.5 151 VCL 3050 -238.5 211 G116 4372 227 271 DUMMY7 3412 227 32 GNDO -3200 -238.5 92 HS 100 -238.5 152 C21+ 3100 -238.5 212 G114 4356 110 272 DUMMY8 3396 110 33 LCM1 -3150 -238.5 93 VS 150 -238.5 153 C21+ 3150 -238.5 213 G112 4340 227 273 S396 3380 227 34 VDDIO -3100 -238.5 94 TESTDA[2] 200 -238.5 154 C21+ 3200 -238.5 214 G110 4324 110 274 S395 3364 110 35 GM2 -3050 -238.5 95 TESTDA[1] 250 -238.5 155 C21- 3250 -238.5 215 G108 4308 227 275 S394 3348 227 36 GNDO -3000 -238.5 96 TESTDA[0] 300 -238.5 156 C21- 3300 -238.5 216 G106 4292 110 276 S393 3332 110 37 GM1 -2950 -238.5 97 GND 350 -238.5 157 C21- 3350 -238.5 217 G104 4276 227 277 S392 3316 227 38 VDDIO -2900 -238.5 98 GND 400 -238.5 158 C22+ 3400 -238.5 218 G102 4260 110 278 S391 3300 110 39 GM0 -2850 -238.5 99 GND 450 -238.5 159 C22+ 3450 -238.5 219 G100 4244 227 279 S390 3284 227 40 GNDO -2800 -238.5 100 GND 500 -238.5 160 C22+ 3500 -238.5 220 G98 4228 110 280 S389 3268 110 41 SDA -2750 -238.5 101 GND 550 -238.5 161 C22- 3550 -238.5 221 G96 4212 227 281 S388 3252 227 42 GS -2700 -238.5 102 GND 600 -238.5 162 C22- 3600 -238.5 222 G94 4196 110 282 S387 3236 110 43 SPI4W -2650 -238.5 103 VDDI 650 -238.5 163 C22- 3650 -238.5 223 G92 4180 227 283 S386 3220 227 44 VDDIO -2600 -238.5 104 VDDI 700 -238.5 164 C23+ 3700 -238.5 224 G90 4164 110 284 S385 3204 110 45 TESTDA[6] -2550 -238.5 105 VDDI 750 -238.5 165 C23+ 3750 -238.5 225 G88 4148 227 285 S384 3188 227 46 TESTDA[5] -2500 -238.5 106 VDDI 800 -238.5 166 C23+ 3800 -238.5 226 G86 4132 110 286 S383 3172 110 47 TESTDA[4] -2450 -238.5 107 VDDI 850 -238.5 167 C23- 3850 -238.5 227 G84 4116 227 287 S382 3156 227 48 TESTDA[3] -2400 -238.5 108 VDDI 900 -238.5 168 C23- 3900 -238.5 228 G82 4100 110 288 S381 3140 110 49 TESTOSC -2350 -238.5 109 VCC 950 -238.5 169 C23- 3950 -238.5 229 G80 4084 227 289 S380 3124 227 50 OSC -2300 -238.5 110 VCC 1000 -238.5 170 VGL 4000 -238.5 230 G78 4068 110 290 S379 3108 110 51 VDD -2250 -238.5 111 VCC 1050 -238.5 171 VGL 4050 -238.5 231 G76 4052 227 291 S378 3092 227 52 VDD -2200 -238.5 112 VCI1 1100 -238.5 172 VGL 4100 -238.5 232 G74 4036 110 292 S377 3076 110 53 VDD -2150 -238.5 113 VCI1 1150 -238.5 173 VGH 4150 -238.5 233 G72 4020 227 293 S376 3060 227 54 VDD -2100 -238.5 114 VCI1 1200 -238.5 174 VGH 4200 -238.5 234 G70 4004 110 294 S375 3044 110 55 VDD -2050 -238.5 115 VREF 1250 -238.5 175 VGH 4250 -238.5 235 G68 3988 227 295 S374 3028 227 56 VDD -2000 -238.5 116 VREF 1300 -238.5 176 VCOMH 4300 -238.5 236 G66 3972 110 296 S373 3012 110 57 AGND -1950 -238.5 117 VREF 1350 -238.5 177 VCOMH 4350 -238.5 237 G64 3956 227 297 S372 2996 227 58 AGND -1900 -238.5 118 TEST 1400 -238.5 178 VCOMH 4400 -238.5 238 G62 3940 110 298 S371 2980 110 59 AGND -1850 -238.5 119 VPRER_OUT 1450 -238.5 179 VCOML 4450 -238.5 239 G60 3924 227 299 S370 2964 227 60 AGND -1800 -238.5 120 VCOML 4500 -238.5 240 G58 3908 110 300 S369 2948 110 AVDD 1500 -238.5 180 Page 16 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color X No. Name X Y No. Name X Y No. Name No. Name X Y No. Name 301 S368 2932 227 361 S308 1972 227 421 S248 1012 227 481 S192 -324 110 541 S132 -1284 110 302 S367 2916 110 362 S307 1956 110 422 S247 996 110 482 S191 -340 227 542 S131 -1300 227 303 S366 2900 227 363 S306 1940 227 423 S246 980 227 483 S190 -356 110 543 S130 -1316 110 304 S365 2884 110 364 S305 1924 110 424 S245 964 110 484 S189 -372 227 544 S129 -1332 227 305 S364 2868 227 365 S304 1908 227 425 S244 948 227 485 S188 -388 110 545 S128 -1348 110 306 S363 2852 110 366 S303 1892 110 426 S243 932 110 486 S187 -404 227 546 S127 -1364 227 307 S362 2836 227 367 S302 1876 227 427 S242 916 227 487 S186 -420 110 547 S126 -1380 110 308 S361 2820 110 368 S301 1860 110 428 S241 900 110 488 S185 -436 227 548 S125 -1396 227 309 S360 2804 227 369 S300 1844 227 429 S240 884 227 489 S184 -452 110 549 S124 -1412 110 310 S359 2788 110 370 S299 1828 110 430 S239 868 110 490 S183 -468 227 550 S123 -1428 227 311 S358 2772 227 371 S298 1812 227 431 S238 852 227 491 S182 -484 110 551 S122 -1444 110 312 S357 2756 110 372 S297 1796 110 432 S237 836 110 492 S181 -500 227 552 S121 -1460 227 313 S356 2740 227 373 S296 1780 227 433 S236 820 227 493 S180 -516 110 553 S120 -1476 110 314 S355 2724 110 374 S295 1764 110 434 S235 804 110 494 S179 -532 227 554 S119 -1492 227 315 S354 2708 227 375 S294 1748 227 435 S234 788 227 495 S178 -548 110 555 S118 -1508 110 316 S353 2692 110 376 S293 1732 110 436 S233 772 110 496 S177 -564 227 556 S117 -1524 227 317 S352 2676 227 377 S292 1716 227 437 S232 756 227 497 S176 -580 110 557 S116 -1540 110 318 S351 2660 110 378 S291 1700 110 438 S231 740 110 498 S175 -596 227 558 S115 -1556 227 319 S350 2644 227 379 S290 1684 227 439 S230 724 227 499 S174 -612 110 559 S114 -1572 110 320 S349 2628 110 380 S289 1668 110 440 S229 708 110 500 S173 -628 227 560 S113 -1588 227 321 S348 2612 227 381 S288 1652 227 441 S228 692 227 501 S172 -644 110 561 S112 -1604 110 322 S347 2596 110 382 S287 1636 110 442 S227 676 110 502 S171 -660 227 562 S111 -1620 227 323 S346 2580 227 383 S286 1620 227 443 S226 660 227 503 S170 -676 110 563 S110 -1636 110 324 S345 2564 110 384 S285 1604 110 444 S225 644 110 504 S169 -692 227 564 S109 -1652 227 325 S344 2548 227 385 S284 1588 227 445 S224 628 227 505 S168 -708 110 565 S108 -1668 110 326 S343 2532 110 386 S283 1572 110 446 S223 612 110 506 S167 -724 227 566 S107 -1684 227 327 S342 2516 227 387 S282 1556 227 447 S222 596 227 507 S166 -740 110 567 S106 -1700 110 328 S341 2500 110 388 S281 1540 110 448 S221 580 110 508 S165 -756 227 568 S105 -1716 227 329 S340 2484 227 389 S280 1524 227 449 S220 564 227 509 S164 -772 110 569 S104 -1732 110 330 S339 2468 110 390 S279 1508 110 450 S219 548 110 510 S163 -788 227 570 S103 -1748 227 331 S338 2452 227 391 S278 1492 227 451 S218 532 227 511 S162 -804 110 571 S102 -1764 110 332 S337 2436 110 392 S277 1476 110 452 S217 516 110 512 S161 -820 227 572 S101 -1780 227 333 S336 2420 227 393 S276 1460 227 453 S216 500 227 513 S160 -836 110 573 S100 -1796 110 334 S335 2404 110 394 S275 1444 110 454 S215 484 110 514 S159 -852 227 574 S99 -1812 227 335 S334 2388 227 395 S274 1428 227 455 S214 468 227 515 S158 -868 110 575 S98 -1828 110 336 S333 2372 110 396 S273 1412 110 456 S213 452 110 516 S157 -884 227 576 S97 -1844 227 337 S332 2356 227 397 S272 1396 227 457 S212 436 227 517 S156 -900 110 577 S96 -1860 110 338 S331 2340 110 398 S271 1380 110 458 S211 420 110 518 S155 -916 227 578 S95 -1876 227 339 S330 2324 227 399 S270 1364 227 459 S210 404 227 519 S154 -932 110 579 S94 -1892 110 340 S329 2308 110 400 S269 1348 110 460 S209 388 110 520 S153 -948 227 580 S93 -1908 227 341 S328 2292 227 401 S268 1332 227 461 S208 372 227 521 S152 -964 110 581 S92 -1924 110 342 S327 2276 110 402 S267 1316 110 462 S207 356 110 522 S151 -980 227 582 S91 -1940 227 343 S326 2260 227 403 S266 1300 227 463 S206 340 227 523 S150 -996 110 583 S90 -1956 110 344 S325 2244 110 404 S265 1284 110 464 S205 324 110 524 S149 -1012 227 584 S89 -1972 227 345 S324 2228 227 405 S264 1268 227 465 S204 308 227 525 S148 -1028 110 585 S88 -1988 110 346 S323 2212 110 406 S263 1252 110 466 S203 292 110 526 S147 -1044 227 586 S87 -2004 227 347 S322 2196 227 407 S262 1236 227 467 S202 276 227 527 S146 -1060 110 587 S86 -2020 110 348 S321 2180 110 408 S261 1220 110 468 S201 260 110 528 S145 -1076 227 588 S85 -2036 227 349 S320 2164 227 409 S260 1204 227 469 S200 244 227 529 S144 -1092 110 589 S84 -2052 110 350 S319 2148 110 410 S259 1188 110 470 S199 228 110 530 S143 -1108 227 590 S83 -2068 227 351 S318 2132 227 411 S258 1172 227 471 Dummy9 212 227 531 S142 -1124 110 591 S82 -2084 110 352 S317 2116 110 412 S257 1156 110 472 Dummy10 196 110 532 S141 -1140 227 592 S81 -2100 227 353 S316 2100 227 413 S256 1140 227 473 Dummy11 -196 110 533 S140 -1156 110 593 S80 -2116 110 354 S315 2084 110 414 S255 1124 110 474 Dummy12 -212 227 534 S139 -1172 227 594 S79 -2132 227 355 S314 2068 227 415 S254 1108 227 475 S198 -228 110 535 S138 -1188 110 595 S78 -2148 110 356 S313 2052 110 416 S253 1092 110 476 S197 -244 227 536 S137 -1204 227 596 S77 -2164 227 357 S312 2036 227 417 S252 1076 227 477 S196 -260 110 537 S136 -1220 110 597 S76 -2180 110 358 S311 2020 110 418 S251 1060 110 478 S195 -276 227 538 S135 -1236 227 598 S75 -2196 227 359 S310 2004 227 419 S250 1044 227 479 S194 -292 110 539 S134 -1252 110 599 S74 -2212 110 360 S309 1988 110 420 S249 1028 110 480 S193 -308 227 540 S133 -1268 227 600 S73 -2228 227 Page 17 of 183 Y ILI9163 X Y Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color No. Name No. Name X Y No. Name X Y 601 S72 -2244 110 X Y 661 S12 -3204 110 721 G89 -4164 110 602 S71 -2260 227 662 S11 -3220 227 722 G91 -4180 227 603 S70 -2276 110 663 S10 -3236 110 723 G93 -4196 110 604 S69 -2292 227 664 S9 -3252 227 724 G95 -4212 227 605 S68 -2308 110 665 S8 -3268 110 725 G97 -4228 110 606 S67 -2324 227 666 S7 -3284 227 726 G99 -4244 227 607 S66 -2340 110 667 S6 -3300 110 727 G101 -4260 110 608 S65 -2356 227 668 S5 -3316 227 728 G103 -4276 227 609 S64 -2372 110 669 S4 -3332 110 729 G105 -4292 110 610 S63 -2388 227 670 S3 -3348 227 730 G107 -4308 227 611 S62 -2404 110 671 S2 -3364 110 731 G109 -4324 110 612 S61 -2420 227 672 S1 -3380 227 732 G111 -4340 227 613 S60 -2436 110 673 Dummy13 -3396 110 733 G113 -4356 110 614 S59 -2452 227 674 Dummy14 -3412 227 734 G115 -4372 227 615 S58 -2468 110 675 Dummy15 -3428 110 735 G117 -4388 110 616 S57 -2484 227 676 Dummy16 -3444 227 736 G119 -4404 227 617 S56 -2500 110 677 G1 -3460 110 737 G121 -4420 110 618 S55 -2516 227 678 G3 -3476 227 738 G123 -4436 227 619 S54 -2532 110 679 G5 -3492 110 739 G125 -4452 110 620 S53 -2548 227 680 G7 -3508 227 740 G127 -4468 227 621 S52 -2564 110 681 G9 -3524 110 741 G129 -4484 110 622 S51 -2580 227 682 G11 -3540 227 742 G131 -4500 227 623 S50 -2596 110 683 G13 -3556 110 743 G133 -4516 110 624 S49 -2612 227 684 G15 -3572 227 744 G135 -4532 227 625 S48 -2628 110 685 G17 -3588 110 745 G137 -4548 110 626 S47 -2644 227 686 G19 -3604 227 746 G139 -4564 227 627 S46 -2660 110 687 G21 -3620 110 747 G141 -4580 110 628 S45 -2676 227 688 G23 -3636 227 748 G143 -4596 227 629 S44 -2692 110 689 G25 -3652 110 749 G145 -4612 110 630 S43 -2708 227 690 G27 -3668 227 750 G147 -4628 227 631 S42 -2724 110 691 G29 -3684 110 751 G149 -4644 110 632 S41 -2740 227 692 G31 -3700 227 752 G151 -4660 227 633 S40 -2756 110 693 G33 -3716 110 753 G153 -4676 110 634 S39 -2772 227 694 G35 -3732 227 754 G155 -4692 227 635 S38 -2788 110 695 G37 -3748 110 755 G157 -4708 110 636 S37 -2804 227 696 G39 -3764 227 756 G159 -4724 227 637 S36 -2820 110 697 G41 -3780 110 757 G161 -4740 110 638 S35 -2836 227 698 G43 -3796 227 758 Dummy17 -4756 227 639 S34 -2852 110 699 G45 -3812 110 759 Dummy18 -4772 110 640 S33 -2868 227 700 G47 -3828 227 641 S32 -2884 110 701 G49 -3844 110 ALK-R 4841 -220 642 S31 -2900 227 702 G51 -3860 227 ALK-L -4841 -220 643 S30 -2916 110 703 G53 -3876 110 644 S29 -2932 227 704 G55 -3892 227 645 S28 -2948 110 705 G57 -3908 110 646 S27 -2964 227 706 G59 -3924 227 647 S26 -2980 110 707 G61 -3940 110 648 S25 -2996 227 708 G63 -3956 227 649 S24 -3012 110 709 G65 -3972 110 650 S23 -3028 227 710 G67 -3988 227 651 S22 -3044 110 711 G69 -4004 110 652 S21 -3060 227 712 G71 -4020 227 653 S20 -3076 110 713 G73 -4036 110 654 S19 -3092 227 714 G75 -4052 227 655 S18 -3108 110 715 G77 -4068 110 656 S17 -3124 227 716 G79 -4084 227 657 S16 -3140 110 717 G81 -4100 110 658 S15 -3156 227 718 G83 -4116 227 659 S14 -3172 110 719 G85 -4132 110 660 S13 -3188 227 720 G87 -4148 227 Page 18 of 183 ILI9163 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 16 16 16 98 S1 ~ S396 19 G1 ~ G162 98 16 70 50 60 75 Input Pad 35 15 35 Page 19 of 183 32 41 19 41 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6. Function Description 6.1. MCU Interface Type Selection The selection of a given interfaces are done by setting P68, IM2, IM1, and IM0 pins as show in below tables. Table 6.1.1 MCU Interface Type Selection P68 IM2 IM1 IM0 Interface Read back selection - 0 - - Serial interface 0 1 0 0 8080 MCU 8-bit Parallel 0 1 0 1 0 1 1 0 0 1 1 1 - 0 - - Serial interface 1 1 0 0 6800 MCU 8-bit Parallel 1 1 0 1 1 1 1 0 1 1 1 1 Via the read instruction (12-bit, 16-bit and 18-bit read parameter) 8080 MCU 16-bit RDX strobe(16-bit read data and 8-bit read parameter) Parallel 8080 MCU 9-bit Parallel 8080 MCU 18-bit RDX strobe(9-bit read data and 8-bit read parameter) RDX strobe(18-bit read data and 8-bit read parameter) Parallel Via the read instruction (12-bit, 16-bit and 19-bit read parameter) 6800 MCU 16-bit 6800 MCU 9-bit Parallel 6800 MCU 18-bit E strobe(8-bit read data and 8-bit read parameter) E strobe(9-bit read data and 8-bit read parameter) Parallel Parallel RDX strobe(8-bit read data and 8-bit read parameter) E strobe(16-bit read data and 8-bit read parameter) E strobe(18-bit read data and 8-bit read parameter) 6.2. Serial Interface The Module uses a 3-wire 9-bit serial interface or 4-pins/8bits bi-directional interface for communication between the micro controller and the LCD driver chip. The 3-pin serial use: CSX (chip enable), SCL(serial clock) and SDA(serial data input/output) and the 4-pins serial use: CSX(chip enable), D/XC(data/ command select), SCL(serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary. Table 7.2.1 Serial Interface Type Selection IM2 0 0 4WSPI 0 1 Interface 3-Pins Serial Interface 4-Pins Serial Interface Read back selection Via the read instruction(8-bits, 24-bits and 32-bits read parameter) Via the read instruction(8-bits, 24-bits and 32-bits read parameter) 6.2.1 Command Write The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-Pins serial data packet contains a control bit D/CX and a transmission byte and in 4-pins serial case, data packet contains just transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is “low”, the Page 20 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 transmission byte is interpreted as a command byte. If D/CX is “high”, the transmission byte is stored I the display data RAM (Memory write command), or command register as parameter. Any instruction can be sent in any order to the Driver. The MSB is transmitted first. The serial interface is initialized when CSX is high status. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicated the start of data transmission. Figure5: 3-pins Serial Data Stream Format Transmission byte(TB) may be a command or a date MSB D/CX LSB D7 D6 D5 D4 D/CX D3 D2 D1 D0 D/CX TB D/CX TB TB Figure6: 4-pins Serial Data Stream Format Transmission byte(TB) may be a command or a date MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 TB TB TB When CSX is “high”, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low. SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX=’0’) or parameter/RAM data (D/CX=’1’). It is sampled when first rising edge of SCL (3-pin serial interface) or 8th rising edge of SCL (4-pins serial interface). If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-pin serial interface) or D7(4-pins serial interface) of the next byte at the next rising edge of SCL. 6.2.2 Read Function 8-bit S TB TB P S Host CSX SCL Driver SDA (SDI) SDA (SDP) D/CX D7 D6 D5 D4 D3 Hi-Z D2 D1 Hi-Z D0 D7 D6 D5 D4 D/CX D3 D2 D1 D0 Figure7: 3-Pin Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: Page 21 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color S TB ILI9163 TB P S Host CSX SCL Driver SDA (SDI) D/CX D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z SDA (SDP) Hi-Z D/CX D3 D2 D23 D22 D21 D20 D19 D1 D0 Dummy Clock Cycle Figure8: 3-Pin Serial Protocol (for RDDID command: 24-bit read) S TB TB P S Host CSX SCL Driver SDA (SDI) SDA (SDP) D/CX D7 D6 D5 D4 D3 Hi-Z D2 D1 D0 Hi-Z D31 D30 D29 D28 D27 D/CX D3 D2 D1 D0 Dummy Clock Cycle Figure9: 3-Pin Serial Protocol (for RDDST command: 32-bit read) Page 22 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color P TB TB S ILI9163 S CSX Host (MCU to Driver) SCL 0 D/CX SDA (SDI) Host (Driver to MCU) D7 D6 D5 D4 D3 D2 D1 Hi-Z SDA (SDO) Hi-Z D0 D7 D6 D5 D4 D7 D3 D2 D1 D0 Figure10: 4-pins Serial Protocol (for RDID1/RDID2/RDID3/0AH/0BH/0CH/0DH/0EH/0FH command; 8-bits S TB P TB S CSX Host (MCU to Driver) SCL 0 D/CX SDA (SDI) Host (Driver to MCU) D7 D6 D5 D4 D3 D2 D1 Hi-Z D0 Hi-Z SDA (SDO) D23 D22 D21 D7 D2 D1 D0 Dummy Clock Cycle Figure11: 4-pins Serial Protocol (for RDID command: 24-bits read) S TB P TB S CSX Host (MCU to Driver) SCL 0 D/CX SDA (SDI) Host (Driver to MCU) SDA (SDO) D7 D6 D5 D4 D3 Hi-Z D2 D1 Hi-Z D0 D31 D30 D29 D28 D27 D26 D7 D2 D1 D0 Dummy Clock Cycle Figure12: 4-pins Serial Protocol (for RDST command: 32-bits read) Page 23 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.3. 8080-Series Parallel Interface (P68=’0’) The MCU uses a 11-wires 8-data parallel interface or 12-wires 9-data parallel interface or 19-wires 16-data parallel interface or 21-wires 18-data parallel interface. The chip-select CSX (active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write, RDX is the parallel data read and D[17:0] is parallel data. The graphics controller chip reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=’1’, D[17,0] bits are display RAM data or command parameters. When D/C=’0’, D[17,0] bits are commands. The 8080-series bi-direction interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is low state (GND). Interface bus width can be selected with IM2, IM1 and IM0. The interface function of 8080-series parallel interface are given in Table 8.2.4 Table 7.2.4The function of 8080-series parallel interface P68 IM2 IM1 IM0 Interface 0 1 0 0 8-bit Parallel 0 0 0 1 1 1 0 1 1 1 0 1 16-bit Parallel 9-bit Parallel 18-bit Parallel D/CX 0 RDX 1 WRX Ç 1 1 Ç 1 1 0 Ç Ç 1 1 1 Ç 1 1 Ç 1 1 0 Ç Ç 1 1 1 Ç 1 1 Ç 1 1 0 Ç Ç 1 1 1 Ç 1 1 Ç 1 1 Ç Ç 1 1 Function Write 8-bit command(D7 to D0) Write 8-bit display data or 8-bit parameter(D7 to D0) Read 8-bit display data(D7 to D0) Read 8-bit parameter or status(D7 to D0) Write 8-bit command(D7 to D0) Write 16-bit display data or 8-bit parameter(D15 to D0) Read 16-bit display data(D15 to D0) Read 8-bit parameter or status(D7 to D0) Write 8-bit command(D7 to D0) Write 9-bit display data or 8-bit parameter(D8 to D0) Read 9-bit display data (D8 to D0) Read 8-bit parameter or status(D7 to D0) Write 8-bit command(D7 to D0) Write 18-bit display data or 8-bit parameter(D17 to D0) Read 18-bit display data(D17 to D0) Read 8-bit parameter or status(D7 to D0) Note: applied for command code: Dah, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh 6.3.1 Write Cycle/Sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control (D/CX, RDX, WRX) and data signals (D[17…0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are a command if the control signal is low (= ‘0’) and vice versa it is data (= ‘1’). The write cycle is described in the following figure. Page 24 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 WRX D[7:0], D[8:0] or D[15:0], D[17:0] The display read D[17:0], D[15:0], D[8:0] or D[7:0] lines when there is rising edge of WRX The host asserts D[17:0], D[15:0], D[8:0] or D[7:0] lines when there is falling edge of WRX The host negates D[17:0], D[15:0], D[8:0] or D[7:0] lines. Note: WRX is an unsynchronized signal (it can be stopped) Figure13: 8080-Series WRX Protocol 1-byte command 2-byte command n-byte command (number of parameter = n-1 CMD CMD PA1 CMD PA1 Pa n-2 CMD CMD PA1 CMD PA1 Pa n-2 CMD CMD PA1 CMD PA1 Pa n-2 Pa n-1 P CSX D/CX RDX WRX D[17:0] Host D[17:0] (MPU to LCD) Driver D[17:0] (LCD to MPU) Hi-Z CMD: Write command code PA: Write parameter or RAM data Signals on D[17:0], D/CX and WRX pins during CSX=＂H＂ are ignore Figure14: 8080-Series Parallel bus protocol (write to register or display RAM) 6.3.2 Read Cycle/Sequence The read cycle (RDX high-low-high sequence) means that the host reads information from the display via interface. The display sends data (D[17…0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX. Page 25 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 RDX D[7:0], D[8:0] or D[15:0], D[17:0] The host reads D[17:0], D[15:0], D[8:0] or D[7:0] lines when there is a rising edge of RDX. The display asserts D[17:0], D[15:0], D[8:0] or D[7:0] lines when there is a falling edge of RDX. The display negates D[17:0], D[15:0], D[8:0] or D[7:0] lines Note: RDX is an unsynchronized signal (It can be stopped). Figure15: 8080-Series RDX Protocol Read command Read display RAM data CMD DM PA1 CMD CMD DM PA CMD DM Data Data P CSX D/CX RDX WRX D[17:0] Host D[17:0] (MPU to LCD) CMD Driver D[17:0] (LCD to MPU) Hi-Z DM PA PA Hi-Z CMD: Write command code PA: Write parameter or RAM data PA Hi-Z CMD DM Hi-Z DM PA PA Signals on D[17:0], D/CX, RDX and WRX pins during CSX=＂H＂ are ignore Figure16: 8080-Series parallel bus protocol (Read from register or display RAM) Page 26 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.4. 6800-Series Parallel Interface (P68=’1’) The MCU uses a 11-wires 8-data parallel interface or 12-wires 9-data parallel interface or 19-wires 16-data parallel interface or 21-wires 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX(active low) is an external reset signal. WRX is the parallel data write, RDX is the parallel data read and D[17:0] is parallel data. The Graphics Controller Chip reads the data at the falling edge of E signal when R/WX=’1’ and writes the data at the falling of the E signal when R/WX=’0’. The D/CX is the data/command flag. When D/CX=’1’, D[17,0] bits are display RAM data or command parameters. When D/C=’0’, D[17,0] bits are commands. The 6800-series bi-direction interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and IM0. The interface function of 6800-series parallel interface are given in Table 8.2.7 Table 7.2.7 The function of 6800-series parallel interface P68 1 1 1 1 IM2 1 1 1 1 IM1 0 0 1 1 IM0 0 1 0 1 Interface 8-bit Parallel 16-bit Parallel 9-bit Parallel 18-bit Parallel D/CX RDX WRX 0 1 È 1 1 È 1 È 1 1 È 1 0 1 È 1 1 È 1 È 1 1 È 1 0 1 È 1 1 È 1 È 1 1 È 1 0 1 È 1 1 È 1 È 1 1 È 1 Function Write 8-bit command(D7 to D0) Write 8-bit display data or 8-bit parameter(D7 to D0) Read 8-bit display data(D7 to D0) Read 8-bit parameter or status(D7 to D0) Write 8-bit command(D7 to D0) Write 16-bit display data or 8-bit parameter(D15 to D0) Read 16-bit display data(D15 to D0) Read 8-bit parameter or status(D7 to D0) Write 8-bit command(D7 to D0) Write 9-bit display data or 8-bit parameter(D8 to D0) Read 9-bit display data (D8 to D0) Read 8-bit parameter or status(D7 to D0) Write 8-bit command(D7 to D0) Write 18-bit display data or 8-bit parameter(D17 to D0) Read 18-bit display data(D17 to D0) Read 8-bit parameter or status(D7 to D0) Note : applied for command code : Dah, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh Page 27 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.4.1 Write Cycle/Sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17…0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are a command if the control signal is low (= ‘0’) and vice versa it is data (= ‘1’). The write cycle is described in the following figure. R/WX = 0 E D[7:0], D[8:0] or D[15:0], D[17:0] The display read D[17:0], D[15:0], D[8:0] or D[7:0] lines when there is rising edge of E The host asserts D[17:0], D[15:0], D[8:0] or D[7:0] lines when there is falling edge of E The host negates D[17:0], D[15:0], D[8:0] or D[7:0] lines. Note: E is unsynchronized signal (it can be stopped) Figure17: 6800-Series Write Protocol 1-byte command 2-byte command D[17:0] RESX S N-byte command (number of parameter = N-1 CMD CMD PA1 CMD PA1 PA N-2 PA N-1 P S CMD CMD PA1 CMD PA1 PA N-2 PA N-1 P S CMD CMD PA1 CMD PA1 PA N-2 PA N-1 P ｀1＇ CSX D/CX R/WX E D[17:0] Host [17:0] Host to LCD Driver [17:0] LCD to Host CMD: Write command code PA: Write parameter or RAM data Signals on D[17:0], D/CX, R/WX, E pins during CSX=＂1＂ are ignore Figure18: 6800-Series parallel bus protocol (write to register or display RAM) Page 28 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.4.2 Read Cycle/Sequence The read cycle means that the host reads information (commend or/and data) to the display via the interface. Each read cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data (D[17…0]). D/CX bit is control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’) R/WX = 1 RDX D[7:0], D[8:0] or D[15:0], D[17:0] The host reads D[17:0], D[15:0], D[8:0] or D[7:0] lines when there is a rising edge of E The display asserts D[17:0], D[15:0], D[8:0] or D[7:0] lines when there is a falling edge of E The display negates D[17:0], D[15:0], D[8:0] or D[7:0] lines Note: E is an unsynchronized signal (It can be stopped). Figure19: 6800-Series Read Protocol Read display RAM data Read Parameter D[17:0] RESX S CM D CM D PA 1 CM D DM data data P CM D PA CM D DM data data P ｀ 1＇ CSX D/CX R/W X ｀ 0＇ E D[17:0] S CM D Host [17:0] Host to LCD S CM D Driver [17:0] LCD to Host S Hi-Z Hi-Z DM Hi-Z CM D PA CM D: W rite command code PA: W rite parameter or RAM data DM P data data P Signals on D[17:0], D/CX, R/W X, E pins during CSX=＂ 1＂ are ignored Figure20: 6800-Series Parallel bus protocol (Read from register or display RAM) Page 29 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.5. Display Data Transfer Recovery If there is a break in data transmission by RESX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous its and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been High state. See the following example. S TB TB P CSX RESX Wait for more than 10us Host (MCU to Driver) SCL SDA D/CX D7 D6 D5 D4 D3 D2 D/CX D7 D6 D5 D4 D3 D2 D1 D0 Command/parameter/Data SCL and SDA during RESX=L is invalid and next byte becomes command Figure21: Serial bus protocol, write mode – interrupted by RESX If there is a break in data transmission by CSX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command data, before Bit D0 of the byte has been completed. Then the DRIVER will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line(CSX) is next activated. See the following example. TB TB S P CSX Host (MCU to Driver) SCL SDA D/CX D7 D6 D5 D4 Command/parameter/ Data D/CX D7 D6 D5 D4 D3 D2 D1 D0 Command/parameter/Data Break Figure22: Serial bus protocol, write mode – interrupted by CSX If1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The inter face is ready to receive next byte as show below. Page 30 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Note: Break can be e.g. another command or noise pulse. 6.6. Display Data Transfer Pause It will be possible when transferring a Command, Frame Memory Data or Multiple Parameter Data to invoke a pause in the data transmission. If the Chip Select Line is released after a whole byte of a Frame Memory Data or Multiple Parameter Data has been completed, then the Display Module will wait and continue the Frame Memory Data or Parameter Data Transmission from the point where it was paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive either the command’s parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below: Break CMD1 PARA11 PARA12 PARA11 is sucessfully sent but the PARA12 is breaked and need to be transferred again CMD2 CMD1 PARA11 PARA12 PARA13 Command 1 with 1st parameter(PARA11) should be executed again to write remained parameter(PARA12 and PARA13) Figure23: Write interrupts recovery (serial interface) If 1, 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of command remains previous value. Break CMD1 PARA11 PARA11 is sucessfully sent but the other parameters are not sent and break ha CMD2 CMD1 PARA11 PARA12 PARA13 Command 1 with 1st parameter(PARA11) should be executed again to write remained parameter(PARA12 and PARA13) Figure24: Write interrupts recovery (both serial and parallel interface) Page 31 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.6.1 Serial Interface Pause TB S P TB SCEX Host (MCU to Driver) SCL SDA D/CX D7 D7 D5 D4 D3 D2 D1 D0 D/CX D7 D6 D5 D4 D3 D2 D1 D0 Command/parameter/Data Command/parameter/Data SCL and SDA during CSX=H is invalid Figure25: Serial interface Pause Protocol (pause by CSX) CSX D/CX RDX WRX D[7:0] D7 to D0 D7 to D0 Command/ parameter Pause Command/ parameter Figure26: Parallel bus Pause Protocol (paused by CSX) This applies to the following 4 conditions: 1. Command-Pause-Command 2. Command-Pause-Parameter 3. Parameter-Pause-Command 4. Parameter-Pause-Parameter 6.7. Display Data Transfer Mode The Module has three kinds color modes for transferring data to the display RAM. These are 12-bit color per pixel, 16-bit color per pixel and 18-bit color per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods. Method 1: The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is written. Page 32 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Method 2: Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is downloaded. Note: 1. These apply to this Data Transfer Color mode on both Serial and Parallel interfaces. 2. The Frame Memory can contain both odd and even number of pixels for both Methods. Only complete pixel data will be stored in the Frame Memory. Page 33 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.8. Display Data Color Coding 6.8.1 Serial Interface Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bits input 65K colors, RGB 5-6-5-bitsinput 262K colors, RGB 6-6-6-bits input Note 1: pixel data with the 12-bits color depth information. Note 2: The most significant bits are: Rx3, Gx3 and Bx3 Note 3: The least significant bits are:Rx0, Gx0 and Bx0 Note 4: X = don’t care – Can be set to ‘0’ or ‘1’ Figure27: Write data for RGB4-4-4 bits input 4-pin 8-bit Series data protocol RESX ｀1' IM2 ｀0＇ SPI4W = ｀1＇, IM1. IM0= xx CSX D/CX 1 1 Pixel n SDA D7 D6 D5 D4 D3 R1 4 R1 3 R1 2 R1 1 R1 0 D2 D1 D0 G1 5 G1 4 G1 3 Pixel n+1 D7 D6 G1 2 G1 1 D5 G1 0 D4 B1 4 D3 B1 3 D2 B1 2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 B1 1 B1 0 R2 4 R2 3 R2 2 R2 1 R2 0 G2 5 G2 4 G2 3 SCL 16-bit Loo-Up Table for 65k Colors mapping (16-bit to 18 bit) 18-bit Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: pixel data with the 16-bits color depth information. Note 2: The most significant bits are: Rx4, Gx5 and Bx4 Note 3: The least significant bits are:Rx0, Gx0 and Bx0 Note 4: X = Don’t care – Can be set to ‘0’ or ‘1’ Figure28: Write data fro RGB 5-6-5-bits input Page 34 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 3-pin 9-bit Series data protocol RESX ｀1' IM2 ｀0＇ SPI4W = ｀0＇, IM1. IM0= xx CSX Pixel n D8 SDA D7 R1 5 1 D6 R1 4 D5 R1 3 D4 R1 2 D3 R1 1 D2 R1 0 D1 D0 - D8 - D7 G1 5 1 D6 D5 D4 G1 4 G1 3 G1 2 D3 G1 1 D2 G1 0 D1 D0 D8 - - 1 D7 B1 5 D6 B1 4 D5 B1 3 D4 B1 2 D3 B1 1 D2 D1 B1 0 - D0 - SCL 18-bit Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Figure29: Write data for RGB 6-6-6 bits input 4-pin 8-bit Series data protocol RESX ｀1' IM2 ｀0＇ SPI4W = ｀1＇, IM1. IM0= xx CSX D/CX 1 1 1 Pixel n SDA D7 D6 D5 D4 D3 D2 R1 5 R1 4 R1 3 R1 2 R1 1 R1 0 D1 D0 D7 G1 5 D6 G1 4 D5 G1 3 D4 G1 2 D3 G1 1 D2 D1 D0 G1 0 D7 D6 D5 D4 B1 5 B1 4 B1 3 B1 2 D3 B1 1 D2 D1 D0 B1 0 SCL 18-bit Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: pixel data with the 18-bits color depth information. Note 2: The most significant bits are: Rx5, Gx5 and Bx5 Note 3: The least significant bits are:Rx0, Gx0 and Bx0 Note 4: X = Don’t care – Can be set to ‘0’ or ‘1’ Page 35 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Read data for 3-W SPI RGB RESX ｀1' IM2 ｀0＇ SPI4W = ｀0＇, IM1. IM0= xx CSX (SPI CSX) Host SCL SDA - 0 SDA Driver High-Z R2Eh High-Z D23 D22 D21 D20 D19 D18 D17 D16 D2 D1 D0 D23 D0 D23 D22 D21 D20 D19 1-Pixel data 9 Dummy Clock Read Data format as below D23 D22 D21 D20 R1 5 R1 4 R1 3 R1 2 D19 D18 R1 1 D17 R1 0 D16 D15 D14 - G1 5 - G1 4 D13 D12 D11 R1 3 R1 2 R1 R1 13 D10 D9 R1 0 - D8 D7 D6 - B1 5 B1 4 D5 D4 D3 D2 D1 D0 B1 3 B1 2 B1 1 B1 0 - - Note: X = Don’t care – Can be set to ‘0’ or ‘1’ RESX ｀1' IM2 ｀0＇ SPI4W = ｀1＇, IM1. IM0= xx CSX Host SCL 0 D/CX SDA - High-Z R2Eh Driver High-Z SDA D23 D22 D21 D20 D19 D18 D17 D16 D2 D1 D22 D21 D20 D19 1-Pixel data 8 Dummy Clock Read Data format as below D23 R1 5 D22 D21 D20 R1 4 R1 3 R1 2 D19 D18 R1 1 R1 0 D17 - D16 D15 D14 - G1 5 G1 4 D13 D12 D11 R1 3 R1 2 R1 R1 13 D10 D9 R1 0 - D8 D7 D6 - B1 5 B1 4 D5 D4 D3 D2 D1 D0 B1 3 B1 2 B1 1 B1 0 - - Note: X = Don’t care – Can be set to ‘0’ or ‘1’ Figure30: Read data for SPI RGB 6-6-6-bits Page 36 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 1 pixel (3 sub-pixels) per 2 transfer RESX 1 IM1/IM0 IM[1:0] = “00＂ CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D7 0 R1, Bit4 G1, Bit2 R1, Bit4 G1, Bit2 D6 0 R1, Bit3 G1, Bit1 R1, Bit3 G1, Bit1 D5 1 R1, Bit2 G1, Bit0 R1, Bit2 G1, Bit0 D4 0 R1, Bit1 B1, Bit4 R1, Bit1 B1, Bit4 D3 1 G1, Bit0 B1, Bit3 R1, Bit0 B1, Bit3 D2 1 G1, Bit5 B1, Bit2 G1, Bit5 B3, Bit2 D1 0 G1, Bit4 B1, Bit1 G1, Bit4 B3, Bit1 D0 0 G1, Bit3 B1, Bit0 G1, Bit3 B3, Bit0 16-bit Pixel n Pixel n+1 16-bit Loo-Up Table for 65k Colors mapping (16-bit to 18-bit) 18-bit 18-bit Frame Memoy R G B 1 1 1 R G B 2 2 2 R G B 3 3 3 Note 1: The data orde r is as follows, MSB =D7, LSB =D0 and pi cture data is MSB=Bit3, LSB=Bit 0 for Green and MSB=B it4, LSB=B it0 for Red, Green and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bits col or depth information. Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’ Figure31: Write 8-bits data for RGB 5-6-5-bits input Page 37 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 2 pixels (6 sub-pixels) per 3 transfer RESX IM1/IM0 1 IM1, IM0 = 00 CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D7 0 R1, Bit3 B1, Bit3 G2, Bit3 R3, Bit3 D6 0 R1, Bit2 B1, Bit2 G2, Bit2 R3, Bit2 D5 1 R1, Bit1 B1, Bit1 G2, Bit1 R3, Bit1 D4 0 R1, Bit0 B1, Bit0 G2, Bit0 R3, Bit0 D3 1 G1, Bit3 R2, Bit3 B2, Bit3 G3, Bit3 D2 1 G1, Bit2 R2, Bit2 B2, Bit2 G3, Bit2 D1 0 G1, Bit1 R2, Bit1 B2, Bit1 G3, Bit1 D0 0 G1, Bit0 R2, Bit0 B2, Bit0 G3, Bit0 Pixel n Pixel n+1 12-bit 12-bit Loo-Up Table for 4096 Colors mapping (12-bit to 18-bit) 18-bit 18-bit Frame Memoy R 1 G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 12-bits color depth information. Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’ Figure32: Write 8-bit data for RGB 4-4-4-bits input Page 38 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 1 pixel (3 sub-pixels) per 2 transfer RESX 1 IM1/IM0 IM[1:0] = “00＂ CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D7 0 R1, Bit4 G1, Bit2 R1, Bit4 G1, Bit2 D6 0 R1, Bit3 G1, Bit1 R1, Bit3 G1, Bit1 D5 1 R1, Bit2 G1, Bit0 R1, Bit2 G1, Bit0 D4 0 R1, Bit1 B1, Bit4 R1, Bit1 B1, Bit4 D3 1 G1, Bit0 B1, Bit3 R1, Bit0 B1, Bit3 D2 1 G1, Bit5 B1, Bit2 G1, Bit5 B3, Bit2 D1 0 G1, Bit4 B1, Bit1 G1, Bit4 B3, Bit1 D0 0 G1, Bit3 B1, Bit0 G1, Bit3 B3, Bit0 16-bit Pixel n Pixel n+1 16-bit Loo-Up Table for 65k Colors mapping (16-bit to 18-bit) 18-bit 18-bit Frame Memoy R 1 G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit3, LSB=Bit 0 for Green and MSB=Bit4, LSB=Bit0 for Red, Green and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bits color depth information. Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’ Figure33: Write 8-bits data for RGB 5-6-5-bits input Page 39 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 1 pixel (3 sub-pixels) per 3 transfer RESX IM1/IM0 1 IM1, IM0 = 00 CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D7 0 R1, Bit5 G1, Bit5 B1, Bit5 R2, Bit5 D6 0 R1, Bit4 G1, Bit4 B1, Bit4 R2, Bit4 D5 1 R1, Bit3 G1, Bit3 B1, Bit3 R2, Bit3 D4 0 R1, Bit2 G1, Bit2 B1, Bit2 R2, Bit2 D3 1 R1, Bit1 G1, Bit1 B1, Bit1 R2, Bit1 D2 1 R1, Bit0 G1, Bit0 B1, Bit0 R2, Bit0 D1 0 D0 0 Pixel n Frame Memoy 18-bit R 1 G 1 B 1 18-bit R 2 G 2 B 2 R 3 G 3 Pixel n+1 B 3 Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’ Figure34: Write 8-bit data for RGB 6-6-6-bits input Page 40 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.8.3 16-bit Parallel Interface (IM2=’1’, IM1, IM0=”01”) Different display data formats are available for three colors depth supported by listed below 4k colors, RGB 4-4-4-bits input 65K colors, RGB 5-6-5-bits input 262K colors, RGB 6-6-6-bits input 1 pixels (3 sub-pixels) per 1 transfer, 12-bits/pixel RESX IM1/IM0 1 IM1, IM0 = 01 CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D15 - - - - - D14 - - - - - D13 - - - - - D12 - - - - - D11 - R1, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D10 - R1,Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D9 - R1,Bit1 R2, Bit1 R3, Bit1 R4, Bit1 D8 - R1,Bit0 R2, Bit0 R3, Bit0 R4, Bit0 D7 0 G1, Bit3 G2, Bit3 G3, Bit3 G4, Bit3 D6 0 G1, Bit2 G2, Bit2 G3, Bit2 G4, Bit2 D5 1 G1, Bit1 G2, Bit1 G3, Bit1 G4, Bit1 D4 0 G1, Bit0 G2, Bit0 G3, Bit0 G4, Bit0 D3 1 B1, Bit3 B2, Bit3 B3, Bit3 B4, Bit3 D2 1 B1, Bit2 B2, Bit2 B3, Bit2 B4, Bit2 D1 0 B1, Bit1 B2, Bit1 B3, Bit1 B4, Bit1 D0 0 B1, Bit0 B2, Bit0 B3, Bit0 B4, Bit0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 12-bit 12-bit Loo-Up Table for 4096 Colors mapping (12-bit to 18-bit) 18-bit Frame Memoy R 1 18-bit G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note1: The data order is as follows, MSB = D15, LSB = D0 and picture data is MSB = Bit3, LSB = Bit0 for Red, Green and Blue data. Note 2: 1-times transfer (D7 to D0) is used to transmit 1 pixel data with the 12-bit color depth information. Note 3: ‘=’ Don’t care – Can be set to ‘0’ or ‘1’ Figure35: Write 16-bit data for RGB4-4-4-bits input (4k-color) Page 41 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 1 pixel (3 sub-pixels) per 1 transfer, 16-bits/pixel 1 RESX IM1/IM0 IM[1:0] = “01＂ CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D15 - R1, Bit4 R2, Bit4 R3, Bit4 R4, Bit4 D14 - R1, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D13 - R1,Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D12 - R1,Bit1 R2, Bit1 R3, Bit1 R4, Bit1 D11 - R1,Bit0 R2, Bit0 R3, Bit0 R4, Bit0 D10 - G1, Bit5 G2, Bit5 G3, Bit5 G4, Bit5 D9 - G1, Bit4 G2, Bit4 G3, Bit4 G4, Bit4 D8 - G1, Bit3 G2, Bit3 G3, Bit3 G4, Bit3 D7 0 G1, Bit2 G2, Bit2 G3, Bit2 G4, Bit2 D6 0 G1, Bit1 G2, Bit1 G3, Bit1 G4, Bit1 D5 1 G1, Bit0 G2, Bit0 G3, Bit0 G4, Bit0 D4 0 B1, Bit4 B2, Bit4 B3, Bit4 B4, Bit4 D3 1 B1, Bit3 B2, Bit3 B3, Bit3 B4, Bit3 D2 1 B1, Bit2 B2, Bit2 B3, Bit2 B4, Bit2 D1 0 B1, Bit1 B2, Bit1 B3, Bit1 B4, Bit1 D0 0 B1, Bit0 B2, Bit0 B3, Bit0 B4, Bit0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 16-bit 16-bit Loo-Up Table for 4096 Colors mapping (16-bit to 18-bit) 18-bit Frame Memoy R 1 18-bit G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note1: The data order is as follows, MSB = D15, LSB = D0 and picture data is MSB = Bit5, LSB = Bit0 for Red and Blue and MSB=Bit5, LSB=Bit 0 for Green data. Note 2: 1-time transfer (D7 to D0) is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: ‘=’ Don’t care – Can be set to ‘0’ or ‘1’ Figure36: Write 16-bit data for RGB 5-6-5-bits input (65k colors) Page 42 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 2 pixels (6 sub-pixels) per 2 transfer, 18-bits/pixel RESX IM1/IM0 1 IM1, IM0 = 01 CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D15 - R1, Bit5 B1, Bit5 G2, Bit5 R3, Bit5 D14 - R1, Bit4 B1, Bit4 G2, Bit4 R3, Bit4 D13 - R1, Bit3 B1, Bit3 G2, Bit3 R3, Bit3 D12 - R1,Bit2 B1, Bit2 G2, Bit2 R3, Bit2 D11 - R1,Bit1 B1, Bit1 G2, Bit1 R3, Bit1 D10 - R1,Bit0 B1, Bit0 G2, Bit0 R3, Bit0 D9 - - - - - D8 - - - - - D7 0 G1, Bit5 R2, Bit5 B2, Bit5 G3, Bit5 D6 0 G1, Bit4 R2, Bit4 B2, Bit4 G3, Bit4 D5 1 G1, Bit3 R2, Bit3 B2, Bit3 G3, Bit3 D4 0 G1, Bit2 R2, Bit2 B2, Bit2 G3, Bit2 D3 1 G1, Bit1 R2, Bit1 B2, Bit1 G3, Bit1 D2 1 G1, Bit0 R2, Bit0 B2, Bit0 G3, Bit0 D1 0 - - - - D0 0 - - - - Pixel n Pixel n+1 18-bit Frame Memoy R 1 18-bit G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note1: The data order is as follows, MSB = D15, LSB = D0 and picture data is MSB = Bit2, LSB = Bit0 for Red and Green and MSB=Bit1, LSB=Bit 0 for Blue data. Note 2: 1-time transfer (D7 to D0) is used to transmit 1 pixel data with the 8-bit color depth information. Note 3: ‘=’ Don’t care – Can be set to ‘0’ or ‘1’ Figure37: Write 16-bit data for RGB 6-6-6-bits input (262K colors) Page 43 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.8.4 9-bit Parallel Interface (IM2=’2’, IM1, IM0=”10”) Different display data formats are available for three colors depth supported by listed below 262K colors, RGB6-6-6-bits input 2 pixels (6 sub-pixels) per 4 transfer, 18-bits/pixel RESX 1 IM1/IM0 IM1, IM0 = 10 CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D8 - R1, Bit5 G1, Bit2 R2, Bit5 G2, Bit2 D7 0 R1, Bit4 G1, Bit1 R2, Bit4 G2, Bit1 D6 0 R1, Bit3 G1, Bit0 R2, Bit3 G2, Bit0 D5 1 R1, Bit2 B1, Bit5 R2, Bit2 B2, Bit5 D4 0 R1, Bit1 B1, Bit4 R2, Bit1 B2, Bit4 D3 1 R1, Bit0 B1, Bit3 R2, Bit0 B2, Bit3 D2 1 G1, Bit5 B1, Bit2 G2, Bit5 B2, Bit2 D1 1 G1, Bit4 B1, Bit1 G2, Bit4 B2, Bit1 D0 1 G1, Bit3 B1, Bit0 G2, Bit3 B2, Bit0 Pixel n+1 18-bit Pixel n 18-bit Frame Memoy R 1 G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note1: The data order is as follows, MSB = D8, LSB = D0 and picture data is MSB = Bit5, LSB = Bit0 for Red and Green and Blue data. Note 2: 3-times is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: ‘=’ Don’t care – Can be set to ‘0’ or ‘1’ Figure38: Write 9-bit data for RGB 6-6-6-bits input(262k-color) Page 44 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 6.8.5 18-bit Parallel Interface (IM2=’1’, IM1, IM0=”11”) Different display data formats are available for three colors depth supported by listed below 4k colors, RGB 4-4-4-bits input 65K colors, RGB 5-6-5-bits input 262K colors, RGB 6-6-6-bits input 1 pixel (3 sub-pixels) per 1 transfer, 12-bits/pixel RESX IM1/IM0 1 IM1, IM0 = 11 CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D17 - - - - - D16 - - - - - : : : : : : : : D12 - - : : - - : : - D11 - R1, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D10 - R1,Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D9 - R1,Bit1 R2, Bit1 R3, Bit1 R4, Bit1 D8 - R1,Bit0 R2, Bit0 R3, Bit0 R4, Bit0 D7 0 G1, Bit3 G2, Bit3 G3, Bit3 G4, Bit3 D6 0 G1, Bit2 G2, Bit2 G3, Bit2 G4, Bit2 D5 1 G1, Bit1 G2, Bit1 G3, Bit1 G4, Bit1 D4 0 G1, Bit0 G2, Bit0 G3, Bit0 G4, Bit0 D3 1 B1, Bit3 B2, Bit3 B3, Bit3 B4, Bit3 D2 1 B1, Bit2 B2, Bit2 B3, Bit2 B4, Bit2 D1 0 B1, Bit1 B2, Bit1 B3, Bit1 B4, Bit1 D0 0 B1, Bit0 B2, Bit0 B3, Bit0 Pixel n Pixel n+2 Pixel n+1 12-bit B4, Bit0 Pixel n+3 12-bit Loo-Up Table for 4096 Colors mapping (12-bit to 18-bit) 18-bit Frame Memoy R 1 18-bit G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note1: The data order is as follows, MSB = D11, LSB = D0 and picture data is MSB = Bit3, LSB = Bit0 for Red, Green and Blue data. Note 2: 1-time is used to transmit 1 pixel data with the 12-bit color depth information. Note 3: ‘=’ Don’t care – Can be set to ‘0’ or ‘1’ Figure39: Write 18-bits data for RGB 4-4-4-bits input (4k colors) Page 45 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 1 pixel (3 sub-pixels) per 1 transfer, 16-bits/pixel RESX 1 IM1/IM0 IM1, IM0 = 11 CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D17 - D16 - D15 - R1, Bit4 R2, Bit4 R3, Bit4 R4, Bit4 D14 - R1, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D13 - R1,Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D12 - R1,Bit1 R2, Bit1 R3, Bit1 R4, Bit1 D11 - R1,Bit0 R2, Bit0 R3, Bit0 R4, Bit0 D10 - G1, Bit5 G2, Bit5 G3, Bit5 G4, Bit5 D9 - G1, Bit4 G2, Bit4 G3, Bit4 G4, Bit4 D8 - G1, Bit3 G2, Bit3 G3, Bit3 G4, Bit3 D7 0 G1, Bit2 G2, Bit2 G3, Bit2 G4, Bit2 D6 0 G1, Bit1 G2, Bit1 G3, Bit1 G4, Bit1 D5 1 G1, Bit0 G2, Bit0 G3, Bit0 G4, Bit0 D4 0 R1, Bit4 R2, Bit4 R3, Bit4 R4, Bit4 D3 1 R1, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D2 1 R1, Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D1 0 R1, Bit1 R2, Bit1 R3, Bit1 R4, Bit1 D0 0 R1, Bit0 R2, Bit0 R3, Bit0 R4, Bit0 Pixel n Pixel n Pixel n Pixel n 16-bit 16-bit Loo-Up Table for 65k Colors mapping (16-bit to 18-bit) 18-bit Frame Memoy R 1 18-bit G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note1: The data order is as follows, MSB = D15, LSB = D0 and picture data is MSB = Bit5, LSB = Bit0 for Green and MSB=Bit 4, LSB=Bit 0 for Blue data. Note 2: 1-time is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: ‘=’ Don’t care – Can be set to ‘0’ or ‘1’ Figure40: Write 18-bits data for RGB 5-6-5-bits input (65k-color) Page 46 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 1 pixel (3 sub-pixels) per 1 transfer, 18-bits/pixel RESX IM1/IM0 1 IM1, IM0 = 11 CSX D/CX WRX RDX R/WX ｀1＇ 8080-Series control pins 6800-Series control pins ｀0＇ E D17 - R1, Bit5 R2, Bit5 R2, Bit5 R2, Bit5 D16 - R1, Bit4 R2, Bit4 R3, Bit4 R4, Bit4 D15 - R1, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D14 - R1,Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D13 - R1,Bit1 R2, Bit1 R3, Bit1 R4, Bit1 D12 - R1,Bit0 R2, Bit0 R3, Bit0 R4, Bit0 D11 - G1, Bit5 G2, Bit5 G3, Bit5 G4, Bit5 D10 - G1, Bit4 G2, Bit4 G3, Bit4 G4, Bit4 D9 - G1, Bit3 G2, Bit3 G3, Bit3 G4, Bit3 D8 - G1, Bit2 G2, Bit2 G3, Bit2 G4, Bit2 D7 0 G1, Bit1 G2, Bit1 G3, Bit1 G4, Bit1 D6 0 G1, Bit0 G2, Bit0 G3, Bit0 G4, Bit0 D5 1 R1, Bit5 R2, Bit5 R3, Bit5 R4, Bit5 D4 0 R1, Bit4 R2, Bit4 R3, Bit4 R4, Bit4 D3 1 R1, Bit3 R2, Bit3 R3, Bit3 R4, Bit3 D2 1 R1, Bit2 R2, Bit2 R3, Bit2 R4, Bit2 D1 0 R1, Bit1 R2, Bit1 R3, Bit1 R4, Bit1 D0 0 R1, Bit0 R2, Bit0 R3, Bit0 R4, Bit0 Pixel n Pixel n Pixel n Pixel n 18-bit Frame Memoy 18-bit R 1 G 1 B 1 R 2 G 2 B 2 R 3 G 3 B 3 Note1: The data order is as follows, MSB = D17, LSB = D0 and picture data is MSB = Bit5, LSB = Bit0 for Red, Green and Blue data. Note 2: 1-time(D17 to D0) is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: ‘=’ Don’t care – Can be set to ‘0’ or ‘1’ Figure41: Write 18-bit data for RGB 6-6-6-bits input (262K colors) Page 47 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 7. Display Data RAM 7.1. Configuration The display data RAM stores display dots and consists of 384,504 bits (132x18x162 bits). There is no restriction on access to the RAM even when the display data on the same address is loaded to DAC. There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory. LCD Glass (132 x RGB x 162) Display Data RAM Organization MPU I/F Look-up table Latch Display Data RAM (132 x 162 x 18-bit) Liner Address Counter Row Address Counter Column Address Counter Scan Address Counter Host Interface Page 48 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 7.2. Memory to Display Address Mapping 7.2.1 132RGB x 132 resolution (GM[2:0] = “101”, SMX=SMY=SRGB=’0’) G1 B1 R2 G2 : : : : : : : : : : : : : : : : 1 132 S6 - - - - S391 S392 S393 S394 S395 S396 2 131 RGB Order RGB=1 S5 RGB=0 S4 RGB=1 1 2 3 4 5 6 7 8 9 10 11 12 : : : : 125 126 127 128 129 130 131 132 RA MY=0 MY=1 1 132 R1 2 131 3 130 4 129 5 128 6 127 7 126 8 125 9 124 10 123 11 122 12 121 : : : : : : : : : : : : 125 8 126 7 127 6 128 5 129 4 130 3 131 2 132 1 MX-0 CA MX-1 S3 RGB=0 S2 Piexel132 RGB=1 S1 Piexel131 RGB=0 Source Out RGB=0 Gate - - -- Pixel2 RGB=1 Pixel1 SA ML=0 ML=1 B2 - - - - R131 G131 B131 R132 G132 B132 1 132 - - -2 131 - - -3 130 - - -4 129 - - -5 128 - - -6 127 - - -7 126 - - -8 125 - - -9 124 - - -10 123 - - -11 122 - - -12 121 : : : : : : : : : : : : : : : : : : - - -: : : : : : : : : : : : : : : : : : - - -125 8 - - -126 7 - - -127 6 - - -128 5 - - -129 4 - - -130 3 - - -131 2 - - -132 1 ---131 132 2 1 ---- Page 49 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 7.2.2 130RGB x 130 resolution(GM[2:0] = “100”, SMX=SMY=SRGB=’0’) G1 B1 R2 G2 : : : : : : : : : : : : : : : : 1 130 S12 - - - - S391 S392 S393 S394 S395 S396 2 129 RGB Order RGB=1 S11 RGB=0 S10 RGB=1 1 2 3 4 5 6 7 8 9 10 11 12 : : : : 123 124 125 126 127 128 129 130 RA MY=0 MY=1 1 130 R1 2 129 3 128 4 127 5 126 6 125 7 124 8 123 9 122 10 121 11 120 12 119 : : : : : : : : : : : : 123 8 124 7 125 6 126 5 127 4 128 3 129 2 130 1 MX-0 CA MX-1 S9 RGB=0 S8 Piexel130 RGB=1 S7 Piexel129 - - -- RGB=0 Source Out RGB=0 Gate Pixel2 RGB=1 Pixel1 SA ML=0 ML=1 B2 - - - - R129 G129 B129 R130 G130 B130 1 130 - - -2 129 - - -3 128 - - -4 127 - - -5 126 - - -6 125 - - -7 124 - - -8 123 - - -9 122 - - -10 121 - - -11 120 - - -12 119 : : : : : : : : : : : : : : : : : : - - -: : : : : : : : : : : : : : : : : : - - -123 8 - - -124 7 - - -125 6 - - -126 5 - - -127 4 - - -128 3 - - -129 2 - - -130 1 ---129 130 2 1 ---- Page 50 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 7.2.3 128RGB x 160 resolution (GM[2:0] = “011”, SMX=SMY=SRGB=’0’) Note RA = Row Address CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 51 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 7.2.4 120RGB x 160 resolution (GM[2:0] = “010”, SMX=SMY=SRGB=’0’) Note RA = Row Address CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 52 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 7.2.5 128RGB x 128 resolution (GM[2:0] = “001”, SMX=SMY=SRGB=’0’) Note RA = Row Address CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 53 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 7.2.6 132RGB x 162 resolution (GM[2:0] = “000”, SMX=SMY=SRGB=’0’) Note RA = Row Address CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command Page 54 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 7.3. MCU to memory write/read direction (Address Counter) The address counter set the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected(RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the”Write access” is activated on the RAM. The locations of RAM are addressed by the address pointers. When GM=011, 132RGB x 162, the address ranges are X=0 to X=131 (83h) and Y=0 to Y=161 (A1h). Addresses outside these ranges are not allowed. Before writing to the RAM a window must be defined into which will be written. The window is programmable via the command register XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0(0h) YS=0(0h) and XE=131(83h), YE=161(A1h) In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address(X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS) For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and “MADCTR”, define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Below table shows the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image orientation, the controls for the column and page counters apply as below: Condition When RAMWR/RAMRD command is accepted Complete Pixel Read/Write action The Column counter value is larger than “End Column(XE)” The Column counter value is larger than “End Column (XE)” and the Row counter value is larger than “End Row(YE)” Page 55 of 183 Column Counter Return to “Start Column (XS)” Increment by 1 Return to “Start Column (XS)” Return to “Start Column (XS)” Row Counter Return to “Start Row (YS) No change Increment by 1 Return to “Start Row (YS) Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Figure42: Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY) Display Data Direction MADCTR Parameter MV MX MY Image in the Memory (MPU) H/W position(0,0) B Normal 0 0 Image in the Driver (DDRAM) 0 B X-Y address (0,0) X: CASET Y: RASET E E Y-Mirror 0 0 1 E B X-Mirror 0 1 X-Y address (0,0) X: CASET Y: RASET 1 B 0 E 1 B E H/W position(0,0) B X-Y Exchange 1 0 0 E X-Y Exchange Y-Mirror 0 1 X-Y address (0,0) X: CASET Y: RASET B 1 1 E B B 0 X-Y address (0,0) X: CASET Y: RASET E E XY Exchange E H/W position(0,0) B 1 X-Y address (0,0) X: CASET Y: RASET 1 E XY Exchange X-Y address (0,0) X: CASET Y: RASET B H/W position(0,0) B 1 X-Y address (0,0) X: CASET Y: RASET E H/W position(0,0) B 0 B H/W position(0,0) E X-Mirror Y-Mirror E H/W position(0,0) B H/W position(0,0) E 1 E Page 56 of 183 B X-Y address (0,0) X: CASET Y: RASET Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 8. Tearing Effect Output Line The Tearing Effect output line supplies to the MCU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect Signal is defined by the Parameter of the Tearing Effect Line On command. The signal can be used by the MCU to synchronize Frame Memory Writing when displaying video images. 8.1. Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Sync information only: tvdl tvdh Vertical Time Scale tvdh = The LCD display is not updated from the Frame Memory. Tvdl = The LCD display is updated from the Frame Memory (except Invisible Line – see below). Mode 2, the Tearing Effect Output signal consists of V-Sync and H-Sync information, There is one V-sync and 162 H-sync pulses per field: tvdh tvdl V-Sync V-Sync Invisible Line 1st Line 162th Line thdh = The LCD display is not updated from the Frame Memory. Thdl = The LCD display is updated from the Frame Memory (except Invisible Line – see above). Bottom Line 1st Line 2nd Line TE (mode 2) TE (mode 1) Note: During Sleep In Mode, the Tearing Effect Output Pin is active Low. Page 57 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 8.2. Tearing Effect Line Timing The Tearing Effect signal is described below: tvdl tvdh Vertical Timing Horizontal Timing thdl thdh Table 8.2.1 AC characteristics of Tearing Effect Signal Symbol tvdl tvdh thdl thdh Idle Mode Off/On (Frame Rate = 58.9Hz) Parameter Vertical Timing Low Duration Vertical Timing High Duration Horizontal Timing Low Duration Horizontal Timing High Duration min 13 1000 33 25 max 500 unit Ms μs μs μs descritpion Notes: 1. The timings in Table 8.3.1 apply when MADCTL B4=0 and B4=1 2. The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. Figure43: Rise and fall times tr tf 80% 80% 20% 20% The Tearing Effect Output Line is fed back to the MCU and should be used as shown below to avoid Tearing Effect: Page 58 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 8.2.1 Example 1 MCU Write is Faster than Panel Read Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: 8.2.2 Example 2 MCU Write is slower than Panel Read The MCU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync Page 59 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the MCU to Frame memory write position. Page 60 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 9. Power ON/OFF Sequence VDDI and VDD can be applied in any order. VDD and VDDI can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX has been released. During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. Notes: 1. There will be no damage to the display module if the power sequences are not met. 2. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. 3. There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. 4. If RESX line is not held stable by host during Power On Sequence as defined in Sections 8.5.1 and 8.5.2, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. 9.1. Case 1 – RESX line is held high or Unstable by Host at Power –On If RESX line is held high or unstable by the host during Power On, then a Hardware Reset must be applied after both VDD and VDDI have been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset. Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level. 9.2. Case 2 – RESX line is held Low by Host at Power On If RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum Page 61 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 10μsec after both VDD and VDDI have been applied. Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level. 9.3. Uncontrolled Power Off The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. The display module must meet following requirements: 1. There cannot be any damages for the display module or the display module cannot cause any damages for the host or lines of the interface. 2. There cannot be any abnormal visible effects (= Display must be blank) within 1 second on the display and remains blank until “Power On Sequence” powers it up. 10. Power Level Definition 10.1. Power Levels 6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode. Page 62 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 In this mode, the DC:DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. V.. Power Off Mode. In this mode, both VDD and VDDI are removed. Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed. Page 63 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 10.2. Power Flow Chart Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode. Note 2: There is not any limitation, which is not specified by Nokia, when there is changing from one power mode to another power mode. Page 64 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 11. Gamma Curves Page 65 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 12. Reset 12.1. Registers The registers that are initialized are listed below. Reset Table (Default Value, GM=000, 128RGB x 160) Item Frame memory Sleep In/Out Display In/Out Display mode(normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address(XS) After Power On Random In Off Normal Off Off 0000h After Hardware Reset No Change In Off Normal Off Off 0000h Column: end Address(XE) 007Fh 007Fh Row: Start Address(YS) 0000h 0000h Row: End Address(YE) 009Fh 009Fh GC0 TBD 0000h 009Fh Off 0000h 00A0h 0000h 0000h Off 0(Mode1) GC0 TBD 0000h 009Fh Off 0000h 00A0h 0000h 0000h Off 0(Mode1) No Change In Off Normal Off Off 0000h 007Fh(127d) (when MV=0) 009Fh(159d) (when MV=1) 0000h 009Fh(159d) (when MV=0) 007Fh(127d) (when MV=1) GC0 No Change 0000h 009Fh Off 0000h 00A0h 0000h 0000h Off 0(Mode1) 0/0/0/0/0/0 0/0/0/0/0/0 No change 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value 6 (18-Bit/Pixel) No change 08h 00h 6 (18-Bit/Pixel) 08h No change No change 00h 00h 00h 54h MTP Value MTP Value 00h 00h 00h 54h MTP Value MTP Value Gamma Setting Color Set Partial: Start Address(PSL) Partial: End Address(PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area(TFA) Scroll: Scroll area(VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address(SSA) Tearing: On/Off Tearing Effect Mode*3 Memory Data Access Control (MY/MX/MV/ML/MH/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 After Software Reset Notes: 1. There will be no abnormal visible effects on the display when S/W or H/W Reset are applied. 2. After Powered-On Reset finishes within 10μs after both VDD & VDDI are applied. 3. Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. Page 66 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Reset Table (Default Value, GM=010, 120RGB x 160) Item After Power On Frame memory Sleep In/Out Display In/Out Display mode(normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address(XS) Random In Off Normal Off Off 0000h After Hardware Reset No Change In Off Normal Off Off 0000h After Software Reset Column: end Address(XE) 0077h 0077h Row: Start Address(YS) 0000h 0000h Row: End Address(YE) 009Fh 009Fh Gamma Setting Color Set Partial: Start Address(PSL) Partial: End Address(PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area(TFA) Scroll: Scroll area(VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address(SSA) Tearing: On/Off Tearing Effect Mode*3 Memory Data Access Control (MY/MX/MV/ML/MH/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 GC0 TBD 0000h 009Fh Off 0000h 00A0h GC0 TBD 0000h 009Fh Off 0000h 00A0h No Change In Off Normal Off Off 0000h 0077h(119d) (when MV=0) 0077h(159d) (when MV=1) 0000h 009Fh(159d) (when MV=0) 0077h(119d) (when MV=1) GC0 No Change 0000h 009Fh Off 0000h 00A0h 0000h 0000h 0000h 0000h Off 0(Mode1) 0000h Off 0(Mode1) 0000h Off 0(Mode1) 0/0/0/0/0/0 0/0/0/0/0/0 No change 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value No change 08h No change No change 00h 00h 00h 54h MTP Value MTP Value Notes: 1. There will be no abnormal visible effects on the display when S/W or H/W Reset are applied. 2. After Powered-On Reset finishes within 10μs after both VDD & VDDI are applied. 3. Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. Page 67 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Reset Table (Default Value, GM=010, 128RGB x 128) Item After Power On Frame memory Sleep In/Out Display In/Out Display mode(normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address(XS) Random In Off Normal Off Off 0000h After Hardware Reset No Change In Off Normal Off Off 0000h After Software Reset Column: end Address(XE) 007Fh 007Fh Row: Start Address(YS) 0000h 0000h Row: End Address(YE) 007Fh 007Fh Gamma Setting Color Set Partial: Start Address(PSL) Partial: End Address(PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area(TFA) Scroll: Scroll area(VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address(SSA) Tearing: On/Off Tearing Effect Mode*3 Memory Data Access Control (MY/MX/MV/ML/MH/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 GC0 TBD 0000h 007Fh Off 0000h 0080h GC0 TBD 0000h 007Fh Off 0000h 0080h No Change In Off Normal Off Off 0000h 007Fh(127d) (when MV=0) 0077h(127d) (when MV=1) 0000h 007Fh(127d) (when MV=0) 007Fh(127d) (when MV=1) GC0 No Change 0000h 007Fh Off 0000h 0080h 0000h 0000h 0000h 0000h Off 0(Mode1) 0000h Off 0(Mode1) 0000h Off 0(Mode1) 0/0/0/0/0/0 0/0/0/0/0/0 No change 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value No change 08h No change No change 00h 00h 00h 54h MTP Value MTP Value Notes: 1. There will be no abnormal visible effects on the display when S/W or H/W Reset are applied. 2. After Powered-On Reset finishes within 10μs after both VDD & VDDI are applied. 3. Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. Page 68 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Reset Table (Default Value, GM=011, 132RGB x 162) Item After Power On Frame memory Sleep In/Out Display In/Out Display mode(normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address(XS) Random In Off Normal Off Off 0000h After Hardware Reset No Change In Off Normal Off Off 0000h After Software Reset Column: end Address(XE) 0083h 0083h Row: Start Address(YS) 0000h 0000h Row: End Address(YE) 00A1h 00A1h Gamma Setting Color Set Partial: Start Address(PSL) Partial: End Address(PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area(TFA) Scroll: Scroll area(VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address(SSA) Tearing: On/Off Tearing Effect Mode*3 Memory Data Access Control (MY/MX/MV/ML/MH/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 GC0 TBD 0000h 00A1h Off 0000h 00A2h GC0 TBD 0000h 00A1h Off 0000h 00A2h No Change In Off Normal Off Off 0000h 0083h(131d) (when MV=0) 00A1h(161d) (when MV=1) 0000h 00A1h(161d) (when MV=0) 0083h(131d) (when MV=1) GC0 No Change 0000h 00A1h Off 0000h 00A2h 0000h 0000h 0000h 0000h Off 0(Mode1) 0000h Off 0(Mode1) 0000h Off 0(Mode1) 0/0/0/0/0/0 0/0/0/0/0/0 No change 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value No change 08h No change No change 00h 00h 00h 54h MTP Value MTP Value Notes: 1. There will be no abnormal visible effects on the display when S/W or H/W Reset are applied. 2. After Powered-On Reset finishes within 10μs after both VDD & VDDI are applied. 3. Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. Page 69 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Reset Table (Default Value, GM=100, 130RGB x 130) Item Frame memory Sleep In/Out Display In/Out Display mode(normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address(XS) After Power On Random In Off Normal Off Off 0000h After Hardware Reset No Change In Off Normal Off Off 0000h Column: end Address(XE) 0081h 0081h Row: Start Address(YS) 0000h 0000h Row: End Address(YE) 0081h 0081h GC0 TBD 0000h 0081h Off 0000h 0082h 0000h 0000h Off 0(Mode1) GC0 TBD 0000h 0081h Off 0000h 0082h 0000h 0000h Off 0(Mode1) After Software Reset No Change In Off Normal Off Off 0000h 0081h(when MV=0) 0081h(when MV=1) 0000h 0081h(when MV=0) 0081h(when MV=1) GC0 No Change 0000h 0081h Off 0000h 0082h 0000h 0000h Off 0(Mode1) 0/0/0/0/0/0 0/0/0/0/0/0 No change 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value No change 08h No change No change 00h 00h 00h 54h MTP Value MTP Value Gamma Setting Color Set Partial: Start Address(PSL) Partial: End Address(PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area(TFA) Scroll: Scroll area(VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address(SSA) Tearing: On/Off Tearing Effect Mode*3 Memory Data Access Control (MY/MX/MV/ML/MH/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 Notes: 1. There will be no abnormal visible effects on the display when S/W or H/W Reset are applied. 2. After Powered-On Reset finishes within 10μs after both VDD & VDDI are applied. 3. Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. Page 70 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Reset Table (Default Value, GM=101, 132RGB x 132) Item Frame memory Sleep In/Out Display In/Out Display mode(normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address(XS) After Power On Random In Off Normal Off Off 0000h After Hardware Reset No Change In Off Normal Off Off 0000h Column: end Address(XE) 0083h 0083h Row: Start Address(YS) 0000h 0000h Row: End Address(YE) 0083h 0083h GC0 TBD 0000h 0083h Off 0000h 0084h 0000h 0000h Off 0(Mode1) GC0 TBD 0000h 0083h Off 0000h 0084h 0000h 0000h Off 0(Mode1) No Change In Off Normal Off Off 0000h 0083h(when MV=0) 0083h(when MV=1) 0000h 0083h(when MV=0) 0083h(when MV=1) GC0 No Change 0000h 0083h Off 0000h 0084h 0000h 0000h Off 0(Mode1) 0/0/0/0/0/0 0/0/0/0/0/0 No change 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 54h MTP Value MTP Value No change 08h No change No change 00h 00h 00h 54h MTP Value MTP Value Gamma Setting Color Set Partial: Start Address(PSL) Partial: End Address(PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area(TFA) Scroll: Scroll area(VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address(SSA) Tearing: On/Off Tearing Effect Mode*3 Memory Data Access Control (MY/MX/MV/ML/MH/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 After Software Reset Notes: 1. There will be no abnormal visible effects on the display when S/W or H/W Reset are applied. 2. After Powered-On Reset finishes within 10μs after both VDD & VDDI are applied. 3. Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. 12.2. Input/Output Pins 12.2.1 Output Pins, I/O Pins Output or Bi-direction pins After Power On After Hardware Reset After Software Reset TE Low Low Low D17to D0(Output driver) High-Z(Inactive) High-Z(Inactive) High-Z(Inactive) Page 71 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Note: There will be no output from D[7..0] and SDA during Power On/Off sequences, Hardware Reset and Software Reset. 12.2.2 Input Pins Input During Power On After After Hardware After Software During Power Off pins Process Power On Reset Reset Process RESX TBD Input invalid Input invalid Input invalid ? CSX Input invalid Input invalid Input invalid Input invalid Input invalid D/CX Input invalid Input invalid Input invalid Input invalid Input invalid WRX Input invalid Input invalid Input invalid Input invalid Input invalid RDX Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid D17 to D0 SDA 12.3. Reset Timing (VSS=0V, VDDI=1.65V to 1.95V, VDD=2.6V to 2.9V, Ta = -30 to 70℃) Symbol Parameter Related MIN TYP MAX 10 - - - - - 5 - - - 120 Note Unit - μs When reset applied ms Pins tRESW tREST *1) Reset low pulse width RESX *2) Reset complete width during Sleep in mode When reset applied ms during Sleep out mode Note 1. Spike due to an electrostatic discharge on RESX line does not cause system reset according to the table below. Page 72 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 RESX Pulse Action Shorten than 5μs Reset Rejected Longer than 10μs Reset Between 5μs and 10μs Reset starts (It depends on voltage and temperature condtion.) 2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then return to Default condition for Hardware Reset. 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX. 4. Spike Rejection also applies during a valid reset pulse as shown below: 5. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec. 13. SleepOut – Command and Self-Diagnostic Functions of Display 13.1. Register loading Detection Sleep Out-command (See section 16.1.2.12 Sleep Out (11h)) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from EEPROM (or similar device) to registers of the display controller is working properly. There are compared factory values of the EEPROM and register values of the display controller by the display controller. If those both values (EEPROM and register values) are same, there is inverted (= increased by 1) a bit, which is defined in command 16.1.2.10 “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of this command is D7). If those both values are not same, the bit(D7) is not inverted (= increased by 1) The flow chart for this internal function is following: Page 73 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Note: There is not compared and loaded register values, which can be changed by user (00h to Afh and Dah to DDh), by the display module. 13.2. Functionality Detection Sleep Out-command (See section 16.1.2.12 Sleep Out (11h)) is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (only Booster voltage level). If functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command 16.1.2.10 “Read Display Self-Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (=increased by 1). The flow chart for this internal function is following: Page 74 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Note: There is needed 120msec after Sleep Out –command, when there is changing from Sleep In –mode to Sleep Out –mode, before there is possible to check if Nokia’s functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out –mode. Page 75 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14. Command 14.1. Command List Hex Command Code Description Number of Display Architecture Implementation Parameters Requirement Type 1 Type 2 Type 3 00h nop No Operation 0 Yes Yes Yes 01h soft_reset Software Reset 0 Yes Yes Yes 06h get_red_channel Get the red component of the pixel at (0, 0). 1 No Yes Yes 07h get_green_channel Get the green component of the pixel at (0, 0). 1 No Yes Yes 08h get_blue_channel Get the blue component of the pixel at (0, 0). 1 No Yes Yes 0Ch get_pixel_format Get the current pixel format. 1 Yes Yes Yes 0Ah get_power_mode Get the current power mode. 1 Yes Yes Yes 1 Yes Yes Yes 1 Yes Yes Yes Yes Get the frame memory to the display panel read 0Bh get_address_mode 0Dh get_display_mode 0Eh get_signal_mode Get display module signaling mode. 1 Yes Yes 0Fh get_diagnostic_result Get Peripheral Self-Diagnostic Result 1 Yes Yes Yes 10h enter_sleep_mode Power for the display panel is off. 0 Yes Yes Yes 11h exit_sleep_mode Power for the display panel is on. 0 Yes Yes Yes 0 Yes Yes No 0 Yes Yes No order. Get the current display mode from the peripheral. Part of the display area is used for image 12h enter_partial_mode 13h enter_normal_mode 20h exit_invert_mode Displayed image colors are not inverted. 0 Yes Yes Yes 21h enter_invert_mode Displayed image colors are inverted. 0 Yes Yes Yes 26h set_gamma_curve 1 Yes Yes Yes display. The whole display area is used for image display. Selects the gamma curve used by the display device. 28h set_display_off Blanks the display device. 0 Yes Yes Yes 29h set_display_on Show the image on the display device. 0 Yes Yes Yes 2Ah set_column_address Set the column extent. 4 Yes Yes No 2Bh set_page_address Set the page extent. 4 Yes Yes No 2Ch write_memory_start Variable Yes Yes No Variable optional No No Variable Yes Yes No 4 Yes Yes No 6 Yes No No 0 Yes No No 1 Yes No No Transfer image data from the Host Processor to the peripheral starting at the location provided by set_column_address and set_page_address. 2Dh write_LUT Fills the peripheral look-up table with the provided data. Transfer image data from the peripheral to the 2Eh read_memory_start Host Processor interface starting at the location provided by set_column_address and set_page_address. 30h set_partial_area 33h set_scroll_area 34h set_tear_off 35h set_tear_on Defines the partial display area on the display device. Defines the vertical scrolling and fixed area on display device. Synchronization information is not sent from the display module to the host processor. Synchronization information is sent from the display module to the host processor at the start of VFP. Page 76 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color 36h set_address_mode Set the read order from frame memory to the display panel. 1 ILI9163 Yes Yes Yes 37h set_scroll_start Defines the vertical scrolling starting point. 2 Yes No No 38h exit_idle_mode Full color depth is used on the display panel. 0 Yes No No 39h enter_idle_mode 0 Yes No No 3Ah set_pixel_format 1 Yes Yes Yes 3Ch write_memory_continue Variable Yes Yes No Variable Yes Yes No 2 Yes No No 2 Yes Yes No Reduced color depth is used on the display panel. Defines how many bits per pixel are used in the interface. Transfer image information from the Host Processor interface to the peripheral from the last written location. Read image data from the peripheral continuing 3Eh read_memory_continue after the last read_memory_continue or read_memory_start. Synchronization information is sent from the 44h set_tear_scanline 45h get_scanline display module to the host processor when the display device refresh reaches the provided scanline. Dah Read ID1 DBh Read ID2 DCh Read ID3 Get the current scanline. Notes: 1. There will be no abnormal visible effects on the display when S/W or H/W Reset are applied. 2. After Powered-On Reset finishes within 10μs after both VDD & VDDI are applied. 3. Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. Page 77 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2. Command Description 14.2.1 NOP (00h) 00H Command Parameter NOP (No Operation) D/CX RDX WRX D17-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ X 0 0 0 0 0 0 0 0 00 NO PARAMETER This command is an empty command; it does not have any effect on the display module. However it can be used to terminate Frame Memory Write or Read as described in RAMWR (Memory Write) and RAMRD (Memory Read) Description Commands. X = Don’t care. Restriction None Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence N/A SW Reset N/A HW Reset N/A Default Flow Chart None Page 78 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.2 Software Reset (01h) 01H Command Parameter SWRESET (Software Reset) D/CX RDX WRX D17-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ X 0 0 0 0 0 0 0 1 01 NO PARAMETER When the Software Reset command is written, it causes software reset. It resets the commands and parameters to their S/W Reset default values. (See default tables in each command description.) Description Note: The Frame Memory contents are affected by this command. X = Don’t care Register Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Availability Default Status Default Value Power On Sequence N/A SW Reset N/A HW Reset N/A Legend SW RESET command Parameter Display whole blank screen Display Flow Chart Action Mode Set Commands to S/W Default Vaule Sequential transfer Sleep in Mode Page 79 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.3 Read Display Identification Information (04h) 00H RDDIDIF (Read Display Identification Information) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 0 0 1 0 0 04 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 x ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 54h 1 ↑ 1 x ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 80h 1 ↑ 1 x ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 66h Command 1 st Parameter 2 nd Parameter 3 rd Parameter 4 th Parameter This read byte returns 24-bit display identification information. st The 1 Parameter is dummy read. nd The 2 Parameter (ID17 to ID10): LCD module’s manufacture ID. rd (ID27 to ID20): LCD module/driver version ID th (ID37 to ID30): LCD module/driver version ID The 3 Parameter Description The 4 Parameter Note: Commands RDID1/2/3(Dah, DBh, DCh) read data correspond to the parameters 2,3,4 of command 04h, respectively Restriction - Status Register Availability Note: ID1 can be Default option Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value ID1 ID2 modified by metal ID3 Power On Sequence 54h 80h 66h SW Reset 54h 80h 66h HW Reset 54h 80h 66h Page 80 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Serial I/F Mode ILI9163 Parallel I/F Mode RDDID(04h) Legend RDDID(04h) Host command Driver Parameter Dummy Clock Dummy Read Display Action Flow Chart Send ID 1[7:0] Mode Send ID 1[7:0] Sequential transfer Send ID 2[7:0] Send ID 2[7:0] Send ID 3[7:0] Send ID 3[7:0] 14.2.4 Read Display Status (09h) 09H Command 1 RDDIDIF (Read Display Identification Information) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 0 1 0 0 1 09h 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 x BOTSON MY MX MV ML RGB MH ST24 x 1 ↑ 1 x ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON x 1 ↑ 1 x VSSON ST14 INVON ST12 ST11 DISON TEON GCS2 x 1 ↑ 1 x GCS1 GCS0 TELOM HSON VSON PCKON DEON ST0 x st Parameter 2 nd Parameter 3 rd Parameter 4 th Parameter 5 th Parameter This command indicates the current status of the display as described in the table below: Bit Description Value BSTON Booster Voltage Status “1”=Booster on,”0”=Booster off MY Row Address Order(MY) “1”=Decrement, (Bottom to Top, when MADCTL(36h) D7=’1’) “0”=Increment, (Top to Bottom, when MADCTL(36h) D7=’0’) Description MX Column Address Order(MX) “1”=Decrement, (Right to Left, when MADCTL(36h) D6=’1’) “0”=Increment, (Left to Right, when MADCTL(36h) D6=’0’) MV Row/Column Exchange(MV) “1”=Row/column exchange, (when MADCTL (36h) D5=’1’) “0”=Normal (MV=0), (when MADCTL(36h)D5=’0’) ML Vertical refresh Order(ML) “1”=Decrement, (LCD refresh Bottom to Top, when Page 81 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 MADCTL(36h)D4=’1’) “0”=Increment, (LCD refresh Top to Bottom, when MADCTL(36h)D4=’0’) RGB RGB/BGR Order(RGB) “1”=BGR,(When MADCTL(36h)D3=’1’) “0”=RGB,(When MADCTL(36h)D3=’0’) MH Horizontal refresh Order(MH) “1”=Decrement, (LCD refresh Right to Left, when MADCTL(36h) D2=’1’) “0”=Increment, (LCD refresh Left to Right, when MADCTL(36h) D2=’0’) ST24 Not Used ST23 Not Used IFPF2 Interface Color Pixel Format “011”=12-bit/pixel IFPF1 Definition “101”=16-bit/pixel “110”=18-bit/pixel IFPF0 IDMON Idle Mode On/Off “1”=On,”0”=Off PTLON Partial Mode On/Off “1”=On,”0”=Off SLOUT Sleep In/Out “1”=On,”0”=Off NORON Display Normal Mode On/Off “1”=Normal Display, “0”=Normal Display Off VSSON Vertical Scrolling Status “1”=Scroll on,”0”=Scroll off ST14 Horizontal Scroll Status “0” INVON Inversion Status “1”=On, “0”=Off ST12 All Pixels On(Not Used) “0” ST11 All Pixels On(Not Used) “0” DISON Display On/Off “1”=On, “0”=Off TEON Tearing effect line on/off “1”=On, “0”=Off GCS2 Gamma Curve Selection “000”=GC0 “001”=GC1 “010”=GC2 “011”=GC3 “100” to “111” = Not defined GCS1 GCS TELOM Tearing effect line mode “0”=mode1,”1”=mode2 STO For Future Use “0” Note: For Bits ST30 to ST28, also refer to Section 8-11 Page 82 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Status Register Availability Status Default Power On Sequence ILI9163 Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value(ST31 to ST0) ST[31-24] ST[23-16] ST[15-8] ST[7-0] 0000-0000 0110-0001 0000-0000 0000-0000 SW Reset 0xxx-xxx0 0xxx-0001 0000-0000 0000-0000 HW Reset 0000-0000 0110-0001 0000-0000 0000-0000 Serial I/F Mode RDDST(09h) Parallel I/F Mode Legend RDDID(09h) Host Driver command Parameter Dummy Clock Dummy Read Display Action Flow Chart Send ST[31:24] Send ST[31:24] Mode Sequential transfer Send ST[23:16] Send ST[23:16] Send ST[15:8] Send ST[15:8] Send ST[7:0] Send ST[7:0] Page 83 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.5 Read Display Power Mode (0Ah) 0AH RDDPM (Read Display Power Mode) Inst / Para D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 0 0 0 0 1 0 1 0 0Ah 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 x D7 D6 D5 D4 D3 D2 D1 D0 08h 1 st Parameter 2 nd Parameter This command indicates the current status of the display as described in the table below: Descriptio n Bit Description D7 Booster Voltage Status Value D6 Idle Mode On/Off D5 Partial Mode On/Off D4 Sleep In/Out D3 Display Normal Mode On/Off “1”=Booster on, “0”=Booster off “1”=Idle Mode On, “0”=Idle Mode Off “1”=Partial Mode on, “0”=Partial Mode Off “1”=Sleep Out, “0”=Sleep In “1”=Normal Display, “0”=Partial Display D2 Display On/Off D1 Not Defined “1”=Display On, “0”=Display Off Set to ‘0’ D0 Not Defined Set to ‘0’ Status Register Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value(D7 to D0) Power On Sequence Default Serial I/F Mode Availability Normal Mode On, Idle Mode Off, Sleep Out 0000_1000(08h) SW Reset 0000_1000(08h) HW Reset 0000_1000(08h) Parallel I/F Mode Legend command RDDPM(0Ah) RDDPM(0Ah) Parameter Host Flow Chart Display Driver Action Send D[7:0] Dummy Read Mode Sequential transfer Send D [7:0] Page 84 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.6 Read Display MADCTL (0Bh) 0BH RDDMADCTL (Read Display MADCTL) D/CX RDX WRX D17-0 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 0 0 0 0 1 0 1 1 0Bh st 1 ↑ 1 x x x x x x x x x x nd 1 ↑ 1 x D7 D6 D5 D4 D3 D2 D1 D0 00h 1 Parameter 2 Parameter This command indicates the current status of the display as described in the table below: Bit Description Description Value D7 Page Address Order “1”=Decrement, “0”=Increment D6 Column Address Order D5 Page/Column Order “1”=Row/column exchange(MV=1) D4 Line Address Order “1”=LCD Refresh Bottom to Top D3 RGB/BGR Order D2 Display Data Latch Order “1”=Decrement, “0”=Increment “0”=Normal(MV=0) “0”=LCD Refresh Top to Bottom “1”=BGR, “0”=RGB “1”=LCD Refresh right to left “0”=LCD Refresh left to right D1 Switching between Segment outputs and RAM Set to ‘0’ D0 Switching between Common outputs and RAM Set to ‘0’ Status Register Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Availability Normal Mode On, Idle Mode Off, Sleep Out Default Value(D7 to D0) Power On Sequence 0000_0000(00h) SW Reset Serial I/F Mode No Change Parallel I/F Mode Legend command RDDMADCTR(0Bh) RDDMADCTR(0Bh) Parameter Host Flow Chart Display Driver Action Send D[7:0] Dummy Read Mode Sequential transfer Send D [7:0] Page 85 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.7 Read Display Pixel Format (0Ch) 0CH Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 0 1 1 0 0 0Ch 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 x x x x x D3 IFPF2 IFPF1 IFPF0 66h st Parameter 2 RDDCOLMOD (Read Display COLMOD) nd Parameter This command indicates the current status of the display as described in the table below: Bit Descriptio n Description Value D3 ”0” (Not used) “011”=12 bit/pixel IFPF2 IFPF 1 “101”=16 bit/pixel Control Interface Color Format “110”=18 bit/pixel IFPF 0 The others = not defined Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence Default Serial I/F Mode 0110_0110(18bit/pixel) SW Reset No Change HW Reset 0110_0110(18bit/pixel) Parallel I/F Mode Legend command RDDCOLMOD(0Eh) RDDCOLMOD(0Eh) Parameter Host Display Driver Flow Chart Action Send D[7:0] Dummy Read Mode Sequential transfer Send D [7:0] Page 86 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.8 Read Display Image Mode (0Dh) 0DH Command 1 RDDIM (Read Display Image Mode) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 0 1 1 0 1 0Dh 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 x D7 D6 D5 D4 D3 D2 D1 D0 00h st Parameter 2 nd Parameter Description Bit Description Value D7 Vertical Scrolling On/Off “1”=Vertical scrolling is On, “0”=Vertical scrolling is Off D6 Horizontal Scrolling On/Off “0”(Not used) D5 Inversion On/Off “1”=Inversion is On, “0”=Inversion is Off D4 All Pixels On “0” (Not used) D3 All Pixel Off “0” (Not used) “000”=GC0; “001”=GC1; “010”=GC2; “011”=GC3 D2 D1 “100” to “111” = Not defined Gamma Curve Selection D0 Status Register Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Serial I/F Mode Availability Default Value(D7 to D0) Power On Sequence 0000_0000(00h) SW Reset 0000_0000(00h) Parallel I/F Mode Legend command RDDID(0Dh) RDDPM(0Dh) Parameter Host Flow Chart Display Driver Action Send D[7:0] Dummy Read Mode Sequential transfer Send D [7:0] Page 87 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.9 Read Display Signal Mode (0Eh) 0EH Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 0 1 1 1 0 0Eh 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 x D7 D6 x x x x 0 0 00h st Parameter 2 RDDSM (Read Display Signal Mode) nd Parameter This command indicates the current status of the display as described in the table below: Description Bit Description Value D7 Tearing Effect Line On/Off “1”=On, “0”=Off D6 Tearing Effect Line Mode “0”=mode1, “1”=mode2 D1 Not Used “1”=On, “0”=Off D0 Not Used “1”=On, “0”=Off Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Serial I/F Mode Default Value(D7 to D0) Power On Sequence 0000_0000(00h) SW Reset 0000_0000(00h) Parallel I/F Mode Legend command RDDID(0Eh) RDDPM(0Eh) Parameter Host Flow Chart Display Driver Action Send D[7:0] Dummy Read Mode Sequential transfer Send D [7:0] Page 88 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.10 Read Display Signal Mode (0Fh) 0EH Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 0 1 1 1 1 0Fh 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 x D7 D6 D5 D4 D3 D2 D1 D0 00h st Parameter 2 RDDSM (Read Display Signal Mode) nd Parameter This command indicates the current status of the display as described in the table below: Bit Description D7 Register Loading Detection Value D6 Functionality Detection Descriptio D5 Not Used “0” n D4 Not Used “0” D3 Not Used “0” D2 Not Used “0” D1 Not Used “0” D0 Not Used “0” Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Serial I/F Mode Default Value(D7 to D0) Power On Sequence 0000_0000(00h) SW Reset 0000_0000(00h) Parallel I/F Mode Legend command RDDID(0Fh) RDDPM(0Fh) Parameter Host Flow Chart Display Driver Send 2nd Parameter Action Dummy Read Mode Send 2nd Parameter Page 89 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.11 Sleep In (10h) 10H Command Parameter SLPIN (Sleep In) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 1 0 0 0 0 10h No Parameter This command causes the LCD module to enter the minimum power consumption mode. Description In this mode e.g. the DC/DC converter is stopped, Internal oscillator is stopped, and panel scanning is stopped. MCU interface and memory are still working and the memory keeps its contents. This command has no effect when module is already in sleep in mode. Sleep In Mode can only be left by the Sleep Out Command (11h). It will be necessary to wait 5msec before sending next command; this is to allow time for the supply Restriction voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Status Register Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Availability Normal Mode On, Idle Mode Off, Sleep Out Default Value Power On Sequence SW Reset Sleep In Mode Sleep In Mode It takes 120msec to get into Sleep In mode after SLPIN command issued. Legend command SPLIN Stop DC/DC Converter Parameter Display Action Flow Chart Display whole blank screen (automatic No effect to DISP ON/OFF command) Drain charge from LCD panel Mode Stop Internal Oscillator Sequential transfer Sleep In Mode Page 90 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.12 Sleep Out (11h) 11H Command SLPOUT (Sleep Out) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 1 0 0 0 1 11h Parameter No Parameter Descriptio n This command turns off sleep mode. In this mode e.g. the DC/DC converter is enabled, Internal oscillator is started, and panel scanning is started. This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be left by the Sleep In Command (10h). It will be necessary to wait 5msec before sending next command; this is to allow time for the supply voltages and clock circuits to stabilize. The display module loads all display supplier’s factory default values to the registers during this 5msec and there cannot Restriction be any abnormal visual effect on the display image if factory default and register values are same when this load is done and when the display module is already Sleep Out –mode. The display module is doing self-diagnostic functions during this 5msec. It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent. This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be left by HW Reset, Software Reset (01h), Sleep In (10h), or a NMI event trigger. Status Register Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Flow Chart Availability Normal Mode On, Idle Mode Off, Sleep Out Power On Sequence Default Value Sleep In Mode SW Reset Sleep In Mode HW Reset Sleep In Mode It takes 120msec to become Sleep Out mode after SLPOUT command issued. Page 91 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend command SPLOUT Display whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF Commands) Parameter Display Action Start Internal Oscillator Mode Display Memory contents in accordance with the current command table settings Sequential transfer Start DC-DC Converter Sleep In Mode Charge Offset voltage for LCD Panel Page 92 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.13 Partial Mode On (12h) 12H Command Parameter PTLON (Partial Mode On) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 1 0 0 1 0 12h No Parameter This command turns on partial mode. The partial mode is described by the Partial Area command (30h). To leave Partial mode, the Normal Display On command (13h) should be written. Description X = Don’t care Note: If a command is written in a frame cycle, the command becomes effective from the next frame. Restriction This command has no effect during Partial mode is active. Status Register Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Power On Sequence Default Flow Chart Availability Normal Mode On, Idle Mode Off, Sleep Out Default Value Normal Display Mode On SW Reset Normal Display Mode On HW Reset Normal Display Mode On See Partial Area (30h) Page 93 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.14 Normal Display Mode On (13h) 13H Command Parameter PTLON (Partial Mode On) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 0 1 0 0 1 1 13h No Parameter This command returns the display to normal mode. Normal display mode on means Partial mode off and Scroll mode Off. Description Exit from NORON by the Partial mode On command(12h) X = Don’t care Note: If a command is written in a frame cycle, the command becomes effective from the next frame. Restriction Register Availability This command has no effect when Normal Display mode is active. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Flow Chart Power On Sequence Default Value Normal Display Mode On SW Reset Normal Display Mode On HW Reset Normal Display Mode On See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command. Page 94 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.15 Display Inversion Off (20h) 20H Command Parameter PTLON (Partial Mode On) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 0 0 0 0 0 20h No Parameter This command is used to recover from display inversion mode. This command makes no change of contents of frame memory. This command does not change any other status. Memory Display Panel Description X = don’t care Restriction This command has no effect when module is already in inversion off mode. Status Register Availability Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Availability Normal Mode On, Idle Mode Off, Sleep Out Power On Sequence Default Value Normal Display Mode Off SW Reset Normal Display Mode Off HW Reset Normal Display Mode Off Legend Display Inversion On Mode command Parameter Display Flow Chart INVOFF(20h) Action Mode Display Inversion Off Mode Page 95 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.16 Display Inversion On (21h) 21H Command Parameter PTLON (Partial Mode On) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 0 0 0 0 1 21h No Parameter This command is used to enter into display inversion mode. This command makes no change of contents of frame memory. Every bit is inverted from the frame memory to the display. This command does not change any other status. To exit from Display inversion On, the Display Inversion Off command(20h) should be written. Memory Display Panel Description X = don’t care Restriction This command has no effect when module is already in inversion on mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence Default Value Normal Display Mode Off SW Reset Normal Display Mode Off HW Reset Normal Display Mode Off Legend Display Inversion On Mode command Parameter Display Flow Chart INVON(21h) Action Mode Display Inversion Off Mode Page 96 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.17 Gamma Set (26h) 26H GAMSET (Gamma Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 0 0 1 0 0 1 1 0 26h Parameter 1 1 ↑ x GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0 01h This command is used to select the desired Gamma curve for the current display. A maximum of 4 fixed gamma curves can be selected. The curves are defined Gamma Curve Correction Power Supply Circuit. The curve is selected by setting the appropriate bit in the parameter as described in the Table: GC[7..0] Parameter Curve Selected 01h GC0 Gamma Curve 1 02h GC1 Gamma Curve 2 04h GC2 Gamma Curve 3 08h GC3 Gamma Curve 4 Description Note: All other values are undefined. X = don’t care Values of GC[7..0] not shown in table above are invalid and will not change the current selected Gamma curve until valid Restriction value is received. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence Default Value 01h SW Reset 01h HW Reset 01h Partial Mode Legend GAMSET (26h) command Parameter Flow Chart Display 1st Parameter: GC[7:0] Action Mode New Gamma Curve Loaded Page 97 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.18 Display Off (28h) 28H Command Parameter DISPOFF (Display Off) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 0 1 0 0 0 28h No Parameter This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and blank page inserted. This command makes no change of contents of frame memory. This command does not change any other status. There will be no abnormal visible effect on the display. Exit from this command by Display On(29h) Memory Display Panel Description X = don’t care Restriction This command has no effect when module is already in display off mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence Default Value Display Off SW Reset Display Off HW Reset Display Off Flow Chart Page 98 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend Display On Mode command Parameter Display DISPOFF(28h) Action Mode Display Off Mode Sequential transfer Page 99 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.19 Display On (29h) 29H Command Parameter DISPON (Display On) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 0 1 0 0 1 29h No Parameter This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. This command makes no change of contents of frame memory. This command does not change any other status. Memory Display Panel Description X = don’t care Restriction Register Availability This command has no effect when module is already in display on mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence Default Value Display Off SW Reset Display Off HW Reset Display Off Flow Chart Page 100 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend Display On Mode command Parameter Display DISPON(29h) Action Mode Display Off Mode Page 101 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.20 Column Address Set (2Ah) 2AH CASET (Column Address Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 0 1 0 1 0 2Ah 1 1 ↑ x XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS8 - 1 1 ↑ x XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 - 1 1 ↑ x XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8 - 1 1 ↑ x XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0 - Command 1 st Parameter 2 nd Parameter 3 rd Parameter 4 th Parameter This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The values of XS[15:0] and XE[15:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. XS[15:0] XE[15:0] Description X = don’t care XS [15:0] always must be equal to or less than XE[15:0]. When XS[15:0] or XE[15:0] is greater than maximum address like below, data of out of range will be ignored. 1. 132X132 memory base (GM=’101’) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦131(0083h):MV=”0”) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦131(0083h):MV=”1”) 2. 130X130 memory base (GM=’100’) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦129(0081h):MV=”0”) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦129(0081h):MV=”1”) 3. 128X160 memory base (GM=’011’) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦127(007Fh):MV=”0”) Restriction (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦159(009Fh):MV=”1”) 4. 120X160 memory base (GM=’010’) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦119(0077h):MV=”0”) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦159(009Fh):MV=”1”) 5. 128X128 memory base (GM=’001’) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦127(007Fh):MV=”0”) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦127(007Fh):MV=”1”) 6. 132X162 memory base (GM=’000’) (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦131(0083h):MV=”0”) Page 102 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 (Parameter range: 0≦XS[15:0] ≦XE[15:0] ≦127(00A1h):MV=”1”) X = Don’t care Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes 1. 132 x 132 memory base(GM=’101’) Status Power On Sequence 0000h S/W Reset 0000h HW Reset 0000h Status XS[15:0] 0000h S/W Reset 0000h HW Reset 0000h XS[15:0] 0000h S/W Reset 0000h HW Reset 0000h 0000h S/W Reset 0000h HW Reset 0000h 2. 130 x 130 memory base(GM=’100’) 0083h(131) 0083h(131) XE[15:0] 3. EX[15:0] (MV=1) 128 x 160 memory base(GM=’011’) 0081h(129) 0081h(129) 0081h(129) 0081h(129) 4. XE[15:0] 120 x 160 memory base(GM=’010’) EX[15:0] (MV=1) 007Fh(127) 007Fh(127) 5. 009Fh(159) 128 x 128 memory base(GM=’001’) 007Fh(127) XE[15:0] 6. EX[15:0] (MV=1) 132 x 162 memory base(GM=’000’) 0077h(119) 007Fh(119) 009Fh(159) 0077h(119) Default Value XS[15:0] Power On Sequence 0000h S/W Reset 0000h HW Reset 0000h Status 0083h(131) Default Value XS[15:0] Power On Sequence Status EX[15:0] (MV=1) 0083h(131) Default Value Power On Sequence Status XE[15:0] Default Value Power On Sequence Status Default Default Value XS[15:0] XE[15:0] EX[15:0] (MV=1) 007Fh(127) 007Fh(127) 009Fh(127) 0077h(119) Default Value XS[15:0] Power On Sequence 0000h S/W Reset 0000h HW Reset 0000h XE[15:0] EX[15:0] (MV=1) 0083h(131) 0083h(131) 00A1h(161) 0083h(131) Page 103 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 CASET (2Ah) 1st &2nd Parameter XS[15:0] 3rd & 4thparmeter XE[15:0] Legend command RASET (2Bh) Parameter If Needed Display Flow Chart 1st &2nd Parameter YS[15:0] 3rd & 4thparmeter YE[15:0] Action Mode Sequential transfer RAMWR(2Ch) Image Data D1[17:0],D2[17:0]..Dn[17:0] Any Commend Page 104 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.21 Page Address Set (2Bh) 2BH PASET (Page Address Set) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 0 1 0 1 1 2Bh 1 1 ↑ x YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8 - 1 1 ↑ x YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 - 1 1 ↑ x YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8 - 1 1 ↑ x YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 - Command 1 st Parameter 2 nd Parameter 3 rd Parameter 4 th Parameter This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes. Each value represents one Page line in the Frame Memory. YS[15:0] Description YE[15:0] YS [15:0] always must be equal to or less than EP [15:0]. When YS[15:0] or YE[15:0] is greater than maximum row address like below, data of out of range will be ignored. 1. 132X132 memory base (GM=’101’) (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦131(0083h)):MV=”0” (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦131(0083h)):MV=”1” 2. 130X130 memory base (GM=’100’) (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦129(0081h)):MV=”0” (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦129(0081h)):MV=”1” 3. Restriction 128X160 memory base (GM=’011’) (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦159(009Fh)):MV=”0” (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦127(007Fh)):MV=”1” 4. 120X160 memory base (GM=’010’) (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦159(009Fh)):MV=”0” (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦119(0077h)):MV=”1” 5. 128X128 memory base (GM=’001’) (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦127(007Fh)):MV=”0” (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦127(007Fh)):MV=”1” 6. 132X162 memory base (GM=’000’) Page 105 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦161(00A1h)):MV=”0” (Parameter range: 0≦YS[15:0] ≦YE[15:0] ≦131(0083h)):MV=”1” X = Don’t care Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes 1. 132 x 132 memory base(GM=’101’) Status Default Value YS[15:0] Power On Sequence 0000h S/W Reset 0000h HW Reset 0000h Status YX[15:0] (MV=1) 2. base(GM=’100’) 0083h(131) 0083h(131) 0083h(131) 130 x 130 memory 3. 0083h(131) 128X160 memory base(GM=’011’) Default Value YS[15:0] Power On Sequence 0000h S/W Reset 0000h HW Reset 0000h Status YE[15:0] YX[15:0] (MV=1) 4. 0081h(129) Power On Sequence 0000h 0081h(129) 5. 0081h(129) SW Reset 0000h HW Reset 0000h Status YE[15:0] (MV=0) 120X160 memory base(GM=’010’) 0081h(129) YE[15:0] (MV=1) 009Fh(159) 009Fh(159) 120X160 memory base(GM=’001’) Default Value YS[15:0] Default YE[15:0] 007Fh(127) 6. 132X162 memory base(GM=’000’) 009Fh(159) Default Value YS[15:0] Power On Sequence 0000h SW Reset 0000h HW Reset 0000h Status YE[15:0] (MV=0) YE[15:0] (MV=1) 009Fh(159) 009Fh(159) 0077h(119) 009Fh(159) Default Value YS[15:0] Power On Sequence 0000h SW Reset 0000h HW Reset 0000h Status YE[15:0] (MV=0) YE[15:0] (MV=1) 007Fh(127) 007Fh(127) 007Fh(127) 007Fh(127) Default Value YS[15:0] Power On Sequence 0000h SW Reset 0000h YE[15:0] (MV=0) YE[15:0] (MV=1) 00A1h(161) 00A1h(161) Page 106 of 183 0083h(131) Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Partial Mode CASET (2Ah) 1st &2nd Parameter XS[15:0] 3rd & 4thparmeter XE[15:0] RASET (2Bh) If Needed Flow Chart 1st &2nd Parameter YS[15:0] 3rd & 4thparmeter YE[15:0] Legend command Parameter RAMWR(2Ch) Display Action Image Data D1[17:0],D2[17:0]..Dn[17:0] Mode Sequential transfer Any Commend Page 107 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.22 Memory Write (2Ch) 2CH RAMWR (Memory Write) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 0 0 1 0 1 1 0 0 2Ch st 1 1 ↑ D17-8 1 1 ↑ x D7 ︰ D6 ︰ D5 ︰ D4 ︰ D3 ︰ D2 ︰ D1 ︰ D0 ︰ ︰ 1 1 ↑ D17-8 D7 D6 D5 D4 D3 D2 D1 D0 - 1 Parameter ︰ TH N Parameter This command is used to transfer data from MCU to frame memory. This command makes no change to the other driver status. When this command is accepted, the column register and the page register are reset to the Start Column/ Start Page positions. Description The Start Column / Start Page positions are different in accordance with MADCTL setting. Then D[17:0] is stored in frame memory and the column refister and the row register incremented. Sending any other command can stop frame Write. X=Don’t care In all color modes, there is no restriction on length of parameters. 1. 132X132 memory base (GM=’101’) 132X132X18-bit memory can be written by this command. Memory range(0000h, 0000h) -> (0083h,083h) 2. 130X130 memory base (GM=’100’) 130X130X18-bit memory can be written by this command. Memory range(0000h, 0000h) -> (0081h,081h) 3. 128X160 memory base (GM=’011’) 128X160X18-bit memory can be written by this command. Memory range(0000h, 0000h) -> (007Fh,09Fh) Restriction 4. 120X160 memory base (GM=’010’) 120X160X18-bit memory can be written by this command. Memory range(0000h, 0000h) -> (0077h,09Fh) 5. 128X128 memory base (GM=’001’) 120X128X18-bit memory can be written by this command. Memory range(0000h, 0000h) -> (007Fh,007Fh) 6. 132X162 memory base (GM=’000’) 132X162X18-bit memory can be written by this command. Memory range(0000h, 0000h) -> (0083h,00A1h) Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Page 108 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Default ILI9163 Status Default Value Power On Sequence Contents of memory is set randomly SW Reset Contents of memory is not cleared HW Reset Contents of memory is not cleared Legend CASET (2Ah) command Parameter Image Data D1[17:0],D2[17:0]..Dn[17:0] Flow Chart Display Action Mode Any Commend Sequential transfer Page 109 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.23 Color Setting fro 4K, 65K and 262K (2Dh) 2DH RAMWR (Memory Write) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 0 0 1 0 1 1 0 1 2Dh st 1 1 ↑ x x x R005 R004 R003 R002 R001 R000 - 1 1 ↑ x x x Rnn5 Rnn4 Rnn3 Rnn2 Rnn1 Rnn0 - 1 Parameter ︰ nd 1 1 ↑ x x x R315 R314 R313 R312 R311 R310 - rd 1 1 ↑ x x x G005 G004 G003 G002 G001 G000 - 1 1 ↑ x x x Gnn5 Gnn4 Gnn3 Gnn2 Gnn1 Gnn0 - th 1 1 ↑ x x x G635 G634 G633 G632 G631 G630 - th 1 1 ↑ x x x B005 B004 B003 B002 B001 B000 1 1 ↑ x x x Bnn5 Bnn4 Bnn3 Bnn2 Bnn1 Bnn0 - 1 1 ↑ x x x B315 B314 B313 B312 B311 B310 - 32 Parameter 33 Parameter ︰ 96 Parameter 97 Parameter ︰ th 128 Parameter This command is used to define the LUT for 12bit-to-18-bit color depth conversations 128-Bytes must be written to the LUT regardless of the color mode. In this condition, 4K-color(4-4-4), and 65K-color(5-6-5) data input are transferred 6That-6(G)-6(B) through RGB LUT Description table. This command has no effect on other commands/parameters and Contents of frame memory. Visible change takes effect next time the Frame Memory is written to. Restriction Do not send any command before the last data is sent or LUT is not defined correctly. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Contents of memory is set randomly SW Reset Contents of memory is not cleared HW Reset Contents of memory is not cleared Partial Mode Legend RGBSET(2Dh) command Flow Chart Parameter 1st Parameter : : 64th Parameter 65th Parameter : : 128th Parameter Display Action Mode Sequential transfer Page 110 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.24 Memory Read (2Eh) 2EH RAMRD (Memory Read) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 0 0 1 0 1 1 1 0 2Eh st 1 ↑ 1 x x x x x x x x x x nd 1 ↑ 1 x ↑ 1 x D16 ︰ D15 ︰ D14 ︰ D13 ︰ D12 ︰ D11 ︰ D10 ︰ x 1 D17 ︰ th 1 ↑ 1 x Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 x 1 Parameter 2 Parameter ︰ N Parameter x This command is used to transfer data from frame memory to MCU. This command makes no change to other driver status. When this command is accepted, the column register and then row register are reset to the Start Column/ Start Row positions. Description The Start Column / Start Row positions are different in accordance with MADCTL setting. Then D [17:0] is read back from the frame memory and the column register and the row register incremented. Frame Read can be stopped by sending any other command. “Display Data Format” for color coding(18 bit cases), when there is used 8,9,16 or 18 data lines for image data. X = Don’t care In all color modes, the Frame Read is always 24 bit so there is no restriction on length of parameters. Restriction Note: Memory Read is only possible via the Parallel Interface Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Contents of memory is set randomly SW Reset Contents of memory is not cleared HW Reset Contents of memory is not cleared CASET (2Eh) Legend command Dummy Read Parameter Display Flow Chart Action Image Data D1[17:0],D2[17:0]..Dn[17:0] Mode Sequential transfer Any Commend Page 111 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.25 Partial Area (30h) 30H PLTAR (Partial Area) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 0 0 1 1 0 0 0 0 30h st 1 1 ↑ x PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8 - nd 1 1 ↑ x PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 - rd 1 1 ↑ x PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8 - th 1 1 ↑ x PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 - 1 Parameter 2 Parameter 3 Parameter 4 Parameter This command defines the partial mode’s display area. There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory Line Pointer. If End Row>Start Row when MADCTL B4=0: Start Row Non-Display Area PSL[15:0] Partial Area End Row PEL[15:0] Non-Display Area If End Row > Start Row when MADCTL ML=1: End Row Description Non-Display Area PEL[15:0] Partial Area Start Row PSL[15:0] Non-Display Area If End Row < Start Row when MADCTL ML=0: End Row Partial Area PEL[15:0] Non-Display Area Start Row PSL[15:0] Partial Area If End Row < Start Row when MADCTL ML=1: Page 112 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Partial Area Start Row PSL[15:0] Non-Display Area End Row PEL[15:0] Partial Area If End Row = Start Row then the Partial Area will be one row deep. Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value PSL[15:0] Default PEL[15:0] GM “xxx” “101” “100” “011” “010” “001” “000” Power On Sequence 0000h 0083h 0081h 009Fh 009Fh 007Fh 00A1h SW Reset 0000h 0083h 0081h 009Fh 009Fh 007Fh 00A1h HW Reset 0000h 0083h 0081h 009Fh 009Fh 007Fh 00A1h 1. To Enter partial Mode PTLAR(30h) 2. To Exit Partial Mode Partial Mode 1st & 2nd Parameter PSL[15:0] DISPOFF(28h) 3rd & 4th Parameter PEL[15:0] NORON(13h) Optional to prevent Tearing Effect Image Display Legend Flow Chart PTLON(12h) Partial Mode OFF command Parameter Partial Mode RAMRW(2Ch) Display Action Image Data D1[17:0],D2[17:0]..Dn[17:0] Mode Sequential transfer DISPON(29h) Page 113 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.26 Vertical Scrolling Definition (33h) 33H Command st 1 Parameter nd 2 Parameter rd 3 Parameter th 4 Parameter th 5 Parameter th 6 Parameter VSCRDEF (Vertical Scrolling Definition) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 1 0 0 1 1 33h TFA TFA TFA TFA TFA TFA TFA TFA 15 14 13 12 11 10 9 8 TFA TFA TFA TFA TFA TFA TFA TFA 7 6 5 4 3 2 1 0 VSA VSA VSA VSA VSA VSA VSA VSA 15 14 13 12 11 10 9 8 VSA VSA VSA VSA VSA VSA VSA VSA 7 6 5 4 3 2 1 0 BFA BFA BFA BFA BFA BFA BFA BFA 15 14 13 12 11 10 9 8 BFA BFA BFA BFA BFA BFA BFA BFA 7 6 5 4 3 2 1 0 1 1 ↑ x 1 1 ↑ x 1 1 ↑ x 1 1 ↑ x 1 1 ↑ x 1 1 ↑ x - This command defines the Vertical Scrolling Area of the display. When MADCTL ML=0 e & Th 1st 2nd parameter TFA[15...0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). e Th 3rd & 4th parameter VSA[15...0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address). The first line read from Frame Memory appears immediately after the bottom most line of the Top Fixed Area. e & Th 5th 6th parameter BFA[15...0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer. (0, 0) Top Fixed Area TFA[15:0] First line read from memory VSA[15:0] BFA[15:0] Description Bottom Fixed Area When MADCTL ML=1 e & Th 1st 2nd parameter TFA[15...0] describes the Top Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). e Th 3rd & 4th parameter VSA[15...0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address). The first line read from Frame Memory appears immediately after the top most line of the Top Fixed Area. e & Th 5th 6th parameter BFA[15...0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory and Display). (0, 0) BFA[15:0] Top Fixed Area Top Fixed Area Bottom Fixed Area VSA[15:0] TFA[15:0] Top Fixed Area Page 114 of 183 First line read from memory Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 The condition is (TFA+VSA+BFA)=128 in 128RGBx128 (GM=”001”) The condition is (TFA+VSA+BFA)=130 in 130RGBx130 (GM=”100”) The condition is (TFA+VSA+BFA)=132 in 132RGBx132 (GM=”101”) Restriction The condition is (TFA+VSA+BFA)=160 in 128RGBx160 (GM=”011”) or 120RGBx160(GM=”010”) The condition is (TFA+VSA+BFA)=162 in 132RGBx162(GM=”000”) Otherwise Scrolling mode is undefined. In Vertical Scroll Mode, MADCTL parameter MV should be set to ‘0’ – this affects the Frame memory Write. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value TFA[15:0] Default Flow Chart 1. VSA[15:0] BFA[15:0] GM “xx” “101” “100” “011” “010” “001” “000” “xx” Power On Sequence 0000h 0083h 0081h 00A0h 00A0h 0080h 00A2h 0000h SW Reset 0000h 0083h 0081h 00A0h 00A0h 0080h 00A2h 0000h HW Reset 0000h 0083h 0081h 00A0h 00A0h 0080h 00A2h 0000h To enter Vertical Scroll Mode: Page 115 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Normal Mode ILI9163 Legend command SCRLAR (33h) Parameter Display 1st & 2nd parameter : TFA[15:0] Action Mode 3rd & 4th Parameter VSA[15:0] Sequential transfer 5th & 6th Parameter BFA[15:0] CASET(2Ah) 1st & 2nd parameter : XS[15:0] 3rd & 4th Parameter XE[15:0] Redefines the Frame Memory Window that the scroll data will be written to see Note CASET(2Bh) 1st & 2nd parameter : YS[15:0] 3rd & 4th Parameter YE[15:0] MADCTR(36h) Parameter : MY, MX, MV, ML, MH, RGB Only required for nonrolling scrolling Optional – it may be necessary to redefine the frame Memory RAMRW(2Ch) Scroll Image Data VSCSAD(37h) 1st & 2nd parameter : SSA[15:0] Scroll Mode Page 116 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Note 1 The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed. 2. Continuous Scroll: Normal Mode Legend command CASET(2Ah) Parameter Display 1st & 2nd parameter : XS[15:0] Action Mode 3rd & 4th Parameter XE[15:0] Sequential transfer RASET(2Bh) 1st & 2nd parameter : YS[15:0] 3rd & 4th Parameter YE[15:0] RAMRW(2Ch) Scroll Image Data Only required for nonrolling scrolling V.. VSCSAD(37h) 1st & 2nd parameter : SSA[15:0] 3. To Leave Vertical Scroll Mode: Page 117 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Scroll Mode (Optional) To prevent Tearing Effect Image Display DISOFF(28h) MORON(12h)/PTLON(12h) Scroll Mode Off RAMRW(2Ch) Image Data D1[17:0],D2[17:0]...Dn[17:0] DISON(29h) Note2: Scroll Mode can be left by both the Normal Display Mode On (13h) and Partial Mode On (12h) commands. Page 118 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.27 Tearing Effect Line Off (34h) 34H Command Parameter TEOFF (Tearing Effect Line OFF) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 1 0 1 0 0 34h NO PARAMETER Description This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Restriction This command has no effect when Tearing Effect output is already OFF. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence OFF SW Reset OFF HW Reset OFF Legend TE Line Output ON command Parameter Display Flow Chart TEOFF(34h) Action TE Line Output OFF Mode Sequential transfer Page 119 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.28 Tearing Effect Line On (35h) 35H Command 1 TEON (Tearing Effect Line ON) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 1 0 1 0 1 35h 1 1 ↑ x x x x x x x x M 00h st Parameter This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTL bit ML. The Tearing Effect Line On has one parameter which describes the mode of the Tearing Effect Output Line. (X=Don’t Care). When M=0: The Tearing Effect Output line consists of both V-Blanking and H-Blanking information.: tvdl Description tvdh Vertical Time Scale When M=1: The Tearing Effect Output Line consists of both V-Blanking and H-Blanking information: tvdh tvdl V-Sync V-Sync Invisible Line 1st Line 480th Line Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Restriction This command has no effect when Tearing Effect output is already OFF. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence Tearing effect off & M=0 SW Reset Tearing effect off & M=0 HW Reset Tearing effect off & M=0 Page 120 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend TE Line Output OFF command Parameter TEON(35h) Display Flow Chart 1st parameter: (M) Action Mode TE Line Output ON Page 121 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.29 Memory Access Control (36h) 36H Command 1 st Parameter MADCTL (Memory Access Control) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 1 0 1 1 0 36h 1 1 ↑ x MY MX MV ML RGB MH x x 00h This command defines read/write scanning direction of frame memory. This command makes no change on the other driver status. Bit Assignment Bit Description Comment MY Row Address Order MX Column Address Order MV Page/Column Selection ML Vertical Order These 3 bits controls MPU to memory write/read direction. LCD Vertical refresh direction control Color selector switch control RGB RGB/BGR Order 0=RGB color filter panel 1=BGR color filter panel MH B5 B6 Display data latch order B7 ‘1’=LCD Refresh right to left ‘0’=LCD Refresh left to right Im a ge in Fra me Me mory B5 B6 B7 B Description 0 0 0 0 Ima ge in Fra m e Me mory B 0 1 0 0 E E E E 1 1 0 1 B B B 0 1 0 B 1 1 0 E E E 0 1 E 1 1 B Page 122 of 183 1 1 B Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 B3 = 0 Memory R G B Display Panel Sent RGB R G B B3 = 1 Memory R Restriction G B Display Panel Sent BGR B G R st -D1 and D0 of the 1 parameter are set to “00” internally. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence MY=0,MX=0,MV=0,ML=0,RGB=0,MH=0 SW Reset No Change HW Reset MY=0,MX=0,MV=0,ML=0,RGB=0,MH=0 Legend command Parameter MADCTR(36h) Display Flow Chart 1st parameter: (MY, MX, MV, ML, RGB, MH) Action Mode Sequential transfer Page 123 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.30 Vertical Scrolling Start Address (37h) 37H Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 1 0 1 1 1 37h SSA SSA SSA SSA SSA SSA SSA SSA 15 14 13 12 11 10 9 8 st Parameter 2 VSCRSADD (Vertical Scrolling Start Address) nd Parameter 1 ↑ 1 x 00h SSA SSA SSA SSA SSA SSA SSA 00h 7 6 5 4 3 2 1 0 This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start Address command has one parameter which describes the address of the line in the Frame Memory that will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: This command Start the scrolling. 1 ↑ 1 x SSA When MADCTL ML=0 Example: GM=000, 132RGBx162 When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 162 and Vertical Scrolling Pointer SSA=’3’. Frame Memory (0, 0) Pointer ML=0 Display 0 1 SSA[15:0] 2 3 4 .. .. 159 160 (0, 161) Description 161 When MADCTL ML=1 Example: GM=000, 132RGBx162 When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 162 and SSA=’3’. Frame Memory (0, 161) Pointer ML=1 Display 161 160 159 .. .. 4 3 SSA[15:0] 2 1 0 (0, 0) Note: When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. SSA refers to the Frame Memory scan address When new Pointer position and Picture Data, internal system works as 128x128 and maximum scan address becomes 127 internal of 161. X=Don’t care Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter Restriction the fixed area (defined by Vertical Scrolling Definition (33h) – otherwise undesirable image will be displayed on the Panel. SSA[15:0] is based on 1-line unit. SSA[15:0] =0000h, 0001h, 0002h, 003h, …, 00A1h Page 124 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Flow Chart ILI9163 Default Value Power On Sequence 0000h SW Reset 0000h HW Reset 0000h See Vertical Scrolling Definition (33h) description. Page 125 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.31 Idle Mode Off (38h) 38H IDMOFF (Idle Mode Off) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 1 1 0 0 0 38h Command Parameter NO PARAMETER This command is used to recover from Idle mode on. There will be no abnormal visible effect on the display mode change transition. Description In the Idle off mode 1. LCD can display maximum 4096, 65K, 262K colors. 2. Normal frame frequency is applied. X = don’t care Restriction This command has no effect when module is already in idle off mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence Idle Mode Off SW Reset Idle Mode Off HW Reset Idle Mode Off Legend Idle mode on command Parameter Display Flow Chart IDMOFF(38h) Action Mode Idle mode off Sequential transfer Page 126 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.32 Idle Mode On (39h) 39H IDMON (Idle Mode On) Command Parameter D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 1 1 0 0 1 39h NO PARAMETER This command is used to enter into Idle mode on. There will be no abnormal visible effect on the display mode change tranition. In the Idle mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off(38h) command. Memory Panel Display Description Restriction R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Black 0XXXXX 0XXXXX 0XXXXX Blue 0XXXXX 0XXXXX 1XXXXX 0XXXXX Red 1XXXXX 0XXXXX Magenta 1XXXXX 0XXXXX 1XXXXX Green 0XXXXX 1XXXXX 0XXXXX Cyan 0XXXXX 1XXXXX 1XXXXX Yellow 1XXXXX 1XXXXX 0XXXXX White 1XXXXX 1XXXXX 1XXXXX This command has no effect when module is already in idle on mode. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence Idle Mode Off SW Reset Idle Mode Off Flow Chart Page 127 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend Idle mode off command Parameter Display IDMOFF(39h) Action Mode Idle mode on Sequential transfer Page 128 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.33 Interface Pixel Format (3Ah) 39H IDMON (Idle Mode On) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 0 0 1 1 1 0 1 0 3Ah 1 1 ↑ x D3 IFPF2 IFPF1 IFPF0 66h Command 1 st Parameter This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface. The formats are shown in the table: Bit Description D3 Description Value “0” (Not Used) IFPF2 Control Interface Color “011”=12 bit/pixel IFPF1 Format “101”=16 bit/pixel “110”=18 bit/pixel IFPF0 The others = not defined Note 1. In 12-bits/Pixel, 16-bits/Pixel mode, the LUT is applied to transfer data into the Frame Memory. X = don’t care Restriction There is no visible effect until the Frame Memory is written to. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 18bit/pixel SW Reset No change Legend 18-bit/Pixel Mode command Parameter COLMOD(3Ah) Display Flow Chart 1st parameter: IFPF[2:0] = “xxx＂ Action Mode 18-bit/Pixel Mode Page 129 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.34 Read ID1 (DAh) DAH Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 1 1 0 1 0 DAh x x x x x x x x ID16 ID15 ID14 ID13 ID12 ID11 ID10 54h st Parameter 2 RDID1 (Read ID1) 1 nd Parameter 1 ↑ ↑ 1 x x 1 x ID17 This read byte return 8-bit LCD module’s ID. The 1st parameter is dummy data Description The 2nd parameter (ID17to ID10): LCD module manufacturer ID X = Don’t care Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value Power On Sequence 54h SW Reset 54h HW Reset 54h Default Note : ID1 can be modified by metal option Serial I/F Mode Parallel I/F Mode Legend command RDID1(DAh) RDID1(DAh) Host Driver Parameter Display Flow Chart Send 2nd parameter ID1[7:0] Dummy Read Action Mode Send 2nd parameter ID1[7:0] Page 130 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.35 Read ID2 (DBh) DBH Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 1 1 0 1 1 DBh 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 80h st Parameter 2 RDID2 (Read ID2) nd Parameter x This read byte returns 8-bit LCD module/driver version ID e Th 1st parameter is dummy data e Th 2nd parameter (ID26 to ID20): LCD module/driver version ID Parameter Range: ID=80h to FFh Description , Note : See command RDDID(04h) 3rd parameter D7 to D0 Version Changes 80h TBD TBD 81h TBD TBD 82h TBD TBD 83h TBD TBD - TBD TBD Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Serial I/F Mode Status Default Value Power On Sequence See Description SW Reset See Description HW Reset See Description Parallel I/F Mode Legend command RDID2(DBh) RDID2(DBh) Host Driver Flow Chart Send 2nd parameter ID2[7:0] Dummy Read Parameter Display Action Mode Send 2nd parameter ID2[7:0] Page 131 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.36 Read ID3 (DCh) DCH Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 1 1 1 0 0 DCh 1 x x x x x x x x x x 1 x ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 66h st Parameter 2 RDID3 (Read ID3) 1 nd Parameter 1 ↑ ↑ -This read byte return 8-bit LCD module/driver ID e -Th 1st parameter is dummy data Description e -Th 2nd parameter (ID37 to ID30): LCD module/driver ID -Parameter range: ID=00h to FFh , Note : See command RDDID(04h) 4th parameter Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Serial I/F Mode Status Default Value Power On Sequence 66h SW Reset 66h HW Reset 66h Parallel I/F Mode Legend command RDID3(DCh) RDID3(DBh) Host Driver Flow Chart Send 2nd parameter ID3[7:0] Dummy Read Parameter Display Action Mode Send 2nd parameter ID3[7:0] Page 132 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.38 Frame Rate Control(In normal mode/Full colors) (B1h) B1h Frame Rate Control(In normal mode/Full colors) D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ 1 0 1 1 0 0 0 1 B1h st 1 1 ↑ x x x DIVA4 DIVA3 DIVA2 DIVA1 DIVA0 x nd 1 1 ↑ x x VPA5 VPA4 VPA3 VPA2 VPA1 VPA0 x 1 Parameter 2 Parameter Sets the division ratio for internal clocks of Normal mode at CPU interface mode. DIVA[4:0]: division ratio for internal clocks when Normal mode. VPA[5:0]: Vsync porch for internal clocks when Normal mode Frame _ rate = (1) 200kHz ( Line + VPA[5 : 0])( DIVA[4 : 0] + 4) When GM=101(132*132) In Normal mode, line=132, Default value DIVA[4:0]=17, VPA[5:0]=20, Frame rate=62.7Hz (2) When GM=100(130*130) In Normal mode, line=130, Default value DIVA[4:0]=17, VPA[5:0]=20, Frame rate=63.5Hz Description (3) When GM=011(128*160) In Normal mode, line=160, Default value DIVA[4:0]=14, VPA[5:0]=20, Frame rate=61.7Hz (4) When GM=010(120*160) In Normal mode, line=160, Default value DIVA[4:0]=14, VPA[5:0]=20, Frame rate=61.7Hz (5) When GM=001(128*128) In Normal mode, line=128, Default value DIVA[4:0]=17, VPA[5:0]=20, Frame rate=64.4Hz (6) When GM=000(132*162) In Normal mode, line=162, Default value DIVA[4:0]=14, VPA[5:0]=20, Frame rate=61Hz Restriction Status Register Availability (1) Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes When GM=000(132*162), GM=011(128*160) or GM=010(120*160) Default Value Status Default (2) Availability DIVA[4:0] VPA[5:0] Power On Sequence 0Eh/14d 14h/20d S/W Reset 0Eh/14d 14h/20d H/W Reset 0Eh/14d 14h/20d When GM=001(128*128), GM=100(130*130), GM=101(132*132) Default Value Status DIVA[4:0] VPA[5:0] Power On Sequence 11h/17d 11h/17d S/W Reset 11h/17d 11h/17d H/W Reset 11h/17d 11h/17d Page 133 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend RGBCTR1(B1h) command Parameter 1st parameter: DIVA[4:0] 2nd parameter:VPA[4:0] Display Flow Chart Action Mode Sequential transfer 14.2.39 Frame Rate Control(In Idle mode/8-colors) (B2h) B2h Frame Rate Control(In Idle mode/Full colors) D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 1 0 1 1 0 0 1 0 B2h st 1 1 ↑ x x x DIVB4 DIVB3 DIVB2 DIVB1 DIVB0 x nd 1 1 ↑ x x VPB5 VPB4 VPB3 VPB2 VPB1 VPB0 x Command 1 Parameter 2 Parameter Sets the division ratio for internal clocks of Idle mode at CPU interface mode. DIVB[4:0]: division ratio for internal clocks when Idle mode. VPB[5:0]: Vsync porch for internal clocks when Idle mode Frame _ rate = (1) 200kHz ( Line + VPB[5 : 0)( DIVB[4 : 0] + 4) When GM=101(132*132) In Normal mode, line=132, Default value DIVA[4:0]=17, VPA[5:0]=20, Frame rate=62.7Hz (2) When GM=100(130*130) In Normal mode, line=130, Default value DIVA[4:0]=17, VPA[5:0]=20, Frame rate=63.5Hz Description (3) When GM=011(128*160) In 8-color mode, line=160, Default value DIVB[4:0]=14, VPB[5:0]=20, Frame rate=61.7Hz (4) When GM=010(120*160) In (5) 8-color l mode, line=160, Default value DIVB[4:0]=14, VPB[5:0]=20, Frame rate=61.7Hz When GM=001(128*128) In 8-color mode, line=128, Default value DIVB[4:0]=17, VPB[5:0]=20, Frame rate=64.4Hz (6) When GM=000(132*162) In Restriction 8-color mode, line=162, Default value DIVB[4:0]=14, VPB[5:0]=20, Frame rate=61Hz - Page 134 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Status Register Availability (1) (2) Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes When GM=000(132*162), GM=011(128*160) or GM=010(120*160) Default Value Status Default ILI9163 DIVB[4:0] VPB[5:0] Power On Sequence 0Eh/14d 14h/20d S/W Reset 0Eh/14d 14h/20d H/W Reset 0Eh/14d 14h/20d When GM=001(128*128), GM=100(130*130), GM=101(132*132) Default Value Status DIVB[4:0] VPB[5:0] Power On Sequence 11h/17d 11h/17d S/W Reset 11h/17d 11h/17d H/W Reset 11h/17d 11h/17d Legend command FRMCTR2(B2h) Parameter Display Flow Chart 1st parameter: DIVB[4:0] 2nd parameter: VPB[4:0] Action Mode Sequential transfer Page 135 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.40 Frame Rate Control(In Partial mode/full colors) (B3h) B3h Frame Rate Control(In Partial mode/Full colors) D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 1 0 1 1 0 0 1 1 B3h st 1 1 ↑ x x x DIVC4 DIVC3 DIVC2 DIVC1 DIVC0 x nd 1 1 ↑ x x VPC5 VPC4 VPC3 VPC2 VPC1 VPC0 x Command 1 Parameter 2 Parameter Sets the division ratio for internal clocks of Partial mode at CPU interface mode. DIVB[4:0]: division ratio for internal clocks when Partial mode. VPB[5:0]: Vsync porch for internal clocks when Partial mode (1) When GM=101(132*132) In Normal mode, line=132, Default value DIVA[4:0]=17, VPA[5:0]=20, Frame rate=62.7Hz (2) When GM=100(130*130) In Normal mode, line=130, Default value DIVA[4:0]=17, VPA[5:0]=20, Frame rate=63.5Hz Description (3) When GM=011(128*160) In Partial mode, line=160, Default value DIVC[4:0]=14, VPC[5:0]=20, Frame rate=61.7Hz (4) When GM=010(120*160) In Partial mode, line=160, Default value DIVC[4:0]=14, VPC[5:0]=20, Frame rate=61.7Hz (5) When GM=001(128*128) In Partial mode, line=128, Default value DIVC[4:0]=17, VPC[5:0]=20, Frame rate=64.4Hz (6) When GM=000(132*162) In Partial mode, line=162, Default value DIVC[4:0]=14, VPC[5:0]=20, Frame rate=61Hz Restriction Status Register Availability (1) Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes When GM=000(132*162), GM=011(128*160) or GM=010(120*160) Default Value Status Default (3) Availability Normal Mode On, Idle Mode Off, Sleep Out DIVC4:0] VPC[5:0] Power On Sequence 0Eh/14d 14h/20d S/W Reset 0Eh/14d 14h/20d H/W Reset 0Eh/14d 14h/20d When GM=001(128*128), GM=100(130*130), GM=101(132*132) Default Value Status DIVB[4:0] VPB[5:0] Power On Sequence 11h/17d 11h/17d S/W Reset 11h/17d 11h/17d H/W Reset 11h/17d 11h/17d Page 136 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend command FRMCTR2(B3h) Parameter Display Flow Chart 1st parameter: DIVC[4:0] 2nd parameter: VPC[4:0] Action Mode Sequential transfer Page 137 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.41 Display Inversion Control (B4h) B4h Display Inversion Control D/CX Command 1 WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 0 RDX 1 ↑ x 1 0 1 1 0 1 0 0 HEX B4h 1 1 ↑ x 0 0 0 0 0 NLA NLB NLC 02H st Parameter -Display Inversion mode control -NLA: Inversion setting in full colors normal mode(Normal mode on) NLA Inversion setting in full colors normal mode 0 Line Inversion 1 Frame Inversion -NLB: Inversion setting in Idle mode(Idle mode on) Description NLA Inversion setting in Idle mode 0 Line Inversion 1 Frame Inversion -NLC: Inversion setting in full colors partial mode(Partial mode on/Idle mode off) NLA Restriction Inversion setting in full colors partial mode 0 Line Inversion 1 Frame Inversion If this register not using the register need be reserved. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Value NLA Default NLB NLC D7-0 Power On Sequence 0d 1d 0d 02h S/W Reset 0d 1d 0d 02h H/W Reset 0d 1d 0d 02h Legend command INVCTR(B4h) Parameter Display Flow Chart 1st Parameter NLA, NLB, NLC Action Mode Sequential transfer Page 138 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.44 Source Driver Direction Control (B7h) B7h Command 1 st Display Inversion Control D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 0 1 1 0 1 1 1 B7h 1 1 ↑ x 0 0 0 0 0 0 0 CRL 00h -CRL: Source output direction select register CRL Descriptio Module source output direction GM=’101’ GM=’100’ GM=’011’ GM=’010’ GM=’001’ GM=’000’ S1 -> S7 -> S7 -> S7 -> S7 -> S1 -> S396 S396 S390 S366 S390 S396 S1 -> S396 -> S366 -> S390 -> S396 -> S7 S7 S1 0 n 1 S390 ->S7 S396 Restrictio n S7 If this register not using the register need be reserved. Status Register Availabilit y Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Availability Normal Mode On, Idle Mode Off, Sleep Out Default Value CRL Power On Sequence 0d S/W Reset 0d H/W Reset 0d Legend command SDOCTR(B7h) Parameter Display Flow Chart Action 1st Parameter: CRL Mode Sequential transfer Page 139 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.45 Gate Driver Direction Control (B8h) B8h Comman d 1 st Display Inversion Control D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 0 1 1 1 0 0 0 B8h 1 1 ↑ x 0 0 0 0 0 0 0 CTB 00h -CTB: Gate output direction select register Module gate output direction CTB Descriptio n Restrictio n Register Availabilit y GM=’011’,’01 GM=’101’ GM=’100’ GM=’000’ 0 G2 -> G133 G2 -> G131 G2 -> G161 G2 -> G129 G1 -> G162 1 G133 -> G2 G131 -> G2 G161 ->G2 G129 -> G2 G162 -> G1 If this register not using the register need be reserved. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default GM=’011’ 0’ Default Value CRL Power On Sequence 0d S/W Reset 0d H/W Reset 0d Legend command GDOCTR(D8h) Parameter Display Flow Chart Action 1st Parameter: CTB Mode Sequential transfer Page 140 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.46 Power_Control1 (C0h) C0H Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 0 0 0 0 0 C0h 0 0 0 VRH4 VRH3 VRH2 VRH1 VRH0 x 0 0 0 0 0 VC2 VC1 VC0 02h st Parameter 2 Power_Control1 1 1 ↑ 1 1 ↑ x nd Parameter x Set the GVDD and voltage Description VRH[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GVDD 5.00 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 3.75 3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.25 3.00 VC[2:0] 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 VCI1 2.75 2.70 2.65 2.60 2.55 2.50 2.45 2.40 Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status Default LCM=”00” LCM=”01” LCM=”10” LCM=”11” TN-TR LCD TN-TM LCD TN-TM LC Type2 MVA-TR LCD VRH[4:0]/VC[2:0] VRH[4:0]/VC[2:0] VRH[4:0]/VC[2:0] VRH[4:0]/VC[2:0] Power On Sequence 21d/2d 5d/2d 10d/5d 1d/2d SW Reset 21d/2d 5d/2d 10d/5d 1d/2d HW Reset 21d/2d 5d/2d 10d/5d 1d/2d Page 141 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend command PWCTR1(C0h) Parameter Display Flow Chart Action 1st Parameter: VRH[4:0] Mode Sequential transfer Page 142 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.47 Power_Control2 (C1h) C1H Command 1 Power_Control2 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 0 0 0 0 1 C1h 1 1 ↑ x 0 0 0 0 0 BT2 BT1 BT0 07h st Parameter Set the AVDD, VCL, VGH and VGL supply power level. BT[2:0] Description AVDD VCL VGH VGL 000 0 2xVCI1 -1xVCI1 4xVCI1 -3xVCI1 001 1 2xVCI1 -1xVCI1 4xVCI1 -4xVCI1 010 2 2xVCI1 -1xVCI1 5xVCI1 -3xVCI1 011 3 2xVCI1 -1xVCI1 5xVCI1 -4xVCI1 100 4 2xVCI1 -1xVCI1 5xVCI1 -5xVCI1 101 5 2xVCI1 -1xVCI1 6xVCI1 -3xVCI1 110 6 2xVCI1 -1xVCI1 6xVCI1 -4xVCI1 111 7 2xVCI1 -1xVCI1 6xVCI1 -5xVCI1 If this register not using the register need be reserved. Restriction The deviation value of VGH/VGL between with Measurement and Specification VGH-VGL <= 32V Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value BT[2:0] Power On Sequence 7d SW Reset 7d HW Reset 7d Legend command PWCTR2(C1h) Parameter Display Flow Chart Action 1st Parameter: BT[2:0] Mode Sequential transfer Page 143 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.48 Power_Control3 (C2h) C2H Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 0 0 0 1 0 C2h 1 1 ↑ x 0 0 0 0 0 APA2 APA1 APA0 00h 1 1 ↑ x 0 0 0 0 0 DCA2 DCA1 DCA0 06h st Parameter 2 Power_Control3 nd Parameter Set the amount of current in Operation amplifier in normal mode/full colors. Adjust the amount of fixed current from the fixed current sources in the operational amplifier for the source driver. APA[2:0] Amount of Current in Operational Amplifier 000 0 Least 001 1 Small 010 2 Medium Low 011 3 Medium 100 4 Medium High 101 5 Large 110 6 Reserved 111 7 Reserved Set the Booster circuit Step-up cycle in Normal mode/full colors Description DC=A[2:0] Step-up cycle in Booster circuit 1 Step-up cycle in Booster circuit 2,3 000 0 BCLK/1 BCLK/4 001 1 BCLK/1 BCLK/8 010 2 BCLK/1 BCLK/8 011 3 BCLK/2 BCLK/16 100 4 BCLK/2 BCLK/16 101 5 BCLK/4 BCLK/32 110 6 BCLK/4 BCLK/64 111 7 BCLK/8 BCLK/64 Note: BCLK is Clock frequency for Booster circuit. Restriction If some parameter of the register is not use the register need to be reserved. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value APA[2:0] DCA[2:0] Power On Sequence 0d 6d SW Reset 0d 6d HW Reset 0d 6d Page 144 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend command PWCTR3(C2h) Parameter Display Flow Chart Action 1st Parameter: APA[2:0] 2nd Parameter: DCA[2:0] Mode Sequential transfer Page 145 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.49 Power_Control4 (C3h) C3H Power_Control4(in Idle mode/8 colors) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 1 1 0 0 0 0 1 1 C3h st 1 1 ↑ x 0 0 0 0 0 APB2 APB1 APB0 00h nd 1 1 ↑ x 0 0 0 0 0 DCB2 DCB1 DCB0 07h 1 Parameter 2 Parameter Set the amount of current in Operational amplifier in Idle mode/8-colors Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. APA[2:0] 000 Description Amount of Current in Operational Amplifier 0 Least 001 1 Small 010 2 Medium Low 011 3 Medium 100 4 Medium High 101 5 Large 110 6 Reserved 111 7 Reserved Set the Booster circuit Step-up cycle in Normal mode/full colors DC=A[2:0] Step-up cycle in Booster circuit 1 Step-up cycle in Booster circuit 2,3 000 0 BCLK/1 BCLK/4 001 1 BCLK/1 BCLK/8 010 2 BCLK/1 BCLK/8 011 3 BCLK/2 BCLK/16 100 4 BCLK/2 BCLK/16 101 5 BCLK/4 BCLK/32 110 6 BCLK/4 BCLK/64 111 7 BCLK/8 BCLK/64 Note: BCLK is Clock frequency for Booster circuit Restriction If some parameter of the register not use the register need to be reserved. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value APB[2:0] DCB[2:0] Power On Sequence 0d 7d SW Reset 0d 7d HW Reset 0d 7d Page 146 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend command PWCTR4(C3h) Parameter Display Flow Chart Action 1st Parameter: APB[2:0] 2nd Parameter: DCB[2:0] Mode Sequential transfer Page 147 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.50 Power_Control 5 (C4h) C4H Power_Control_5(in Partial mode/full mode) D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 1 1 0 0 0 1 0 0 C4h st 1 1 ↑ x 0 0 0 0 0 APC2 APC1 APC1 01h nd 1 1 ↑ x 0 0 0 0 0 DCC2 DCC1 DCC0 07h 1 Parameter 2 Parameter Set the amount of current in Operational amplifier in Partial mode/full-colors Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. APA[2:0] Description Amount of Current in Operational Amplifier 000 0 Least 001 1 Small 010 2 Medium Low 011 3 Medium 100 4 Medium High 101 5 Large 110 6 Reserved 111 7 Reserved Set the Booster circuit Step-up cycle in Normal mode/full colors DC=A[2:0] Step-up cycle in Booster circuit 1 Step-up cycle in Booster circuit 2,3 000 0 BCLK/1 BCLK/4 001 1 BCLK/1 BCLK/8 010 2 BCLK/1 BCLK/8 011 3 BCLK/2 BCLK/16 100 4 BCLK/2 BCLK/16 101 5 BCLK/4 BCLK/32 110 6 BCLK/4 BCLK/64 111 7 BCLK/8 BCLK/64 Note: BCLK is Clock frequency for Booster circuit Restriction If some parameter of the register not use the register need to be reserved. Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value APB[2:0] DCC[2:0] Power On Sequence 1d 7d SW Reset 1d 7d HW Reset 1d 7d Page 148 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend command PWCTR5(C4h) Parameter Display Flow Chart Action 1st Parameter: APC[2:0] 2nd Parameter: DCC[2:0] Mode Sequential transfer Page 149 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.51 VCOM_Control 1 (C5h) C5H VCOM_Control1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX Command 0 1 ↑ x 1 1 0 0 0 1 0 1 C5h st 1 1 ↑ x x VMH6 VMH5 VMH4 VMH3 VMH2 VMH1 VMH0 - nd 1 1 ↑ x 0 VML6 VML5 VML4 VML3 VML2 VML1 VML0 - 1 Parameter 2 Parameter Set VCOMH Voltage VMH[6:0] 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VCOMH 2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 3.075 3.100 3.125 3.150 VMH[6:0] 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 VCOMH 3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725 3.750 3.775 3.800 3.825 VMH[6:0] 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VCOMH 3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 4.325 4.350 4.375 4.400 4.425 4.450 4.475 4.500 VMH[6:0] 1010001 81 1010010 82 1010011 83 1010100 84 1010101 85 1010110 86 1010111 87 1011000 88 1011001 89 1011010 90 1011011 91 1011100 92 1011101 93 1011110 94 1011111 95 1100000 96 1100001 97 1100010 98 1100011 99 1100100 100 1100101 101 VCOMH 4.525 4.550 4.575 4.600 4.625 4.650 4.675 4.700 4.725 4.750 4.775 4.800 4.825 4.850 4.875 4.900 4.925 4.950 4.975 5.000 Not Permitted 01111111 127 -Set VCOML Voltage VML[6:0] 0000000 0000001 0000010 0000011 00000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VCOML -2.500 -2.475 -2.450 -2.425 -2.400 -2.375 -2.350 -2.325 -2.300 -2.275 -2.250 -2.225 -2.200 -2.175 -2.150 -2.125 -2.100 -2.075 -2.050 -2.025 -2.000 -1.975 -1.950 -1.925 -1.900 -1.875 -1.850 VML[6:0] 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 VCOML -1.825 -1.800 -1.775 -1.750 -1.725 -1.700 -1.675 -1.650 -1.625 -1.600 -1.575 -1.550 -1.525 -1.500 -1.475 -1.450 -1.425 -1.400 -1.375 -1.350 -1.325 -1.300 -1.275 -1.250 -1.225 -1.200 -1.175 VML[6:0] 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VCOML -1.150 -1.125 -1.100 -1.075 -1.050 -1.025 -1.000 -0.975 -0.950 -0.925 -0.900 -0.875 -0.850 -0.825 -0.800 -0.775 -0.750 -0.725 -0.700 -0.675 -0.650 -0.625 -0.600 -0.575 -0.550 -0.525 -0.500 VML[6:0] 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 1111111 127 VCOML -0.475 -0.450 -0.425 -0.400 -0.375 -0.350 -0.325 -0.300 -0.275 -0.250 -0.225 -0.200 -0.175 -0.150 -0.125 -0.100 -0.075 -0.050 -0.025 0.000 Not Permitted -If this register not using the register need be reserved. Restriction -The VCOM amplitude: VCOMH-VCOML <=5.5V -The deviation value of VCOMH/VCOML between with Measurement and Specification: Max <=25mV -The deviation value of VCOMAC between with Measurement and Specification: Max <= 50mV Page 150 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Status ILI9163 Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Value Status nVM Default LCM=”00” LCM=”01” LCM=”10” TN-TR LC type TN-TM LC type TN-TM LC type2 LCM=”11” MVA-TR LC type VMH[6:0]/VML[6:0 VMH[6:0]/VML[6:0 VMH[6:0]/VML[6:0 VMH[6:0]/VML[6:0 Power On Sequence 0d 37d/45d 79d/77d 67d/77d 60d/54d SW Reset 0d 37d/45d 79d/77d 67d/77d 60d/54d HW Reset 0d 37d/45d 79d/77d 67d/77d 60d/54d Legend command VMCTR(C5h) Parameter Display Flow Chart Action 1st Parameter: VMH[6:0] 2nd Parameter: VML[6:0] Mode Sequential transfer 14.2.52 VCOM_Control 2 (C6h) C6H VCOM_Control2 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 Command 0 1 ↑ x 1 1 0 0 0 1 1 0 C6h st 1 1 ↑ x 0 0 VMA5 VMA4 VMA3 VMA2 VMA1 VMA0 13h/06h 1 Parameter HEX -Set VCOMAC Voltage Description Restriction Register Availability Default In this case, these registers don’t be used. - Page 151 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.53 VCOM Offset Control (C7h) C7H Command 1 VCOM Offset Control D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 0 0 1 1 1 C7h 1 1 ↑ 0 nVM* VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0 40h st Parameter -Set VCOMH Voltage VMF[6:0] VCOMH Output 0 “VMH” “VML” 1 “VMH”-63d “VML”-63d 2 “VMH”-62d “VML”-62d : : : 62 “VMH”-2d “VML”-2d 63 “VMH”-1d “VML”-1d 64 “VMH” “VML” 65 “VMH”+1d “VML”+1d 66 “VMH”+2d “VML”+2d : : : 126 “VMH”+62d “VML”+62d 127 “VMH”+63d “VML”+63d Description VCOML Output Level If “VMH”+xd or “VML”+xd is less than 0d, it becomes 0d If “VMH”+xd or “VML”+xd is large than 100d, it becomes 100d VMF[5:0] are stored in NV memoy to contrast -Select the VMF[6:0]value Restriction nVM VMF[6:0] value 0 VCOM offset value from NV memory 1 VCOM offset value in the VMF[6:0] registers -If this register not use the register need be reserved. -To control the VCOM output voltage with VMF[5::0] command, nVM parameter should be set ‘1’ Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value VMF[6:0] Power On Sequence 40h SW Reset 40h HW Reset 40h Page 152 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend command VMOFCTR(C7h) Parameter Display Flow Chart Action 1st Parameter: nVM, VMF[6:0] Mode Sequential transfer Page 153 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.54 Write ID4 Value (D3h) D3H Read the ID4 value D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 1 0 0 1 1 D3h 1 ↑ 1 x x x x x x x x x x 1 ↑ 1 x ID417 ID416 ID415 ID414 ID413 ID412 ID411 ID410 01h 1 ↑ 1 x ID427 ID426 ID425 ID424 ID423 ID422 ID421 ID420 21h 1 ↑ 1 x x x x x ID433 ID432 ID431 ID430 x 1 ↑ 1 x x x x x x x x x x Command 1 st Parameter 2 nd Parameter 3 rd Parameter 4 th Parameter 5 th Parameter -Read the Driver IC information from mask value. -Ignored the EXTC pin. st -The 1 parameter is dummy data nd -The 2 parameter ID41[7:0] is Driver IC ID code. (Default value=01h) -The value be defined later Description -Currently, “01h”, “02h”, “03h”, “05h” can’t be used. rd -The 3 parameter ID42[7:0] is Driver IC Part number ID. (The code be define by Driver IC Vendor, and default value=21h) th -The 4 parameter ID43[7:0] is Driver IC version ID -When the Driver maker modifies any function it should be modify the parameters at this ID code before sample out also. -If Driver Maker don’t need 2 parameter if can’t reduce to one parameter. -If the parameters are not enough Driver makers can add or reduce yourself Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value ID41[7:0] ID42[7:0] ID43[7:0] Power On Sequence 01h 21h TBD SW Reset 01h 21h TBD HW Reset 01h 21h TBD Page 154 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color Serial I/F Mode Parallel I/F Mode ILI9163 Legend command RDID4(D3h) RDID4(D3h) Host Driver Dummy Clock Dummy Read Parameter Display Action Mode Flow Chart Send ID41[7:0] Send ID41[7:0] Send ID42[7:0] Send ID42[7:0] Send ID43[7:0] Send ID43[7:0] Send ID4N[7:0] Send ID4N[7:0] Page 155 of 183 Sequential transfer Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.55 NV Memory Function Controller (D7h) D7H Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 1 1 0 1 0 D7h 1 1 ↑ x 0 1 0 1 0 1 0 1 55h 1 1 ↑ x 1 0 1 0 1 0 1 0 AAh 1 1 ↑ x 0 1 1 0 0 1 1 0 66h st Parameter 2 NV Memory Function Controller1 nd Parameter 3 rd Parameter Description MTP write EPWRITE commend Please see MTP Access sequence for program(Data write) for more detail Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence SW Reset HW Reset N/A N/A N/A Flow Chart Page 156 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.56 NV Memory Function Controller 2(DEh) DEH Command 1 D/CX RDX WRX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ x 1 1 0 1 1 0 1 0 DEh 1 1 ↑ x 0 1 0 1 0 1 0 1 55h 1 1 ↑ x 1 0 1 0 1 0 1 0 AAh 1 1 ↑ x 0 1 1 0 0 1 1 0 66h st Parameter 2 NV Memory Function Controller 2 nd Parameter 3 rd Parameter Description MTP write EPWRITE command Please see MTP Access sequence for program(Data write) for more detail Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Power On Sequence SW Reset HW Reset Default Value N/A N/A N/A Legend command EPWRITE(D7h) Parameter Display Flow Chart Action 1st Parameter 2nd Parameter 3rd Parameter Mode Sequential transfer Page 157 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.57 Positive Gamma Correction Setting (E0h) E1H Postive Gamma Correction Setting Command 1 RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 1 1 1 0 0 0 0 1 E1h 1 1 ↑ x x VP0[5:0] x 1 1 ↑ x x VP1[5:0] x 1 1 ↑ x x VP2[5:0] x 1 1 ↑ x x VP4[5:0] x 1 1 ↑ x x VP6[5:0] x 1 1 ↑ x x 1 1 ↑ x x 1 1 ↑ 1 1 ↑ x 1 1 ↑ x x 1 1 ↑ x x VP57[5:0] x 1 1 ↑ x x VP59[5:0] x 1 1 ↑ x x VP61[5:0] x 1 1 ↑ x x VP62[5:0] x 1 1 ↑ x x VP63[5:0] x st Parameter 2 D/CX nd Parameter 3 rd Parameter 4 th Parameter 5 th Parameter 6 th Parameter 7 x VP20[6:0] x th Parameter 9 VP13[4:0] th Parameter 8 x VP36[3:0] VP27[3:0] x th Parameter 10 x th Parameter 11 VP43[6:0] x VP50[5:0] x th Parameter 12 th Parameter 13 th Parameter 14 th Parameter 15 th Parameter Description Restriction Set the gray scale voltage to adjust the gamma characteristics of the TFT panel. It apply to gamma curve selection for only activate when EXTC=1 and GAM_R_SEL=1 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value st th 1 ~ 9 Parameter Power On Sequence All ”00” SW Reset All ”00” HW Reset All ”00” Page 158 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend GAMCTRP0(E0h) command Parameter Display Flow Chart 1st Parameter 2nd Parameter : : 9th Parameter Action Mode Sequential transfer Page 159 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.58 Negative Gamma Correction Setting (E1h) E1H Negative Gamma Correction Setting Command 1 RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 1 1 1 0 0 0 0 1 E1h 1 1 ↑ x x 1 1 ↑ x x 1 1 ↑ x x 1 1 ↑ x x 1 1 ↑ x x 1 1 ↑ x x 1 1 ↑ x x 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ st Parameter 2 D/CX nd Parameter 3 rd Parameter 4 th Parameter 5 th Parameter 6 th Parameter 7 th Parameter 8 th Parameter 9 th Parameter 10 th Parameter 11 th Parameter 12 th Parameter 13 th Parameter 14 th Parameter 15 th Parameter Description Restriction VN0[5:0] x VN1[5:0] x VN2[5:0] x VN4[5:0] x VN6[5:0] x x VN13[4:0] VN20[6:0] VN36[3:0] x VN27[3:0] x x VN43[6:0] x x x x x x x x x x x x x x x VN50[5:0] x VN57[5:0] x VN59[5:0] VN61[5:0] x VN62[5:0] x VN63[5:0] x Set the gray scale voltage to adjust the gamma characteristics of the TFT panel. It apply to gamma curve selection for only activate when EXTC=1 and GAM_R_SEL=1 Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default x Default Value st th 1 ~ 9 Parameter Power On Sequence All ”00” SW Reset All ”00” HW Reset All ”00” Page 160 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Legend GAMCTRN0(E1h) command Parameter Display Flow Chart 1st Parameter 2nd Parameter : : 9th Parameter Action Mode Sequential transfer Page 161 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 14.2.59 GAM_R_SEL (F2h) F2h Gamma Setting (Green) Command 1 D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 1 ↑ 1 1 1 1 0 0 1 0 F2h GAM_R_ st 1 Parameter 1 ↑ x x x x x x x SEL Write GAM_R_SEL: Gamma adjustment E0h and E1h enable control Descriptio n 0: Disable (Default) 1: Enable Restriction Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Register Normal Mode On, Idle Mode On, Sleep Out Yes Availability Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Status Default Default Value Power On Sequence 0h SW Reset 0h HW Reset 0h Page 162 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 15. Example Connection with Panel direction and Different Resolution 15.1. Application of connect with panel direction (when GM=’011’) Case 1: (This is default case) - 1st Pixel is at Left Top of the panle - RGB filter order = RGB G161 Driver IC ( Bump down) S7 S390 G3 00h 01h 02h __ __ __ __ 7Dh 7Eh G160 - Direction default setting(H/W) SMX = 0 SMY = 0 SRGB = 0 G2 7Fh G1 G2 1st Pixel G3 G4 S1 = Filter R S2 = Filter G S3 = Filter B - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY -XY- Exchange control by MV IC (Bump down) LCD Front side CF Glass G157 G158 G159 G160 TFT Glass Page 163 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Case 2: - 1st Pixel is at Left Top of the panel - RGB filter order = BGR G161 Driver IC ( Bump down) S7 S390 G3 00h 01h 02h __ __ __ __ 7Dh 7Eh G160 - Direction default setting(H/W) SMX = 0 SMY = 0 SRGB = 1 G2 7Fh G1 G2 S1 = Filter B S2 = Filter G S3 = Filter R 1st Pixel G3 G4 - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY -XY- Exchange control by MV IC (Bump down) LCD Front side G157 CF Glass G158 G159 G160 TFT Glass Case3: - 1st Pixel is at Right Bottom of the panel - RGB filter order = “RGB” G161 Driver IC ( Bump down) S7 S390 G3 00h 01h 02h __ __ __ __ 7Dh 7Eh G160 - Direction default setting(H/W) SMX = 0 SMY = 0 SRGB = 0 G2 7Fh G1 S1 = Filter R S2 = Filter G S3 = Filter B G2 G3 G4 - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY -XY- Exchange control by MV IC (Bump down) LCD Front side CF Glass G157 G158 1st Pixel G159 G160 TFT Glass Page 164 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Case 4: - 1st Pixel is at Right-Bottom of the panel - RGB filter order = “BGR” G161 Driver IC ( Bump down) S7 S390 G3 00h 01h 02h __ __ __ __ 7Dh 7Eh G160 - Direction default setting(H/W) SMX = 0 SMY = 0 SRGB = 1 G2 7Fh G1 G2 S1 = Filter B S2 = Filter G S3 = Filter R 1st Pixel G3 G4 - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY -XY- Exchange control by MV IC (Bump down) G157 LCD Front side CF Glass G158 G159 G160 TFT Glass Page 165 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 15.2. Application of connection with Different resolution Case 1 of Resolution (132RGB x 132)(GM[2:0]=”101”) RAM size=132 x 132 x 18-bits(Used) Display size = 132RGB x 132 1) Example for SMX=SMY=’0’ G133 GRAM size(132x132x18-bits) 00h 01h 02h __ __ 76h 77h G3 G132 G2 (0,0) __ 82h 83h 00h 000h 001h Driver IC ( Bump down) S1 S396 01h 02h __ __ __ 76h 77h __ 82h 83h G1 G 2 (0,0) 002h 1st Pixel G2 G3 G4 G4 (131,131 ) G129 9DH G130 9EH G158 G131 9FH G132 Unused area - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV (131,131) - Direction default setting (H/W) SMX = 0 SMY = 0 SRGB = 0 Page 166 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 2) Example for SMX=SMY=’1’ G133 GRAM size(132x132x18-bits) 00h 01h 02h __ __ 76h __ 77h 82h 001h S1 83h 00h 000h G132 Driver IC ( Bump down) G3 01h 02h S396 __ __ __ 76h 77h __ G2 82h 83h G1 (0,0) (131,131) 002h G2 G2 G4 G4 G3 (131,131) G129 9DH G158 G130 9EH G131 1st Pixel 9FH G132 (0,0) Unused area - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV - Direction default setting (H/W) SMX = 1 SMY = 1 SRGB = 0 Case 2 of Resolution (130RGB x 130)(GM[2:0]=”100”) RAM size=130 x 130 x 18-bits(Used) Display size = 130RGB x 130 1) Example for SMX=SMY=’0’ Page 167 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color G131 GRAM size(130x130x18-bits) 00h 01h 02h __ __ 76h 77h ILI9163 G130 Driver IC ( Bump down) G3 S7 S396 G2 (0,0) __ 80h 81h 00h 000h 01h 02h __ __ __ 76h 77h __ 80h 81h G1 001h (0,0) 1st Pixel 002h G2 G2 G4 G4 G3 (129,129) G127 9DH G158 G128 9EH G129 9FH G130 Unused area - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV (129,129) - Direction default setting (H/W) SMX = 0 SMY = 0 SRGB = 0 2) Example for SMX=SMY=’1’ G131 GRAM size(130x130x18-bits) 00h 01h 02h __ __ 76h 77h __ 80h 001h S7 81h 00h 000h G130 Driver IC ( Bump down) G3 01h 02h S396 __ __ __ 76h 77h __ G2 80h 81h G1 (0,0) (129,129) 002h G2 G2 G4 G4 G3 (129,129) G127 9DH G158 G128 9EH G129 1st Pixel 9FH G130 (0,0) Unused area - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV - Direction default setting (H/W) SMX = 1 SMY = 1 SRGB = 0 Page 168 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Case 3 of Resolution (128RGB x 160)(GM[2:0]=”011”) RAM size=128 x 160 x 18-bits(Used) Display size = 128RGB x 160 1) Example for SMX=SMY=’0’ G161 GRAM size(128x160x18-bits) 00h 01h 02h __ __ __ __ 7Dh S7 S390 G2 (0,0) 7Eh 7Fh 00h 000h 001h G160 Driver IC ( Bump down) G3 01h 02h __ __ __ __ 7Dh 7Eh 7Fh G1 (0,0) 1st Pixel 002h G2 G3 G4 G157 9DH G158 9EH G159 9FH G160 (127,159) (127,159) - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV - Direction default setting (H/W) SMX = 0 SMY = 0 SRGB = 0 2) Example for SMX=SMY=’1’ Page 169 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color G161 GRAM size(128x160x18-bits) 00h 01h 02h __ __ __ __ 7Dh 7Eh 7Fh 001h 00h G160 Driver IC ( Bump down) G3 000h ILI9163 S7 01h 02h S390 __ __ __ __ 7Dh 7Eh G2 7Fh G1 (0,0) G2 (127,159) 002h G3 G4 G157 9DH G158 9EH G159 9FH 1st Pixel G160 (127,159) (0,0) - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV - Direction default setting (H/W) SMX = 1 SMY = 1 SRGB = 0 Case4 of Resolution (120RGB x 160)(GM[2:0]=”010”) RAM size=120 x 160 x 18-bits(Used) Display size = 120RGB x 160 1) Example for SMX=SMY=’0’ Page 170 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color G161 GRAM size(120x160x18-bits) 00h 01h 02h __ __ __ 76h 77h G160 Driver IC ( Bump down) G3 S7 S366 G2 (0,0) __ 7Eh 7Fh 000h 001h ILI9163 00h 01h 02h __ __ __ __ 75h 76h 77h G1 (0,0) G2 1st Pixel 002h G3 G4 G157 9DH (119,159) G158 9EH G159 9FH G160 (119,159) Unused area - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV - Direction default setting (H/W) SMX = 0 SMY = 0 SRGB = 0 2) Example for SMX=SMY=’1’ G161 GRAM size(120x160x18-bits) 00h 01h 02h __ __ __ __ 75h 76h 77h 00h 000h 001h G160 Driver IC ( Bump down) G3 S7 01h 02h S366 __ __ __ __ 7Dh 7Eh G2 7Fh G1 (0,0) G2 (119,159) 002h G3 G4 G157 9DH G158 9EH G159 9FH 1st Pixel G160 (119,159) (0,0) - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV - Direction default setting (H/W) SMX = 1 SMY = 1 SRGB = 0 Page 171 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Case 5 of Resolution (128RGBx128)(GM[2:0]=”001”) RAM size=128 x 128 x 18-bits(Used) 1) Example for SMX=SMY=’0’ G129 GRAM size(128x128x18-bits) 00h 01h 02h __ __ 76h 77h __ S7 S390 G2 (0,0) 7Eh 7Fh 00h 000h 001h G128 Driver IC ( Bump down) G3 01h 02h __ __ __ 76h 77h __ 7Eh 7Fh G1 (0,0) 1st Pixel 002h G2 G2 G4 G4 G3 (127,127) G125 9DH G158 G126 9EH G127 9FH G128 Unused area (127,127) - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV - Direction default setting (H/W) SMX = 0 SMY = 0 SRGB = 0 2) Example for SMX=SMY=’1’ Page 172 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color G129 GRAM size(128x128x18-bits) 00h 01h 02h __ __ 76h 77h __ 7Eh 001h S7 7Fh 00h G128 Driver IC ( Bump down) G3 000h ILI9163 01h 02h S390 __ __ __ 76h 77h __ G2 7Eh 7Fh G1 (0,0) G2 G2 G4 G4 (127,127) 002h G3 (127,127) G125 9DH G158 G126 9EH 1st Pixel G127 9FH G128 (0,0) Unused area - Direction default setting (H/W) SMX = 1 SMY = 1 SRGB = 0 - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV Case 6 of Resolution (132RGB x 162)(GM[2:0]=”000”) RAM size = 132 x 162 x 18-bits(Used) Display size = 132RGB x 162 1) Example for SMX=SMY=’0’ Page 173 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color G161 GRAM size(132x162x18-bits) 00h 01h 02h __ __ __ __ __ __ 81h 82h 83h (0,0) 00h G162 Driver IC ( Bump down) G1 000h ILI9163 S1 01h S396 02h __ __ __ __ 81h G2 82h 83h G1 001h (0,0) 1st pixel 002h G2 G2 G4 G4 G3 G159 9FH G160 A0H G161 A1H G162 (131,161) (131,161) - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV - Direction default setting (H/W) SMX = 0 SMY = 0 SRGB = 0 2) Example for SMX=SMY=’1’ G161 GRAM size(132x162x18-bits) 00h 01h 02h __ __ __ __ __ __ 81h 82h 83h (131,161) 000h 001h 00h G162 Driver IC ( Bump down) G1 S1 01h 02h S396 __ __ __ __ 81h G2 82h 83h G1 (0,0) 002h G2 G2 G4 G4 G3 G159 9FH G160 A0H G161 1st pixel A1H G162 (131,161) - Display direction control (S/W) - X- Mirror control by MX - Y- Mirror control by MY - XY- Exchange control by MV (0,0) - Direction default setting (H/W) SMX = 1 SMY = 1 SRGB = 0 Page 174 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 16. OTP Programming Flow Start C onnect external pow er 6.5V to DDVDH E X T C pin = V D D I R ead m ark bits of com m and D 5h to check the program m ing status of ID 2 or ID 3 or V M F W rite com m and D 6 h to set O T P data and address Y es W rite com m and D 7h to start O T P program W ait 6.5m s Y es Program other byte No R em ove external pow er Softw are reset or sleep out com m and or H W reset to update O T P value in register C heck ID 2, ID 3, V M F, C trl, M ark all correct ? No Y es END Page 175 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 17. Electrical Characteristics 17.1. Absolute Maximum Ratings The absolute maximum rating is listed on following table. When ILI9163 is used out of the absolute maximum ratings, the ILI9163 may be permanently damaged. To use the ILI9163 within the following electrical characteristics limit is strongly recommended for normal operation. If these electrical characteristic conditions are exceeded during normal operation, the ILI9163 will malfunction and cause poor reliability. Item Symbol Value Note Supply voltage VDD V -0.3 ~ + 4.6 Supply voltage (Logic) VDDI V -0.3 ~ + 4.6 Supply voltage (Digital) VCC V -0.3 ~ + 2.4 Driver supply voltage VGH-VGL V -0.3 ~ + 33.0 Logic input voltage range VIN V -0.3 ~ VDDI + 0.3 Logic output voltage range VO V -0.3 ~ VDDI + 0.3 Operating temperature Topr °C -40 ~ + 85 Storage temperature Tstg °C -55 ~ + 110 Notes: If the absolute maximum rating of even is one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Page 176 of 183 Unit Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 17.2. DC Characteristics Item Symbol Uni t Condition Min. Typ. Max. Note Note2 Power & Operation Voltage Analog Operating VDD V Operating voltage 2.6 2.78 3.3 Logic Operating voltage VDDI V I/O supply voltage 1.65 1.8/2.78 3.3 Digital Operating voltage VCC V Digital supply voltage Gate Driver High voltage VGH V 10.0 16.0 Gate Driver Low voltage VGL V -16.0 -9.0 Note3 19 32 Note3 voltage Driver Supply voltage V 1.8 ｜VGH-VGL｜ Note2 Note2 Note3 Input/Output Logic High level input voltage Logic Low level input voltage Logic High level output voltage Logic High level output voltage Logic High level input current Logic Low level input current Logic input leakage current VIH V 0.7VDDI VDDI Note1,2,3 VIL V VSS 0.3VDDI Note1,2,3 VOH V IOH = -1.0mA 0.8VDDI VDDI Note1,2,3 VOL V IOL = 1.0mA VSS 0.2VDDI Note1,2,3 IIH µA 1 Note1,2,3 IIL µA IIL µA -1 VIN = VDDI or VSS Note1,2,3 -0.1 +0.1 Note1,2,3 VCOM Operation VCOM High voltage VCOMH V Ccom=12nF 2.5 5.0 Note 3 VCOM Low voltage VCOML V Ccom=12nF -2.5 0.0 Note 3 VOMA V ｜VCOMH-VCOML｜ 4.0 5.5 Note 3 Vsout V 0.1 AVDD-0.1 Note4 GVDD V 3.0 5.0 Note3 Tr µS 20 Note4,5 20 Note4 15 - 35 Note8 6*7 Note3 5 Note3 VCOM Amplitude voltage Source Driver Source output range Gamma reference voltage Source output setting time Output deviation voltage (Source output channel) Output offset voltage Vdev mV mV VOFSET mV AVDD V Below with 99% precision 15 Sout >= 4.2V Sout <=0.8V 4.2V>Sout>0.8V Booster Operation 1 st Booster (VDDx2) voltage 1 st Booster(VDDx2) Drop voltage Liner range VDDx2, drop VLinear % 4.5*6 I loading = 1mA V 0.2 AVDD-0.2 Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=GND=0V, Ta=-30 to 70℃ (to +85℃ no damage) Note2: Please supply digital VDDI voltage equal or less than analog VDD voltage. (VDDI≦VDD) Note2,3,4: When the measurements are performed with LCD module. Measurement Points are like below. Note3: CSX, RDX, WRX, D[23:0], D/CX, RESX, TE, PCLK, VS, HS, DE, SDA, SCL, GM2, GM1, GM0, LCM,RCM1, RCM0, P68, IM2, IM1, IM0, SRGB, REV, SMX, SMY, RL, TB, IDM, SHUT, PREG, GS and Test pins. Note5: Source channel loading = 10pF/channel, Gate channel loading = 50pF/channel Page 177 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 Note6: VDD=2.6V or VCI1=2.6V Note7: VDD=3.3V or VCI1=3.3V Note8: The Max. value is between with Note 4 measure point and Gamma setting value. 17.3. AC Characteristics 17.4. Display Module Parallel 18/16/9/8-bit Bus Note: Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Table 17.4.1 AC characteristics of parallel CPU I/F in asynchronous mode Signal D/CX CSX Symbol Parameter min max unit tast Address setup time 0 ns taht Address hold time(Write/Read) 10 ns tchw ”S”"H" Pulse Widtch 0 ns tcs Chip Select setup time (Write) 10 ns trcs Chip Select setup time (Read ID) 45 ns trcsfm Chip Select setup time (Read FM) 355 ns tcsf Chip Select Wait time(Write/read) 10 ns Page 178 of 183 description Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color twc Write cycle 66 ns twrh Controlpulse H duration 15 ns twrl Control pulse L duration 15 ns trc Read cycle (ID) 160 ns trdh Control pulse H duration(ID) 90 ns trdl Control pulse L duration(ID) 45 ns Read cycle (FM) 450 ns trdhfm Control pulse H duration (FM) 90 ns trdlfm Control pulse L duration (FM) 355 ns tdst Data setup time 10 ns tdht Data hold time 10 ns trat Read access time (ID) 40 ns tratfm Read access time (FM) 340 ns todh Output disable time 80 ns WRX RDX trcfm RDX ILI9163 D[17..0] 20 When read ID data When read from frame memory For maximum CL = 30pF For minimum CL = 8pF Note 1: VDDI 1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=GND=0V, Ta=-30 to 70 °C (to +85°C no damage) Note 2: This input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for input signals 17.5. Display Serial Interface 17.5.1 3-pin Serial Interface Table 17.5.1.1: 3-pin Serial Interface Characteristics Signal CSX SCL Symbol Parameter MIN TCSS Chip select setup time 15 ns TCSH Chip select hold time 60 ns TCHW Chip select setup time 40 ns TSCYCW Serial clock cycle(Write) 66 ns Page 179 of 183 MAX Unit Description Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color TSHW S“L”"H" pulse width(Write) 1 ns TSLW S“L”"L" pulse width(Write) 15 ns TSCYCR Serial clock cycle(Read) 150 ns TSHR S“L”"H" pulse width(Read) 60 ns TSLR S“L”"L" pulse width(Read) 60 ns TSDS Data setup time 10 ns SDA(DIN) TSDH Data hold time 10 ns (DOUT) TACC Access time 10 TOH Output disable time 15 50 ILI9163 ns For maximum CL = 30pF ns For minimum CL = 8pF Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=GND=0V. Ta=-30 to 70℃ (to +85℃ no damage) Note 2 : The input signal rise time and fall time(tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 10% and 90% of VDDI for Input signals. 17.5.2 4-pin Serial Interface Table 6.1.3.2: 4 pin Serial Interface Characteristics Signal CSX SCL Symbol Parameter MIN TCSS Chip select setup time 15 ns TCSH Chip select hold time 60 ns TCHW Chip select setup time 40 ns TSCYCW Serial clock cycle(Write) 66 ns TSHW S“L”"H" pulse width(Write) 1 ns TSLW S“L”"L" pulse width(Write) 15 ns TSCYCR Serial clock cycle(Read) 150 ns TSHR S“L”"H" pulse width(Read) 60 ns Page 180 of 183 MAX Unit Description Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color TSLR S“L”"L" pulse width(Read) 60 ns TDCS D/CX setup time 7 ns TDCH D/CX hold time 7 ns TSDS Data setup time 10 ns SDA(DIN) TSDH Data hold time 10 ns (DOUT) TACC Access time 10 TOH Output disable time 15 D/CX 50 ILI9163 ns For maximum CL = 30pF ns For minimum CL = 8pF Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=GND=0V. Ta=-30 to 70℃ (to +85℃ no damage) Note 2 : The input signal rise time and fall time(tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 10% and 90% of VDDI for Input signals. Page 181 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 17.6. Reset Timing Characteristics Reset Timing Characteristics (VDDI = 1.65 ~ 3.3 V) Item Symbol Unit Min. Typ. Reset low-level width tRES ms 1 - - Reset rise time trRES µs - - 10 tRES nRE S ET Max. trRES VIH VIL Page 182 of 183 Version: 0.18 a-Si TFT LCD Single Chip Driver 132RGBx162 Resolution and 262K color ILI9163 18. Revision History Version No. Date V.01 2007/08/30 V0.11 2007/10/8 Page Description New Created P177 Add Ch15 : Example Connection with Panel direction and Different Resolution P151 Modify Interanal Oscillator Modify the input pad size and input pad coordination V0.13 2007/11/01 16, 20 V0.14 2007/11/28 85,86,89,121 Modify HEX 123,166 106,146,150 Modify Parameter 112,135,138, Modify RDX/WRX 139,141,143 146 Modify Descirption – internal oscillator 1 Modify PTG[1:0] to PTG[0] 147 Modify PT[1:0] VCOM output on non-display area 152,185 Modify AVDD, VCL 177,178,181 Modify SMX/SMY=1 183, V0.15 2008/03/17 184 Add OTP Programming Flow All Remove RGB Interface 14 Modify Chip Thickness 300um Æ 280um Modify Pad Height 90um Æ 75um V0.16 2008/03/28 13,189 Remove VCC 10,11 Add HS/VS/PCLK/DE/TB/RL Definition V0.17 2008/05/07 35 Update RGB Interface V0.18 2008/07/24 All Remove RGB Interface Page 183 of 183 Version: 0.18