SITRONIX ST7773

ST
Sitronix
ST7773
262K Color Single-Chip TFT Controller/Driver
1. Introduction
ST7773 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 528 source line and 220 gate
line driver circuits. This chip can be connected to a microprocessor direct through Serial Peripheral Interface (SPI) or
8-bits/9-bits/16-bits/18-bits parallel interface. The display data is stored in the on-chip Display Data RAM (DDRAM) of
176x220x18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power
consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to
make a display system with fewer components.
2. Features
Single chip TFT-LCD Controller/Driver with RAM
Built-in Circuits
On-chip Display Data RAM (i.e. Frame Memory)
-
DC/DC converter
-
176 x 220 x 18 = 696,960 bits
-
Adjustable VCOM
LCD Driver Output Circuits:
-
4 preset gamma curves (1.0, 1.8, 2.2 & 2.5)
-
Source Outputs: 176 RGB channels
-
Oscillator for display clock generation
-
Gate Outputs: 220 channels
-
Timing controller
Display Resolution
Built-in NV Memory for LCD Initial Register Setting
-
-
7-bits for ID2
Display Colors (Color Mode)
-
7-bits for VCOM adjustment
-
Full Color: 262K, RGB=(666) max., Idle Mode OFF
Wide Supply Voltage Range
-
176 (RGB) x 220
Color Reduce: 8-color, RGB=(111), Idle Mode ON
-
I/O Voltage (VDDI to DGND): 1.6V~3.3V
Programmable Pixel Color Format (Color Depth) for
-
Analog Voltage (VDD to AGND): 2.7V~3.3V
Various Display Data input Format
On-Chip Power System
-
12-bit/pixel: RGB=(444) using whole frame memory
-
Source Voltage (GVDD to AGND): 3.0V~5.0V
-
16-bit/pixel: RGB=(565) using whole frame memory
-
VCOM HIGH level (VCOMH to AGND): 2.5V to 5.0V
-
18-bit/pixel: RGB=(666) using whole frame memory
-
VCOM LOW level (VCOML to AGND): -2.5V to 0.0V
-
Gate driver HIGH level (VGH to AGND):
Various Interfaces
-
Parallel 8080-series MCU Interface
-
3-line serial interface
+10.0V to 16V
-
(8-bit, 9-bit, 16-bit & 18-bit)
-13V to -5.5V
Display Features
Operating Temperature: -30°C to +85°C
-
Programmable partial display duty
-
Line inversion, frame inversion
-
Supporting MVA type LC
-
Support both normal-black & normal-white LC
ST7773
Gate driver LOW level (VGL to AGND):
8080 MCU Interface: 8-bit/9-bit/16-bit/18-bit
Serial Peripheral Interface : 3-line
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice
Ver. 2.0
1
2008-7-7
ST7773
3. Pad arrangement
G220
G216
G6
G2
G8
G4
S527
S525
ST7773
(Bump-up)
S528
S526
G218
G214
S3
S1
S4
S2
G1
G5
G3
G7
G215
G219
Ver. 2.0
G213
G217
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VREF
C23N
C23N
C23N
C23P
C23P
C23P
C22N
C22N
C22N
C22P
C22P
C22P
VGH
VGH
VGH(O)
VGL
VGL
VGL
VCOML
VCOML
VCOML
VCOML
VCOMH
VCOMH
VCOMH
VCOMH
VCL
VCL
VCL
VCL(O)
C21N
C21N
C21N
C21P
C21P
C21P
VCI1
VCI1
VCI1
VCI1
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AVDD
AVDD(O)
AVDD(O)
AVDD(O)
AVDD(O)
C12N
C12N
C12N
C12N
C12P
C12P
C12P
C12P
C11N
C11N
C11N
C11N
C11P
C11P
C11P
C11P
GVDD
GVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VCC(O)
VCC
VCC
VCC
VCC
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
TEST
TEST
TEST
DGNDO
TEST
DGNDO
D/CX(SCI)
DGNDO
RESX
TEST
TEST
WRX
RDX
CSX
TE
OSC
DGNDO
VDDIO
D0(SDA)
D1
D2
D3
D4
D5
D6
D7
D8
DGNDO
D9
D10
D11
D12
D13
D14
D15
D16
D17
TEST
TPO[7]
TPO[6]
TPO[5]
TPO[4]
TPO[3]
TPO[2]
TPO[1]
TPO[0]
TPI[3]
TPI[2]
TPI[1]
TPI[0]
VDDIO
DGNDO
VDDIO
TEST
TEST
DGNDO
TEST
TEST
TEST
TEST
TEST
VDDIO
SMY
SMX
SRGB
DGNDO
TEST
TEST
VDDIO
TEST
DGNDO
AUTO
TEST
TEST
IM2
IM1
IM0
VDDIO
EXTC
DUMMYA
View point: bump view
Chip size (um): 17370x820
PAD coordinate: pad center
Coordinate origin: chip center
Chip thickness (um): 300(typical)
Bump height (um): 15(typical)
Bump hardness (HV): 75(typical)
Pad arrangement (Unit: um):
Output: pad No. 1 ~ 751 = 18 x 96
Input: pad No. 752 ~ 947 = 50 x 96
70
96
50
50
Alignment mark (unit: um):
Left align mark (-8120.58,-300)
Left align mark ( 8080.6,-300)
30
40
30
Alignment mark
2
2008-07-07
ST7773
4. Pad Center Coordinates
Unit: um
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
1
G220
7028
299
41
G140
6308
299
2
G218
7010
168
42
G138
6290
168
3
G216
6992
299
43
G136
6272
299
4
G214
6974
168
44
G134
6254
168
5
G212
6956
299
45
G132
6236
299
6
G210
6938
168
46
G130
6218
168
7
G208
6920
299
47
G128
6200
299
8
G206
6902
168
48
G126
6182
168
9
G204
6884
299
49
G124
6164
299
10
G202
6866
168
50
G122
6146
168
11
G200
6848
299
51
G120
6128
299
12
G198
6830
168
52
G118
6110
168
13
G196
6812
299
53
G116
6092
299
14
G194
6794
168
54
G114
6074
168
15
G192
6776
299
55
G112
6056
299
16
G190
6758
168
56
DUMMYA
6038
168
17
G188
6740
299
57
G110
6020
299
18
G186
6722
168
58
G108
6002
168
19
G184
6704
299
59
G106
5984
299
20
G182
6686
168
60
G104
5966
168
21
G180
6668
299
61
G102
5948
299
22
G178
6650
168
62
G100
5930
168
23
G176
6632
299
63
G98
5912
299
24
G174
6614
168
64
G96
5894
168
25
G172
6596
299
65
G94
5876
299
26
G170
6578
168
66
G92
5858
168
27
G168
6560
299
67
G90
5840
299
28
G166
6542
168
68
G88
5822
168
29
G164
6524
299
69
G86
5804
299
30
G162
6506
168
70
G84
5786
168
31
G160
6488
299
71
G82
5768
299
32
G158
6470
168
72
G80
5750
168
33
G156
6452
299
73
G78
5732
299
34
G154
6434
168
74
G76
5714
168
35
G152
6416
299
75
G74
5696
299
36
G150
6398
168
76
G72
5678
168
37
G148
6380
299
77
G70
5660
299
38
G146
6362
168
78
G68
5642
168
39
G144
6344
299
79
G66
5624
299
40
G142
6326
168
80
G64
5606
168
Ver.2.0
3
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
81
G62
5588
299
121
S519
4275
168
82
G60
5570
168
122
S518
4257
299
83
G58
5552
299
123
S517
4239
168
84
G56
5534
168
124
S516
4221
299
85
G54
5516
299
125
S515
4203
168
86
G52
5498
168
126
S514
4185
299
87
G50
5480
299
127
S513
4167
168
88
G48
5462
168
128
S512
4149
299
89
G46
5444
299
129
S511
4131
168
90
G44
5426
168
130
S510
4113
299
91
G42
5408
299
131
S509
4095
168
92
G40
5390
168
132
S508
4077
299
93
G38
5372
299
133
S507
4059
168
94
G36
5354
168
134
S506
4041
299
95
G34
5336
299
135
S505
4023
168
96
G32
5318
168
136
S504
4005
299
97
G30
5300
299
137
S503
3987
168
98
G28
5282
168
138
S502
3969
299
99
G26
5264
299
139
S501
3951
168
100
G24
5246
168
140
S500
3933
299
101
G22
5228
299
141
S499
3915
168
102
G20
5210
168
142
S498
3897
299
103
G18
5192
299
143
S497
3879
168
104
G16
5174
168
144
S496
3861
299
105
G14
5156
299
145
S495
3843
168
106
G12
5138
168
146
S494
3825
299
107
G10
5120
299
147
S493
3807
168
108
G8
5102
168
148
S492
3789
299
109
G6
5084
299
149
S491
3771
168
110
G4
5066
168
150
S490
3753
299
111
G2
5048
299
151
S489
3735
168
112
S528
4437
299
152
S488
3717
299
113
S527
4419
168
153
S487
3699
168
114
S526
4401
299
154
S486
3681
299
115
S525
4383
168
155
S485
3663
168
116
S524
4365
299
156
S484
3645
299
117
S523
4347
168
157
S483
3627
168
118
S522
4329
299
158
S482
3609
299
119
S521
4311
168
159
S481
3591
168
120
S520
4293
299
160
S480
3573
299
Ver.2.0
4
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
161
S479
3555
168
201
S439
2835
168
162
S478
3537
299
202
S438
2817
299
163
S477
3519
168
203
S437
2799
168
164
S476
3501
299
204
S436
2781
299
165
S475
3483
168
205
S435
2763
168
166
S474
3465
299
206
S434
2745
299
167
S473
3447
168
207
S433
2727
168
168
S472
3429
299
208
S432
2709
299
169
S471
3411
168
209
S431
2691
168
170
S470
3393
299
210
S430
2673
299
171
S469
3375
168
211
S429
2655
168
172
S468
3357
299
212
S428
2637
299
173
S467
3339
168
213
S427
2619
168
174
S466
3321
299
214
S426
2601
299
175
S465
3303
168
215
S425
2583
168
176
S464
3285
299
216
S424
2565
299
177
S463
3267
168
217
S423
2547
168
178
S462
3249
299
218
S422
2529
299
179
S461
3231
168
219
S421
2511
168
180
S460
3213
299
220
S420
2493
299
181
S459
3195
168
221
S419
2475
168
182
S458
3177
299
222
S418
2457
299
183
S457
3159
168
223
S417
2439
168
184
S456
3141
299
224
S416
2421
299
185
S455
3123
168
225
S415
2403
168
186
S454
3105
299
226
S414
2385
299
187
S453
3087
168
227
S413
2367
168
188
S452
3069
299
228
S412
2349
299
189
S451
3051
168
229
S411
2331
168
190
S450
3033
299
230
S410
2313
299
191
S449
3015
168
231
S409
2295
168
192
S448
2997
299
232
S408
2277
299
193
S447
2979
168
233
S407
2259
168
194
S446
2961
299
234
S406
2241
299
195
S445
2943
168
235
S405
2223
168
196
S444
2925
299
236
S404
2205
299
197
S443
2907
168
237
S403
2187
168
198
S442
2889
299
238
S402
2169
299
199
S441
2871
168
239
S401
2151
168
200
S440
2853
299
240
S400
2133
299
Ver.2.0
5
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
241
S399
2115
168
281
S359
1395
168
242
S398
2097
299
282
S358
1377
299
243
S397
2079
168
283
S357
1359
168
244
S396
2061
299
284
S356
1341
299
245
S395
2043
168
285
S355
1323
168
246
S394
2025
299
286
S354
1305
299
247
S393
2007
168
287
S353
1287
168
248
S392
1989
299
288
S352
1269
299
249
S391
1971
168
289
S351
1251
168
250
S390
1953
299
290
S350
1233
299
251
S389
1935
168
291
S349
1215
168
252
S388
1917
299
292
S348
1197
299
253
S387
1899
168
293
S347
1179
168
254
S386
1881
299
294
S346
1161
299
255
S385
1863
168
295
S345
1143
168
256
S384
1845
299
296
S344
1125
299
257
S383
1827
168
297
S343
1107
168
258
S382
1809
299
298
S342
1089
299
259
S381
1791
168
299
S341
1071
168
260
S380
1773
299
300
S340
1053
299
261
S379
1755
168
301
S339
1035
168
262
S378
1737
299
302
S338
1017
299
263
S377
1719
168
303
S337
999
168
264
S376
1701
299
304
S336
981
299
265
S375
1683
168
305
S335
963
168
266
S374
1665
299
306
S334
945
299
267
S373
1647
168
307
S333
927
168
268
S372
1629
299
308
S332
909
299
269
S371
1611
168
309
S331
891
168
270
S370
1593
299
310
S330
873
299
271
S369
1575
168
311
S329
855
168
272
S368
1557
299
312
S328
837
299
273
S367
1539
168
313
S327
819
168
274
S366
1521
299
314
S326
801
299
275
S365
1503
168
315
S325
783
168
276
S364
1485
299
316
S324
765
299
277
S363
1467
168
317
S323
747
168
278
S362
1449
299
318
S322
729
299
279
S361
1431
168
319
S321
711
168
280
S360
1413
299
320
S320
693
299
Ver.2.0
6
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
321
S319
675
168
361
S279
-45
168
322
S318
657
299
362
S278
-63
299
323
S317
639
168
363
S277
-81
168
324
S316
621
299
364
S276
-99
299
325
S315
603
168
365
S275
-117
168
326
S314
585
299
366
S274
-135
299
327
S313
567
168
367
S273
-153
168
328
S312
549
299
368
S272
-171
299
329
S311
531
168
369
S271
-189
168
330
S310
513
299
370
S270
-207
299
331
S309
495
168
371
S269
-225
168
332
S308
477
299
372
S268
-243
299
333
S307
459
168
373
S267
-261
168
334
S306
441
299
374
S266
-279
299
335
S305
423
168
375
S265
-297
168
336
S304
405
299
376
DUMMYA
-315
299
337
S303
387
168
377
S264
-333
168
338
S302
369
299
378
S263
-351
299
339
S301
351
168
379
S262
-369
168
340
S300
333
299
380
S261
-387
299
341
S299
315
168
381
S260
-405
168
342
S298
297
299
382
S259
-423
299
343
S297
279
168
383
S258
-441
168
344
S296
261
299
384
S257
-459
299
345
S295
243
168
385
S256
-477
168
346
S294
225
299
386
S255
-495
299
347
S293
207
168
387
S254
-513
168
348
S292
189
299
388
S253
-531
299
349
S291
171
168
389
S252
-549
168
350
S290
153
299
390
S251
-567
299
351
S289
135
168
391
S250
-585
168
352
S288
117
299
392
S249
-603
299
353
S287
99
168
393
S248
-621
168
354
S286
81
299
394
S247
-639
299
355
S285
63
168
395
S246
-657
168
356
S284
45
299
396
S245
-675
299
357
S283
27
168
397
S244
-693
168
358
S282
9
299
398
S243
-711
299
359
S281
-9
168
399
S242
-729
168
360
S280
-27
299
400
S241
-747
299
Ver.2.0
7
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
401
S240
-765
168
441
S200
-1485
168
402
S239
-783
299
442
S199
-1503
299
403
S238
-801
168
443
S198
-1521
168
404
S237
-819
299
444
S197
-1539
299
405
S236
-837
168
445
S196
-1557
168
406
S235
-855
299
446
S195
-1575
299
407
S234
-873
168
447
S194
-1593
168
408
S233
-891
299
448
S193
-1611
299
409
S232
-909
168
449
S192
-1629
168
410
S231
-927
299
450
S191
-1647
299
411
S230
-945
168
451
S190
-1665
168
412
S229
-963
299
452
S189
-1683
299
413
S228
-981
168
453
S188
-1701
168
414
S227
-999
299
454
S187
-1719
299
415
S226
-1017
168
455
S186
-1737
168
416
S225
-1035
299
456
S185
-1755
299
417
S224
-1053
168
457
S184
-1773
168
418
S223
-1071
299
458
S183
-1791
299
419
S222
-1089
168
459
S182
-1809
168
420
S221
-1107
299
460
S181
-1827
299
421
S220
-1125
168
461
S180
-1845
168
422
S219
-1143
299
462
S179
-1863
299
423
S218
-1161
168
463
S178
-1881
168
424
S217
-1179
299
464
S177
-1899
299
425
S216
-1197
168
465
S176
-1917
168
426
S215
-1215
299
466
S175
-1935
299
427
S214
-1233
168
467
S174
-1953
168
428
S213
-1251
299
468
S173
-1971
299
429
S212
-1269
168
469
S172
-1989
168
430
S211
-1287
299
470
S171
-2007
299
431
S210
-1305
168
471
S170
-2025
168
432
S209
-1323
299
472
S169
-2043
299
433
S208
-1341
168
473
S168
-2061
168
434
S207
-1359
299
474
S167
-2079
299
435
S206
-1377
168
475
S166
-2097
168
436
S205
-1395
299
476
S165
-2115
299
437
S204
-1413
168
477
S164
-2133
168
438
S203
-1431
299
478
S163
-2151
299
439
S202
-1449
168
479
S162
-2169
168
440
S201
-1467
299
480
S161
-2187
299
Ver.2.0
8
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
481
S160
-2205
168
521
S120
-2925
168
482
S159
-2223
299
522
S119
-2943
299
483
S158
-2241
168
523
S118
-2961
168
484
S157
-2259
299
524
S117
-2979
299
485
S156
-2277
168
525
S116
-2997
168
486
S155
-2295
299
526
S115
-3015
299
487
S154
-2313
168
527
S114
-3033
168
488
S153
-2331
299
528
S113
-3051
299
489
S152
-2349
168
529
S112
-3069
168
490
S151
-2367
299
530
S111
-3087
299
491
S150
-2385
168
531
S110
-3105
168
492
S149
-2403
299
532
S109
-3123
299
493
S148
-2421
168
533
S108
-3141
168
494
S147
-2439
299
534
S107
-3159
299
495
S146
-2457
168
535
S106
-3177
168
496
S145
-2475
299
536
S105
-3195
299
497
S144
-2493
168
537
S104
-3213
168
498
S143
-2511
299
538
S103
-3231
299
499
S142
-2529
168
539
S102
-3249
168
500
S141
-2547
299
540
S101
-3267
299
501
S140
-2565
168
541
S100
-3285
168
502
S139
-2583
299
542
S99
-3303
299
503
S138
-2601
168
543
S98
-3321
168
504
S137
-2619
299
544
S97
-3339
299
505
S136
-2637
168
545
S96
-3357
168
506
S135
-2655
299
546
S95
-3375
299
507
S134
-2673
168
547
S94
-3393
168
508
S133
-2691
299
548
S93
-3411
299
509
S132
-2709
168
549
S92
-3429
168
510
S131
-2727
299
550
S91
-3447
299
511
S130
-2745
168
551
S90
-3465
168
512
S129
-2763
299
552
S89
-3483
299
513
S128
-2781
168
553
S88
-3501
168
514
S127
-2799
299
554
S87
-3519
299
515
S126
-2817
168
555
S86
-3537
168
516
S125
-2835
299
556
S85
-3555
299
517
S124
-2853
168
557
S84
-3573
168
518
S123
-2871
299
558
S83
-3591
299
519
S122
-2889
168
559
S82
-3609
168
520
S121
-2907
299
560
S81
-3627
299
Ver.2.0
9
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
561
S80
-3645
168
601
S40
-4365
168
562
S79
-3663
299
602
S39
-4383
299
563
S78
-3681
168
603
S38
-4401
168
564
S77
-3699
299
604
S37
-4419
299
565
S76
-3717
168
605
S36
-4437
168
566
S75
-3735
299
606
S35
-4455
299
567
S74
-3753
168
607
S34
-4473
168
568
S73
-3771
299
608
S33
-4491
299
569
S72
-3789
168
609
S32
-4509
168
570
S71
-3807
299
610
S31
-4527
299
571
S70
-3825
168
611
S30
-4545
168
572
S69
-3843
299
612
S29
-4563
299
573
S68
-3861
168
613
S28
-4581
168
574
S67
-3879
299
614
S27
-4599
299
575
S66
-3897
168
615
S26
-4617
168
576
S65
-3915
299
616
S25
-4635
299
577
S64
-3933
168
617
S24
-4653
168
578
S63
-3951
299
618
S23
-4671
299
579
S62
-3969
168
619
S22
-4689
168
580
S61
-3987
299
620
S21
-4707
299
581
S60
-4005
168
621
S20
-4725
168
582
S59
-4023
299
622
S19
-4743
299
583
S58
-4041
168
623
S18
-4761
168
584
S57
-4059
299
624
S17
-4779
299
585
S56
-4077
168
625
S16
-4797
168
586
S55
-4095
299
626
S15
-4815
299
587
S54
-4113
168
627
S14
-4833
168
588
S53
-4131
299
628
S13
-4851
299
589
S52
-4149
168
629
S12
-4869
168
590
S51
-4167
299
630
S11
-4887
299
591
S50
-4185
168
631
S10
-4905
168
592
S49
-4203
299
632
S9
-4923
299
593
S48
-4221
168
633
S8
-4941
168
594
S47
-4239
299
634
S7
-4959
299
595
S46
-4257
168
635
S6
-4977
168
596
S45
-4275
299
636
S5
-4995
299
597
S44
-4293
168
637
S4
-5013
168
598
S43
-4311
299
638
S3
-5031
299
599
S42
-4329
168
639
S2
-5049
168
600
S41
-4347
299
640
S1
-5067
299
Ver.2.0
10
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
641
G1
-5678
299
681
G81
-6398
299
642
G3
-5696
168
682
G83
-6416
168
643
G5
-5714
299
683
G85
-6434
299
644
G7
-5732
168
684
G87
-6452
168
645
G9
-5750
299
685
G89
-6470
299
646
G11
-5768
168
686
G91
-6488
168
647
G13
-5786
299
687
G93
-6506
299
648
G15
-5804
168
688
G95
-6524
168
649
G17
-5822
299
689
G97
-6542
299
650
G19
-5840
168
690
G99
-6560
168
651
G21
-5858
299
691
G101
-6578
299
652
G23
-5876
168
692
G103
-6596
168
653
G25
-5894
299
693
G105
-6614
299
654
G27
-5912
168
694
G107
-6632
168
655
G29
-5930
299
695
G109
-6650
299
656
G31
-5948
168
696
DUMMYA
-6668
168
657
G33
-5966
299
697
G111
-6686
299
658
G35
-5984
168
698
G113
-6704
168
659
G37
-6002
299
699
G115
-6722
299
660
G39
-6020
168
700
G117
-6740
168
661
G41
-6038
299
701
G119
-6758
299
662
G43
-6056
168
702
G121
-6776
168
663
G45
-6074
299
703
G123
-6794
299
664
G47
-6092
168
704
G125
-6812
168
665
G49
-6110
299
705
G127
-6830
299
666
G51
-6128
168
706
G129
-6848
168
667
G53
-6146
299
707
G131
-6866
299
668
G55
-6164
168
708
G133
-6884
168
669
G57
-6182
299
709
G135
-6902
299
670
G59
-6200
168
710
G137
-6920
168
671
G61
-6218
299
711
G139
-6938
299
672
G63
-6236
168
712
G141
-6956
168
673
G65
-6254
299
713
G143
-6974
299
674
G67
-6272
168
714
G145
-6992
168
675
G69
-6290
299
715
G147
-7010
299
676
G71
-6308
168
716
G149
-7028
168
677
G73
-6326
299
717
G151
-7046
299
678
G75
-6344
168
718
G153
-7064
168
679
G77
-6362
299
719
G155
-7082
299
680
G79
-6380
168
720
G157
-7100
168
Ver.2.0
11
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
721
G159
-7118
299
761
DGNDO
-7398.58
-299
722
G161
-7136
168
762
TEST
-7328.58
-299
723
G163
-7154
299
763
VDDIO
-7258.58
-299
724
G165
-7172
168
764
TEST
-7188.58
-299
725
G167
-7190
299
765
TEST
-7118.58
-299
726
G169
-7208
168
766
DGNDO
-7048.58
-299
727
G171
-7226
299
767
SRGB
-6978.58
-299
728
G173
-7244
168
768
SMX
-6908.58
-299
729
G175
-7262
299
769
SMY
-6838.58
-299
730
G177
-7280
168
770
VDDIO
-6768.58
-299
731
G179
-7298
299
771
TEST
-6698.58
-299
732
G181
-7316
168
772
TEST
-6628.58
-299
733
G183
-7334
299
773
TEST
-6558.58
-299
734
G185
-7352
168
774
TEST
-6488.58
-299
735
G187
-7370
299
775
TEST
-6418.58
-299
736
G189
-7388
168
776
DGNDO
-6348.58
-299
737
G191
-7406
299
777
TEST
-6278.58
-299
738
G193
-7424
168
778
TEST
-6208.58
-299
739
G195
-7442
299
779
VDDIO
-6138.58
-299
740
G197
-7460
168
780
DGNDO
-6068.58
-299
741
G199
-7478
299
781
VDDIO
-5998.58
-299
742
G201
-7496
168
782
TPI[0]
-5928.58
-299
743
G203
-7514
299
783
TPI[1]
-5858.58
-299
744
G205
-7532
168
784
TPI[2]
-5788.58
-299
745
G207
-7550
299
785
TPI[3]
-5718.58
-299
746
G209
-7568
168
786
TPO[0]
-5648.58
-299
747
G211
-7586
299
787
TPO[1]
-5578.58
-299
748
G213
-7604
168
788
TPO[2]
-5508.58
-299
749
G215
-7622
299
789
TPO[3]
-5438.58
-299
750
G217
-7640
168
790
TPO[4]
-5368.58
-299
751
G219
-7658
299
791
TPO[5]
-5298.58
-299
752
DUMMYA
-8028.58
-299
792
TPO[6]
-5228.58
-299
753
EXTC
-7958.58
-299
793
TPO[7]
-5158.58
-299
754
VDDIO
-7888.58
-299
794
TEST
-5088.58
-299
755
IM0
-7818.58
-299
795
D17
-5018.58
-299
756
IM1
-7748.58
-299
796
D16
-4948.58
-299
757
IM2
-7678.58
-299
797
D15
-4878.58
-299
758
TEST
-7608.58
-299
798
D14
-4808.58
-299
759
TEST
-7538.58
-299
799
D13
-4738.58
-299
760
AUTO
-7468.58
-299
800
D12
-4668.58
-299
Ver.2.0
12
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
801
D11
-4598.58
-299
841
VDDI
-1798.58
-299
802
D10
-4528.58
-299
842
VDDI
-1728.58
-299
803
D9
-4458.58
-299
843
VDDI
-1658.58
-299
804
DGNDO
-4388.58
-299
844
VDDI
-1588.58
-299
805
D8
-4318.58
-299
845
VDDI
-1518.58
-299
806
D7
-4248.58
-299
846
VDDI
-1448.58
-299
807
D6
-4178.58
-299
847
VCC
-673.45
-299
808
D5
-4108.58
-299
848
VCC
-603.45
-299
809
D4
-4038.58
-299
849
VCC
-533.45
-299
810
D3
-3968.58
-299
850
VCC
-463.45
-299
811
D2
-3898.58
-299
851
VCCO
-393.45
-299
812
D1
-3828.58
-299
852
VDD
88.26
-299
813
D0(SDA)
-3758.58
-299
853
VDD
158.26
-299
814
VDDIO
-3688.58
-299
854
VDD
228.26
-299
815
DGNDO
-3618.58
-299
855
VDD
298.26
-299
816
OSCP
-3548.58
-299
856
VDD
368.26
-299
817
TEP
-3478.58
-299
857
VDD
438.26
-299
818
CSX
-3408.58
-299
858
VDD
508.26
-299
819
RDX
-3338.58
-299
859
VDD
578.26
-299
820
WRX
-3268.58
-299
860
VDD
648.26
-299
821
TEST
-3198.58
-299
861
VDD
718.26
-299
822
TEST
-3128.58
-299
862
GVDD
788.26
-299
823
RESX
-3058.58
-299
863
GVDD
858.26
-299
824
DGNDO
-2988.58
-299
864
C11P
2232.71
-299
825
D/CX(SCI)
-2918.58
-299
865
C11P
2302.71
-299
826
DGNDO
-2848.58
-299
866
C11P
2372.71
-299
827
TEST
-2778.58
-299
867
C11P
2442.71
-299
828
DGNDO
-2708.58
-299
868
C11N
2512.71
-299
829
TEST
-2638.58
-299
869
C11N
2582.71
-299
830
TEST
-2568.58
-299
870
C11N
2652.71
-299
831
TEST
-2498.58
-299
871
C11N
2722.71
-299
832
DGND
-2428.58
-299
872
C12P
2792.71
-299
833
DGND
-2358.58
-299
873
C12P
2862.71
-299
834
DGND
-2288.58
-299
874
C12P
2932.71
-299
835
DGND
-2218.58
-299
875
C12P
3002.71
-299
836
DGND
-2148.58
-299
876
C12N
3072.71
-299
837
DGND
-2078.58
-299
877
C12N
3142.71
-299
838
DGND
-2008.58
-299
878
C12N
3212.71
-299
839
DGND
-1938.58
-299
879
C12N
3282.71
-299
840
VDDI
-1868.58
-299
880
AVDDO
3352.71
-299
Ver.2.0
13
2008-07-07
ST7773
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
881
AVDDO
3422.71
-299
921
VCOML
6222.71
-299
882
AVDDO
3492.71
-299
922
VCOML
6292.71
-299
883
AVDDO
3562.71
-299
923
VGL
6362.71
-299
884
AVDD
3632.71
-299
924
VGL
6432.71
-299
885
AVDD
3702.71
-299
925
VGL
6502.71
-299
886
AVDD
3772.71
-299
926
VGHO
6572.71
-299
887
AVDD
3842.71
-299
927
VGH
6642.71
-299
888
AGND
3912.71
-299
928
VGH
6712.71
-299
889
AGND
3982.71
-299
929
C22P
6782.71
-299
890
AGND
4052.71
-299
930
C22P
6852.71
-299
891
AGND
4122.71
-299
931
C22P
6922.71
-299
892
AGND
4192.71
-299
932
C22N
6992.71
-299
893
AGND
4262.71
-299
933
C22N
7062.71
-299
894
AGND
4332.71
-299
934
C22N
7132.71
-299
895
AGND
4402.71
-299
935
C23P
7202.71
-299
896
AGND
4472.71
-299
936
C23P
7272.71
-299
897
AGND
4542.71
-299
937
C23P
7342.71
-299
898
AGND
4612.71
-299
938
C23N
7412.71
-299
899
AGND
4682.71
-299
939
C23N
7482.71
-299
900
AGND
4752.71
-299
940
C23N
7552.71
-299
901
VCI1
4822.71
-299
941
VREF
8172.06
-299
902
VCI1
4892.71
-299
942
VCOM
8242.06
-299
903
VCI1
4962.71
-299
943
VCOM
8312.06
-299
904
VCI1
5032.71
-299
944
VCOM
8382.06
-299
905
C21P
5102.71
-299
945
VCOM
8452.06
-299
906
C21P
5172.71
-299
946
VCOM
8522.06
-299
907
C21P
5242.71
-299
947
VCOM
8592.06
-299
908
C21N
5312.71
-299
909
C21N
5382.71
-299
910
C21N
5452.71
-299
911
VCLO
5522.71
-299
912
VCL
5592.71
-299
913
VCL
5662.71
-299
914
VCL
5732.71
-299
915
VCOMH
5802.71
-299
916
VCOMH
5872.71
-299
917
VCOMH
5942.71
-299
918
VCOMH
6012.71
-299
919
VCOML
6082.71
-299
920
VCOML
6152.71
-299
Ver.2.0
14
2008-07-07
ST7773
G1~G220
VCI1
GVDD
VREF
S1~S528
5. Block diagram
220 Gate buffer
Voltage reference
528 Source buffer
Level shifter
DAC
Gamma circuit
Gate decoder
Level Shifter
Data Latch
Gamma Table
Vcom generator
VCOMH
VCOM
VCOML
Display Ram
176 x 220 x 18bits
Display control
OSC
C11P
Color conversion
LUT table
C11N
Instruction
register
eeprom
C12P
C12N
Booster 1/2/4
C21P
C21N
C22P
C22N
MCU IF
C23P
C23N
VDD
VDDI
AVDD
VCL
VGH
VGL
SMY
SMX
EXTC
IM [2:0]
DC/X (SCL)
CSX
RDX
WRX
GS
SRGB
D[17:0]
Ver. 2.0
15
2008-07-07
ST7773
6. Pin description
6.1 Power supply pin
Name
VDD
VDDI
AGND
DGND
I/O
I
I
I
I
Description
Power supply for analog, digital system and booster circuit.
Power supply for I/O system.
System ground for analog system and booster circuit.
System ground for I/O system and digital system.
Count
Connect pin
VDD
VDDI
GND
GND
6.2 Interface logic pin
Name
I/O
IM2
I
Description
Count
Connect pin
1
DGND/VDDI
2
DGND/VDDI
1
MCU
1
MCU
1
MCU
1
MCU
1
MCU
1
-
18
MCU
1
MCU
MCU Parallel interface bus and Serial interface select
IM2=’1’, Parallel interface
IM2=’0’, Serial interface.
- MCU parallel interface type selection
-If not used, please fix this pin at VDDI or DGND level.
IM1,IM0
I
RESX
I
CSX
I
D/CX
(SCI)
I
IM1
IM0
Parallel interface
0
0
MCU 8-bit parallel
0
1
MCU 16-bit parallel
1
0
MCU 9-bit parallel
1
1
MCU 18-bit parallel
-This signal will reset the device and it must be applied to properly initialize
the chip.
-Signal is active low.
-Chip selection pin (“Low” is enable).
-Display data/command selection pin in MCU interface.
-D/CX=’1’: display data or parameter.
-D/CX=’0’: command data.
-In serial interface, this is used as SCL.
-Read enable in 8080 MCU parallel interface.
-If not used, please connect this pin to VDDI or DGND.
-Write enable in MCU parallel interface.
WRX
I
-If not used, please connect this pin to VDDI or DGND.
-Monitoring pin of internal oscillator clock and is turned ON/OFF by S/W
command.
OSC
O
-When this pin is inactive (function OFF), this pin is DGND level.
-If not used, please open this pin.
-D[17:0] are used as MCU parallel interface data bus.
-D0 is the serial input/output signal in serial interface mode.
D[17:0]
I/O
-In serial interface, D[17:1] are not used and should be connected to VDDI
or DGND.
-Tearing effect output pin to synchronies MCU to frame rate, activated by
S/W command.
TE
O
-When this pin is inactive, this pin is DGND level.
-If not used, please open this pin.
Note1. When in parallel mode, no use data pin must be connected to “1” or “0”.
Note2.When CSX=”1”,there is no influence to the paraller and serial interface.
Note3. “1” =”HIGH”= VDDI level, “0” =”LOW”= DGND level.
RDX
Ver. 2.0
I
16
2008-07-07
ST7773
6.3 Mode selection pin
Name
I/O
EXTC
I
SRGB
I
SMX
I
SMY
I
AUTO
I
Ver. 2.0
Description
-To use extended command set, please connect this pin to VDDI.
-During normal operation, please open this pin (internal Rpull-down=2MΩ).
EXTC
Enable/disable modification of extend command
0
Only use default command set
1
Use extended command set
-RGB arrangement selection pin for color filter design.
SRGB
RGB arrangement
S1, S2, S3 filter order = ’R’, ’G’, ’B’
0
S1, S2, S3 filter order = ‘B’, ‘G’, ‘R’
1
-Scanning direction of source output selection pin.
SMX
Scanning direction of source output
0
S1->S528
1
S528->S1
-Scanning direction of gate output selection pin.
SMY
Scanning direction of gate output
0
G1->G220
1
G220->G1
-Please connect this pin to VDDI.
17
Count
Connect pin
1
VDDI/DGND
1
VDDI/DGND
1
VDDI/DGND
1
VDDI/DGND
1
VDDI
2008-07-07
ST7773
6.4 Driver output pin
Name
S1 to
S528
G1 to
G220
I/O
VCI1
I/O
AVDD
I
AVDDO
O
VCL
I
VCLO
O
VGH
I
VGHO
O
VGL
I
VREF
O
GVDD
O
VCOMH
O
VCOML
O
VCOM
O
C11P,
C11N
C12P,
C12N
C21P,
C21N
C22P,
C22N
C23P,
C23N
VDDIO
DGNDO
VCCO
Description
Count
Connect pin
O
- Source driver output pins.
528
-
O
- Gate driver output pins.
220
-
4
Capacitor
4
AVDDO
4
Capacitor
3
VCLO
1
Capacitor
2
VGHO
1
Capacitor
3
VGLO
1
Capacitor
2
Capacitor
4
Capacitor
4
Capacitor
- A power supply for the TFT-LCD common electrode.
6
Common
electrode
O
- Capacitor connecting pins for step-up circuit 1 (for AVDDO)
16
Step-up
Capacitor
O
- Capacitor connecting pins for step-up circuit 2 and 4 (for VGHO,
VGLO, VCLO)
18
Step-up
Capacitor
6
9
-
5
Capacitor
- A reference voltage for step-up circuit 1.
- Connect a capacitor for stabilization.
- Power input pin for analog circuits.
- In normal usage, connect it to AVDDO.
- Output of step-up circuit 1
- Connect a capacitor for stabilization.
- Power input pin for VCOM circuit.
- In normal usage, connect it to VCLO.
- A power output pin of step-up circuit 4.
- When VCOML is higher than AGND, VCLO=AGND.
- Connect a capacitor for stabilization.
- Power input pin for gate driver circuit.
- In normal usage, connect it to VGHO.
- Positive output pin of the step-up circuit 2.
- Connect a capacitor for stabilization.
- Power input pin for gate driver circuit.
- Negative output of the step-up circuit 2 is connected inside the driver.
- Connect a capacitor for stabilization.
- A reference voltage for power system.
- Connect a capacitor for stabilization.
- A power output of grayscale voltage generator.
- Connect a capacitor for stabilization.
- When internal GVDD generator is not used, connect an external
power supply (AVDD-0.5V) to this pin.
- Positive voltage output of VCOM.
- Connect a capacitor for stabilization.
- Negative voltage output of VCOM.
- Connect a capacitor for stabilization.
O
O
-VDDI voltage output level for monitoring.
-DGND voltage output level for monitoring.
-Monitoring pin of internal digital reference voltage.
-Connect a capacitor for stabilization.
O
6.5 Test pin
Name
TEST
TPI[3]~[0]
TPO[7]~[0]
I/O
I
I
O
Dummy
-
Ver. 2.0
Description
-Please connect this pin to DGND
-Please open these pins.
-Please open these pins.
-These pins are dummy (have no function inside).
-Can allow signal traces pass through these pads on TFT glass.
18
Count
19
4
8
Connect pin
DGND
Open
Open
4
Open
2008-07-07
ST7773
7. Driver electrical characteristics
7.1 Absolute operation range
Item
Symbol
Rating
Unit
Supply voltage
VDD
- 0.3 ~ +4.6
V
Supply voltage (Logic)
VDDI
- 0.3 ~ +4.6
V
Supply voltage (Digital)
VCC
-0.3 ~ +4.6
V
Driver supply voltage
VGH-VGL
-0.3 ~ +30.0
V
Logic input voltage range
VIN
0.3 ~ VDDI + 0.3
V
Logic output voltage range
VO
0.3 ~ VDDI + 0.3
V
Operating temperature range
TOPR
-30 ~ +85
℃
Storage temperature range
TSTG
-40 ~ +125
℃
Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be
degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be
physically damaged. Be sure to use the product within the recommend range.
7.2 DC characteristic
Parameter
Symbol
Condition
Min
Specification
TYP
Max
Power & operation voltage
System voltage
VDD
Operating voltage
2.7
2.8
Interface operation
VDDI
I/O supply voltage
1.6
1.8
voltage
Gate driver high voltage
VGH
10
Gate driver low voltage
VGL
-13
Gate driver supply
| VGH-VGL |
15.5
voltage
Input / Output
Logic-high input voltage
VIH
0.7VDDI
Logic-low input voltage
VIL
VSS
Logic-high output voltage
VOH
IOH = -1.0mA
0.8VDDI
Logic-low output voltage
VOL
IOL = +1.0mA
VSS
Input leakage current
IIL
IOH = -1.0mA
-1
VCOM voltage
VCOM high voltage
VCOMH
Ccom=22nF
2.5
VCOM low voltage
VCOML
Ccom=22nF
-2.5
VCOM amplitude
VCOMAC
|VCOMH-VCOML|
4.0
Source driver
Gamma reference
GVDD
3.0
voltage
Source output settling
Below with 99%
Tr
25
time
precision
Output offset voltage
VOFSET
Note 1: VDDI=1.6 to 3.3V, VDD=2.7 to 3.3V, AGND=DGND=0V, TA=-25 ℃
Note 2, Source channel loading= 10pF/channel, Gate channel loading=50pF/channel.
Note 3, The Max. value is between measured point of gamma setting value.
Related
Pins
Unit
3.3
V
3.3
V
16
-5.5
V
V
29.0
V
VDDI
0.3VDDI
VDDI
0.2VDDI
+1
V
V
V
V
uA
5.0
0.0
6.0
V
V
V
5.0
V
30
us
Note 2
35
mV
Note 3
Note 1
Note 1
Note 1
Note 1
Note 1
7.3 Power consumption
Ta=25℃, Frame rate = 60Hz, the registers setting are IC default setting.
Operation mode
Current consumption
Typical
Maximum
IDD+IDDI
IDD+IDDI
(mA)
(mA)
Inversion
mode
Image
One Line
Note 1
2.2
3.0
One Line
Note 2
2.2
3.0
Note 1
1.3
1.6
Note 2
1.3
1.6
N/A
0.015
0.025
-Normal mode
-Partial + Idle mode (40 lines)
-Sleep-in mode
One Line
N/A
Typical case:
TA = 25 ℃
VDD = 2.8 V
VDDI = 1.8 V
Notes:
1. All pixels black.
2. All pixels white.
Ver. 2.0
19
Worst case:
TA = 25 ℃
VDD = 2.7~3.3V
VDDI = 1.6~3.3V
2008-07-07
ST7773
8. Timing chart
8.1 Parallel interface characteristics(8080-series MCU interface): 18, 16, 9 or 8-bits bus
Fig. 8.1.1 Parallel interface timing characteristics (8080-series MCU interface)
Signal
Symbol
Parameter
Min
TAST
Address setup time
10
D/CX
TAHT
Address hold time (Write/Read)
15
TCHW
Chip select “H” pulse width
0
TCS
Chip select setup time (Write)
30
TRCS
Chip select setup time (Read ID)
150
CSX
TRCSFM
Chip select setup time (Read FM)
250
TCSF
Chip select wait time (Write/Read)
10
TCSH
Chip select hold time
10
TWC
Write cycle
100
WRX
TWRH
Control pulse “H” duration
40
TWRL
Control pulse “L” duration
30
TRC
Read cycle (ID)
160
RDX (ID)
TRDH
Control pulse “H” duration (ID)
40
TRDL
Control pulse “L” duration (ID)
100
TRCFM
Read cycle (FM)
400
RDX (FM)
TRDHFM
Control pulse “H” duration (FM)
40
TRDLFM
Control pulse “L” duration (FM)
300
TDST
Data setup time
10
TDHT
Data hold time
15
D[17:0]
TRAT
Read access time (ID)
TRATFM
Read access time (FM)
TODH
Output disable time
45
Note 1: VDDI=1.6 to 3.3V, VDD=2.7 to 3.3V, AGND=DGND=0V, Ta= 25 ℃
Ver. 2.0
20
Max
100
100
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
-
-(3-transfer for one pixel)
10MHz
When read ID data
When read from frame
memory
For maximum CL=30pF
2008-07-07
ST7773
Fig. 8.1.2 Rising and falling timing for input and output signal
Fig.8.1.3 Chip selection (CSX) timing
Fig. 8.1.4 Write-to-read and read-to-write timing
NOTE: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are
specified as 30% and 70% of VDDI for Input signals.
Ver. 2.0
21
2008-07-07
ST7773
8.3 Serial interface characteristics (3-line serial)
CSX
VIH
TCHW
VIL
TSCYCW/TSCYCR
TCSH
TCSS
TSLW/TSLR
SCL
TSHW/TSHR
TSDS
SDA
TSCC
VIH
VIL
TSDH
VIH
VIL
TOH
TACC
VIH
VIL
VIH
SDA
(DOUT)
VIL
Fig. 8.3.1 3-line serial interface timing
Signal
CSX
SCL
SDA
(DIN)
(DOUT)
Symbol
TCSS
TCSH
TSCC
TCHW
TSCYCW
TSHW
TSLW
TSCYCR
TSHR
TSLR
TSDS
TSDH
TACC
TOH
Parameter
Min
Max
Chip select setup time
60
Chip select hold time
60
Chip select setup time
10
Chip select hold time
10
Serial clock cycle (Write)
65
SCL “H” pulse width (Write)
20
SCL “L” pulse width (Write)
40
Serial clock cycle (Read)
150
SCL “H” pulse width (Read)
60
SCL “L” pulse width (Read)
80
Data setup time
10
Data hold time
15
Access time
80
Output disable time
45
80
Table 8.3: 3-line Serial Interface Characteristics
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
For maximum CL=30pF
Note 1: VDDI=1.6 to 3.3V, VDD=2.7 to 3.3V, AGND=DGND=0V, Ta=25℃
Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are
specified as 30% and 70% of VDDI for Input signals.
Ver. 2.0
22
2008-07-07
ST7773
9. Function description
9.1 Interface type selection
The selection of given interfaces are done by setting IM2, IM1, and IM0 pins as shown in following table.
Table 9.1.1 Selection of MCU interface
IM2
IM1
IM0
Interface
0
3-line serial interface
1
0
0
8080 MCU 8-bit parallel
1
0
1
8080 MCU 16-bit parallel
1
1
0
8080 MCU 9-bit parallel
1
1
1
8080 MCU 18-bit parallel
Read back selection
Via the read instruction
RDX strobe (8-bit read data and 8-bit read parameter)
RDX strobe (16-bit read data and 8-bit read parameter)
RDX strobe (9-bit read data and 8-bit read parameter)
RDX strobe (18-bit read data and 8-bit read parameter)
Table 9.1.2 Pin connection according to various MCU interface
IM2 IM1 IM0
Interface
RDX
WRX
0
3-line serial interface
Note1 Note1
1
0
0
8080 8-bit parallel
RDX
WRX
1
0
1
8080 16-bit parallel
RDX
WRX
1
1
0
8080 9-bit parallel
RDX
WRX
1
1
1
8080 18-bit parallel
RDX
WRX
D/CX
SCL
D/CX
D/CX
D/CX
D/CX
Read back selection
D[17:1]: unused, D0: SDA
D[17:8]: unused, D7-D0: 8-bit data
D[17:16]: unused, D15-D0: 16-bit data
D[17:9]: unused, D8-D0: 9-bit data
D17-D0: 18-bit data
Note 1. Unused pins must be connected to DGND or VDDI.
9.2 Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write
cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit
is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is
low (=’0’) and vice versa it is data (=’1’).
Fig. 9.2.1 8080-series WRX protocol
Note: WRX is an unsynchronized signal (It can be stopped).
Ver. 2.0
23
2008-07-07
ST7773
Fig. 9.2.2 8080-series parallel bus protocol, write to register or display RAM
9.3 Read cycle sequence
The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The
driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising
edge of RDX.
Fig. 9.2.3 8080-series RDX protocol
Note: RDX is an unsynchronized signal (It can be stopped).
Ver. 2.0
24
2008-07-07
ST7773
Read parameter
D[17:0]
Read display data
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
D[17:0]
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
Host D[17:0]
Host to LCD
S
CMD
Driver D[17:0]
LCD to Host
S
RESX “1”
CSX
D/CX
RDX
WRX
Hi-Z
Hi-Z
DM
CMD
PA1
Hi-Z
Hi-Z
P
DM & data
PAN-2
PAN-1
P
Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.
CMD: write command code
PA: parameter or display data
Fig. 9.2.4 8080-series parallel bus protocol, read data from register or display RAM
Ver. 2.0
25
2008-07-07
ST7773
9.4 Serial interface
The selection of this interface is done by IM2=”Low”.
The serial interface is either 3-lines/9-bits bi-directional interface for communication between the micro controller and the
LCD driver. The 3-lines serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output), Serial
clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary.
9.4.1 Command Write Mode
The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data
packet contains a control bit D/CX and a transmission byte. Any instruction can be sent in any order to the driver. The MSB
is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no
effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission.
Transmission byte (TB) may be command or data
D/CX
D7
D6
D5
D4
D3
D2
D1
TB
D/CX
D7
D6
D5
D4
D0
TB
D3
D2
D1
D0
D/CX
D7
D6
D5
D4
D3
D2
D1
D0
Fig. 9.4.1 Serial interface data stream format
When CSX is “high”, SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling edge
of CSX, SCL can be high or low (see Fig 9.4.2). SDA is sampled at the rising edge of SCL. D/CX indicates whether the byte
is command (D/CX=’0’) or parameter/RAM data (D/CX=’1’). D/CX is sampled when first rising edge of SCL. If CSX stays
low after the last bit of command/data byte, the serial interface expects the D/CX bit of the next byte at the next rising edge
of SCL.
Fig. 9.4.2 3-line serial interface write protocol (write to register with control bit in transmission)
9.4.2 Read Functions
The read mode of the interface means that the micro controller reads register value from the driver. To achieve read
function, the micro controller first has to send a command (read ID or register command) and then the following byte is
transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below
figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of
SCL. Thus the micro controller is supported to read at the rising edge of SCL.
After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL
of the last bit.
Serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
Ver. 2.0
26
2008-07-07
ST7773
Serial protocol (for RDDID command: 24-bit read)
Serial Protocol (for RDDST command: 32-bit read)
Fig. 9.4.4 3-line serial interface read protocol
Ver. 2.0
27
2008-07-07
ST7773
9.5 Data Transfer Break and Recovery
If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple
parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have
reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next
activated after RESX have been HIGH state. See the following example
Host
(MCU to driver)
Fig. 9.5.1 Serial bus protocol, write mode – interrupted by RESX
If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple
parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have
reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next
activated. See the following example
Fig. 9.5.2 Serial bus protocol, write mode – interrupted by CSX
If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one
and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the
parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is
ready to receive next byte as shown below.
Fig.9.5.3 Write interrupts recovery (serial interface)
Ver. 2.0
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2008-07-07
ST7773
If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent,
then the parameters that were successfully sent are stored and the other parameter of that command remains previous
value.
Fig. 9.5.4 Write interrupts recovery (both serial and parallel Interface)
9.6 Data transfer pause
It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the
data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data
has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the
point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then
the display module will receive either the command‘s parameters (if appropriate) or a new command when the chip select
line is next enabled as shown below.
This applies to the following 4 conditions:
1) Command-Pause-Command
2) Command-Pause-Parameter
3) Parameter-Pause-Command
4) Parameter-Pause-Parameter
9.6.1 Serial interface pause
Fig. 9.6.1 Serial interface pause protocol (pause by CSX)
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2008-07-07
ST7773
9.6.2 Parallel interface pause
Fig. 9.6.2 Parallel bus pause protocol (paused by CSX)
9.7 Data Transfer Modes
The module has three kinds color modes for transferring data to the display RAM. These are 12-bits color per pixel, 16-bits
color per pixel and 18-bits color per pixel. The data format is described for each interface. Data can be downloaded to the
frame memory by 2 methods.
9.7.1 Method 1
The Image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame
memory pointer is reset to the start point and the next frame is written.
9.7.2 Method 2
Image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write. Then
start memory write command is sent, and a new frame is downloaded.
Note:
1) These apply to all data transfer Color modes on both serial and parallel interfaces.
2) The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be
stored in the frame memory.
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9.8 Data Color Coding
9.8.1 8-bit Parallel Interface (IM2, IM1, IM0= “100”)
Different display data formats are available for three Colors depth supported by listed below.
- 4k Colors, RGB 4,4,4-bit input,
- 65k Colors, RGB 5,6,5-bit input,.
- 262k Colors, RGB 6,6,6-bit input,
9.8.1.1 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h”
There are 2 pixels (6 sub-pixels) per 3-bytes.
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue
data.
Note 2. 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to '0' or '1'
Ver. 2.0
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ST7773
9.8.1.2 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h”
There is 1 pixel (3 sub-pixels) per 2-bytes.
RESX
IM[2:0]
“1”
“100”
CSX
D/CX
WRX
RDX
R/WX
“1”
8080-series control pins
“0”
E
6800-series control pins
D7
0
R1, Bit 4
G1, Bit 2
R2, Bit 4
G2, Bit 2
D6
0
R1, Bit 3
G1, Bit 1
R2, Bit 3
G2, Bit 1
D5
1
R1, Bit 2
G1, Bit 0
R2, Bit 2
G2, Bit 0
D4
0
R1, Bit 1
B1, Bit 4
R2, Bit 1
B2, Bit 4
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n
Pixel n+1
16 bits
16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4,
LSB=Bit 0 for Red and Blue data.
Note 2.2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to '0' or '1'
Ver. 2.0
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ST7773
9.8.1.3 8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h”
There is 1 pixel (3 sub-pixels) per 3-bytes.
RESX
IM[2:0]
“1”
“100”
CSX
D/CX
WRX
RDX
R/WX
“1”
8080-series control pins
“0”
E
6800-series control pins
D7
0
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
D6
0
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
D5
1
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
D4
0
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
D3
1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
D2
1
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
-
Pixel n
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue
data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to '0' or '1'
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ST7773
9.8.2 16-Bit Parallel Interface (IM2,IM1, IM0= “101”)
Different display data formats are available for three colors depth supported by listed below.
- 4k colors, RGB 4,4,4-bit input
- 65k colors, RGB 5,6,5-bit input
- 262k colors, RGB 6,6,6-bit input
9.8.2.1 16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h”
There is 1 pixel (3 sub-pixels) per 1 bytes, 12-bit/pixel.
Note1. The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue
data.
Note 2.1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.
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9.8.2.2 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h”
There is 1 pixel (3 sub-pixels) per 1 bytes, 16-bit/pixel.
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit
4, LSB=Bit 0 for Red and Blue data.
Note 2.1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to '0' or '1'
Ver. 2.0
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9.8.2.3 16-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h”
There are 2 pixel (6 sub-pixels) per 3 bytes, 18-bit/pixel.
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and
Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to '0' or '1'
Ver. 2.0
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2008-07-07
ST7773
9.8.3 9-Bit Parallel Interface (IM2, IM1, IM0=“110”)
Different display data formats are available for three colors depth supported by listed below.
- 262k colors, RGB 6,6,6-bit input
RESX
IM[2:0]
“1”
“110”
CSX
D/CX
WRX
RDX
R/WX
“1”
8080-series control pins
“0”
E
6800-series control pins
D8
-
R1, Bit 5
G1, Bit 2
R2, Bit 5
G2, Bit 2
D7
0
R1, Bit 4
G1, Bit 1
R2, Bit 4
G2, Bit 1
D6
0
R1, Bit 3
G1, Bit 0
R2, Bit 3
G2, Bit 0
D5
1
R1, Bit 2
B1, Bit 5
R2, Bit 2
B2, Bit 5
D4
0
R1, Bit 1
B1, Bit 4
R2, Bit 1
B2, Bit 4
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
Pixel n
B2, Bit 0
Pixel n+1
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue
data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to '0' or '1'
Ver. 2.0
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ST7773
9.8.4 18-Bit Parallel Interface (IM2, IM1, IM0=“111”)
Different display data formats are available for three colors depth supported by listed below.
- 4k colors, RGB 4,4,4-bit input
- 65k colors, RGB 5,6,5-bit input
- 262k colors, RGB 6,6,6-bit input.
9.8.4.1 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”
There are 1 pixel (3 sub-pixels) per 1 byte, 12-bit/pixel.
RESX
IM[2:0]
“1”
“111”
CSX
D/CX
WRX
RDX
R/WX
“1”
8080-series control pins
“0”
E
6800-series control pins
D17
-
-
-
-
-
D16
-
-
-
-
-
D15
-
-
-
-
-
D14
-
-
-
-
-
D13
-
-
-
-
-
D12
-
-
-
-
-
D11
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D10
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D9
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D8
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D7
0
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D6
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D5
1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D4
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
12 bits
12 bits
Look-Up Table for 4096 Color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1
Ver. 2.0
G1
B1
R2
38
G2
B2
R3
G3
B3
2008-07-07
ST7773
Note1. The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue
data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information.
9.8.4.2 18-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”
There are 1 pixel (3 sub-pixels) per 1 byte, 16-bit/pixel.
RESX
IM[2:0]
“1”
“111”
CSX
D/CX
WRX
RDX
R/WX
“1”
8080-series control pins
“0”
E
6800-series control pins
D17
-
-
-
-
-
D16
-
-
-
-
-
D15
-
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
D14
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D13
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D12
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D11
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D10
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D9
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D8
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D7
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D6
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D5
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
16 bits
16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit
4, LSB=Bit 0 for Red and Blue data.
Ver. 2.0
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2008-07-07
ST7773
Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.
9.8.4.3 18-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”
There are 1 pixel (3 sub-pixels) per 1 bytes, 18-bit/pixel.
RESX
IM[2:0]
“1”
“111”
CSX
D/CX
WRX
RDX
R/WX
“1”
8080-series control pins
“0”
E
6800-series control pins
D17
-
R1, Bit 5
R2, Bit 5
R3, Bit 5
R4, Bit 5
D16
-
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
D15
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D14
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D13
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
D12
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
D11
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
D10
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
D9
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D8
-
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D7
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D6
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D5
1
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
18 bits
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note1. The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and
Blue data.
Note 2.1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.
N
Ver. 2.0
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2008-07-07
ST7773
9.8.5 3-line serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input
9.8.5.1 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”
Note 1. pixel data with the 12-bit color depth information
Note 2. The most significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
9.8.5.2 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”
Note 1. pixel data with the 16-bit color depth information
Note 2. The most significant bits are: Rx4, Gx5 and Bx4
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Ver. 2.0
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2008-07-07
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9.8.5.3 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”
Note 1. pixel data with the 18-bit color depth information
Note 2. The most significant bits are: Rx5, Gx5 and Bx5
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Ver. 2.0
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2008-07-07
ST7773
9.9 Display Data RAM
9.9.1 Configuration
The display module has an integrated 176x220x18-bit graphic type static RAM. This 696,960-bit memory allows to store
on-chip a 176xRGBx220 image with an 18-bpp resolution (262K-color).
There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or
Write to the same location of the Frame Memory.
Fig. 9.9.1 Display data RAM organization
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2008-07-07
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9.9.2 Memory to Display Address Mapping
1
2
3
4
5
6
7
8
|
|
|
|
|
213
214
215
216
217
218
219
220
G0
B0
R1
G1
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0
175
S6 -------- S523 S524 S525 S526 S527 S528
1
174
RGB
Order
RGB=1
S5
RGB=0
S4
Pixel 176
RGB=1
RA
MY=' 0 ' MY=' 1 '
0
219
R0
1
218
2
217
3
216
4
215
5
214
6
213
7
212
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
212
7
213
6
214
5
215
4
216
3
217
2
218
1
219
0
MX=' 0 '
CA
MX=' 1 '
S3
Pixel 175
--------
RGB=0
S2
RGB=0
S1
RGB=1
Source Out
RGB=0
Gate Out
Pixel 2
RGB=1
Pixel 1
SA
ML=' 0 ' ML=' 1 '
B1 -------- R174 G174 B174 R175 G175 B175
0
219
-------1
218
-------2
217
-------3
216
-------4
215
-------5
214
-------6
213
-------7
212
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-------212
7
-------213
6
-------214
5
-------215
4
-------216
3
-------217
2
-------218
1
-------219
0
174
175
-------1
0
--------
Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
MX =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
Ver. 2.0
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2008-07-07
ST7773
9.9.3 Normal Display On or Partial Mode On, Vertical Scroll Off
In this mode, contents of the frame memory within an area where column pointer is 00h to AFh and page pointer is 00h to
DBh is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
1). Example for Normal Display On (MX=MY=ML=’0’ ,SMX=SMY=’0’)
Scan
176 Columns
176 Columns
Order
00h
00
10
20
30
40
50
60
01h ---- ---- A6h A7h
01
11
21
31
41
51
---0Y
1Y
2Y
3Y
4Y
5Y
AFh
0Z
1Z
2Z
3Z
4Z
5Z
6Z
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
DAh
DBh
1
2
3
|
|
|
|
|
|
176 x 220 x18bit
Frame RAM
|
|
|
|
X0 X1 X2
XX XY XZ 218
Y0 Y1 Y2 Y3 YW YX YY YZ 219
Z0 Z1 Z2 Z3 ZW ZX ZY ZZ 220
00
10
20
30
40
50
60
01
11
21
31
41
51
0Y
1Y
2Y
3Y
4Y
5Y
0Z
1Z
2Z
3Z
4Z
5Z
6Z
G1
G2
G3
|
|
|
|
|
|
176 x 220 x18bit
LCD Panel
|
|
|
|
X0 X1 X2
XX XY XZ G218
Y0 Y1 Y2 Y3 YW YX YY YZ G219
Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G220
Display area =220 lines
220 Lines
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
DAh
DBh
2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=D7h, MX=MV=ML=’0’ ,SMX=SMY=’0’)
Scan
176 Columns
176 Columns
Order
220 Lines
Ver. 2.0
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
DAh
DBh
00h
00
10
20
30
40
50
60
U0
V0
W0
X0
Y0
Z0
01h ---- ---- A6h A7h
01
11
21
31
41
51
---0Y
1Y
2Y
3Y
4Y
5Y
AFh
0Z
1Z
2Z
3Z
4Z
5Z
6Z
00
10
20
30
40
50
60
1
2
3
|
|
|
|
|
|
176 x 220 x18bit
Fram e RAM
|
U1
UY UZ
|
V1
VX VY VZ
|
W1 W2
WX WY WZ
|
X1 X2
XX XY XZ 218
Y1 Y2 Y3 YW YX YY YZ 219
Z1 Z2 Z3 ZW ZX ZY ZZ 220
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 1X 1Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z
1Z
2Z
3Z
4Z
5Z
6Z
176RGB x 220
LCD Panel
S0
U0
V0
W0
X0
Y0
Z0
45
U1
V1
W1
X1
Y1
Z1
V2
W2
X2
Y2 Y3
Z2 Z3
VX
WX
XX
YW YX
ZW ZX
UY
VY
WY
XY
YY
ZY
SZ
UZ
VZ
WZ
XZ
YZ
ZZ
G1
G2
G3
|
|
|
|
|
|
|
|
|
|
|
|
G218
G219
G220
Non-Display
area =4 lines
Display area
=212 lines
Non-Display
area =4 lines
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ST7773
9.9.4 Vertical Scroll Mode
There is vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and Vertical Scrolling
Start Address” (37h).
Fig. 9.9.2 Difference between Scrolling and original
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=220. In this case, scrolling is applied as shown below.
1). Example for TFA =3, VSA=215, BFA=2, SSA=4, ML=0: Scrolling
176 Columns
176 Columns
Scan
Order
220 Lines
Ver. 2.0
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
00h
00
10
20
30
40
50
60
S0
U0
V0
W0
X0
Y0
Z0
01h
01
11
21
31
41
51
U1
V1
W1
X1
Y1
Z1
---- ---- ---- ---- ---- AEh AFh
02 03
0W 0X 0Y 0Z 1
12 13
1W 1X 1Y 1Z 2
22
2X 2Y 2Z 3
32
3X 3Y 3Z |
42
4X 4Y 4Z |
5Y 5Z |
6Z |
|
|
176 x 220 x18 bit
Fram e RAM
|
|
SZ |
UY UZ |
V2
VX VY VZ |
W2
WX WY WZ |
X2
XX XY XZ 218
Y2 Y3
YW YX YY YZ 219
Z2 Z3
ZW ZX ZY ZZ 220
SSA
00
10
20
40
50
60
01
11
21
41
51
02 03
12 13
22
42
0W 0X 0Y
1W 1X 1Y
2X 2Y
4X 4Y
5Y
0Z
1Z
2Z
4Z
5Z
6Z
176R G B x 220
LCD Panel
S0
U0
V0
W0
X0
30
Y0
Z0
46
U1
V1
W1
X1
31
Y1
Z1
V2
W2
X2
32
Y2 Y 3
Z2 Z 3
VX
WX
XX
3X
YW YX
ZW ZX
UY
VY
WY
XY
3Y
YY
ZY
SZ
UZ
VZ
WZ
XZ
3Z
YZ
ZZ
G1
G2
G3
|
|
|
|
|
|
|
|
|
|
|
|
G218
G219
G220
TFA
VSA
BFA
2008-07-07
ST7773
2). Example for TFA =3, VSA=215, BFA=2, SSA=215, ML=1: Scrolling: TFA and BFT are exchanged
176 Columns
Scan
176 Columns
Order
220 Lines
Ver. 2.0
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
00h
00
10
20
30
40
50
60
S0
U0
V0
W0
X0
Y0
Z0
01h
01
11
21
31
41
51
U1
V1
W1
X1
Y1
Z1
---- ---- ---- ---- ---- AEh AFh
02 03
0W 0X 0Y 0Z 220
12 13
1W 1X 1Y 1Z 219
22
2X 2Y 2Z 218
32
3X 3Y 3Z |
42
4X 4Y 4Z |
5Y 5Z |
6Z |
|
|
176 x 220 x18 bit
Fram e RAM
|
|
SZ |
UY UZ |
V2
VX VY VZ |
W2
WX WY WZ |
X2
XX XY XZ 3
Y2 Y3
YW YX YY YZ 2
Z2 Z3
ZW ZX ZY ZZ 1
00
10
60
70
80
90
A0
01
11
61
71
81
02 03
12 13
62
72
82
0W 0X 0Y
1W 1X 1Y
6X 6Y
7X 7Y
8X 8Y
0Z
1Z
6Z
7Z
8Z
9Z
AZ
176R G B x 220
SSA
LCD Panel
20
30
40
50
X0
Y0
Z0
47
21
31
41
51
X1
Y1
Z1
22
32
42
X2
Y 2 Y3
Z 2 Z3
2X 2Y 2Z
3X 3Y 3Z
4X 4Y 4Z
5Y 5Z
XX X Y XZ
YW YX Y Y YZ
ZW ZX Z Y ZZ
G1
G2
G3
|
|
|
|
|
|
|
|
|
|
|
|
G218
G219
G220
2008-07-07
BFA
VSA
TFA
ST7773
9.9.5 Vertical Scroll Example
There are 2 types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and
“Vertical Scrolling Start Address” (37h).
Case 1: TFA + VSA + BFA≠220
N/A. Do not set TFA + VSA + BFA≠220. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA=220 (Scrolling)
Example1) When MADCTL parameter ML=”0”, TFA=0, VSA=220, BFA=0 and VSCSAD=80.
Example2) When MADCTL parameter ML=”1”, TFA=30, VSA=190, BFA=0 and VSCSAD=80.
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9.10 Address Counter
The address counter sets the addresses of the display data RAM for writing and reading.
Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit),
according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM.
The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=175 (AFh) and Y=0 to
Y=219 (DBh). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that
will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE
designating the end address.
For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h)
and XE=175(AFh), YE=219 (DBh).
In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps
around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address
increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next
row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS).
For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and ”MADCTL” (see
section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All
combinations of flags are allowed. Section 9.12 show the available combinations of writing to the display RAM. When MX,
MY and MV will be changed the data bust be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as section 9.11 below:
Condition
Column Counter
Return to “Start
When RAMWR/RAMRD command is accepted
Column (XS)”
Complete Pixel Read / Write action
Increment by 1
Return to “Start
The Column counter value is larger than “End Column (XE)”
Column (XS)”
The Column counter value is larger than “End Column (XE)” and
Return to “Start
the Row counter value is larger than “End Row (YE)”
Column (XS)”
Ver. 2.0
49
Row Counter
Return to “Start
Row (YS)”
No change
Increment by 1
Return to “Start
Row (YS)”
2008-07-07
ST7773
9.11. Memory Data Write/ Read Direction
The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be
written is controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.
Fig. 9.11.1 Data streaming order
MADCTL
(36h)
Physical row point
MV
0
0
0
0
1
1
1
1
MX
0
0
1
1
0
0
1
1
MV
0
1
0
1
0
1
0
1
CASET
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (175-Physical Column Pointer)
Direct to (175-Physical Column Pointer)
Direct to Physical Row Pointer
Direct to (219-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (219-Physical Row Pointer)
RASET
Direct to Physical Row Pointer
Direct to (219-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (219-Physical Row Pointer)
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (175-Physical Column Pointer)
Direct to (175-Physical Column Pointer)
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by
MADCTL bits B7 (MY), B6 (MX), B5 (MV). The write order for each pixel unit is
One pixel unit represents 1 column and 1page counter value on the Frame Memory.
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ST7773
9.11.2 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY)
Display Data
Direction
Normal
MADCTL
Parameter
MV MX MY
0
0
0
Image in the Host
(MPU)
B
Image in the Driver
(DDRAM)
H/W position (0,0)
B
X-Y address (0,0)
X: CASET
F
Y-Mirror
0
0
1
B
Y: RASET
F
F
H/W position (0,0)
X-Y address (0,0)
X: CASET
F
X-Mirror
0
1
0
B
Y: RASET
B
B
H/W position (0,0)
X-Y address (0,0)
X: CASET
Y: RASET
F
X-Mirror
Y-Mirror
0
1
1
B
F
H/W position (0,0)
F
X-Y address (0,0)
X: CASET
B
F
X-Y Exchange
1
0
0
B
H/W position (0,0)
Y: RASET
B
X-Y address (0,0)
X: RASET
F
X-Y Exchange
Y-Mirror
1
0
1
B
Y: CASET
F
F
H/W position (0,0)
X-Y address (0,0)
X: RASET
F
X-Y Exchange
X-Mirror
1
1
0
B
Y: CASET
B
B
H/W position (0,0)
X-Y address (0,0)
X: RASET
Y: CASET
F
X-Y Exchange
X-Mirror
Y-Mirror
1
1
1
B
H/W position (0,0)
F
B
X-Y address (0,0)
X: RASET
Y: CASET
F
Ver. 2.0
F
51
2008-07-07
ST7773
9.12 Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled
by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the
Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when
displaying video images.
9.12.1 Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see below)
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 220
H-sync pulses per field.
Tvdl Tvdh
Vertical timing scale
V-sync
V-sync
Invisible
line
1st
line
2nd
line
219th
line
220 th
line
thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
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ST7773
9.12.2 Tearing Effect Line Timings
The Tearing Effect signal is described below:
Table 9.12.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 58.9 Hz)
Symbol
Parameter
min
max
unit
tvdl
Vertical Timing Low Duration
13
ms
tvdh
Vertical Timing High Duration
1000
µs
thdl
Horizontal Timing Low Duration
33
µs
thdh
Horizontal Timing Low Duration
25
500
µs
NOTE: The timings in Table 9.3.1 apply when MADCTL ML=0 and ML=1
description
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:
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ST7773
9.12.3 Example 1: MPU Write is faster than panel read
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of
the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame
refresh has a complete new image:
B
Ver. 2.0
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2008-07-07
ST7773
9.12.4 Example 2: MPU write is slower than panel read.
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the
Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing
download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position.
B
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2008-07-07
ST7773
9.13 Preset Values
ST7773 will set preset values on our production line for each display module. Any of these preset values do not need
customer’s SW support.
9.14 Power ON/OFF Sequence
The power on/off sequence is illustrated bleow:(VDD must be powered on then VDDI)
TrPW ≧ 0 ns
TfPW ≧ 0ns
VDD
VDDI
Timing when the latter signal rises up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross
point of 90% of 2.8V, not 2.7V.
Timing when the latter signal falls down to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross
point of 90% of 2.8V, not 2.7V.
Tr PW-RESX = min 10us
RESX
Tf PW-RESX = min 120ms
System is reset immediately by low pulse of RESX.
About the HW reset setting, please refer to the Sec.
9.18.3.
9.15.3 Uncontrolled Power Off
The uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. It will
neither damange the module or the host interface
If uncontrolled power-off happened, the display will go blank and there will not be any visible effects on the display (blank
display) and remains blank until “Power On Sequence” powers it up.
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9.16 Power Level Definition
9.16.1 Power Level
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power
Consumption:
1. Normal Mode On (full display), Idle Mode Off, Sleep Out.
In this mode, the display is able to show maximum 262,144 colors.
2. Partial Mode On, Idle Mode Off, Sleep Out.
In this mode part of the display is used with maximum 262,144 colors.
3. Normal Mode On (full display), Idle Mode On, Sleep Out.
In this mode, the full display area is used but with 8 colors.
4. Partial Mode On, Idle Mode On, Sleep Out.
In this mode, part of the display is used but with 8 colors.
5. Sleep In Mode
In this mode, the DC: DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and
memory works with VDDI power supply. Contents of the memory are safe.
6. Power Off Mode
In this mode, both VDD and VDDI are removed.
9.16.2 Power Flow Chart
Normal display mode on = NOR ON
Partial display mode on = PTL ON
Idle mode off = IDM OFF
Idle mode on = IDM ON
Sleep out = SLP OUT
Sleep in = SLP IN
NOR ON
PTL ON
Sleep out
Normal display mode on
Idle mode off
IDM ON
Power on sequence
HW reset
SW reset
SLP IN
SLP OUT
Sleep in
Normal display mode on
Idle mode off
Sleep out
Normal display mode on
Idle mode on
Sleep out
Partial display mode on
Idle mode off
PTL ON
NOR ON
Ver. 2.0
PTL ON
IDM OFF
IDM ON
IDM ON
NOR ON
SLP IN
SLP OUT
SLP IN
SLP OUT
IDM OFF
Sleep out
Partial display mode on
Idle mode on
Sleep in
Normal display mode on
Idle mode on
Sleep in
Partial display mode on
Idle mode off
IDM ON
SLP IN
SLP OUT
57
IDM OFF
IDM OFF
Sleep in
Partial display mode on
Idle mode on
PTL ON
NOR ON
2008-07-07
ST7773
9.17 Reset Table
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
After Power On
Random
In
Off
Normal
Off
Off
0000h
After Hardware Reset
No Change
In
Off
Normal
Off
Off
0000h
Column: End Address (XE)
00AFh
00AFh
Row: Start Address (YS)
0000h
0000h
Row: End Address (YE)
00DBh
00DBh
GC0
See Section 9.19
0000h
00DBh
Off
0000h
00DCh
0000h
0000h
Off
0 (Mode1)
GC0
See Section 9.19
0000h
00DBh
Off
0000h
00DCh
0000h
0000h
Off
0 (Mode1)
After Software Reset
No Change
In
Off
Normal
Off
Off
0000h
00AFh (175d) (when
MV=0)
00DBh (219d) (when
MV=1)
0000h
00DBh (219d) (when
MV=0)
00AFh (175d) (when
MV=1)
GC0
No Change
0000h
00DBh
Off
0000h
00DCh
0000h
0000h
Off
0 (Mode1)
0/0/0/0/0
0/0/0/0/0
No Change
Gamma setting
RGB for 256, 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Scroll: Vertical scrolling
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
Scroll Start Address (SSA)
Tearing: On/Off
Tearing Effect Mode *3)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
6 (18-Bit/Pixel)
6 (18-Bit/Pixel)
RDDPM
08h
08h
RDDMADCTL
00h
00h
RDDCOLMOD
6 (18-Bit/Pixel)
6 (18-Bit/Pixel)
RDDIM
00h
00h
RDDSM
00h
00h
RDDSDR
00h
00h
ID1
29h
29h
ID2
Note1. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
No Change
08h
No Change
No Change
00h
00h
00h
29h
-
9.18.1 Module Input/Output Pins
9.18.1.1 Output or Bi-directional (I/O) Pins
Output or Bi-directional pins
After Power On
After Hardware Reset
After Software Reset
TE
Low
Low
Low
D17 to D0 (Output driver)
High-Z (Inactive)
High-Z (Inactive)
High-Z (Inactive)
Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
9.18.1.2 Input Pins
Input pins
RESX
CSX
D/CX
WRX
RDX
D17 to D0
P/SX
Ver. 2.0
During Power
On Process
See 9.15
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
After Power On
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
After Hardware
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
58
After Software
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
During Power
Off Process
See 9.15
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
2008-07-07
ST7773
9.18.2 Reset Timing
VSS=0V, VDDI=1.6 to 3.3V, VDD=2.7 to 3.3V, Ta = 25℃)
Symbol
Parameter
Related Pins
MIN
tRESW
*1) Reset low pulse width
RESX
10
tREST
Reset complete time
-
120
TYP
-
MAX
-
-
-
Note
-
Unit
us
ms
Note 1 Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table
below.
Note 2. During Reset Complete Time, ID2 and VCOMOF value in EEPROM will be latched to internal register during this
period.This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising
edge of RESX.
Note 3. Spike Rejection also applies during a valid reset pulse as shown below:
RESX Pulse
Shorter than 5us
Longer than 10us
Between 5us and 10us
Action
Reset Rejected
Reset
Reset starts (It depends on voltage and temperature condition.)
10us
"RESET" is accepted
10us
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2008-07-07
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9.19 External Light Source
The operation of the module can meet customer’s Environmental reliability requirements.
9.20 Oscillator
The chip has on-chip oscillator that does not require external components. This oscillator output signal is used for system
clock generation for internal display operation.
9.21 System Clock Generator
The timing generator produces the various signals to driver the internal circuitty. Internal chip operation is not affected by
operations on the data bus.
9.22 Instruction Decoder and Register
The instruction decoder indentifies command words arriving at the interface and routes the following data bytes to their
destination. The command set can be found in “Command” section.
9.23 Source Driver
The source driver block includes 176x3 source outputs (S1 to S528), which should be connected directly to the TFT-LCD.
The source output signals are generated in the data processing block after the data is read out of the RAM and latched,
which represent the simulatance selected rows.
9.24 Gate Driver
The gate driver block includes 220 channel gate output (G0 to G219) which should be connected directly to the TFT-LCD.
S1 – S528
1
2
3
4
5
6
7
8
9
10
11
12
G1
G2
G3
VGH
G4
VGL
G5
G6
G7
G8
G9
G10
G11
G12
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10. Command
10.1 System function Command List and Description
Table 10.1.1 System Function command List (1)
Instruction Refer D/CX WRX RDX D17-8
NOP
10.1.1 0
SWRESET 10.1.2 0
0
1
RDDID 10.1.3
1
1
0
1
1
RDDST 10.1.4
1
1
1
↑
-
1
1
1
↑
1
1
1
1
1
0
↑
1
-
1
1
0
RDD
10.1.6 1
MADCTL
1
1
1
↑
1
1
↑
↑
1
↑
↑
-
0
RDD
10.1.7
1
COLMOD
1
↑
1
-
1
1
↑
↑
-
0
↑
1
-
1
1
1
1
↑
↑
-
0
↑
1
-
1
1
1
1
↑
↑
-
RDDPM
10.1.5
RDDIM
10.1.8
RDDSM
10.1.9
↑
↑
↑
1
1
1
↑
↑
↑
1
↑
↑
↑
↑
D7
D6
D5
D4
D3
D2
D1
D0
(Hex) Function
0
0
0
0
0
0
(00h) No Operation
0
0
0
0
0
1
(01h) Software reset
(04h) Read Display ID
0
0
0
1
0
0
Dummy read
ID1 read
ID15
ID14
ID13
ID12 ID11
ID10
ID2 read
ID25
ID24
ID23
ID22 ID21 ID20
0
0
1
0
0
1
(09h) Read Display Status
Dummy read
MX
MV
ML
RGB
MH
ST24
IFPF1 IFPF0 IDMON PTLON SLOUT NORON
INVON ST21
ST11 DISON TEON GCS2
TELON HSON VSON PCKON DEON ST0
Read Display Power
0
0
0
0
1
0
1
0
(0Ah)
Mode
Dummy read
BSTON IDMONPTLON SLPOUT NORON DISON D1
D0
0
0
0
0
1
0
1
1
(0Bh Read Display MADCTL
Dummy read
MY
MX
MV
ML
RGB
MH
D1
D0
Read Display Pixel
0
0
0
0
1
1
0
0
(0Ch)
Format
Dummy read
D7
D6
D5
D4
D3
IFPF2 IFPF1 IFPF0
Read Display Image
0
0
0
0
1
1
0
1
(0Dh)
Mode
Dummy read
VSSON D6 INVON
D4
D3
GCS2 GCS1 GCS0
Read Display Signal
0
0
0
0
1
1
1
0
(0Eh)
Mode
Dummy read
TEON TELON HSON VSON PCKON DEON D1
D0
0
0
0
ID17
‘1’
0
BSTON
ST23
VSSON
GCS1
0
0
0
ID16
ID26
0
MY
IFPF2
ST14
GCS0
“-“: Don’t care
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Table 10.1.2 System Function command List (2)
Instruction Refer D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
1
0
1
SLPIN
SLPOUT
PTLON
NORON
10.1.11
10.1.12
10.1.13
10.1.14
0
0
0
0
↑
↑
↑
↑
1
1
1
1
-
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
INVOFF
INVON
10.1.15
10.1.16
GAMSET
10.1.17
0
0
0
1
0
0
0
1
1
1
1
0
1
1
1
1
0
1
0
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↑
↑
-
0
0
0
0
0
0
XS15
XS7
XE15
XE7
0
YS15
YS7
YE15
YE7
0
D7
0
D7
0
0
0
0
0
0
XS14
XS6
XE14
XE6
0
YS14
YS6
YE14
YE6
0
D6
0
D6
1
1
1
1
1
1
XS13
XS5
XE13
XE5
1
YS13
YS5
YE13
YE5
1
D5
1
D5
0
0
0
0
0
0
XS12
XS4
XE12
XE4
0
YS12
YS4
YE12
YE4
0
D4
0
D4
0
0
0
GC3
1
1
1
XS11
XS3
XE11
XE3
1
YS11
YS3
YE11
YE3
1
D3
1
D3
0
0
1
GC2
0
0
0
XS10
XS2
XE10
XE2
0
YS10
YS2
YE10
YE2
1
D2
1
D2
DISPOFF 10.1.18
DISPON 10.1.19
CASET
10.1.20
RASET
10.1.21
RAMWR
10.1.22
RAMRD
10.1.23
(Hex) Function
(10h)
(11h)
(12h)
(13h)
Sleep in & booster off
Sleep out & booster on
Partial mode on
Partial mode off (Normal)
Display inversion off (normal)
Display inversion on
Gamma curve select
Display off
Display on
Column address set
X address start: 0≦S≦X
0
0
(20h)
0
1
(21h)
1
0
(26h)
GC1 GC0
0
0
(28h)
0
1
(29h)
1
0
(2Ah)
XS9 XS8
XS1 XS0
X address end: XS≦XE≦X
XE9 XE8
XE1 XE0
1
1
(2Bh) Row address set
Y address start: 0≦YS≦Y
YS9 YS8
YS1 YS0
Y address end: YS≦YE≦Y
YE9 YE8
YE1 YE0
0
0
(2Ch) Memory write
Write data
D1
D0
1
0
(2Eh) Memory read
Dummy read
Read data
D1
D0
“-“: Don’t care
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Table 10.1.3 System Function command List (3)
Instruction Refer D/CX WRX RDX D17-8
D7
D6
D5
D4
D3
D2
D1
D0 (Hex)
Function
0
1
PTLAR 10.1.24 1
1
1
0
1
1
SCRLAR 10.1.25 1
1
1
1
TEOFF 10.1.26 0
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
-
0
↑
1
-
0
0
1
1
0
1
0
1
(35h) Tearing effect mode set & on
1
↑
1
-
-
-
-
-
-
-
-
M
M=”0”: Mode1, M=”1”: Mode2
0
1
0
1
1
0
0
0
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
-
0
10.1.33 1
↑
1
-
1
1
0
1
1
0
1
0
1
↑
-
-
-
-
-
-
-
-
-
RDID2
1
0
10.1.34 1
1
0
1
↑
1
1
↑
↑
1
↑
↑
1
-
ID17
1
ID27
1
ID16
1
ID26
1
ID15
0
ID25
0
ID14
1
ID24
1
ID13
1
ID23
1
RDID3
10.1.35 1
1
↑
-
-
-
-
-
-
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
TEON
10.1.27
MADCTL 10.1.28
VSCSAD 10.1.29
IDMOFF 10.1.30
IDMON 10.1.31
COLMOD 10.1.32
RDID1
0
0
1
1
0
0
0
0 (30h) Partial start/end address set
PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8
Partial start address (0,1,2, ..P)
PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0
PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8
Partial end address (0,1,2, .., P)
PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0
0
0
1
1
0
0
1
1 (33h) Scroll area set
TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8
Top fixed area (0,1,2, .., S)
TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0
VSA15VSA14VSA13VSA12 VSA11VSA10 VSA9 VSA8
Vertical scroll area (0,1,2, .., S)
VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8
Bottom fixed area (0,1,2, .., S)
BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
0
0
1
1
0
1
0
0 (34h) Tearing effect line off
0
0
1
1
0
1
1
0 (36h)
MY
MX
MV
ML
RGB MH
0
0
0
0
1
1
0
1
1
1 (37h)
- SSA8
SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0
0
0
1
1
1
0
0
0 (38h)
0
0
1
1
1
0
0
1 (39h)
0
0
1
1
1
0
1
0 (3Ah)
0
IFPF2 IFPF1IFPF0
Memory data access control
Scroll start address of RAM
SSA = 0, 1, 2, …, 175
Idle mode off
Idle mode on
Interface pixel format
Interface format
(DAh) Read ID1
Dummy read
ID12 ID11 ID10
Read parameter
0
1
1 (DBh) Read ID2
Dummy read
ID22 ID21 ID20
Read parameter
1
0
0 (DCh) Read ID3
-
-
-
ID32 ID31 ID30
Dummy read
Read parameter
“-“: Don’t care
Note 1: After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer
“RESET TABLE” section)
Note 2: Undefined commands are treated as NOP (00 h) command.
Note 3: DE to FF are for factory use of driver supplier.
Note 4: Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during
V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated
immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch),
Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh) of these commands are updated immediately both in Sleep In
mode and Sleep Out mode.
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10.2 Panel Function Command List and Description
Table 10.2.1 Panel Function Command List (1)
Instruction
FRMCTR1
Refer D/CX WRX RDX D23-8
0
↑
1
10.2.2
1
0
FRMCTR2
10.2.3
FRMCTR3
10.2.4
INVCTR
10.2.5
DISSET5
Ver. 2.0
10.2.7
↑
↑
1
1
1
↑
1
0
↑
1
1
↑
1
0
↑
1
1
↑
1
0
↑
1
1
↑
1
D7
1
D6
0
D5
1
-
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
-
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
-
-
D4
D3
1
0
RTNA[7:0]
1
1
D2
0
D1
0
D0
1
0
1
1
0
0
(Hex) Function
(B1h) In normal mode (Full colors)
FPA[4:0]
0
0
1
BPA[4:0]
RTNA_VSYNC setting for
VSYNC mode
0
0
0
1
1
RTNA_VSYNC[7:0]
1
1
1
0
0
0
1
1
0
0
1
0
(B2h) In Idle mode (8 colors)
RTNB[7:0]
1
1
1
0
1
1
0
FPB[4:0]
0
0
0
1
0
0
BPB[4:0]
0
0
0
1
1
1
1
0
0
1
0
(B3h) In partial mode (Full colors)
RTNC[7:0]
1
1
1
0
1
1
0
FPC[4:0]
0
0
0
1
0
0
BPC[4:0]
0
0
0
1
1
1
1
0
1
0
0
(B4h) Display inversion control
0
0
0
NLA NLB NLC
NLA:,NLB,NLC set inversion
0
0
0
0
0
0
1
1
0
1
1
0
(B6h) Display function setting
NO: the amount of non-overlap
NO1 NO0 SDT1 SDT0 EQ1 EQ0
SDT: set amount of source
0
1
0
1
0
1
delay PT: No display area
source/
0
0 PTG1 PTG0 PT1 PT0
0
0
64
0
0
0
0
VCOM/ Gate output control
EQ: set EQ period
2008-07-07
ST7773
Table 10.2.2 Panel Function Command List (2)
Instruction Refer D/CX WRX RDX D17-8
0
↑
1
PWCTR1 10.2.10
1
↑
1
0
↑
1
-
PWCTR2 10.2.11
1
↑
↑
1
1
↑
1
PWCTR3 10.2.12
PWCTR4 10.2.13
1
↑
↑
1
VMOFCTR 10.2.16
8-color
CTR
10.2.18
0
↑
1
1
↑
1
0
↑
1
1
↑
1
1
↑
1
0
↑
1
1
↑
1
0
1
↑
0
1
1
1
0
1
1
-
1
1
0
0
0
0
1
0
-
0
0
0
0
0
-
0
0
0
0
0
0
0
1
1
(C3h) In Idle mode (8-colors)
1
0
0
0
0
0
0
0
-
0
0
0
0
0
0
1
0
-
1
1
0
0
0
1
0
0
-
0
0
0
0
0
-
0
0
0
0
0
-
1
0
0
0
0
1
AP: adjust the
operational amplifier
DCT: adjust the booster
circuit for Idle mode
APB2 APB1 APB0
0
1
DUAL_EN STEP_DIV_EN
1
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
-
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
↑
1
0
↑
PWCTR6 10.2.19
0
VCOM control 1
VMH: VCOMH voltage
control VML: VCOML
voltage control
VCOM offset control
1
0
0
0
0
1
(C9h) Step124 setup
0 CP1_FREQ_SEL[2:0]
0
1
0
0
0 CP2_FREQ_SEL[2:0]
Adjust step1/2/4
booster frequency
0
1
0
0
0 CP4_FREQ_SEL[2:0]
0
1
0
0
0
1
0
0
(F4h)
RD_PULSE_WIDTH[3:0]
Adjust read GRAM
timing control function
0
1
0
1
1
0
0
0
(F8h)
0 8-color 0
0
8-color detect function
0
1
0
0
1
1
0
1
1
-
1
AP: adjust the
operational amplifier
DCT: adjust the booster
circuit for Idle mode
APC2 APC1 APC0
1
In partial mode + Full
colors
VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0
1
↑
(C4h)
1
0
0
0
1
0
1
(C5h)
VMH6 VMH 5 VMH4 VMH3 VMH2 VMH1 VMH0
0
1
1
1
1
0
0
VML6 VML5 VML4 VML3 VML2 VML1 VML0
0
1
1
1
1
0
0
1
0
0
0
1
1
1
(C7h)
0
0
0
1
0
0
1
0
0
0
In normal mode (Full
colors)
0
1
NW_MODE
↑
Power control setting
1
0
0
1
Power control setting
VRH: Set the GVDD
voltage
AP: adjust the
operational amplifier
DC: adjust the booster
circuit for Idle mode
-
-
↑
↑
(C2h)
APA2 APA1 APA0
-
nVM*
Function
VGH: set VGH voltage
VGL: set VGL voltage
VGH2 VGH1 VGH0 VGL3 VGL2 VGL1 VGL0
0
0
0
0
0
1
1
0
1
0
0
1
1
D4
D3
D2
D1
D0 (Hex)
0
0
0
0
0
(C0h)
VRH4 VRH3 VRH2 VRH1 VRH0
0
0
1
0
1
0
0
0
0
1
(C1h)
1
1
STEP CTR 10.2.17
D5
0
0
0
0
1
PWCTR5 10.2.14
VMCTR1 10.2.15
VGH3
D6
1
0
0
1
1
0
0
D7
1
0
0
1
1
0
0
SAPA[2:0]
0
0
SAPB[2:0]
1
0
0
SAPC[2:0]
1
0
0
1
(FCh)
Gate operational
amplifier control
SAPA.: Normal mode
SAPB : Idle mode
SAPC : Partial mode
“-“: Don’t care
Ver. 2.0
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Table 10.2.3 Panel Function Command List (3)
Instruction Refer D/CX WRX RDX D17-8
0
↑
1
10.2.20
WRID2
1
↑
1
-
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
ID26
0
ID25
1
ID24
0
ID23
0
ID22
0
ID21
1
ID20
1
0
0
0
0
0
0
0
0
1
↑
↑
1
1
-
1
1
1
0
0
1
1
0
1
1
1
0
1
1
0
0
0
↑
1
-
1
1
0
1
1
1
1
1
NVCTR3 10.2.24 1
1
1
↑
↑
↑
1
1
1
-
0
1
0
1
1
1
0
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
NVCTR2 10.2.23
(Hex) Function
(D1h) LCM version code
Write ID2 value to
NV memory Set the
LCM version code
at ID2
(DEh) MTP read command
75
MTP write
(DFh) command
55
F0
5A
“-“: Don’t care
Note 1: The D1h to D3h registers are fixed for about ID code setting.
Note 2: The DEh and DFh registers are used for NV Memory function controller. (Ex: write, clear, etc.)
Ver. 2.0
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2008-07-07
ST7773
Table 10.2.4 Panel Function Command List (4)
Instruction Refer D/CX WRX RDX D17-8
↑
0
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
GAMCTRP1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
-
GAMCTRN1
1
↑
1
1
↑
1
0
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
Ver. 2.0
↑
1
D7
1
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
---
D6
1
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
---
D5
1
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
--0
--0
1
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
1
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
--0
-
--0
--0
D3
D2
0
0
VRF0P[5:0]
0
0
VOS0P[5:0]
0
0
PK0P[5:0]
0
0
PK1P[5:0]
0
0
PK2P[5:0]
0
0
PK3P[5:0]
0
0
PK4P[5:0]
0
0
PK5P[5:0]
0
0
PK6P[5:0]
0
0
PK7P[5:0]
0
0
PK8P[5:0]
0
0
PK9P[5:0]
0
0
SELV0P[5:0]
0
0
SELV1P[5:0]
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELV62P[5:0]
0
0
SELV63P[5:0]
0
0
0
0
VRF0N[5:0]
0
0
VOS0N[5:0]
0
0
PK0N[5:0]
0
0
PK1N[5:0]
0
0
PK2N[5:0]
0
0
PK3N[5:0]
0
0
PK4N[5:0]
0
0
PK5N[5:0]
0
0
PK6N[5:0]
0
0
PK7N[5:0]
0
0
PK8N[5:0]
0
0
PK9N[5:0]
0
0
SELV0N[5:0]
0
0
0
SELV1N[5:0]
0
0
0
67
D1
0
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Hex) Function
(E0h) Set Gamma correction
Postiive Polarity
(E1h) Set Gamma correction
Negative Polarity
2008-07-07
ST7773
GAMCTRN1
1
1
↑
↑
1
1
-
---
---
-
0
--0
0
--0
SELV62N[5:0]
0
0
0
0
0
0
SELV63N[5:0]
0
0
0
0
0
0
Negative Polariy
“-“: Don’t care
Note 1: E0-E1 registers are fixed for about Gamma adjusting.
Ver. 2.0
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2008-07-07
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10.1.1 NOP (00h)
00H
Inst / Para
NOP
Parameter
D/CX WRX RDX
0
1
↑
D17-8
-
D7
0
NOP (No Operation)
D6
D5
D4
D3
0
0
0
0
No Parameter
D2
0
D1
0
D0
0
(Code)
(00h)
-
NOTE: “-“ Don’t care
Description -This command is empty command.
10.1.2 SWRESET (01h): Software Reset
01H
Inst / Para
SWRESET
Parameter
D/CX WRX RDX
0
1
↑
D17-8
-
D7
0
SWRESET (Software Reset)
D6
D5
D4
D3
0
0
0
0
No Parameter
D2
0
D1
0
D0
1
(Code)
(01h)
-
NOTE: “-“ Don’t care
-When the Software Reset command is written, it causes a software reset. It resets the commands and
parameters to their S/W Reset default values and all source & gate outputs are set to VSS (display off).
-It will be necessary to wait 5msec before sending new command following software reset.
Description -The display module loads all default values to the registers during 5msec.
-If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending
Sleep Out command.
-Software Reset command cannot be sent during Sleep Out sequence.
10.1.3 RDDID (04h): Read Display ID
RDDID (Read Display ID)
04H
Inst / Para
RDDID
1st Parameter
2nd Parameter
3rt Parameter
D/CX WRX RDX
0
↑
1
1
1
↑
1
1
↑
1
1
↑
D17-8
-
D7
0
ID17
‘1’
D6
0
ID16
ID26
D5
0
ID15
ID25
D4
0
ID14
ID24
D3
0
ID13
ID23
D2
1
ID12
ID22
D1
0
ID11
ID21
D0
0
ID10
ID20
(Code)
(04h)
-
NOTE: “-“ Don’t care
-This read byte returns 24-bit display identification information.
-The 1st parameter is dummy data
Description -The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID.
-The 3rd parameter (ID27 to ID20): LCD module/driver version ID
NOTE: Commands RDID1/2(DAh, DBh) read data correspond to the parameters 2,3, of the command 04h, respectively.
Default Value
Status
Default
Ver. 2.0
Power On Sequence
ID1
ID2
-
-
S/W Reset
29h
29h
H/W Reset
81h
81h
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10.1.4 RDDST (09h): Read Display Status
09H
Inst / Para
RDDST
D/CX WRX RDX
0
↑
1
1st Parameter
2nd Parameter
3rd Parameter
4th Parameter
5th Parameter
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
D17-8
-
D7
0
RDDST (Read Display Status)
D6
D5
D4
D3
0
0
0
1
-
-
-
-
BSTON
ST23
VSSON
GCS1
MY
IFPF2
ST14
GCS0
MX
IFPF1
INVON
TELOM
MV
IFPF0
ST12
HSON
-
D2
0
D1
0
-
-
ML
RGB
MH
IDMON PTLON SLOUT
ST11
DISON TEON
VSON PCKON DEON
D0
1
(Code)
(09h)
-
-
ST24
NORON
GCS2
ST0
NOTE: “-“ Don’t care
This command indicates the current status of the display as described in the table below:
Description
Bit
BSTON
Description
Booster Voltage Status
MY
Row Address Order (MY)
MX
Column Address Order (MX)
MV
Row/Column Exchange (MV)
ML
Scan Address Order (ML)
RGB
RGB/ BGR Order (RGB)
MH
Horizontal Order
ST24
ST23
IFPF2
IFPF1
IFPF0
IDMON
PTLON
SLPOUT
NORON
For Future Use
For Future Use
VSSON
ST14
INVON
ST12
ST11
DISON
TEON
GCSEL2
GCSEL1
Vertical Scrolling Status
Horizontal Scroll Status
Inversion Status
All Pixels On (Not Used)
All Pixels Off (Not Used)
Display On/Off
Tearing effect line on/off
Interface Color Pixel Format
Definition
Idle Mode On/Off
Partial Mode On/Off
Sleep In/Out
Display Normal Mode On/Off
Gamma Curve Selection
GCSEL0
TELOM
HSON
Value
‘1’ =Booster on,
‘0’ =Booster off
‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)
‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’)
‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)
‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’1’)
‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)
‘0’ = Normal, (when MADCTL (36h) D5=’0’)
‘1’ =Decrement,
(LCD refresh Top to Bottom, when MADCTL (36h) D4=’1’)
‘0’=Increment,
(LCD refresh Bottom to Top, when MADCTL (36h) D4=’0’)
‘1’ =BGR, (When MADCTL (36h) D3=’1’)
‘0’ =RGB, (When MADCTL (36h) D3=’0’)
‘1’ =Decrement,
(LCD refresh Left to Right, when MADCTL (36h) D2=’1’)
‘0’ =Increment,
(LCD refresh Right to Left, when MADCTL (36h) D2=’0’)
‘0’
‘0’
“011” = 12-bit / pixel,
“101” = 16-bit / pixel,
“110” = 18-bit / pixel, others are no define
‘1’ = On, “0” = Off
‘1’ = On, “0” = Off
‘1’ = Out, “0” = In
‘1’ = Normal Display,
‘0’ = Partial Display
‘1’ = Scroll on,“0” = Scroll off
‘0’
‘1’ = On, “0” = Off
‘0’
‘0’
‘1’ = On, “0” = Off
‘1’ = On, “0” = Off
“000” = GC0
“001” = GC1
“010” = GC2
“011” = GC3
”100” to “111” = Not defined
‘0’ = mode1, ‘1’ = mode2
‘1’ = On, ‘0’ = Off
Tearing effect line mode
Horizontal Sync. (HS, RGB
I/F)
VSON
Vertical Sync, (VS, RGB I/F)
‘1’ = On, ‘0’ = Off
PCLKON Pixel Clock (PCLK, RGB I/F)
‘1’ = On, ‘0’ = Off
DEON
Data Enable (DE, RGB I/F)
‘1’ = On, ‘0’ = Off
ST0
For Future Use
‘0’
Note: ST0, ST5, ST9, ST11-ST15, ST19, ST23, ST24 are set to ‘0’, when RGB I/F.
Status
Default
Ver. 2.0
Power On Sequence
S/W Reset
H/W Reset
ST[31-24]
0000-0000
0xxx0xx00
0000-0000
70
Default Value (ST31 to ST0)
ST[23-16]
ST[15-8]
0110-0001
0000-0000
0xxx-0001
0000-0000
0110-0001
0000-0000
ST[7-0]
0000-0000
0000-0000
0000-0000
2008-07-07
ST7773
10.1.5 RDDPM (0Ah): Read Display Power Mode
0AH
Inst / Para
RDDPM
D/CX WRX RDX
0
↑
1
1st Parameter
2nd Parameter
1
1
RDDPM (Read Display Power Mode)
D7
D6
D5
D4
D3
0
0
0
0
1
D17-8
-
D2
0
D1
1
1
1
↑
↑
BSTON IDMON PTLON SLPOUT NORON DISON
NOTE: “-” Don’t care, can be set to VDDI or DGND level
D0
0
(Code)
(0Ah)
-
-
-
D1
D0
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
BSTON
Booster Voltage Status
IDMON
Idle Mode On/Off
PTLON
Partial Mode On/Off
SLPON
Sleep In/Out
NORON
Display Normal Mode
On/Off
DISON
Display On/Off
D1
D0
Not Used
Not Used
‘1’ =Booster on,
‘0’ =Booster off
‘1’ = Idle Mode On,
‘0’ = Idle Mode Off
‘1’ = Partial Mode On,
‘0’ = Partial Mode Off
‘1’ = Sleep Out,
‘0’ = Sleep In
‘1’ = Normal Display,
‘0’ = Partial Display
‘1’ = Display On,
‘0’ = Display Off
‘0’
‘0’
Description
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value (D7 to D0)
0000_1000(08h)
0000_1000(08h)
0000_1000(08h)
10.1.6 RDDMADCTL (0Bh): Read Display MADCTL
0BH
Inst / Para
RDDMADCTL
D/CX
0
WRX
↑
RDX
1
1st Parameter
2nd Parameter
1
1
1
1
↑
↑
RDDMADCTL (Read Display MADCTL)
D17-8
D7
D6
D5
D4
D3
0
0
0
0
1
-
MY
MX
MV
ML
RGB
D2
0
D1
1
D0
1
(Code)
(0Bh)
MH
D1
D0
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
This command indicates the current status of the display as described in the table below:
Description
Default
Ver. 2.0
Bit
Description
MX
Row Address Order
MY
Column Address Order
MV
Row/Column Order (MV)
ML
Vertical Refresh Order
RGB
RGB/BGR Order
MH
Horizontal order
D1
D0
Not Used
Not Used
Value
‘1’ = Bottom to Top (When MADCTL B7=’1’)
‘0’ = Top to Bottom (When MADCTL B7=’0’)
‘1’ = Right to Left (When MADCTL B6=’1’)
‘0’ = Left to Right (When MADCTL B6=’0’)
‘1’ = Row/column exchange (MV=1)
‘0’ = Normal (MV=0)
‘1’ =LCD Refresh Bottom to Top
‘0’ =LCD Refresh Top to Bottom
‘1’ =BGR, “0”=RGB
‘1’ =LCD Refresh Right to Left
‘0’ =LCD Refresh Left to Right
‘0’
‘0’
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value (D7 to D0)
0000_0000 (00h)
No change
0000_0000 (00h)
71
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ST7773
10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format
0CH
Inst / Para
RDDCOLMOD
D/CX
0
WRX
↑
RDX
1
D17-8
-
RDDCOLMOD (Read Display Pixel Format)
D7
D6
D5
D4
D3
D2
0
0
0
0
1
1
1st Parameter
1
1
↑
2nd Parameter
1
1
VIPF3
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
VIPF2
VIPF1
VIPF0
D3
IFPF2
D1
0
D0
0
(Code)
(0Ch)
IFPF1
IFPF0
-
This command indicates the current status of the display as described in the table below:
IFPF[2:0]
011
101
110
111
MCU Interface Color Format
12-bit/pixel
16-bit/pixel
18-bit/pixel
No used
3
5
6
7
Others are no define and invalid
VIFPF[2:0]
0101
0110
0111
1110
Description
RGB Interface Color Format
16-bit/pixel (1-times data transfer)
18-bit/pixel (1-times data transfer)
No used
18-bit/pixel (3-times data transfer)
5
6
7
14
Others are no define and invalid
Status
Default
Default Value
IFPF[2:0]
0110 (18 bits/pixel)
No Change
0110 (18 bits/pixel)
Power On Sequence
S/W Reset
H/W Reset
VIPF[3:0]
0110 (18 bits/pixel)
No Change
0110 (18 bits/pixel)
10.1.8 RDDIM (0Dh): Read Display Image Mode
0DH
Inst / Para
RDDIM
1st Parameter
2nd Parameter
D/CX WRX RDX
0
↑
1
1
1
D17-8
-
RDDIM (0Dh): Read Display Image Mode
D7
D6
D5
D4
D3
D2
0
0
0
0
1
1
1
1
↑
↑
VSSON
NOTE: “-” Don’t care, can be set to VDDI or DGND level
D1
0
D0
1
(Code)
(0Dh)
-
-
-
-
-
-
-
-
D6
INVON
D4
D3
GCS2
GCS1
GCS0
This command indicates the current status of the display as described in the table below:
Bit
Description
Value
“1” = Vertical scrolling is On,
VSSON
Vertical Scrolling On/Off
“0” = Vertical scrolling is Off
D6
Horizontal Scrolling On/Off
“0” (Not used)
“1” = Inversion is On,
INVON
Inversion On/Off
“0” = Inversion is Off
Description
D4
All Pixels On
“0” (Not used)
D3
All Pixels Off
“0” (Not used)
GCS2
“000” = GC0,
“001” = GC1,
GCS1
Gamma Curve Selection
“010” = GC2,
GCS0
“011” = GC3, ”100” to “111” = Not defined
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value(D7 to D0)
0000_0000 (00h)
0000_0000 (00h)
0000_0000 (00h)
72
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ST7773
10.1.9 RDDSM (0Eh): Read Display Signal Mode
0EH
Inst / Para
RDDSM
D/CX WRX
0
↑
RDX
1
D17-8
-
RDDSM (0Eh): Read Display Signal Mode
D7
D6
D5
D4
D3
0
0
0
0
1
1st Parameter
1
1
↑
2nd Parameter
1
1
↑
TEON
NOTE: “-” Don’t care, can be set to VDDI or DGND level
D2
1
D1
1
D0
0
(Code)
(0Eh)
-
-
-
-
-
-
-
-
TELOM
HSON
VSON
PCKON
DEON
D1
D0
This command indicates the current status of the display as described in the table below:
Bit
TEON
Description
TELOM
Tearing effect line mode
HSON
Horizontal Sync. (RGB I/F) On/Off
VSON
Vertical Sync. (RGB I/F) On/Off
PCKON
DEON
Default
Ver. 2.0
Description
Tearing Effect Line On/Off
Value
Pixel Clock (PCLK, RGB I/F) On/Off
Data Enable (DE, RGB I/F) On/Off
D1
Not Used
D0
Not Used
Status
Power On Sequence
S/W Reset
H/W Reset
“1” = On,
“0” = Off
“1” = mode1,
“0” = mode2
“1” = On,
“0” = Off
“1” = On,
“0” = Off
“1” = On,
“0” = Off
“1” = On,
“0” = Off
“1” = On,
“0” = Off
“1” = On,
“0” = Off
Default Value(D7~D0)
0000_0000 (00h)
0000_0000 (00h)
0000_0000 (00h)
73
2008-07-07
ST7773
10.1.10 SLPIN (10h): Sleep In
10H
Inst / Para
SLPIN
st
1 Parameter
D/CX
0
WRX
↑
RDX
1
SLPIN (Sleep In)
D7
D6
D5
D4
0
0
0
1
No parameter
D17-8
-
D3
0
D2
0
D1
0
D0
0
(Code)
(10h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command causes the LCD module to enter the minimum power consumption mode.
-In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel
scanning is stopped.
Sleep In
1.6V-3.6V
VDDI
VDD
2.7V-3.5V
Gate Output
Description
STOP
Source Output
0V
VCOM Output
0V
Blanking display (over 1frame display) *
0V
Internal counter
STOP
Internal Oscillator
STOP
DC charge in capacitors
DISCHARGE
0V or VDD
VGH
0V or VDD
VGL
0V
AVDD
0V or VDD
IC Internal reset
0V
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by
the Sleep Out Command (11h).
-It will be necessary to wait 5msec before sending next command, this is to allow time for the supply
Restriction
voltages and clock circuits to stabilize.
-It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before
Sleep In command can be sent.
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Sleep in mode
Sleep in mode
Sleep in mode
74
2008-07-07
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10.1.11 SLPOUT (11h): Sleep Out
11H
Inst / Para
SLPOUT
1st Parameter
D/CX
0
WRX
↑
RDX
1
SLPOUT (Sleep Out)
D7
D6
D5
D4
0
0
0
1
No Parameter
D17-8
-
D3
0
D2
0
D1
0
D0
1
(Code)
(11h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command turns off sleep mode.
-In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is
started.
Sleep Out
Description
VDDI
1.6V-3.6V
VDD
2.7V-3.5V
Internal Oscillator
STOP
AVDD
0V or VDD
Start
VGL
0V
VGH
0V or VDD
Internal counter
STOP
IC Internal reset
0V
Gate Output
STOP
Source Output
0V
0V
Memory Contents
VCOM Output
0V
0V
Memory Contents
Start
STOP
Blanking display (over 1fram e display) *
If DISPON 29h is set
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit
by the Sleep In Command (10h).
-It will be necessary to wait 5msec before sending next command, this is to allow time for the supply
voltages and clock circuits to stabilize.
-DRIVER loads all default values of extended and test command to the registers during this 5msec and
Restriction
there cannot be any abnormal visual effect on the display image if those default and register values are
same when this load is done and when the DRIVER is already Sleep Out mode.
-DRIVER is doing self-diagnostic functions during this 5msec. See also section 9.20.
-It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before
Sleep Out command can be sent
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Sleep in mode
Sleep in mode
Sleep in mode
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10.1.12 PTLON (12h): Partial Display Mode On
12H
Inst / Para
PTLON
st
1 Parameter
D/CX
0
WRX
↑
RDX
1
PTLON (12h): Partial Display Mode On
D17-8
D7
D6
D5
D4
D3
D2
0
0
0
1
0
0
No Parameter
D1
1
D0
0
(Code)
(12h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command turns on Partial mode. The partial mode window is described by the Partial Area command
Description (30h)
-To leave Partial mode, the Normal Display Mode On command (13H) should be written.
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
Normal Mode On
Normal Mode On
Normal Mode On
10.1.13 NORON (13h): Normal Display Mode On
13H
Inst / Para
NORON
st
1 Parameter
D/CX
0
WRX
↑
RDX
1
NORON (Normal Display Mode On)
D17-8
D7
D6
D5
D4
D3
0
0
0
1
0
No Parameter
D2
0
D1
1
D0
1
(Code)
(13h)
-
D1
0
D0
0
(Code)
(20h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command returns the display to normal mode.
Description -Normal display mode on means Partial mode off, Scroll mode Off.
-Exit from NORON by the Partial mode On command (12h)
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
Normal Mode On
Normal Mode On
Normal Mode On
10.1.14 INVOFF (20h): Display Inversion Off
20H
Inst / Para
INVOFF
st
1 Parameter
D/CX
0
WRX
↑
RDX
1
IVNOFF (Normal Display Mode Off)
D17-8
D7
D6
D5
D4
D3
0
0
1
0
0
No Parameter
D2
0
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to recover from display inversion mode.
(Example)
Top-Left (0,0)
Memory
Display
Description
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display Inversion off
Display Inversion off
Display Inversion off
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10.1.15 INVON (21h): Display Inversion On
21H
Inst / Para
INVON
st
1 Parameter
D/CX
0
WRX
↑
IVNOFF (Display Inversion On)
D17-8
D7
D6
D5
D4
D3
0
0
1
0
0
No Parameter
RDX
1
D2
0
D1
0
D0
1
(Code)
(21h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to enter into display inversion mode
-To exit from Display Inversion On, the Display Inversion Off command (20h) should be written.
(Example)
Top-Left (0,0)
Description
Memory
Display
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
Display Inversion off
Display Inversion off
Display Inversion off
10.1.16 GAMSET (26h): Gamma Set
26H
Inst / Para
GAMSET
D/CX
0
WRX
↑
↑
RDX
1
1
D17-8
-
D7
0
1st Parameter
1
GC7
NOTE: “-” Don’t care, can be set to VDDI or DGND level
GAMSET (Gamma Set)
D6
D5
D4
0
1
0
GC6
GC5
GC4
D3
0
D2
1
D1
1
D0
0
GC3
GC2
GC1
GC0
(Code)
(26h)
-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves
can be selected. The curves are defined in section 9.17 The curve is selected by setting the appropriate bit
in the parameter as described in the Table.
GC [7:0]
Description
Default
Ver. 2.0
Parameter
Curve Selected
GS=1
Gamma Curve 1 (G2.2)
Gamma Curve 2 (G1.8)
Gamma Curve 3 (G2.5)
Gamma Curve 4 (G1.0)
01h
GC0
02h
GC1
04h
GC2
08h
GC3
Note: All other values are undefined.
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
01h
01h
01h
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10.1.17 DISPOFF (28h): Display Off
28H
Inst / Para
DISPOFF
st
1 Parameter
D/CX
0
WRX
↑
RDX
1
D17-8
-
DISPOFF (Display Off)
D7
D6
D5
D4
0
0
1
0
No Parameter
D3
1
D2
0
D1
0
D0
0
(Code)
(28h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is
disables and blank page inserted.
-Exit from this command by Display On (29h)
(Example)
Top-Left (0,0)
Memory
Display
Display OFF
VDDI
1.6V-3.6V
VDD
2.7V-3.5V
Description
Gate Output
STOP
Source Output
0V
VCOM Output
0V
Blanking display (over 1 frame display) *
0V
Internal counter
STOP
Internal Oscillator
VGH
VGL
AVDD
IC Internal reset
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display off
Display off
Display off
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10.1.18 DISPON (29h): Display On
29H
Inst / Para
DISPON
st
1 Parameter
D/CX
0
WRX
↑
RDX
1
D17-8
-
DISPON (Display On)
D7
D6
D5
D4
0
0
1
0
No Parameter
D3
1
D2
0
D1
0
D0
1
(Code)
(29h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled.
(Example)
Top-Left (0,0)
Memory
Display
Display ON
1.6V-3.6V
VDDI
Description
VDD
2.7V-3.5V
Blanking display (over 1 frame display) *
Gate Output
STOP
Source Output
0V
Memory Contents
VCOM Output
0V
Memory Contents
Internal counter
STOP
Start
Internal Oscillator
VGH
VGL
AVDD
IC Internal reset
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display off
Display off
Display off
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10.1.19 CASET (2Ah): Column Address Set
2AH
Inst / Para
GAMSET
D/CX
0
WRX
↑
↑
↑
↑
↑
RDX
1
D17-8
-
CASET(Colume Address Set)_
D7
D6
D5
D4
D3
0
0
1
0
0
1st Parameter
1
1
XS15
2nd Parameter
1
1
XS7
3rd Parameter
1
1
XE15
4th Parameter
1
1
XE7
NOTE: “-” Don’t care, can be set to VDDI or DGND level
XS14
XS6
XE14
XE6
XS13
XS5
XE13
XE5
XS12
XS4
XE12
XE4
XS11
XS3
XE11
XE3
D2
1
D1
1
D0
0
XS10
XS2
XE10
XE2
XS9
XS1
XE9
XE1
XS8
XS0
XE8
XE0
(Code)
(2Ah)
-The value of XS [15:0] and XE [15:0] are referred when RAMWR command comes.
-Each value represents one column line in the Frame Memory.
(Example)
XS[15:0]
XE[15:0]
Description
estriction
XS [15:0] always must be equal to or less than XE [15:0]
When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be
ignored.
(Parameter range: 0 ≦ XS [15:0] ≦ XE [15:0] ≦175 (00AFh)): MV=”0”
(Parameter range: 0 ≦ XS [15:0] ≦ XE [15:0] ≦219 (00DBh)): MV=”1”
Status
Default
Ver. 2.0
Power On Sequence
S/W Reset
H/W Reset
Default Value
XS [15:0]
XE [15:0] (MV=’0 ’)
XE [15:0] (MV=’1’)
00AFh (175)
00AFh (175)
00DBh (219)
00AFh (175)
0000h
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10.1.20 RASET (2Bh): Row Address Set
2BH
Inst / Para
RASET (2Bh)
D/CX
0
WRX
RDX
1
D17-8
-
D7
0
RASET (Row Address Set)
D6
D5
D4
D3
0
1
0
1
↑
1st Parameter
1
↑
1
YS15
2nd Parameter
1
↑
1
YS7
3rd Parameter
1
↑
1
YE15
4th Parameter
1
↑
1
YE7
NOTE: “-” Don’t care, can be set to VDDI or DGND level
YS14
YS6
YE14
YE6
YS13
YS5
YE13
YE5
YS12
YS4
YE12
YE4
YS11
YS3
YE11
YE3
D2
0
D1
1
D0
1
YS10
YS2
YE10
YE2
YS9
YS1
YE9
YE1
YS8
YS0
YE8
YE0
(Code)
(2Bh)
The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes.
Each value represents one column line in the Frame Memory.
Example
YS[15:0]
Description
YE[15:0]
Restriction
YS [15:0] always must be equal to or less than YE [15:0]
When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range
will be ignored.
(Parameter range: 0 ≦YS [15:0] ≦YE [15:0] ≦219 (00DBh)): MV=”0”
(Parameter range: 0 ≦YS [15:0] ≦YE [15:0] ≦175 (009Fh)) : MV=”1”
Status
Default
Ver. 2.0
Power On Sequence
S/W Reset
H/W Reset
Default Value
YS [15:0]
0000h
0000h
0000h
YE [15:0] (MV=’0 ’)
YE [15:0] (MV=’1’)
00DBh (219)
00DBh (219)
00AFh (175)
00DBh (219)
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10.1.21 RAMWR (2Ch): Memory Write
2CH
Inst / Para
RAMWR
1st Parameter
∣
D/CX
0
1
1
1
WRX
↑
↑
↑
RDX
1
1
1
1
D17-8
D17-8
∣
Nth Parameter
↑
D17-8
NOTE: “-” Don’t care, can be set to VDDI or DGND level
RAMWR (Memory Write)
D7
D6
D5
D4
0
0
1
0
D7
D6
D5
D4
D3
1
D3
D2
1
D2
D1
0
D1
D0
0
D0
(Code)
(2Ch)
-
∣
∣
∣
∣
∣
∣
∣
∣
∣
D7
D6
D5
D4
D3
D2
D1
D0
-
-When this command is accepted, the column register and the row register are reset to the Start
Column/Start Row positions.
-The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 9.12)
-Sending any other command can stop Frame Write.
Description In all color modes, there is no restriction on length of parameters.
-1. 176x220 memory base (GM = ‘00’)
176x220x18-bit memory can be written by this command
Memory range: (0000h,0000h) -> (00AFh, 00DBh)
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared
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10.1.22 RAMHD (2Eh): Memory Read
2EH
Inst / Para
RAMHD
1st Parameter
2nd Parameter
D/CX
0
WRX
1
1
1
1
1
1
1
1
↑
RDX
1
D17-8
-
↑
↑
D17-8
∣
↑
∣
(N+1)th Parameter
↑
D17-8
NOTE: “-” Don’t care, can be set to VDDI or DGND level
RAMHD (Memory Read)
D7
D6
D5
D4
D3
0
0
1
0
1
D7
D6
D5
D4
D3
D2
1
D1
1
D0
0
(Code)
(2Eh)
D2
D1
D0
-
∣
∣
∣
∣
∣
∣
∣
∣
∣
D7
D6
D5
D4
D3
D2
D1
D0
-
-This command is used to transfer data from frame memory to MCU.
-When this command is accepted, the column register and the row register are reset to the Start
Column/Start Row positions.
-The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 9.12)
Description -Then D[17:0] is read back from the frame memory and the column register and the row register
incremented as section 9.10.2.
-Frame Read can be cancelled by sending any other command.
-See section 9.8 “Data color coding” for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit
data lines for image data.
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared
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10.1.25 PTLAR (30h): Partial Area
30H
Inst / Para
PTLAR
D/CX WRX
0
↑
1st Parameter
2nd Parameter
3rd Parameter
4th Parameter
1
1
1
1
RDX D17-8
1
1
1
1
1
↑
↑
↑
↑
-
D7
0
PTLAR (Partial Area)
D6
D5
D4
D3
0
1
1
0
D2
0
PSL15 PSL14 PSL13 PSL12 PSL11 PSL10
PSL7 PSL6 PSL5 PSL4 PSL3 PSL2
PEL15 PEL14 PEL13 PEL12 PEL11 PEL10
PEL7 PEL6 PEL5 PEL4 PEL3 PEL2
D1
0
D0
0
(Code)
(30h)
PSL9
PSL1
PEL9
PEL1
PSL8
PSL0
PEL8
PEL0
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command defines the partial mode’s display area.
-There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the
second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory
row address counter.
-If End Row > Start Row, when MADCTL ML=’0’
Start Row
Non-displaying Area
PSL [15:0]
Partial Display Area
PEL [15:0]
End Row
Non-displaying Area
-If End Row > Start Row, when MADCTL ML=’1’
End Row
PEL [15:0]
Description
Non-displaying Area
Partial Display Area
PSL [15:0]
Start Row
Non-displaying Area
-If End Row < Start Row, when MADCTL ML=’0’
End Row
PEL [15:0]
Partial Display Area
Non-displaying Area
PSL [15:0]
Partial Display Area
Start Row
-If End Row = Start Row then the Partial Area will be one row deep.
Default Value
Status
Default
Ver. 2.0
Power On Sequence
S/W Reset
H/W Reset
PSL
[15:0]
PEL [15:0]
0000h
00DBh
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10.1.23 SCRLAR (33h): Scroll Area
33H
Inst / Para
PTLAR
1st Parameter
2nd Parameter
3rd Parameter
4th Parameter
5th Parameter
6th Parameter
D/CX WRX RDX D17-8
0
↑
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
-
D7
0
SCRLAR (Scrolll Area)
D6
D5
D4
D3
0
1
1
0
D2
0
TFA15 TFA 14 TFA 13 TFA 12 TFA 11 TFA 10
TFA 7 TFA 6
TFA 5
TFA 4
TFA 3
TFA 2
VSA15 VSA 14 VSA 13 VSA 12 VSA 11 VSA 10
VSA 7 VSA 6 VSA 5 VSA 4 VSA 3 VSA 2
BFA15 BFA 14 BFA 13 BFA 12 BFA 11 BFA 10
BFA 7 BFA 6
BFA 5
BFA 4
BFA 3
BFA 2
D1
1
D0
1
(Code)
(33h)
TFA 9
TFA 1
VSA 9
VSA 1
BFA 9
BFA 1
TFA 8
TFA 0
VSA 8
VSA 0
BFA 8
BFA 0
00h
00h
00h
00h
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command defines the Vertical Scrolling Area of the display.
When MADCTL ML=0
st
nd
－The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame
Memory and Display).
rd
th
－The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of
the Frame Memory [not the display] from the Vertical Scrolling Start Address)
－The first line appears immediately after the bottom most line of the Top Fixed Area.
th
th
－The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the
Frame Memory and Display).
－TFA, VSA and BFA refer to the Frame Memory row address.
Top-Left (0,0)
Top Fixed Area
TFA [15:0]
First line read from
Scroll Fixed Area
VSFA [15:0]
Bottom Fixed Area
BFA [15:0]
When MADCTL ML=1
st
nd
－The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Bottom
Description of the Frame Memory and Display).
rd
th
－The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No.
of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address)
－The first line appears immediately after the top most line of the Top Fixed Area.
th
th
－The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Top
of the Frame Memory and Display).
Top-Left (0,0)
Bottom Fixed Area
BFA [15:0]
Scroll Fixed Area
VSFA [15:0]
First line read from
Top Fixed Area
frame memory
TFA [15:0]
See Section 9.10.1 for details of the Memory to Display Mapping.
-The condition is 0≦(TFA+VSA+BFA) ≦220, otherwise Scrolling mode is undefined.
-In Vertical Scroll Mode, MADCTL parameter MV should be set to ‘0’-this only affects the Frame Memory
Write.
Status
Default
Ver. 2.0
Power On Sequence
S/W Reset
H/W Reset
Default Value
VSA [15:0]
TFA [15:0]
0000h
BFA [15:0]
00DBh
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1. To Enter Vertical Scroll Mode
Normal Mode
Legend
Command
Parameter
SCRLAR (33h)
Display
1st & 2nd Parameter: TFA[15:0]
Action
3rd & 4th Parameter VSA[15:0]
Mode
5th & 6th Parameter BFA[15:0]
Sequential
transfer
CASET (2Ah)
1st & 2nd Parameter XS[15:0]
3rd & 4th Parameter XE[15:0]
RASET (2
Redefines the Frame
memory Window that
the scroll data will be
define
1st & 2nd Parameter YS[15:0]
Flow Chart
Only required
for non-rolling
scrolling
3rd & 4th Parameter YE[15:0]
MADCTL (36h)
Parameter: MY,MX,MV,ML,RGB
Optional –
It may be necessary
to redefine the Frame
Memory Write
Direction.
RAMRW (2Ch)
Scroll Image
Data
VSCSAD (37h)
1st & 2nd Parameter SS A[15:0]1
Scroll Mode
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed.
Ver. 2.0
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Legend
2. Continuous Scroll
Command
1st
Normal Mode
Parameter
CASET (2Ah)
Display
Action
&2nd Parameter XS[15:0]
Mode
rd
3
th
& 4 Parameter XE[15:0]
Sequential
transfer
RASET (2Bh)
1st & 2nd Parameter YS[15:0]
3rd & 4th Parameter YE[15:0]
RAMRW (2Ch)
Only required
for non-rolling
scrolling
Scroll Image
Data
VSCSAD (37h)
1st & 2nd Parameter SSA[15:0]1
3. To Exit Vertical Scroll Mode
Scroll Mode
DISOFF (28h)
OptionTo prevent
Tearing Effect
Image Display
NORON (13h) / PTLON (12h)
Scroll Mode OFF
RAMRW (2Ch)
Image Data
D1[17:0],D2[17:0]…
Dn[17:0]
DISON (29h)
NOTE: Scroll Mode can be exit by both the Normal Display Mode On (13h) and Partial Mode On (12h)
commands.
Ver. 2.0
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10.1.24 TEOFF (34h): Tearing Effect Line OFF
34H
Inst / Para
TEOFF
1st Parameter
D/CX
0
WRX
↑
RDX
1
TEOFF (Tearing Effect Line OFF)
D17-8
D7
D6
D5
D4
D3
0
0
1
1
0
No Parameter
D2
1
D1
0
D0
0
(Code)
(34h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
Description -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Status
Default Value
RCM1,RCM0 = ”00”,”1x”
RCM1,RCM0 = ”01”
Power On Sequence
S/W Reset
H/W Reset
Default
OFF
ON
10.1.25 TEON (35h): Tearing Effect Line ON
35H
Inst / Para
TEON
1st Parameter
D/CX
0
1
WRX
↑
↑
RDX
1
1
D17-8
-
TEON (Tearing Effect Line ON)
D7
D6
D5
D4
D3
0
0
1
1
0
0
0
0
0
D2
1
D1
0
D0
1
0
0
TELOM
0
(Code)
(35h)
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to turn ON the Tearing Effect output signal from the TE signal line.
-This output is not affected by changing MADCTL bit ML.
-The Tearing Effect Line On has one parameter, which describes the mode of the Tearing
Effect Output Line. (“-“=Don’t Care).
－When M=’0’:
The Tearing Effect Output line consists of V-Blanking information only.
tvdl
Description
tvdh
Vertical
time scale
－When M=’1’:
The Tearing Effect Output line consists of both V-Blanking and H-Blinking information.
tvdl
tvdh
Vertical
time scale
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Tearing effect off & TELOM=0
88
Tearing effect on & TELOM=0
2008-07-07
ST7773
10.1.26 MADCTL (36h): Memory Data Access Control
MADCTL (Memory Data Access Control)
36H
Inst / Para
MADCTL
1st Parameter
D/CX
0
1
WRX
↑
↑
RDX
1
1
D17-8
-
D7
0
D6
0
D5
1
D4
1
D3
0
D2
1
D1
1
D0
0
(Code)
(36h)
MY
MX
MV
ML
RGB
MH
0
0
00h
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command defines read/ write scanning direction of frame memory.
-Bit Assignment
Bit
MY
MX
MV
NAME
Row Address Order
Column Address Order
Row/Column Exchange
ML
Vertical Refresh Order
RGB
MH
DESCRIPTION
These 3bits controls MCU to memory
write/read direction. (See Section 9.12)
LCD vertical refresh direction control
‘0’ = LCD vertical refresh Top to Bottom
‘1’ = LCD vertical refresh Bottom to Top
Color selector switch control
‘0’ =RGB color filter panel,
‘1’ =BGR color filter panel)
LCD horizontal refresh direction control
‘0’ = LCD horizontal refresh Left to right
‘1’ = LCD horizontal refresh right to left
RGB-BGR ORDER
Horizontal Refresh Order
ML: Vertical Refresh Order
Memory
Display
Sent First
Sent 2nd
Sent 3rd
Top-Left (0,0)
ML=’0’
Sent Last
Description
Memory
Display
Sent Last
Top-Left (0,0)
ML=’1’
Sent 3rd
Sent 2nd
Sent First
RGB: RGB-BGR Order
RGB=”0”
Driver IC
RG
R
GB
B
SIG1
Ver. 2.0
RGB=”1”
Driver IC
RG
GB
R
B
SIG2
RG
R
GB
B
SIG176
SIG1
SIG2
SIG176
RGB
B
RGB
RG
RGB
B
RGB
B
RGB
B
RGB
B
LCD Panel
R
RG
GBB
RG
R
GB
B
SIG2
RG
R
G BB
SIG176
SIG1
SIG2
SIG176
B
GR
BG
B
RGR
BGR
B GR
B G RR
B
BG
GR
SIG1
B G RR
LCD Panel
89
2008-07-07
ST7773
MH: Horizontal refresh Order
Top-Left (0,0)
Top-Left (0,0)
Memory
ML=’0’
Sent First
Sent 2nd
Status
Power On Sequence
S/W Reset
H/W Reset
Top-Left (0,0)
Sent 3rd
Display
Sent Last
Ver. 2.0
Sent Last
Top-Left (0,0)
Default
ML=’1’
Sent 3rd
Sent 2nd
Sent First
Description
Memory
Display
Default Value
MY=0,MX=0,MV=0,ML=0,RGB=0, MH=0
No Change
MY=0,MX=0,MV=0,ML=0,RGB=0, MH=0
90
2008-07-07
ST7773
10.1.27 VSCSAD (37h): Vertical Scroll Start Address of RAM
37H
Inst / Para
VSCSAD
1st Parameter
2nd Parameter
VSCSAD (Vertical Scroll Start Address of RAM)
D/CX
0
1
1
WRX
↑
↑
↑
RDX
1
1
1
D17-8
-
D7
0
D6
0
D5
1
D4
1
D3
0
D2
1
D1
1
D0
1
(Code)
(37h)
00h
00h
0
0
0
0
0
0
0
SSA8
SSA7
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used together with Vertical Scrolling Definition (33h). These two commands describe the
scrolling area and the scrolling mode.
-The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame
Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated
below:
-This command Start the scrolling.
-Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h).
When MADCTL ML= ‘0’
Example:
－When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=220 and Vertical Scrolling
Pointer SSA= ’3’.
(Example)
Top-Left (0,0)
Description
Scan address
Memory
Display
0
1
2
3
∣
∣
218
219
SSA[15:0]
Scroll start address
G1
G2
G3
G4
|
|
G219
G220
When MADCTL ML = ‘1’
Example:
－When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=220 and SSA= ’3’
(Example)
Top-Left (0,0)
Scan address
Memory
Display
219
218
∣
∣
3
2
1
0
SSA[15:0]
Scroll start address
G1
G2
G3
G4
|
|
G219
G220
NOTE: -When new Pointer position and Picture Data are sent, the result on the display will happen at the next
Panel Scan to avoid tearing effect.
-SSA refers to the Frame Memory scan address.
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
0000h
0000h
0000h
91
2008-07-07
ST7773
10.1.28 IDMOFF (38h): Idle Mode Off
38H
IDMOFF (Idle Mode Off)
Inst / Para
IDMOFF
1st Parameter
D/CX
0
WRX
↑
RDX
1
D17-8
-
D7
D6
D5
0
0
1
No Parameter
D4
1
D3
1
D2
0
D1
0
D0
0
(Code)
(38h)
-
D1
0
D0
1
(Code)
(39h)
-
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to recover from Idle mode on.
-In the idle off mode,
Description
1. LCD can display 4096, 65k or 262k colors.
2. Normal frame frequency is applied.
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
10.1.29 IDMON (39h): Idle Mode On
39H
IDMON (Idle Mode On)
Inst / Para
IDMOFF
1st Parameter
D/CX
0
WRX
↑
RDX
1
D17-8
-
D7
D6
D5
0
0
1
No Parameter
D4
1
D3
1
D2
0
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to enter into Idle mode on.
-There will be no abnormal visible effect on the display mode change transition.
-In the idle on mode,
1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in
the Frame Memory, 8 color depth data is displayed.
2. 8-Color mode frame frequency is applied.
3. Exit from IDMON by Idle Mode Off (38h) command
(Example)
Top-Left (0,0)
Mem ory
Display
Description
Color
Black
Blue
Red
Magenta
Green
Cyan
Yellow
White
Default
Ver. 2.0
R5 R4 R3 R2 R1 R0
0xxxxx
0xxxxx
1xxxxx
1xxxxx
0xxxxx
0xxxxx
1xxxxx
1xxxxx
Status
Power On Sequence
S/W Reset
H/W Reset
G5 G4 G3 G2 G1 G0
0xxxxx
0xxxxx
0xxxxx
0xxxxx
1xxxxx
1xxxxx
1xxxxx
1xxxxx
B5 B4 B3 B4 B1 B0
0xxxxx
1xxxxx
0xxxxx
1xxxxx
0xxxxx
1xxxxx
0xxxxx
1xxxxx
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
92
2008-07-07
ST7773
10.1.30 COLMOD (3Ah): Interface Pixel Format
3AH
COLMOD (3Ah): Interface Pixel Format
Inst / Para
D/CX WRX
↑
COLMOD
0
↑
1st Parameter
1
RDX
1
1
D17-8
-
D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
1
D0
0
0
1
1
0
0
IFPF2
IFPF1
IFPF0
(Code)
(3Ah)
66h
NOTE: “-” Don’t care, can be set to VDDI or DGND level
This command is used to define the format of RGB picture data, which is to be transferred via the
MCU interface and RGB interface. The formats are shown in the table:
IFPF[2:0]
011
101
110
111
Description
MCU Interface Color Format
12-bit/pixel
16-bit/pixel
18-bit/pixel
No used
3
5
6
7
Others are no define and invalid
Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory.
Note 2: When VIPF[3:0]=”1110”,6-bit data width of 3-times transfer is used to transmit 1 pixel data with the 18-bit color
depth information.
Status
Default Value
Power On Sequence
06H(18-bit/Pixel)
VIPF[3:0]
Default
S/W Reset
No Change
H/W Reset
06H(18-bit/Pixel)
10.1.31 RDID1 (DAh): Read ID1 Value
DAH
RDID1 (Read ID1 Value)
Inst / Para
RDID1
D/CX
0
WRX
1st Parameter
2nd Parameter
1
1
1
1
↑
RDX
1
D17-8
-
D7
1
D6
1
D5
0
D4
1
D3
1
D2
0
D1
1
D0
0
(Code)
(DAh)
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
-
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This read byte returns 8-bit LCD module’s manufacturer ID
st
-The 1 parameter is dummy data
Description
nd
-The 2 parameter (ID17 to ID10): LCD module’s manufacturer ID.
nd
NOTE: See command RDDID (04h), 2 parameter.
Default
Ver. 2.0
Status
Power On Sequence
Default Value
S/W Reset
29h
H/W Reset
29h
-
93
2008-07-07
ST7773
10.1.32 RDID2 (DBh): Read ID2 Value
DBH
RDID2 (Read ID2 Value)
Inst / Para
RDID2
D/CX
0
WRX
1st Parameter
2nd Parameter
1
1
1
1
↑
RDX
1
D17-8
-
D7
1
D6
1
D5
0
D4
1
D3
1
D2
0
D1
1
D0
1
(Code)
(DBh)
↑
-
‘1’
ID26
ID25
ID24
ID23
ID22
ID21
ID20
-
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This read byte returns 8-bit LCD module/driver version ID
st
-The 1 parameter is dummy data
nd
Description -The 2 parameter (ID26 to ID20): LCD module/driver version ID
-Parameter Range: ID=80h to FFh
Default
Ver. 2.0
Status
Power On Sequence
Default Value
S/W Reset
81h
H/W Reset
81h
-
94
2008-07-07
ST7773
10.2.1 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)
B1H
Inst / Para
D/CX
WRX
RDX
FRMCTR1
0
↑
1
1st Parameter
2nd Parameter
3rd Parameter
Nth Parameter
1
↑
↑
↑
↑
1
D1
7-8
-
1
1
1
-
1
1
1
FRMCTR1 (Frame Rate Control)
D7
D6
D5
D4
D3
1
0
1
1
0
D2
D1
D0
(Code)
0
0
1
(B1h)
RTNA[7:0]
FPA[4:0]
BPA[4:0]
RTNA_VSYNC[7:0]
3Bh
04h
03h
38h
NOTE: “-“ Don’t care
-Set the frame frequency of the full colors normal mode,recommend to set under 110Hz.
-The frame frequency need to meet 60Hz±5% in this mode
RTNA[7:0]
Description
Ver. 2.0
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
Frame Rate
110
107
104
101
98
95
93
90
88
86
84
82
80
78
77
75
73
72
70
69
68
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
52
51
50
49
49
48
48
47
46
46
45
95
RTNA[7:0]
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Frame Rate
44
43
43
42
42
41
41
41
40
40
39
39
38
38
37
37
37
36
36
36
35
35
35
34
34
34
33
33
33
32
32
32
31
31
31
31
30
30
30
30
29
29
29
29
28
28
28
2008-07-07
ST7773
1001111
79
45
1111111
127
28
Note: OSC output fre. Is 800KHz, FPA=04H and BPA=03H
FPA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Default
Ver. 2.0
Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0 line
1 line
2 lines
3 lines
4 lines
5 lines
6 lines
7 lines
8 lines
9 lines
10 lines
11 lines
12 lines
13 lines
14 lines
15 lines
16 lines
17 lines
18 lines
19 lines
20 lines
21 lines
22 lines
23 lines
24 lines
25 lines
26 lines
27 lines
28 lines
29 lines
30 lines
31 lines
Status
Power On Sequence
S/W Reset
H/W Reset
BPA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0 line
1 line
2 lines
3 lines
4 lines
5 lines
6 lines
7 lines
8 lines
9 lines
10 lines
11 lines
12 lines
13 lines
14 lines
15 lines
16 lines
17 lines
18 lines
19 lines
20 lines
21 lines
22 lines
23 lines
24 lines
25 lines
26 lines
27 lines
28 lines
29 lines
30 lines
31 lines
Default Value
3B/04/03/38 H
3B/04/03/38 H
96
2008-07-07
ST7773
10.2.2 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)
B2H
Inst / Para
FRMCTR2
D/CX
0
1st Parameter
2nd Parameter
3rd Parameter
1
1
1
WRX
↑
↑
↑
↑
RDX
1
1
1
1
FRMCTR2 (Frame Rate Control)
D17-8
D7
D6
D5
D4
D3
1
0
1
1
0
RTNB[7:0]
-
-
-
-
D2
0
D1
1
FPB[4:0]
BPB[4:0]
D0
0
(Code)
(B2h)
3Bh
04h
03h
NOTE: “-“ Don’t care
-Set the frame frequency of the full colors idle mode, ,recommend to set under 110Hz.
-The frame frequency need to meet 60Hz±5% in this mode
RTNB[7:0]
Description
Ver. 2.0
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
Frame Rate
110
107
104
101
98
95
93
90
88
86
84
82
80
78
77
75
73
72
70
69
68
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
52
51
50
49
49
48
48
47
46
46
45
97
RTNB[7:0]
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Frame Rate
44
43
43
42
42
41
41
41
40
40
39
39
38
38
37
37
37
36
36
36
35
35
35
34
34
34
33
33
33
32
32
32
31
31
31
31
30
30
30
30
29
29
29
29
28
28
28
2008-07-07
ST7773
1001111
79
45
1111111
127
28
Note: OSC output fre. Is 800KHz, FPB=04H and BPB=03H
FPB[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Default
Ver. 2.0
Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0 line
1 line
2 lines
3 lines
4 lines
5 lines
6 lines
7 lines
8 lines
9 lines
10 lines
11 lines
12 lines
13 lines
14 lines
15 lines
16 lines
17 lines
18 lines
19 lines
20 lines
21 lines
22 lines
23 lines
24 lines
25 lines
26 lines
27 lines
28 lines
29 lines
30 lines
31 lines
Status
Power On Sequence
S/W Reset
H/W Reset
BPB[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0 line
1 line
2 lines
3 lines
4 lines
5 lines
6 lines
7 lines
8 lines
9 lines
10 lines
11 lines
12 lines
13 lines
14 lines
15 lines
16 lines
17 lines
18 lines
19 lines
20 lines
21 lines
22 lines
23 lines
24 lines
25 lines
26 lines
27 lines
28 lines
29 lines
30 lines
31 lines
Default Value
3B/04/03 H
3B/04/03 H
98
2008-07-07
ST7773
10.2.3 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)
B3H
Inst / Para
FRMCTR3
D/CX
0
1st Parameter
2nd Parameter
3rd Parameter
1
1
1
WRX
↑
↑
↑
↑
RDX
1
1
1
1
FRMCTR3 (Frame Rate Control)
D17-8
D7
D6
D5
D4
D3
1
0
1
1
0
RTNC[7:0]
D2
0
D1
1
FPC[4:0]
BPC[4:0]
-
D0
1
(Code)
(B3h)
3Bh
04h
03h
NOTE: “-“ Don’t care
-Set the frame frequency of the full colors partial mode,recommend to set under 110Hz.
-The frame frequency need to meet 60Hz±5% in this mode
RTNC[7:0]
Description
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Frame Rate
110
107
104
101
98
95
93
90
88
86
84
82
80
78
77
75
73
72
70
69
68
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
52
51
50
49
49
48
48
47
46
46
45
45
RTNC[7:0]
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Frame Rate
44
43
43
42
42
41
41
41
40
40
39
39
38
38
37
37
37
36
36
36
35
35
35
34
34
34
33
33
33
32
32
32
31
31
31
31
30
30
30
30
29
29
29
29
28
28
28
28
Note: OSC output fre. Is 800KHz, FPC=04H and BPC=03H
Ver. 2.0
99
2008-07-07
ST7773
FPC[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Default
Ver. 2.0
Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0 line
1 line
2 lines
3 lines
4 lines
5 lines
6 lines
7 lines
8 lines
9 lines
10 lines
11 lines
12 lines
13 lines
14 lines
15 lines
16 lines
17 lines
18 lines
19 lines
20 lines
21 lines
22 lines
23 lines
24 lines
25 lines
26 lines
27 lines
28 lines
29 lines
30 lines
31 lines
Status
Power On Sequence
S/W Reset
H/W Reset
BPC[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0 line
1 line
2 lines
3 lines
4 lines
5 lines
6 lines
7 lines
8 lines
9 lines
10 lines
11 lines
12 lines
13 lines
14 lines
15 lines
16 lines
17 lines
18 lines
19 lines
20 lines
21 lines
22 lines
23 lines
24 lines
25 lines
26 lines
27 lines
28 lines
29 lines
30 lines
31 lines
Default Value
3B/04/03 H
3B/04/03 H
100
2008-07-07
ST7773
10.2.4 INVCTR (B4h): Display Inversion Control
B4H
Inst / Para
INVCTR
D/CX
0
1st Parameter
1
WRX
↑
↑
RDX
1
INVCTR (Display Inversion Control)
D17-8
D7
D6
D5
D4
D3
D2
1
0
1
1
0
1
-
1
-
0
0
0
0
0
NLA
D1
0
D0
0
(Code)
(B4h)
NLB
NLC
NOTE: “-“ Don’t care
-Display Inversion mode control
-NLA: Inversion setting in full colors normal mode (Normal mode on)
NLA
0
1
Inversion setting in full Colors normal mode
Line Inversion
Frame Inversion
-NLB: Inversion setting in Idle mode (Idle mode on)
Description
NLB
0
1
Inversion setting in Idle mode
Line Inversion
Frame Inversion
-NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off)
NLC
0
1
Inversion setting in full Colors partial mode
Line Inversion
Frame Inversion
Status
Default
Ver. 2.0
Power On Sequence
S/W Reset
H/W Reset
NLA
0d
No Change
0d
101
Default Value
NLB
NLC
1d
0d
No Change
No Change
1d
0d
B4h
02h
No Change
02h
2008-07-07
ST7773
10.2.5 DISSET5 (B6h): Display Function set 5
DISSET (Display Function set 5)
B6H
Inst / Para
DISSET5
D/CX
0
1st Parameter
2nd Parameter
1
1
WRX
↑
↑
↑
RDX
1
D17-8
-
1
1
-
D7
1
0
0
D6
0
0
0
D5
1
NO1
0
D4
1
NO0
0
D3
0
SDT1
PTG1
D2
1
SDT0
PTG0
D1
1
EQ1
PT1
D0
0
EQ0
PT0
(Code)
(B6h)
15h
00h
NOTE: “-“ Don’t care
-1st parameter: Set output waveform relation.
-NO[1:0]: Set the amount of non-overlap of the gate output
NO[1:0]
00
01
10
11
0
1
2
3
Amount of non-overlap of the gate output
Refer the Internal oscillator
Refer the PCLK
No
4 clock cycle
1 clock cycle
16 clock cycle
4 clock cycle
24 clock cycle
6 clock cycle
32 clock cycle
-SDT[1:0]: Set delay amount from gate signal falling edge of the source output.
SDT[1:0]
00
01
10
11
0
1
2
3
Amount of non-overlap of the gate output
Refer the Internal oscillator
Refer the PCLK
No
4 clock cycle
1 clock cycle
8 clock cycle
2 clock cycle
12clock cycle
3 clock cycle
16 clock cycle
-EQ[1:0]: Set the Equalizing period
EQ[1:0]
00
01
10
11
0
1
2
3
Amount of non-overlap of the gate output
Refer the Internal oscillator
Refer the PCLK
No EQ
No EQ
2 clock cycle
4 clock cycle
4 clock cycle
16 clock cycle
6 clock cycle
24 clock cycle
Description
Gate Non-overlap period
Gn
Gn+1
Sn
VCOM
Delay time for
source output
EQ period
-2nd parameter: Set the output waveform in non-display area.
-PTG[1:0]: Determine gate output in a non-display area in the partial mode
PTG[1:0]
00
01
10
11
Gate output in a non-display area
Normal scan
Fix on VGL
Fix on VGL
Fix on VGL
0
1
2
3
-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode
PT[1:0]
00
01
10
11
Ver. 2.0
0
1
2
3
Source output on non-display area
Positive
Negative
V63
V0
V0
V63
AGND
AGND
Hi-z
Hi-z
102
VCOM output on non-display area
Positive
Negative
VCOML
VCOMH
VCOML
VCOMH
AGND
AGND
AGND
AGND
2008-07-07
ST7773
Status
Default
Ver. 2.0
Power On Sequence
S/W Reset
H/W Reset
Default Value
NO[1:0]
STD[1:0]
EQ[1:0]
PTG[1:0]
PT[1:0]
01H
01H
01H
01H
01H
01H
01H
01H
01H
01H
01H
01H
10H
10H
10H
103
2008-07-07
ST7773
10.2.8 PWCTR1 (C0h): Power Control 1
C0H
Inst / Para
PWCTR1
D/CX
0
1st Parameter
1
WRX
↑
↑
RDX
1
D17-8
-
1
-
PWCTR1 (Power Control 1)
D7
D6
D5
D4
D3
1
1
0
0
0
0
0
0
VRH4
VRH3
D2
0
D1
0
D0
0
(Code)
(C0h)
VRH2
VRH1
VRH0
NOTE: “-“ Don’t care
Description -Set the GVDD and VCI1 voltage
VRH[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GVDD
5.00
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
3.75
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
3.25
3.00
Status
Default
Ver. 2.0
Default Value
TM LC type
VRH[4:0]
05H
05H
05H
Power On Sequence
S/W Reset
H/W Reset
104
2008-07-07
ST7773
10.2.9 PWCTR2 (C1h): Power Control 2
C1H
Inst / Para
PWCTR2
D/CX
0
1st Parameter
1
WRX
↑
↑
RDX
1
D17-8
-
1
PWCTR2 (Power Control 2)
D7
D6
D5
D4
D3
1
1
0
0
0
VGH3
VGH2
VGH1
VGH0
VGL3
D2
0
D1
0
D0
1
(Code)
(C1h)
VGL2
VGL1
VGL0
BBh
NOTE: “-“ Don’t care
-Set the VGH and VGL supply power level
VGH[3:0]/VGL[3:0]
Description
VGH
VGL
0000
0
10
-5.5
0001
1
10.5
-6
0010
2
11
-7.5
0011
3
11.5
-8
0100
4
12
-8.5
0101
5
12.5
-9
0110
6
13
-9.5
0111
7
13.5
-10
1000
8
14
-10.5
1001
9
14.5
-11
1010
10
15
-11.5
1011
11
15.5
-12
1100
12
16
-12.5
1101
13
16.5
-13
1110
14
X
-13.5
1111
15
X
X
Unit(V)
Status
Default
Ver. 2.0
Power On Sequence
S/W Reset
H/W Reset
Default Value
VGH[3:0]
0Bh
0Bh
105
VGL[3:0]
0Bh
0Bh
2008-07-07
ST7773
10.2.10 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors)
C2H
Inst / Para
PWCTR3
D/CX
0
1st Parameter
1
WRX
↑
↑
RDX
1
D17-8
-
1
-
PWCTR3 (Power Control 3)
D7
D6
D5
D4
D3
1
1
0
0
0
0
0
0
0
0
D2
0
D1
1
D0
0
(Code)
(C2h)
APA2
APA1
APA0
04h
NOTE: “-“ Don’t care
-Set the amount of current in Operational amplifier in normal mode/full colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the
source driver.
APA[2:0]
000
001
010
011
100
101
110
111
Description
Default
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Reserved
Reserved
0
1
2
3
4
5
6
7
Status
Default Value
APA[2:0]
Power On Sequence
S/W Reset
H/W Reset
04h
04h
10.2.11 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors)
C3H
Inst / Para
PWCTR4
D/CX
0
1st Parameter
1
WRX
↑
↑
RDX
1
D17-8
-
1
-
PWCTR4 (Power Control 4)
D7
D6
D5
D4
D3
1
1
0
0
0
0
0
0
0
0
D2
0
D1
1
D0
1
(Code)
(C3h)
APB2
APB1
APB0
NOTE: “-“ Don’t care
-Set the amount of current in Operational amplifier in Idle mode/8 colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the
source driver.
Description
Default
Ver. 2.0
APB[2:0]
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Reserved
Reserved
Status
Default Value
APB[2:0]
Power On Sequence
S/W Reset
H/W Reset
04h
04h
106
2008-07-07
ST7773
10.2.12 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors)
C4H
Inst / Para
PWCTR5
D/CX
0
1st Parameter
1
WRX
↑
↑
RDX
1
D17-8
-
1
-
PWCTR5 (Power Control 5)
D7
D6
D5
D4
D3
1
1
0
0
0
0
0
0
0
0
D2
1
D1
0
D0
0
(Code)
(C4h)
APC2
APC1
APC0
04h
NOTE: “-“ Don’t care
-Set the amount of current in Operational amplifier in Partial mode/ full-colors.
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the
source driver.
Description
Default
Ver. 2.0
APC[2:0]
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Reserved
Reserved
Status
Default Value
APC[2:0]
Power On Sequence
S/W Reset
H/W Reset
04h
04h
107
2008-07-07
ST7773
10.2.13 VMCTR1 (C5h): VCOM Control 1
C5H
Inst / Para
VMCTR1
D/CX
0
1st Parameter
2nd Parameter
WRX
1
1
↑
↑
↑
RDX
1
D17-8
-
1
-
1
VMCTR1 (VCOM Control 1)
D7
D6
D5
D4
D3
1
1
0
0
0
0
0
VMH6
VML 6
D2
1
D1
0
D0
1
(Code)
(C5h)
VMH5 VMH 4 VMH 3 VMH 2 VMH 1 VMH 0
VML 5 VML 4 VML 3 VML 2 VML 1 VML 0
3Ch
3Ch
NOTE: “-“ Don’t care
Description -Set VCOMH Voltage
VMH[6:0]
0000000
0
0000001
1
0000010
2
0000011
3
0000100
4
0000101
5
0000110
6
0000111
7
0001000
8
0001001
9
0001010
10
0001011
11
0001100
12
0001101
13
0001110
14
0001111
15
0010000
16
0010001
17
0010010
18
0010011
19
0010100
20
0010101
21
0010110
22
0010111
23
0011000
24
0011001
25
0011010
26
VCOMH
2.500
2.525
2.550
2.575
2.600
2.625
2.650
2.675
2.700
2.725
2.750
2.775
2.800
2.825
2.850
2.875
2.900
2.925
2.950
2.975
3.000
3.025
3.050
3.075
3.100
3.125
3.150
VMH[6:0]
0011011
27
0011100
28
0011101
29
0011110
30
0011111
31
0100000
32
0100001 33
0100010
34
0100011
35
0100100
36
0100101
37
0100110
38
0100111
39
0101000
40
0101001
41
0101010
42
0101011
43
0101100
44
0101101
45
0101110
46
0101111
47
0110000
48
0110001
49
0110010
50
0110011
51
0110100
52
0110101
53
VCOMH
VML[6:0]
0011011
0011100
0011101
0011110
0011111
0100000
VCOML
3.175
3.200
3.225
3.250
3.275
3.300
3.325
3.350
3.375
3.400
3.425
3.450
3.475
3.500
3.525
3.550
3.575
3.600
3.625
3.650
3.675
3.700
3.725
3.750
3.775
3.800
3.825
VMH[6:0]
0110110
54
0110111
55
0111000
56
0111001
57
0111010
58
0111011
59
0111100
60
0111101
61
0111110
62
0111111
63
1000000
64
1000001
65
1000010
66
1000011
67
1000100
68
1000101
69
1000110
70
1000111
71
1001000
72
1001001
73
1001010
74
1001011
75
1001100
76
1001101
77
1001110
78
1001111
79
1010000
80
VCOMH
VML[6:0]
0110110
54
0110111
55
0111000
56
0111001
57
0111010
58
0111011
59
0111100
60
0111101
61
0111110
62
0111111
63
1000000
64
1000001
65
1000010
66
1000011
67
1000100
68
1000101
69
1000110
70
1000111
71
1001000
72
1001001
73
1001010
74
1001011
75
1001100
76
1001101
77
1001110
78
1001111
79
1010000
80
VCOML
3.850
3.875
3.900
3.925
3.950
3.975
4.000
4.025
4.050
4.075
4.100
4.125
4.150
4.175
4.200
4.225
4.250
4.275
4.300
4.325
4.350
4.375
4.400
4.425
4.450
4.475
4.500
VMH[6:0]
1010001
81
1010010
82
1010011
83
1010100
84
1010101
85
1010110
86
1010111
87
1011000
88
1011001
89
1011010
90
1011011
91
1011100
92
1011101
93
1011110
94
1011111
95
1100000
96
1100001
97
1100010
98
1100011
99
1100100
100
1100101
101
|
1111111
127
VCOMH
4.525
4.550
4.575
4.600
4.625
4.650
4.675
4.700
4.725
4.750
4.775
4.800
4.825
4.850
4.875
4.900
4.925
4.950
4.975
5.000
Not
Permitted
-Set VCOML Voltage
VML[6:0]
0000000
0
0000001
1
0000010
2
0000011
3
0000100
4
0000101
5
0000110
6
0000111
7
0001000
8
0001001
9
0001010
10
0001011
11
0001100
12
0001101
13
0001110
14
0001111
15
0010000
16
0010001
17
0010010
18
0010011
19
0010100
20
0010101
21
0010110
22
0010111
23
0011000
24
0011001
25
0011010
26
Ver. 2.0
VCOML
-2.500
-2.475
-2.450
-2.425
-2.400
-2.375
-2.350
-2.325
-2.300
-2.275
-2.250
-2.225
-2.200
-2.175
-2.150
-2.125
-2.100
-2.075
-2.050
-2.025
-2.000
-1.975
-1.950
-1.925
-1.900
-1.875
-1.850
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
-1.825
-1.800
-1.775
-1.750
-1.725
-1.700
-1.675
-1.650
-1.625
-1.600
-1.575
-1.550
-1.525
-1.500
-1.475
-1.450
-1.425
-1.400
-1.375
-1.350
-1.325
-1.300
-1.275
-1.250
-1.225
-1.200
-1.175
108
-1.150
-1.125
-1.100
-1.075
-1.050
-1.025
-1.000
-0.975
-0.950
-0.925
-0.900
-0.875
-0.850
-0.825
-0.800
-0.775
-0.750
-0.725
-0.700
-0.675
-0.650
-0.625
-0.600
-0.575
-0.550
-0.525
-0.500
VML[6:0]
1010001
81
1010010
82
1010011
83
1010100
84
1010101
85
1010110
86
1010111
87
1011000
88
1011001
89
1011010
90
1011011
91
1011100
92
1011101
93
1011110
94
1011111
95
1100000
96
1100001
97
1100010
98
1100011
99
1100100
100
1100101
101
|
1111111
127
VCOML
-0.475
-0.450
-0.425
-0.400
-0.375
-0.350
-0.325
-0.300
-0.275
-0.250
-0.225
-0.200
-0.175
-0.150
-0.125
-0.100
-0.075
-0.050
-0.025
0.000
Not
Permitted
2008-07-07
ST7773
Status
Default
Default Value
LCM = “01”
TM LC type
VMH[6:0] / VML[6:0]
3Ch / 3C h
3Ch / 3Ch
Power On Sequence
S/W Reset
H/W Reset
10.2.14 VMOFCTR (C7h): VCOM Offset Control
C7H
Inst / Para
VMOFCTR
D/CX
0
WRX
1st Parameter
1
↑
RDX
1
D17-8
-
↑
1
-
VMOFCTR (VCOM Offset Control)
D7
D6
D5
D4
D3
1
1
0
0
0
0
VMF6
VMF5
VMF4
VMF3
D2
1
D1
1
D0
1
(Code)
(C7h)
VMF2
VMF1
VMF0
3Ch
NOTE: “-“ Don’t care, can be set to VDDI or DGND level
-Set VCOM Voltage level for reduce the flicker issue
Description
VMF[6:0]
4
5
6
|
58
59
60
61
62
|
126
127
VCOMH Output Level
“VMH”-64d
“VMH”-63d
“VMH”-62d
|
“VMH”-2d
“VMH”-1d
“VMH”
“VMH”+1d
“VMH”+2d
|
“VMH”+62d
“VMH”+63d
VCOML Output Level
“VML”-60d
“VML”-59d
“VML”-58d
|
“VML”-2d
“VML”-1d
“VML”
“VML”+1d
“VML”+2d
|
“VML”+62d
“VML”+63d
-IF “VMH”-xd or “VML”-xd is less than 0d, it becomes 0d.
-IF”VMH”+xd or “VML”+xd is large than 100d, it becomes 100d.
-VMF[6:0] are stored in NV memory to contrast.
-The nVM need be used in
Default
Ver. 2.0
1st parameter of VMOFCTR (C7h)
Status
Default Value VMF[5:0]
Power Mode On Sequence
3Ch
S/W Reset
3Ch
H/W Reset
3Ch
109
2008-07-07
ST7773
10.2.15 STEP CTR (C9h): step1/2/4 booster frequency control
BEH
Inst / Para
RDVMOF
RDVMOF (Read the VCOM Offset Value NV memory)
D/CX WRX RDX D17-8 D7
D6
D5
D4
D3
D2
D1
0
↑
1
1
1
0
0
1
0
0
1st Parameter
2nd Parameter
2nd Parameter
1
1
1
↑
↑
↑
1
1
1
-
1
0
0
NW_MODE
0
0
0
0
0
0
0
0
0
DUAL_EN STEP_DIV_EN
D0
1
CP1_FREQ_SEL[2:0]
CP2_FREQ_SEL[2:0]
CP4_FREQ_SEL[2:0]
(Code)
(C9h)
A4h
04h
04h
NOTE: “-“ Don’t care
DUAL_EN：STEP1/2/4 booster mode select, default：1(Dual mode)
STEP_DIV_EN：STEP1/2/3 CLK select OSC frequency divid 4 enable,0(default),1：divid 4
NW_MODE：select panel type,0=Normally White,1=Normally Black
STEP_DIV_EN
Description
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
000
001
010
011
100
101
110
111
STEP_DIV_EN
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Default
Ver. 2.0
CP1_FREQ_SEL[2:0]
0
1
2
3
4
5
6
7
CP4_FREQ_SEL[2:0]
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Step-up cycle
in Booster circuit1
OSC/1024, OSC/4096
OSC/512, OSC/2048
OSC/256, OSC/1024
OSC/128, OSC/512
OSC/64, OSC/256
OSC/32, OSC/128
OSC/16, OSC/64
OSC/8, OSC/32
CP2_FREQ_SEL[2:0]
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Step-up cycle
in Booster circuit 2
OSC/1024, OSC/4096
OSC/512, OSC/2048
OSC/256, OSC/1024
OSC/128, OSC/512
OSC/64, OSC/256
OSC/32, OSC/128
OSC/16, OSC/64
OSC/8, OSC/32
Step-up cycle
in Booster circuit4
OSC/1024, OSC/4096
OSC/512, OSC/2048
OSC/256, OSC/1024
OSC/128, OSC/512
OSC/64, OSC/256
OSC/32, OSC/128
OSC/16, OSC/64
OSC/8, OSC/32
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
A4h/04h/04h
A4h/04h/04h
110
2008-07-07
ST7773
10.2.16 RD PULSE CTR (F4h): Adjust read GRAM timing control function
F8H
Inst / Para
D/CX
8-color detect
0
1st Parameter
1
WRX
↑
RDX
1
D17-8
-
↑
1
-
VMOFCTR (VCOM Offset Control)
D7
D6
D5
D4
D3
1
1
1
1
1
0
1
0
1
D2
0
D1
0
D0
0
RD_PULSE_WIDTH[3:0]
(Code)
(F4h)
55h
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used toadjust read GRAM timing control function
Description
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
55h
55h
55h
10.2.17 8-color (F8h): 8 color detect function
F8H
Inst / Para
D/CX
8-color detect
0
1st Parameter
1
WRX
↑
RDX
1
D17-8
-
↑
1
-
VMOFCTR (VCOM Offset Control)
D7
D6
D5
D4
D3
1
1
1
1
1
0
0
0
0
0
D2
0
D1
0
D0
0
(Code)
(F8h)
8-color
0
0
04h
NOTE: “-” Don’t care, can be set to VDDI or DGND level
Description
Default
Ver. 2.0
-This command is used to turn on/off 8-color detect function
1：enable 8-color detect function
0：disable 8-color detect function
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
04h
04h
04h
111
2008-07-07
ST7773
10.2.18 PWCTR6 (FCh): Power Control 6
FCH
Inst / Para
PWCTR6
RDVMOF (Read the VCOM Offset Value NV memory)
D/CX WRX RDX D17-8 D7
D6
D5
D4
D3
D2
D1
0
↑
1
1
1
1
1
1
1
0
1st Parameter
2nd Parameter
2nd Parameter
1
1
1
↑
↑
↑
1
1
1
-
0
0
0
0
1
0
1
1
0
1
1
0
1
1
0
D0
0
SAPA[2:0]
SAPB[2:0]
SAPC[2:0]
(Code)
(FCh)
3Ch
7Ch
04h
NOTE: “-“ Don’t care
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the
gate driver.
-SAPA[2:0]：Set the amount of current in Operational amplifier in Normal mode.
SAPA[2:0]
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large Low
Large
Large High
-SAPB[2:0]：Set the amount of current in Operational amplifier in Idle mode.
Description
SAPA[2:0]
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large Low
Large
Large High
-SAPC[2:0]：Set the amount of current in Operational amplifier in Partial/Full color mode.
SAPC[2:0]
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Default
Ver. 2.0
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large Low
Large
Large High
Status
Default Value
SAPA[2:0]/ SAPB[2:0]/SAPC[2:0]
Power On Sequence
S/W Reset
H/W Reset
3C/7C/04h
3C/7C/04h
112
2008-07-07
ST7773
10.2.19 WRID2 (D1h): Write ID2 Value
D1H
Inst / Para
WRID2
D/CX
0
1st Parameter
1
WRX
↑
↑
RDX
1
D17-8
-
D7
1
1
-
1
WRID2 (Write ID2 Value)
D6
D5
D4
D3
1
0
1
0
ID26
ID25
ID24
ID23
D2
0
D1
0
D0
1
(Code)
(D1h)
ID22
ID21
ID20
-
NOTE: “-“ Don’t care
Description
-Write 7-bit data of LCD module version to save it to NV memory.
-The 1st parameter ID2[6:0] is LCD Module version ID.
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
-
10.2.20 NVFCTR2 (DEh): NV Memory Function Controller 2
DEH
Inst / Para
NVFCTR1
st
1 Parameter
D/CX
0
1
WRX
↑
↑
NVFCTR1 (NV Memory Function Controller 2)
RDX
D17-8 D7
D6
D5
D4
D3
D2
1
1
1
0
1
1
1
1
0
1
0
1
0
1
D1
1
0
D0
0
1
(Code)
(DEh)
75
NOTE: “-“ Don’t care
1. EEPROM burst read
Description
Default
Ver. 2.0
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Not Fixed
Not Fixed
Not Fixed
113
2008-07-07
ST7773
EEPROM Burst Read
MCU write DEh
Parameter1 (75)
EEPROM CELL
serial out
Write to all Register
Flow
Chart
N
EEPROM RDY
Polling D9h bit0
Y
Next MCU Command
10.2.21 NVFCTR3 (DFh): NV Memory Function Controller 3
DFH
Inst / Para
NVFCTR1
st
1 Parameter
nd
2 Parameter
rd
3 Parameter
rd
4 Parameter
rd
5 Parameter
D/CX
0
1
1
1
1
1
WRX
↑
↑
↑
↑
↑
↑
NVFCTR1 (NV Memory Function Controller 3
RDX
D17-8 D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
(Code)
(DFh)
CA
00
AA
A5
5A
NOTE: “-“ Don’t care
Description EEPROM Write Command
1. EEPROM burst write
Description
Ver. 2.0
114
2008-07-07
ST7773
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Not Fixed
Not Fixed
Not Fixed
Flow
Chart
Ver. 2.0
115
2008-07-07
ST7773
10.2.22 GMCTRP1 (E0h): Gamma (‘+’polarity) Correction Characteristics Setting
E0H
Inst / Para
GMCTRP0 (Gamma ‘+’polarity Correction Characteristics Setting)
D/CX WRX RDX D17-8 D7 D6
D5
D4
D3
D2
D1
GMCTRP1
0
↑
1
-
1
1
st
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
1 Parameter
nd
2 Parameter
rd
3 Parameter
th
4 Parameter
th
5 Parameter
th
6 Parameter
th
7 Parameter
th
8 Parameter
th
9 Parameter
th
10 Parameter
th
11 Parameter
th
12 Parameter
th
13 Parameter
th
14 Parameter
th
15 Parameter
th
16 Parameter
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
0
0
0
0
D0
(Code)
0
(E0h)
VRF0P[5] VRF0P[4] VF0P[3] VRF0P[2] VRF0P[1] VRF0P[0]
VOS0P[5] VOS0P[4] VOS0P[3] VOS0P[2] VOS0P[1] VOS0P[0]
PK0P[5]
PK0P[4]
PK0P[3]
PK0P[2]
PK0P[1]
PK0P[0]
PK1P[5]
PK1P[4]
PK1P[3]
PK1P[2]
PK1P[1]
PK1P[0]
PK2P[5]
PK2P[4]
PK2P[3]
PK2P[2]
PK2P[1]
PK2P[0]
PK3P[5]
PK3P[4]
PK3P[3]
PK3P[2]
PK3P[1]
PK3P[0]
PK4P[5]
PK4P[4]
PK4P[3]
PK4P[2]
PK4P[1]
PK4P[0]
PK5P[5]
PK5P[4]
PK5P[3]
PK5P[2]
PK5P[1]
PK5P[0]
PK6P[5]
PK6P[4]
PK6P[3]
PK6P[2]
PK6P[1]
PK6P[0]
PK7P[5]
PK7P[4]
PK7P[3]
PK7P[2]
PK7P[1]
PK7P[0]
PK8P[5]
PK8P[4]
PK8P[3]
PK8P[2]
PK8P[1]
PK8P[0]
PK9P[5]
PK9P[4]
PK9P[3]
PK9P[2]
PK9P[1]
PK9P[0]
SELV0P[5] SELV0P[4] SELV0P[3] SELV0P[2] SELV0P[1] SELV0P[0]
SELV1P[5] SELV1P[4] SELV1P[3] SELV1P[2] SELV1P[1] SELV1P[0]
SELV62P[5] SELV62P[4] SELV62P[3] SELV62P[2] SELV62P[1] SELV62P[0]
SELV63P[5] SELV63P[4] SELV63P[3] SELV63P[2] SELV63P[1] SELV63P[0]
NOTE: “-“ Don’t care
Register Group
Negative Polarity
High level adjustment
VRF0P[5:0]
SELV0P[5:0]
SELV1P[5:0]
PK0P[5:0]
PK1P[5:0]
PK2P[5:0]
PK3P[5:0]
Description
PK4P[5:0]
Mid level adjustment
PK5P[5:0]
PK6P[5:0]
PK7P[5:0]
PK8P[5:0]
PK9P[5:0]
SELV62P[5:0]
SELV63P[5:0]
Low level adjustment
Ver. 2.0
VOS0P[5:0]
116
Set-up Contents
Variable resistor VRHP
The voltage of grayscale number 0 is selected by
the 64 to 1 selector
The voltage of grayscale number 1 is selected by
the 64 to 1 selector
The voltage of grayscale number 3 is selected by
the 64 to 1 selector
The voltage of grayscale number 6 is selected by
the 64 to 1 selector
The voltage of grayscale number 11 is selected by
the 64 to 1 selector
The voltage of grayscale number 19 is selected by
the 64 to 1 selector
The voltage of grayscale number 27 is selected by
the 64 to 1 selector
The voltage of grayscale number 36 is selected by
the 64 to 1 selector
The voltage of grayscale number 44 is selected by
the 64 to 1 selector
The voltage of grayscale number 52 is selected by
the 64 to 1 selector
The voltage of grayscale number 57 is selected by
the 64 to 1 selector
The voltage of grayscale number 60 is selected by
the 64 to 1 selector
The voltage of grayscale number 62 is selected by
the 64 to 1 selector
The voltage of grayscale number 63 is selected by
the 64 to 1 selector
Variable resistor VRLP
2008-07-07
ST7773
10.2.23 GMCTRN1 (E1h): Gamma ‘-’polarity Correction Characteristics Setting
E0H
Inst / Para
GMCTRP0 (Gamma ‘+’polarity Correction Characteristics Setting)
D/CX WRX RDX D17-8 D7 D6
D5
D4
D3
D2
D1
GMCTRN1
0
↑
1
-
1
1
st
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
1 Parameter
nd
2 Parameter
rd
3 Parameter
th
4 Parameter
th
5 Parameter
th
6 Parameter
th
7 Parameter
th
8 Parameter
th
9 Parameter
th
10 Parameter
th
11 Parameter
th
12 Parameter
th
13 Parameter
th
14 Parameter
th
15 Parameter
th
16 Parameter
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
0
0
0
0
D0
(Code)
1
(E1h)
VRF0N[5] VRF0N[4] VF0N[3] VRF0N[2] VRF0N[1] VRF0N[0]
VOS0N[5] VOS0N[4] VOS0N[3] VOS0N[2] VOS0N[1] VOS0N[0]
PK0N[5]
PK0N[4]
PK0N[3]
PK0N[2]
PK0N[1]
PK0N[0]
PK1N[5]
PK1N[4]
PK1N[3]
PK1N[2]
PK1N[1]
PK1N[0]
PK2N[5]
PK2N[4]
PK2N[3]
PK2N[2]
PK2N[1]
PK2N[0]
PK3N[5]
PK3N[4]
PK3N[3]
PK3N[2]
PK3N[1]
PK3N[0]
PK4N[5]
PK4N[4]
PK4N[3]
PK4N[2]
PK4N[1]
PK4N[0]
PK5N[5]
PK5N[4]
PK5N[3]
PK5N[2]
PK5N[1]
PK5N[0]
PK6N[5]
PK6N[4]
PK6N[3]
PK6N[2]
PK6N[1]
PK6N[0]
PK7N[5]
PK7N[4]
PK7N[3]
PK7N[2]
PK7N[1]
PK7N[0]
PK8N[5]
PK8N[4]
PK8N[3]
PK8N[2]
PK8N[1]
PK8N[0]
PK9[5]
PK9N[4]
PK9N[3]
PK9N[2]
PK9N[1]
PK9N[0]
SELV0N[5] SELV0N[4] SELV0N[3] SELV0N[2] SELV0N[1] SELV0N[0]
SELV1N[5] SELV1N[4] SELV1N[3] SELV1N[2] SELV1N[1] SELV1N[0]
SELV62N[5] SELV62N[4] SELV62N[3] SELV62N[2] SELV62N[1] SELV62N[0]
SELV63N[5] SELV63N[4] SELV63N[3] SELV63N[2] SELV63N[1] SELV63N[0]
NOTE: “-“ Don’t care
Register Group
Negative Polarity
High level adjustment
VRF0N[5:0]
SELV0N[5:0]
SELV1N[5:0]
PK0N[5:0]
PK1N[5:0]
PK2N[5:0]
PK3N[5:0]
Description
PK4N[5:0]
Mid level adjustment
PK5N[5:0]
PK6N[5:0]
PK7N[5:0]
PK8N[5:0]
PK9N[5:0]
SELV62N[5:0]
SELV63N[5:0]
Low level adjustment
Ver. 2.0
VOS0N[5:0]
117
Set-up Contents
Variable resistor VRHN
The voltage of grayscale number 0 is selected by
the 64 to 1 selector
The voltage of grayscale number 1 is selected by
the 64 to 1 selector
The voltage of grayscale number 3 is selected by
the 64 to 1 selector
The voltage of grayscale number 6 is selected by
the 64 to 1 selector
The voltage of grayscale number 11 is selected by
the 64 to 1 selector
The voltage of grayscale number 19 is selected by
the 64 to 1 selector
The voltage of grayscale number 27 is selected by
the 64 to 1 selector
The voltage of grayscale number 36 is selected by
the 64 to 1 selector
The voltage of grayscale number 44 is selected by
the 64 to 1 selector
The voltage of grayscale number 52 is selected by
the 64 to 1 selector
The voltage of grayscale number 57 is selected by
the 64 to 1 selector
The voltage of grayscale number 60 is selected by
the 64 to 1 selector
The voltage of grayscale number 62 is selected by
the 64 to 1 selector
The voltage of grayscale number 63 is selected by
the 64 to 1 selector
Variable resistor VRLN
2008-07-07
ST7773
11. Power structure
11.1. Driver IC Operating voltages Specification
VGH(10~16V)
AVDD
AVDD(4.8~5.3V)
VDD=(2.7V~3.3V)
GVDD(3.0~ 5.0V)
Change Pump
Reference Voltage
Internal
Reference Voltage
VCOMH(2.5 ~ 5.0V)
Vref
AGND=0V
VCOML(-2.5 ~ 0V)
VCI1
VCL(-2.5 ~ -2.75V)
VGL(-13 ~ -5.5V)
Fig 11.1.1 Power Booster Level
Remark
1. AVDD supply to all power source (exclude VGH, VGL)
2. Linear Range: 0.2V ~ AVDD-0.1V (For all output voltage, but exclude VGH, VGL)
3. Above operating voltages is min range.
Ver. 2.0
118
2008-07-07
ST7773
11.2 Power Step1/2/4 Circuit
11.2.1 VCI1 generate from Vref
Fig. 11.2.1 Power Booster Structure (1)
Ver. 2.0
119
2008-07-07
ST7773
11.2.2 EXTERNAL COMPONENTS CONNECTION
Pad Name
VDDI
VDD
VCC
AGND
DGND
C23P, C23N
C22P, C22N
C21P, C22N
C12P, C12N
C11P, C11N
AVDD
VCI1
VGH
VGL
VCL
VREF
GVDD
VCOMH
VCOML
VGL
Rated (Min)
Voltage
Connection
VDDI (Logic Power)
VDD (Analog Power)
Connect to Capacitor (Max 3V): VCC -------||-------- GND
Analog ground (Connect to GND)
Digital ground (Connect to GND)
Connect to Capacitor: C23P -------||--------C23N
Connect to Capacitor: C22P -------||--------C22N
Connect to Capacitor: C21P -------||--- -----C21N
Connect to Capacitor: C12P -------||--------C12N
Connect to Capacitor: C11P -------||--------C11N
Connect to Capacitor: AVDD -------||-------- GND
Connect to Capacitor: AVDD -------||-------- GND
Connect to Capacitor: VGH -------||-------- GND
Connect to Capacitor: VGL -------||-------- GND
Connect to Capacitor: VCL -------||-------- GND
Connect to Capacitor: VREF -------||-------- GND(Optional)
Connect to Capacitor: GVDD -------||-------- GND(Optional)
Connect to Capacitor: VCOMH-------||--------- GND
Connect to Capacitor: VCOML -------||-------- GND
Connect to Schottky diode: VGL -------.|-------- GND
Typical
capacitance value
6.3V
6.3V
6.3V
1.0 uF
1.0 uF
1.0 uF
16.0V
25.0V
6.3V
6.3V
6.3V
6.3V
6.3V
25.0V
16.0V
6.3V
6.3V
6.3V
6.3V
6.3V
30V
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
1.0 uF
Schottky diode(note1)
Note1: Leakage current must to be smaller than 20uA when the schottky diode operates at -30~85℃.
Ver. 2.0
120
2008-07-07
ST7773
12. Gamma structure
12.1 STRUCTURE OF GRAYSCALE AMPLIFIER
The structure of grayscale amplifier is shown as below. 16 voltage levels (VIN0-VIN15) between GVDD and VGS are
determined by the high/ mid/ low level adjustment registers. Each mid-adjustment level is split into 64 levels again by the
internal ladder resistor network. As a result, grayscale amplifier generates 64 voltage levels ranging from V0 to V63 and
outputs one of 64 levels.
Ver. 2.0
121
2008-07-07
ST7773
12.2 ST7773 Gamma Voltage Formula (Positive/ Negative Polarity)
Grayscale
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Ver. 2.0
Voltage Formula(Positive)
VINP0
VINP1
VINP2
VINP3
V3-(V3-V6)*(11/30)
V3-(V3-V6)*(21/30)
VINP4
V6-(V6-V11)*(7/30)
V6-(V6-V11)*(14/30)
V6-(V6-V11)*(20/30)
V6-(V6-V11)*(25/30)
VINP5
V11-(V11-V19)*(4/32)
V11-(V11-V19)*(8/32)
V11-(V11-V19)*(12/32)
V11-(V11-V19)*(16/32)
V11-(V11-V19)*(20/32)
V11-(V11-V19)*(24/32)
V11-(V11-V19)*(28/32)
VINP6
V19-(V19-V27)*(4/32)
V19-(V19-V27)*(8/32)
V19-(V19-V27)* (12/32)
V19-(V19-V27)* (1632/)
V19-(V19-V27)* (20/32)
V19-(V19-V27)* (24/32)
V19-(V19-V27)* (28/32)
VINP7
V27-(V27-V36)* (4/36)
V27-(V27-V36)* (8/36)
V27-(V27-V36)* (12/36)
V27-(V27-V36)* (16/36)
V27-(V27-V36)* (20/36)
V27-(V27-V36)* (24/36)
V27-(V27-V36)* (28/36)
V27-(V27-V36)* (32/36)
VINP8
V36-(V36-V44)*(4/32)
V36-(V36-V44)*(8/32)
V36-(V36-V44)*(12/32)
V36-(V36-V44)*(16/32)
V36-(V36-V44)*(20/32)
V36-(V36-V44)*(24/32)
V36-(V36-V44)*(28/32)
VINP9
V44-(V44-V52)*(4/32)
V44-(V44-V52)*(8/32)
V44-(V44-V52)*(12/32)
V44-(V44-V52)*(16/32)
V44-(V44-V52)*(20/32)
V44-(V44-V52)*(24/32)
V44-(V44-V52)*(28/32)
VINP10
V52-(V52-V57)*(5/30)
V52-(V52-V57)*(11/30)
122
Voltage Formula(Negative)
VINN0
VINN1
VINN2
VINN3
V3-(V3-V6)*(11/30)
V3-(V3-V6)*(21/30)
VINN4
V6-(V6-V11)*(7/30)
V6-(V6-V11)*(14/30)
V6-(V6-V11)*(20/30)
V6-(V6-V11)*(25/30)
VINN5
V11-(V11-V19)*(4/32)
V11-(V11-V19)*(8/32)
V11-(V11-V19)*(12/32)
V11-(V11-V19)*(16/32)
V11-(V11-V19)*(20/32)
V11-(V11-V19)*(24/32)
V11-(V11-V19)*(28/32)
VINN6
V19-(V19-V27)*(4/32)
V19-(V19-V27)*(8/32)
V19-(V19-V27)* (12/32)
V19-(V19-V27)* (1632/)
V19-(V19-V27)* (20/32)
V19-(V19-V27)* (24/32)
V19-(V19-V27)* (28/32)
VINN7
V27-(V27-V36)* (4/36)
V27-(V27-V36)* (8/36)
V27-(V27-V36)* (12/36)
V27-(V27-V36)* (16/36)
V27-(V27-V36)* (20/36)
V27-(V27-V36)* (24/36)
V27-(V27-V36)* (28/36)
V27-(V27-V36)* (32/36)
VINN8
V36-(V36-V44)*(4/32)
V36-(V36-V44)*(8/32)
V36-(V36-V44)*(12/32)
V36-(V36-V44)*(16/32)
V36-(V36-V44)*(20/32)
V36-(V36-V44)*(24/32)
V36-(V36-V44)*(28/32)
VINN9
V44-(V44-V52)*(4/32)
V44-(V44-V52)*(8/32)
V44-(V44-V52)*(12/32)
V44-(V44-V52)*(16/32)
V44-(V44-V52)*(20/32)
V44-(V44-V52)*(24/32)
V44-(V44-V52)*(28/32)
VINN10
V52-(V52-V57)*(5/30)
V52-(V52-V57)*(11/30)
2008-07-07
ST7773
55
56
57
58
59
60
61
62
63
Ver. 2.0
V52-(V52-V57)*(17/30)
V52-(V52-V57)*(23/30)
VINP11
V57-(V57-V60)*(8/30)
V57-(V57-V60)*(18/30)
VINP12
VINP13
VINP14
VINP15
123
V52-(V52-V57)*(17/30)
V52-(V52-V57)*(23/30)
VINN11
V57-(V57-V60)*(8/30)
V57-(V57-V60)*(18/30)
VINN12
VINN13
VINN14
VINN15
2008-07-07
ST7773
13. Example Connection with Panel direction and Different Resolution
Case 1: (This is default case)
- 1st Pixel is at Left Top of the panel
- RGB filter order = RGB
- Direction default setting (H/W)
SMX = ‘0’
ST7773 (Bump Down)
SMY = ‘0’
SRGB = ‘0’
S1 = Filter R
00h 01h 02h------------ AEh AEh AFh
S2 = Filter G
G1
G2
S3 = Filter B
G3
- Display direction control (S/W)
G4
|
|
|
|
|
|
|
|
|
|
|
G217
- X-Mirror control by MX
|
|
|
|
|
|
|
|
|
|
- Y-Mirror control by MY
- XY-Exchange control by MV
IC (Bump down)
LCD Front side
CF Glass
G218
G219
TFT Glass
G220
Case 2:
- 1st Pixel is at Left Top of the panel
- RGB filter order = BGR
- Direction default setting (H/W)
SMX = ‘0’
ST7773 (Bump Down)
SMY = ‘0’
SRGB = ‘1’
S1 = Filter B
00h 01h 02h------------ AEh AEh AFh
G1
S2 = Filter G
G2
S3 = Filter R
G3
|
|
|
|
|
|
|
|
|
|
|
G217
G219
- Display direction control (S/W)
G4
- X-Mirror control by MX
|
|
|
|
|
|
|
|
|
|
- Y-Mirror control by MY
- XY-Exchange control by MV
IC (Bump down)
LCD Front side
G218
TFT Glass
G220
Ver. 2.0
CF Glass
124
2008-07-07
ST7773
Case 3:
- 1st Pixel is at Righ Bottom of the panel
- RGB filter order = RGB
Case 4:
- 1st Pixel is at Righ Bottom of the panel
- RGB filter order = BGR
- Direction default setting (H/W)
SMX = ‘1’
ST7773 (Bump Down)
SMY = ‘1’
SRGB = ‘1’
S1 = Filter B
00h 01h 02h------------ AEh AEh AFh
G1
S2 = Filter G
G2
S3 = Filter R
G3
|
|
|
|
|
|
|
|
|
|
|
G217
G219
- Display direction control (S/W)
G4
- X-Mirror control by MX
|
|
|
|
|
|
|
|
|
|
- Y-Mirror control by MY
- XY-Exchange control by MV
IC (Bump down)
LCD Front side
G218
TFT Glass
G220
Ver. 2.0
CF Glass
125
2008-07-07
ST7773
13.3 MicroProcessor Interface applications
13.3.1 8080-Series MCU Interface for 8-bit data bus (IM1, IM0=”00”)
ST7773
Host
RESX
TE
CSX
D/CX(SCL)
WRX
RDX
D7 to D0
"00"
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
"00"
"00"
"1"
RESX
TE
CSX
D/CX
WRX
RDX
D7 to D0
D15 to D8
D17 to D16
IM1,IM0
IM2
Fig.13.3.1 8080-Series MCU Interface for 8-bit data bus
13.3.2 8080-Series MCU Interface for 16-bit data bus (IM1, IM0=”01”)
ST7773
Host
RESX
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
TE
CSX
D/CX(SCL)
WRX
RDX
D7 to D0
D15 to D8
"00"
"00"
"1"
RESX
TE
CSX
D/CX
WRX
RDX
D7 to D0
D15 to D8
D17 to D16
IM1,IM0
IM2
Fig.13.3.2 8080-Series MCU Interface for 16-bit data bus
Ver. 2.0
126
2008-07-07
ST7773
13.3.3 8080-Series MCU Interface for 9-bit data bus (IM1, IM0=”10”)
ST7773
Host
RESX
TE
CSX
D/CX(SCL)
WRX
RDX
D8 to D0
"00"
"00"
"10"
"1"
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
RESX
TE
CSX
D/CX
WRX
RDX
D8 to D0
D15 to D9
D17 to D16
IM1,IM0
IM2
Fig.13.3.3 8080-Series MCU Interface for 9-bit data bus
13.3.4 8080-Series MCU Interface for 18-bit data bus (IM1, IM0=”11”)
ST7773
Host
RESX
TE
CSX
D/CX(SCL)
WRX
RDX
D7 to D0
D15 to D8
D17 to D16
"11"
"1"
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
RESX
TE
CSX
D/CX
WRX
RDX
D7 to D0
D15 to D8
D17 to D16
IM1,IM0
IM2
Fig.13.3.4 8080-Series MCU Interface for 18-bit data bus
13.3.5 3-line Series Interface(IM2=”0”)
ST7773
Host
RESX
TE
SPI-CSX
SCL
"1"
"1"
SDA
D7 to D1
"00"
Note:
IM2=’0’, SPI I/F
IM2=’1’, MCU I/F
"00"
"00"
"0"
RESX
TE
CSX
D/CX(SCL)
WRX
RDX
D0(SDA)
D7 to D1
D15 to D8
D17 to D16
IM1,IM0
IM2
Fig.13.3.5 SPI 3-lie Interface
Ver. 2.0
127
2008-07-07
ST7773
ST7773 Serial Specification Revision History
Ver. 2.0
Version
Date
Description
1.x
2008/01/--
2.0
2008/07/04 Mass Prooduction release
Preliminary
128
2008-07-07