HD74LV240A Octal Buffers / Drivers with 3-state Outputs REJ03D0327–0300Z (Previous ADE-205-272A (Z)) Rev.3.00 Jun. 23, 2004 Description The HD74V240A has eight inverter drivers with three-state outputs in a 20-pin package. Four inverters are included in one circuit. Each circuit can be independently controlled by the enable signal 1OE or 2OE, which enables outputs when receiving a low-level signal. Low-voltage operation is suitable for battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV240AFPEL SOP–20 pin (JEITA) FP–20DAV FP EL (2,000 pcs/reel) HD74LV240ARPEL HD74LV240ATELL SOP–20 pin (JEDEC) TSSOP–20 pin FP–20DBV TTP–20DAV RP T EL (1,000 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs OE A Output Y L L H H L X L H Z Note: H: L: X: Z: High level Low level Immaterial High impedance Rev.3.00 Jun. 23, 2004 page 1 of 9 HD74LV240A Pin Arrangement 1OE 1 20 VCC 1A1 2 19 2OE 2Y4 3 18 1Y1 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 6 15 2A3 2Y2 7 14 1Y3 1A4 8 13 2A2 2Y1 9 12 1Y4 GND 10 11 2A1 (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input voltage range*1 Output voltage range*1, 2 VCC VI VO V V V Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)*3 IIK IOK IO –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±35 ±70 Storage temperature Tstg ICC or IGND PT 835 757 –65 to 150 mA mA mA mA mW Conditions Output: H or L VCC: OFF or Output: Z VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.3.00 Jun. 23, 2004 page 2 of 9 HD74LV240A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range VI VO IOH 5.5 5.5 VCC 5.5 –50 –2 –8 –16 50 2 8 16 200 100 20 V V V Output current 2.0 0 0 0 — — — — — — — — 0 0 0 –40 85 °C IOL Input transition rise or fall rate ∆t /∆v Operating free-air temperature Ta µA mA µA mA ns/V Conditions H or L High impedance state VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Note: Unused or floating inputs must be held high or low. Logic Diagram 1OE 1A1 1A2 1A3 1A4 1 2OE 2 18 4 16 6 14 8 12 Rev.3.00 Jun. 23, 2004 page 3 of 9 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 HD74LV240A DC Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V) Min Typ Max Unit Input voltage VIH 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 — — — — VCC – 0.1 2.0 2.48 3.8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 — — — — 0.1 0.4 0.44 0.55 ±1 ±5 V Input current Off-state output current IIN IOZ 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 Quiescent supply current ICC 5.5 — — Output leakage current IOFF 0 — Input capacitance CIN 3.3 — VIL Output voltage VOH VOL Test Conditions µA µA IOH = –50 µA IOH = –2 mA IOH = –8 mA IOH = –16 mA IOL = 50 µA IOL = 2 mA IOL = 8 mA IOL = 16 mA VIN = 5.5 V or GND VO = VCC or GND 20 µA VIN = VCC or GND, IO = 0 — 5 µA VI or VO = 0 V to 5.5 V 2.3 — pF VI = VCC or GND V Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00 Jun. 23, 2004 page 4 of 9 HD74LV240A Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL tZH tZL Disable time tHZ tLZ 6.3 8.2 8.5 10.3 9.7 14.2 11.6 14.4 14.6 17.8 14.1 19.2 1.0 1.0 1.0 1.0 1.0 1.0 14.0 17.0 17.0 21.0 16.0 21.0 ns Enable time — — — — — — ns ns Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF A Y OE Y OE Y VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL tZH tZL Disable time tHZ tLZ 4.6 5.9 6.2 7.5 8.3 11.8 7.5 11.0 10.6 14.1 12.5 15.0 1.0 1.0 1.0 1.0 1.0 1.0 9.0 12.5 12.5 16.0 13.5 17.0 ns Enable time — — — — — — ns ns Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF A Y OE Y OE Y VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL tZH tZL Disable time tHZ tLZ 3.4 4.4 4.6 5.6 7.4 9.7 5.5 7.5 7.3 9.3 12.2 14.2 1.0 1.0 1.0 1.0 1.0 1.0 6.5 8.5 8.5 10.5 13.5 15.5 ns Enable time — — — — — — ns ns Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF A Y OE Y OE Y Output-skew Characteristics CL = 50 pF Ta = 25°C Ta = –40 to 85°C Item Symbol VCC (V) Min Max Min Max Unit Output skew tsk (O) 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 — — — 2.0 1.5 1.0 — — — 2.0 1.5 1.0 ns Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested. Rev.3.00 Jun. 23, 2004 page 5 of 9 HD74LV240A Operating Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 5.0 — — 14.0 16.4 — — pF f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Typ 0.6 Max 0.8 Unit 3.3 Min — Quiet output, maximum dynamic VOL VOL (P) Quiet output, minimum dynamic VOL VOL (V) 3.3 — –0.5 –0.8 V Quiet output, minimum dynamic VOH VOH (V) 3.3 — 2.8 — V High-level dynamic input voltage VIH (D) 3.3 2.31 — — V Low-level dynamic input voltage VIL (D) 3.3 — — 0.99 V Test Conditions V Test Circuit VCC VCC Input Pulse generator Zout = 50 Ω See Function Table 1OE, 2OE Output 1 kΩ 1Y1 to 2Y4 OPEN GND 1A1 to 2A4 CL * Note: CL includes the probe and jig capacitance. Rev.3.00 Jun. 23, 2004 page 6 of 9 S1 VCC TEST t PLH /t PHL S1 OPEN t ZH/t HZ t ZL /t LZ GND VCC HD74LV240A • Waveform − 1 tf tr 90% 50% VCC Input A 10% 10% t PLH 90% 50% VCC t PHL VCC 0V VOH Output Y 50% VCC 50% VCC VOL • Waveform − 2 Input OE tf tr 90% 50% VCC 10% t ZL VCC 90% 50% VCC 10% 0V t LZ VCC Waveform − A 50% VCC t ZH Waveform − B VOL + 0.3 V t HZ 50% VCC VOH − 0.3 V VOL VOH 0V Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns 2. Waveform−A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform−B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.3.00 Jun. 23, 2004 page 7 of 9 HD74LV240A Package Dimensions As of January, 2002 Unit: mm 12.6 13 Max 11 1 10 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 20 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Pd plating FP–20DAV — Conforms 0.31 g As of January, 2003 Unit: mm 12.8 13.2 Max 11 1 10 1.27 *0.40 ± 0.06 0.20 ± 0.10 0.935 Max *0.25 ± 0.05 2.65 Max 7.50 20 0.25 10.40 +– 0.40 1.45 0˚ – 8˚ 0.57 0.70 +– 0.30 0.15 0.12 M *Ni/Pd/Au plating Rev.3.00 Jun. 23, 2004 page 8 of 9 Package Code JEDEC JEITA Mass (reference value) FP-20DBV Conforms — 0.52 g HD74LV240A As of January, 2002 Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.20 ± 0.05 1.0 0.13 M 6.40 ± 0.20 *Pd plating Rev.3.00 Jun. 23, 2004 page 9 of 9 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP–20DAV — — 0.07 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .1.0