RENESAS HD74LV393ARPEL

HD74LV393A
Dual 4-bit Binary Counters
REJ03D0333–0300Z
(Previous ADE-205-276A (Z))
Rev.3.00
Jun. 28, 2004
Description
The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by256 counter.
The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter is set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV393AFPEL
HD74LV393ARPEL
HD74LV393ATELL
SOP–14 pin(JEITA)
SOP–14 pin(JEDEC)
TSSOP–14 pin
FP–14DAV
FP–14DNV
TTP–14DV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.3.00 Jun. 28, 2004 page 1 of 10
HD74LV393A
Function Table
Inputs
CLK
CLR
Output
X
H
L
↑
↓
H
L
L
L
L
L
No change
No change
No change
Count up
Note: H:
L:
X:
↑:
↓:
High level
Low level
Immaterial
Low to high transition
High to low transition
Pin Arrangement
1CLK 1
14 VCC
1CLR 2
13 2CLK
1QA 3
12 2CLR
1QB 4
11 2QA
1QC 5
10 2QB
1QD 6
9 2QC
GND 7
8 2QD
(Top view)
Rev.3.00 Jun. 28, 2004 page 2 of 10
HD74LV393A
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage range
VCC
Input voltage range*1
Output voltage range*1, 2
VI
VO
V
V
V
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation at
Ta = 25°C (in still air)*3
IIK
IOK
IO
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
Storage temperature
Tstg
ICC or
IGND
PT
mA
mA
mA
mA
mW
785
500
–65 to 150
Conditions
Output: H or L
VCC: OFF
VI < 0
VO < 0 or VO > VCC
VO = 0 to VCC
SOP
TSSOP
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
Input voltage range
Output voltage range
Output current
VI
VO
IOH
2.0
0
0
—
—
—
—
—
—
—
—
0
0
0
5.5
5.5
VCC
–50
–2
–6
–12
50
2
6
12
200
100
20
V
V
V
µA
mA
–40
85
°C
IOL
Input transition rise or fall rate
∆t /∆v
Operating free-air temperature
Ta
Note: Unused or floating inputs must be held high or low.
Rev.3.00 Jun. 28, 2004 page 3 of 10
µA
mA
ns/V
Conditions
H or L
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
HD74LV393A
Logic Diagram
D
CLK
CK
D
R
CK
Q
D
R
CK
Q
D
R
CK
Q
R
Q
CLR
QA
Timing Diagram
CLK
CLR
QA
QB
QC
QD
Rev.3.00 Jun. 28, 2004 page 4 of 10
QB
QC
QD
HD74LV393A
DC Electrical Characteristics
Ta = –40 to 85°C
Item
Symbol
VCC (V)*
Min
Typ
Max
Unit
Input voltage
VIH
1.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
—
—
—
—
VCC – 0.1
2.0
2.48
3.8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
—
—
—
—
0.1
0.4
0.44
0.55
±1
20
V
Input current
Quiescent supply
current
IIN
ICC
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
Min to Max
2.3
3.0
4.5
Min to Max
2.3
3.0
4.5
0 to 5.5
5.5
Output leakage
current
IOFF
0
—
—
Input capacitance
CIN
3.3
—
1.7
VIL
Output voltage
VOH
VOL
Test Conditions
µA
µA
IOH = –50 µA
IOH = –2 mA
IOH = –6 mA
IOH = –12 mA
IOL = 50 µA
IOL = 2 mA
IOL = 6 mA
IOL = 12 mA
VIN = 5.5 V or GND
VIN = VCC or GND, IO = 0
5
µA
VI or VO = 0 V to 5.5 V
—
pF
VI = VCC or GND
V
V
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Switching Characteristics
VCC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Maximum clock
frequency
fmax
50
90
—
40
—
MHz
Propagation
delay time
tPLH/tPHL
30
—
—
—
60
11.8
15.1
13.4
—
17.7
21.3
20.3
25
1.0
1.0
1.0
—
20.5
24.5
23.5
—
—
—
—
—
—
—
6.0
5.0
5.0
16.7
14.9
18.2
16.2
19.5
10.8
14.2
—
—
—
23.9
22.5
26.1
24.2
27.8
14.8
17.4
—
—
—
1.0
1.0
1.0
1.0
1.0
1.0
1.0
6.0
5.0
5.0
27.5
26.0
30.0
28.0
32.0
17.0
20.0
—
—
—
tPHL
Setup time
Pulse width
tsu
tw
Rev.3.00 Jun. 28, 2004 page 5 of 10
ns
Test
Conditions
FROM
(Input)
TO
(Output)
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CLK
QA
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
ns
ns
QB
QC
QD
CLR
Qn
CLR L before CLK ↓
CLR H
CLK H or L
HD74LV393A
Switching Characteristics (cont)
VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Test
Conditions
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Maximum clock
frequency
fmax
75
45
120
65
—
—
65
35
—
—
MHz
CL = 15 pF
CL = 50 pF
Propagation
delay time
tPLH/tPHL
—
—
—
—
—
—
—
—
—
—
5.0
5.0
5.0
8.6
11.1
10.2
12.7
11.7
14.2
13.0
15.5
7.9
10.4
—
—
—
13.2
16.7
15.8
19.3
18.0
21.5
19.7
23.2
12.3
15.8
—
—
—
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
5.0
5.0
5.0
15.5
19.0
18.5
22.0
21.0
24.5
23.0
26.5
14.5
18.0
—
—
—
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
tPHL
Setup time
Pulse width
tsu
tw
FROM
(Input)
TO
(Output)
CLK
QA
QB
QC
QD
CLR
Qn
CLR L before CLK ↓
CLR H
CLK H or L
ns
ns
VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
Test
Conditions
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Maximum clock
frequency
fmax
125
85
170
115
—
—
105
75
—
—
MHz
CL = 15 pF
CL = 50 pF
Propagation
delay time
tPLH/tPHL
—
—
—
—
—
—
—
—
—
—
4.0
5.0
5.0
5.8
7.3
6.8
8.3
7.7
9.2
8.5
10.0
5.4
6.9
—
—
—
8.5
10.5
9.8
11.8
11.2
13.2
12.5
14.5
8.1
10.1
—
—
—
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
4.0
5.0
5.0
10.0
12.0
11.5
13.5
13.0
15.0
14.5
16.5
9.5
11.5
—
—
—
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
tPHL
Setup time
Pulse width
tsu
tw
FROM
(Input)
TO
(Output)
CLK
QA
QB
QC
QD
CLR
Qn
CLR L before CLK ↓
CLR H
CLK H or L
ns
ns
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test Conditions
Power dissipation capacitance
CPD
3.3
5.0
—
—
12.0
15.0
—
—
pF
f = 10 MHz
Rev.3.00 Jun. 28, 2004 page 6 of 10
HD74LV393A
Noise Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC = (V)
Min
Typ
Max
Unit
Quiet output, maximum
dynamic VOL
VOL (P)
3.3
—
0.4
0.8
V
Quiet output, minimum
dynamic VOL
VOL (V)
3.3
—
–0.4
–0.8
V
Quiet output, minimum
dynamic VOH
VOH (V)
3.3
—
3.2
—
V
High-level dynamic input
voltage
VIH (D)
3.3
2.31
—
—
V
Low-level dynamic input
voltage
VIL (D)
3.3
—
—
0.99
V
Test Circuit
Measurement point
CL*
Note: C L includes the probe and jig capacitance.
Rev.3.00 Jun. 28, 2004 page 7 of 10
Test Conditions
HD74LV393A
• Waveforms − 1
tr
tf
90 %
50 % V CC
CLR
10 %
tw
VCC
10 %
90 %
50 % V CC
CLK
0V
tf
t su
tr
10 %
VCC
90 %
50 % V CC
0V
tw
t PLH
tw
t PHL
VOH
Qn
50 % V CC
50 % V CC
VOL
• Waveforms − 2
CLR
10 %
tr
tf
VCC
90 %
50 % V CC
CLK
0V
90 %
50 % V CC
VCC
10 %
t PHL
0V
VOH
Qn
50 % V CC
VOL
t PHL
t PLH
VOH
50 % V CC
Qn
VOH
Qn
50 % V CC
VOL
Notes: 1. Input waveform: PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
Rev.3.00 Jun. 28, 2004 page 8 of 10
VOL
HD74LV393A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
8
5.5
14
1
1.42 Max
*0.20 ± 0.05
2.20 Max
7
*0.40 ± 0.06
1.15
0˚ – 8˚
0.10 ± 0.10
1.27
0.20
7.80 +– 0.30
0.70 ± 0.20
0.15
0.12 M
Package Code
JEDEC
JEITA
Mass (reference value)
*Ni/Pd/Au plating
FP-14DAV
—
Conforms
0.23 g
As of January, 2003
Unit: mm
8.65
9.05 Max
8
1
7
*0.20 ± 0.05
0.635 Max
1.75 Max
3.95
14
+ 0.10
6.10 – 0.30
1.08
+ 0.67
0.14 – 0.04
*0.40 ± 0.06
+ 0.11
0˚ – 8˚
1.27
0.60 – 0.20
0.15
0.25 M
*Ni/Pd/Au plating
Rev.3.00 Jun. 28, 2004 page 9 of 10
Package Code
JEDEC
JEITA
Mass (reference value)
FP-14DNV
Conforms
Conforms
0.13 g
HD74LV393A
As of January, 2003
Unit: mm
4.40
5.00
5.30 Max
14
8
1
7
0.65
*0.20 ± 0.05
1.0
0.13 M
6.40 ± 0.20
*Ni/Pd/Au plating
Rev.3.00 Jun. 28, 2004 page 10 of 10
0.07 +0.03
–0.04
0.10
*0.15 ± 0.05
1.10 Max
0.83 Max
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-14DV
—
—
0.05 g
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