NTE74195 Integrated Circuit TTL − 4−Bit Parallel Access Shift

NTE74195
Integrated Circuit
TTL − 4−Bit Parallel Access Shift Register
Description:
The NTE74195 is a 4−bit parallel access shift register in a 16−Lead plastic DIP type package and
features parallel inputs, parallel outputs, J−K serial inputs, shift/load control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The register has two distinct
modes of operation:
Parallel (Broadside) Load
Shift (in the direction QA toward QD)
Parallel loading is accomplished by applying the four bits of data and taking the shift/load control input
low. The data is loaded into the associated flip−flop and appears at the outputs after the positive transition of the clock input.
Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this
mode is entered at the J−K inputs. These inputs permit the first stage to perform as a J−K, D−, or T−
type flip−flop as shown in the function table.
Features:
D Synchronous Parallel Load
D Positive Edge−Triggered Clock
D Parallel Inputs and Outputs from Each Flip−Flop
D Direct Overriding Clear
D J and K Inputs to First Stage
D Complementary Outputs from Last Stage
Applications:
D Accumulators/Processors
D Serial−to−Parallel, Parallel−to−Serial Converter
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195mW
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Note 1. Unless otherwise specified, all voltages are referenced to GND.
Recommended Operating Conditions:
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.75
5.0
5.25
V
High−Level Output Current
IOH
−
−
−800
A
Low−Level Output Current
IOL
−
−
16
mA
fclock
0
−
30
MHz
Width of Clock or Clear Pulse
tw(clock)
16
−
−
ns
Width of Clear Input Pulse
tw(clear)
12
−
−
ns
Shift/Load Setup Time
tsu
25
−
−
ns
Serial and Parallel Data Setup Time
tsu
20
−
−
ns
Clear Inactive−State Setup Time
tsu
25
−
−
ns
trelease
−
−
10
ns
Serial and Parallel Data Hold Time
th
0
−
−
ns
Operating Temperature Range
TA
0
−
+70
C
Min
Typ
Max
Unit
Clock Frequency
Shift/Load Release Time
Electrical Characteristics: (Note 2, Note 3)
Parameter
Symbol
Test Conditions
High−Level Input Voltage
VIH
2
−
−
V
Low−Level Input Voltage
VIL
−
−
0.8
V
Input Clamp Voltage
VIK
VCC = MIN, II = −12mA
−
−
−1.5
V
High Level Output Voltage
VOH
VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = -800A
2.4
3.4
−
V
Low Level Output Voltage
VOL
VCC = MIN, VIH = 2V, VIL = 0.8V, IOL = 16mA
−
0.2
0.4
V
Input Current
II
VCC = MAX, VI = 5.5V
−
−
1
mA
High Level Input Current
IIH
VCC = MAX, VI = 2.4V
−
−
40
A
Low Level Input Current
IIL
VCC = MAX, VI = 0.4V
−
−
−1.6
mA
Short−Circuit Output Current
IOS
VCC = MAX, Note 4
−18
−
−57
mA
Supply Current
ICC
VCC = MAX, Note 5
−
39
63
mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time and duration of short−circuit should
not exceed one second.
Note 5. With all outputs open, shift/load grounded, and 4.5V applied to the J, K, and data inputs, ICC
is measured by applying a momentary GND, followed by 4.5V to clear and then applying a
momentary ground, followed by 4.5V to clock.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Maximum Clock Frequency
Symbol
fmax
Test Conditions
RL = 400, CL = 15pF
Min
Typ
Max
Unit
30
39
−
MHz
Propagation Delay Time (from Clear)
tPHL
−
19
30
ns
Propagation Delay Time (from Clock)
tPLH
−
14
22
ns
tPHL
−
17
26
ns
Function Table:
Shift/
Clear Load Clock
L
X
X
H
L

H
H
L
H
H

H
H

H
H

H
H

Inputs
Serial
J
K
X
X
X
X
X
X
L
H
L
L
H
H
H
L
Outputs
A
X
a
X
X
X
X
X
Parallel
B
C
X
X
b
c
X
X
X
X
X
X
X
X
X
X
D
X
d
X
X
X
X
X
QA
L
a
QA0
QA0
L
H
QAn
QB
L
b
QB0
QA0
QAn
QAn
QAn
QC
L
c
QC0
QBn
QBn
QBn
QBn
QD
L
d
QD0
QCn
QCn
QCn
QCn
QD
H
d
QD0
QCn
QCn
QCn
QCn
H = HIGH Level (Steady State)
L = LOW Level (Steady State)
X = Irrelevant (Any input, including transitional)
 = Transition from LOW to HIGH Level
a, b, c, d = The level of steady−state input at inputs A, B, C, or D respectively
QA0, QB0, QC0, QD0 = The level of QA, QB, QC, or QD respectively, before the indicated steady−state
input conditions were established
QAn, QBn, QCn = The level of QA, QB, QC respectively, before the most recent transition of the clock.
Pin Connection Diagram
CLR 1
J 2
K 3
16 VCC
15 QA
14 QB
A 4
13 QC
B 5
12 QD
C 6
11 QD
D 7
10 CLK
GND 8
9 SH/LD
16
9
1
8
.870 (22.0) Max
.260 (6.6)
Max
.200
(5.08)
Max
.100 (2.54)
.700 (17.78)
.099 (2.5) Min