NTE74H103 Integrated Circuit TTL − Dual J−K Negative−Edge

NTE74H103
Integrated Circuit
TTL − Dual J−K Negative−Edge−Triggered
Flip−Flop with Clear
Description:
The NTE74H103 is a dual monolithic, J−K negative−edge−triggered flip−flop in a 14−Lead DIP
type package that features individual J, K, clock, and asynchronous clear inputs to each flip−flop.
When the clock goes high, the inputs are enabled and data will be accepted. Logical state of J and
K inputs may be allowed to change when the clock pulse is in a high state and bistable will perform
according to the truth table as long as minimum set−up times are observed. Input data is transferred to the outputs on the negative edge of the clock pulse.
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Note 1. Unless otherwise specified, all voltages are referenced to GND.
Recommended Operating Conditions:
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.75
5.0
5.25
V
High−Level Input Voltage
VIH
2.0
−
−
V
Low−Level Input Voltage
VIL
−
−
0.8
V
High−Level Output Current
IOH
−
−
−0.5
A
Low−Level Output Current
IOL
−
−
20
mA
Pulse Duration
CLK High
tw
10
−
−
ns
CLK Low
15
−
−
ns
CLR Low
16
−
−
ns
10
−
−
ns
13
−
−
ns
0
−
−
ns
0
−
+70
C
Setup Time Before CLK 
High−Level Data
tsu
Low−Level Data
Hold Time After CLK 
High−Level Data
th
Operating Temperature Range
TA
Electrical Characteristics: (Note 2, Note 3)
Parameter
Symbol
Test Conditions
Input Clamp Voltage
VIK
VCC = MIN, II = −8mA
High Level Output Voltage
VOH
VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = -0.5mA
Low Level Output Voltage
VOL
Min
Typ
Max
Unit
−
−
−1.5
V
2.4
3.4
−
V
VCC = MIN, VIH = 2V, VIL = 0.8V, IOL = 20mA
−
0.2
0.4
V
−
−
1
mA
−
−
50
A
CLR
−
−
100
A
CLK
0
−
−1
mA
−
−1
−2
mA
CLR
−
−1
−2
mA
CLK
−
−3
−4.8
mA
Input Current
II
VCC = MAX, VI = 5.5V
High Level Input Current
Any J or K
IIH
VCC = MAX, VI = 2.4V
Low Level Input Current
Any J or K
IIL
VCC = MAX, VI = 0.4V
Short−Circuit Output Current
IOS
VCC = MAX, Note 4
−40
−
−100
mA
Supply Current
ICC
VCC = MAX, Note 5
−
20
38
mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time, and the duration of the short−circuit
should not exceed one second.
Note 5. With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of
measurement, the clock input is grounded.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
Unit
40
50
−
MHz
−
8
12
ns
−
15
20
ns
−
23
35
ns
tPLH
−
10
15
ns
tPHL
−
16
20
ns
Maximum Clock Frequency
Propagation Delay Time
(From CLR Input to Any Q Output)
fmax
tPLH
Propagation Delay Time
(From CLR Input [CLK high] to Any Q Output)
tPLH
Test Conditions
RL = 280,
CL = 25pF
(From CLR Input [CLK low] to Any Q Output)
Propagation Delay Time
(From CLK Input to Any Q Output)
Function Table:
Inputs
CLR CLK
J
L
X
X
H

L
H

H
H

L
H

H
H
H
X
K
X
L
L
H
H
X
Outputs
Q
Q
L
H
Q0
Q0
H
L
L
H
Toggle
Q0
Q0
Pin Connection Diagram
1CLK 1
14 1J
1CLR 2
1K 3
13 1Q
12 1Q
11 GND
VCC 4
2CLK 5
10 2K
2CLR 6
9 2Q
8 2Q
2J 7
14
8
1
7
.300 (7.62)
.785 (19.95) Max
.200
(5.08)
Max
.100 (2.45)
.600 (15.24)
.099 (2.5) Min