NTE74LS78 Integrated Circuit TTL − Dual J−K Flip−Flop with Preset

NTE74LS78
Integrated Circuit
TTL − Dual J−K Flip−Flop with Preset,
Common Clock and Common Clear
Description:
The NTE74LS78 is a dual J−K flip−flop in a 14−Lead plastic DIP type package that contains two
negative−edge−triggered flip−flops with individual J−K, preset inputs, and common clock and
common clear inputs. The logic levels at the J and K inputs may be allowed to change while the
clock pulse is high and the flip−flop will perform according to the function table as long as minimum
setup and hold times are observed. The preset and clear are asynchronous active low inputs.
When low they override the clock and data inputs forcing the outputs to the steady state levels as
shown in the function table.
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Note 1. Voltage values are with respect to network ground terminal.
Recommended Operating Conditions:
Parameter
Supply Voltage
High−Level Input Voltage
Low−Level Input Voltage
High−Level Output Current
Low−Level Output Current
Clock Frequency
Pulse Duration
CLK High
PRE or CLR Low
Setup Time Before CLK 
Data High or Low
PRE or CLR Inactive
Hold Time Data After CLK 
Operating Temperature Range
Symbol
VCC
VIH
VIL
IOH
IOL
fclock
tw
tsu
th
TA
Min
4.75
2
−
−
−
0
Typ
5.0
−
−
−
−
−
Max
5.25
−
0.8
−0.4
8
30
Unit
V
V
V
20
25
−
−
−
−
ns
20
20
0
0
−
−
−
−
−
−
−
+70
mA
mA
MHz
ns
ns
ns
ns
C
Electrical Characteristics: (Note 2, Note 3)
Parameter
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Symbol
VIK
VOH
VOL
Input Current
J or K
CLR
PRE
CLK
High Level Input Current
J or K
CLR
PRE
CLK
Low Level Input Current
J or K
CLR or CLK
PRE
Short−Circuit Output Current
Supply Current
II
Test Conditions
VCC = MIN, II = −18mA
VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = -0.4mA
VCC = MIN, VIH = 2V,
IOL = 4mA
VIL = MAX
IOL = 8mA
VCC = MAX, VI = 7V
IIH
VCC = MAX, VI = 2.7V
IIL
VCC = MAX, VI = 0.4V
IOS
ICC
VCC = MAX, Note 4, Note 5
VCC = MAX, Note 6
Min
−
2.7
−
−
Typ
−
3.4
0.25
0.35
Max
−1.5
0.4
0.5
Unit
V
V
V
V
−
−
−
−
−
−
−
−
0.1
0.6
0.3
0.8
mA
mA
mA
mA
−
−
−
−
−
−
−
−
20
120
60
160
A
A
A
A
−
−
−
−20
−
−
−
−
−
4
−0.4
−1.6
−0.8
−100
6
mA
mA
mA
mA
mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time, and duration of the short−circuit
should not exceed one second.
Note 5. For certain devices where state commutation can be caused by shorting an output to ground,
an equivalent test may be performed with VO = 2.125Vand the minimum an maximum limits
reduced to one half of their stated values.
Note 6. With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of
measurement, the clock input is grounded.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Maximum Clock Frequency
Symbol
fmax
Test Conditions
Min
Typ
RL = 2k, CL = 15pF
30
−
Propagation Delay Time
tPLH, tPHL
(From PRE, CLR or CLK input to Any Q Output)
Function Tables:
Inputs
PRE CLR CLK
J
K
L
H
X
X
X
H
L
X
X
X
L
L
X
X
X
H
H

L
L
H
H

H
L
H
H

L
H
H
H

H
H
H
H
H
X
X
Outputs
Q
Q
H
L
L
H
H{
H{
Q0
Q0
H
L
L
H
Toggle
Q0
Q0
{ This configuration is nonstable; that is, it will not persist
when wither preset or clear returns to its inactive (high) level.
Max
Unit
45
−
MHz
15
20
ns
Pin Connection Diagram
CLK 1
14 1K
1PRE 2
1J 3
13 1Q
12 1Q
VCC 4
11 GND
CLR 5
10 2J
2PRE 6
9 2Q
2K 7
8 2Q
14
8
1
7
.300 (7.62)
.785 (19.95) Max
.200
(5.08)
Max
.100 (2.45)
.600 (15.24)
.099 (2.5) Min