NTE Electronics NTE74HC573 Datasheet

NTE74HC573
Integrated Circuit
TTL − High Speed CMOS,
Octal D−Type Latch with 3−State Outputs
Description:
The NTE74HC573 is a high speed octal transparent D−type latch with 3−state outputs in a 20−Lead
DIP type package with the capability to drive 15 LS−TTL loads. When the latch−enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels
of the D inputs.
A buffered output−enable (OE) input can be used to place the eight outputs in either a normal logic state
(high or low) or the high−impedance state. In the high−impedance state, the outputs neither load nor
drive the bus lines significantly. The high−impedance state and increased drive provide the capability
to drive bus lines without interface or pullup components.
OE does not affect th internal operations of the latches. Old data can be retained or new data can be
entered while the outputs are in the high−impedance state.
To ensure the high−impedance state during power up or power down, OE should be tied to VCC through
a pullup resistor; the minimum value of th resistor is determined by the current−sinking capability of the
driver.
Features:
D Wide Power Supply Range: 2V to 6V
D Three−State Outputs Directly Drive Bus Lines
D Balanced Propagation Delays and Transition Times
D Bu Driver Outputs Drive up to 15 LS−TTL Loads
D Significant Power Reduction Compared to LS−TTL Logic ICs
Absolute Maximum Ratings: (Note 1, Note 2)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +7.0V
Clamp Diode Current, IIK, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
DC Drain Current (Per Output), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35mA
DC Output Source or Sink Current (Per Output), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
DC VCC or GND Current (Per Pin), ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Maximum Junction, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Typical Thermal Resistance, Junction−to−Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W
Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C
Note 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2. Unless otherwise specified, all voltages are referenced to GND.
Recommended Operating Conditions: (Note 3)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
2.0
−
6.0
V
High−Level Input Voltage
VCC = 2.0V
VIH
1.5
−
−
V
VCC = 4.5V
3.15
−
−
V
VCC = 6.0V
4.2
−
−
V
−
−
0.5
V
VCC = 4.5V
−
−
1.35
V
VCC = 6.0V
−
−
1.8
V
0
−
VCC
V
−
−
1000
ns
VCC = 4.5V
−
−
500
ns
VCC = 6.0V
−
−
400
ns
Low−Level Input Voltage
VCC = 2.0V
VIL
DC Input or Output Voltage
VIN, VOUT
Input Rise or Fall Times
VCC = 2.0V
tr, tf
Note 3. All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
DC Electrical Characteristics:
TA = +25C
Parameter
Minimum HIGH Level Output
Voltage
Symbol
VOH
Test Conditions
VIN = VIH IOUT = −20A
or VIL
IOUT = −6mA
IOUT = −7.8mA
Minimum LOW Level Output
Voltage
Maximum Input Leakage Current
VOL
VIN = VIH
or VIL
VCC
−
Typ
TA = −40 to +85C
Guaranteed Limits
VCC VCC −0.1
VCC −0.1
Unit
V
4.5
−
3.98
3.84
V
6.0
−
5.48
5.34
V
IOUT = 20A
−
−
0.1
0.1
V
IOUT = 6mA
4.5
0.2
0.26
0.33
V
IOUT = 7.8mA
6.0
0.2
0.26
0.33
V
IIN
VIN = VCC or GND
6.0
−
0.1
1.0
A
Three−State Leakage Current
IOZ
VIN = VIH or VIL
6.0
−
0.5
5.0
A
Maximum Quiescent Supply Current
ICC
VIN = VCC or GND, IOUT = 0A
6.0
−
8.0
80
A
Maximum Input Capacitance
CIN
−
−
10
10
pF
Maximum Output Capacitance
COUT
−
−
20
20
pF
Power Dissipation Capacitance
CPD
5
51
−
−
pF
Prerequisite for Switching Specifications:
TA = +25C
Parameter
Pulse Duration (LE High)
Setup Time (Data before LE)
Hold Time (Data after LE)
Symbol
tW
tSU
tH
Test Conditions
TA = −40 to +85C
VCC
Typ
Guaranteed Limits
2.0
−
80
100
Unit
ns
4.5
−
16
20
ns
6.0
−
14
17
ns
2.0
−
50
65
ns
4.5
−
10
13
ns
6.0
−
9
11
ns
2.0
−
40
50
ns
4.5
−
8
10
ns
6.0
−
7
9
ns
Switching Characteristics: (CL = 50pF unless otherwise specified)
TA = +25C
Parameter
Propagation Delay Time
(From Input D to Output Q)
Symbol
tpd
Propagation Delay Time
(From Input LE to Output Q)
tpd
Output Enable and Disable Time
(From Input OE to Output Q)
Output Transition Time (To Output Q)
ten, tdis
tt
Test Conditions
TA = −40 to +85C
VCC
Typ
Guaranteed Limits
2.0
−
175
220
Unit
ns
4.5
−
35
44
ns
6.0
−
30
37
ns
2.0
−
175
220
ns
4.5
−
35
44
ns
6.0
−
30
37
ns
2.0
−
150
190
ns
4.5
−
30
38
ns
6.0
−
26
33
ns
2.0
−
60
75
ns
4.5
−
12
15
ns
6.0
−
10
13
ns
Truth Table:
Inputs
Output
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
H = HIGH Level (Steady State)
L = LOW Level (Steady State)
X = Don’t Care
Q0 = The level of Q before the indicated steady state input conditions were
established.
Z = High Impedance State
Pin Connection Diagram
OE 1
20 VCC
D0 2
D1 3
19 Q0
18 Q1
D2 4
17 Q2
D3 5
16 Q3
D4 6
15 Q4
D5 7
14 Q5
D6 8
13 Q6
D7 9
12 Q7
GND 10
11 LE
20
11
1
10
.300 (7.62)
.260 (6.6) Max
1.200 (30.5) Max
.200
(5.08)
Max
.012
(0.30)
.100 (2.54) Typ
.100 (2.54) Min
.350 (8.89)