VISHAY SI4618DY_09

Si4618DY
Vishay Siliconix
Dual N-Channel 30-V (D-S) MOSFET with Schottky Diode
FEATURES
PRODUCT SUMMARY
VDS (V)
Channel-1
30
Channel-2
30
RDS(on) (Ω)
0.017 at VGS = 10 V
0.0195 at VGS = 4.5 V
0.010 at VGS = 10 V
0.0115 at VGS = 4.5 V
ID (A)a Qg (Typ.)
8.0
12.5
7.5
15.2
17
14.1
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg and UIS Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Notebook Logic dc-to-dc
• Low Current dc-to-dc
SCHOTTKY PRODUCT SUMMARY
VDS (V)
VSD (V)
Diode Forward Voltage
IF (A)a
30
0.43 V at 1.0 A
3.8
D1
SO-8
G1
G1
1
8
D1
S2
2
7
S1/D2
S2
3
6
S1/D2
G2
4
5
S1/D2
N-Channel 1
MOSFET
S1/D2
Schottky Diode
G2
Top View
N-Channel 2
MOSFET
Ordering Information: Si4618DY-T1-E3 (Lead (Pb)-free)
Si4618DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
S2
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Symbol
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
IDM
Pulsed Drain Current (10 µs Pulse Width)
Source-Drain Current Diode Current
Pulsed Source-Drain Current
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
ID
TC = 25 °C
TA = 25 °C
L = 0.1 mH
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
IS
ISM
IAS
EAS
PD
Channel-1
30
± 16
8.0
6.4
Channel-2
30
± 16
15.2
12.1
6.7b, c
5.4b, c
35
1.8
11.4b, c
9.1b, c
60
3.8
1.25b, c
35
15
11.2
1.98
1.26
2.4b, c
35
15
11.2
4.16
2.66
1.38b, c
0.88b, c
2.35b, c
1.5b, c
TJ, Tstg
Unit
V
A
mJ
- 55 to 150
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Channel-1
Typ.
Max.
72
90
RthJA
t ≤ 10 s
Maximum Junction-to-Ambientb, d
RthJF
51
Maximum Junction-to-Foot (Drain)
Steady State
Notes:
a. Based on TC = 25 °C.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under Steady State conditions is 125 °C/W (Channel-1) and 100 °C/W (Channel-2).
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
63
Channel-2
Typ.
Max.
43
53
25
30
Unit
°C/W
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1
Si4618DY
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.a
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
VDS
VGS = 0 V, ID = 1 mA
Ch-1
30
30
V
VGS = 0 V, ID = 1 mA
Ch-2
ΔVDS/TJ
ID = 250 µA
Ch-1
ΔVGS(th)/TJ
ID = 250 µA
Ch-1
VDS = VGS, ID = 1 mA
Ch-1
1
2.5
VDS = VGS, ID = 1 mA
Ch-2
1
2.5
VDS = 0 V, VGS = ± 16 V
Ch-1
100
VDS = 0 V, VGS = ± 16 V
Ch-2
100
VDS = 30 V, VGS = 0 V
Ch-1
0.001
VGS(th)
IGSS
IDSS
ID(on)
RDS(on)
gfs
VDS = 30 V, VGS = 0 V
Ch-2
VDS = 30 V, VGS = 0 V, TJ = 100 °C
Ch-1
VDS = 30 V, VGS = 0 V, TJ = 100 °C
Ch-2
35
-6
0.05
0.5
0.025
3
µA
mA
15
VDS = 5 V, VGS = 10 V
Ch-1
20
VDS = 5 V, VGS = 10 V
Ch-2
20
VGS = 10 V, ID = 8 A
Ch-1
0.014
VGS = 10 V, ID = 8 A
Ch-2
0.0083
0.010
VGS = 4.5 V, ID = 5 A
Ch-1
0.016
0.0195
VGS = 4.5 V, ID = 5 A
Ch-2
0.0095 0.0115
VDS = 15 V, ID = 8 A
Ch-1
40
VDS = 15 V, ID = 8 A
Ch-2
47
Ch-1
1535
Ch-2
2290
Ch-1
205
Ch-2
360
A
0.017
Ω
S
Dynamica
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
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2
Ciss
Channel-1
VDS = 15 V, VGS = 0 V, f = 1 MHz
Coss
Crss
Qg
Channel-2
VDS = 15 V, VGS = 0 V, f = 1 MHz
Ch-1
91
Ch-2
117
VDS = 15 V, VGS = 10 V, ID = 8 A
Ch-1
29
44
VDS = 15 V, VGS = 10 V, ID = 8 A
Ch-2
39
59
Ch-1
12.5
19
Channel-1
VDS = 15 V, VGS = 4.5 V, ID = 8 A
Ch-2
17
26
Ch-1
4.1
Channel-2
VDS = 15 V, VGS = 4.5 V, ID = 8 A
Ch-2
5.6
Ch-1
3.4
Qgs
Qgd
Rg
pF
f = 1 MHz
Ch-2
4
Ch-1
1.8
3.0
Ch-2
1.9
3.0
nC
Ω
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
Si4618DY
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Typ.a
Max.
Ch-1
8
15
Ch-2
9
16
Ch-1
22
33
Ch-2
24
36
Ch-1
20
30
Ch-2
26
39
Ch-1
8
15
Test Conditions
Min.
Unit
Dynamica
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
td(on)
Turn-On Delay Time
tr
Rise Time
Fall Time
Channel-2
VDD = 15 V, RL = 3 Ω
ID ≅ 5 A, VGEN = 10 V, Rg = 1 Ω
Channel-1
VDD = 15 V, RL = 3 Ω
ID ≅ 5 A, VGEN = 4.5 V, Rg = 1 Ω
tf
Channel-2
VDD = 15 V, RL = 3 Ω
ID ≅ 5 A, VGEN = 4.5 V, Rg = 1 Ω
IS
TC = 25 °C
td(off)
Turn-Off Delay Time
Channel-1
VDD = 15 V, RL = 3 Ω
ID ≅ 5 A, VGEN = 10 V, Rg = 1 Ω
Ch-2
8
15
Ch-1
24
36
Ch-2
24
36
Ch-1
87
130
Ch-2
97
145
Ch-1
30
45
Ch-2
35
53
Ch-1
34
51
Ch-2
45
68
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
a
Body Diode Voltage
ISM
VSD
Ch-1
1.8
Ch-2
3.8
Ch-1
35
Ch-2
35
IS = 2 A
Ch-1
0.77
1.1
IS = 1 A
Ch-2
0.37
0.43
Ch-1
22
33
Ch-2
26
39
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Channel-1
IF = 4 A, dI/dt = 100 A/µs, TJ = 25 °C
Ch-1
15
23
Ch-2
15
23
Reverse Recovery Fall Time
ta
Channel-2
IF = 4 A, dI/dt = 100 A/µs, TJ = 25 °C
Ch-1
13
Ch-2
13
Ch-1
9
Ch-2
13
Reverse Recovery Rise Time
tb
A
V
ns
nC
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
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Si4618DY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50
2.0
VGS = 10 V thru 4 V
1.6
I D - Drain Current (A)
I D - Drain Current (A)
40
30
20
3V
10
1.2
0.8
TC = 25 °C
0.4
TC = 125 °C
0.6
1.2
1.8
2.4
3.0
0
1
2
3
4
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.025
2000
0.022
1600
5
Ciss
0.019
VGS = 4.5 V
VGS = 10 V
0.016
1200
800
0.013
400
0.010
0
0
10
20
30
40
50
Coss
Crss
0
6
ID - Drain Current (A)
12
18
24
30
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
1.8
10
ID = 8 A
ID = 8 A
VGS = 10 V
1.6
8
RDS(on) - On-Resistance
(Normalized)
VGS - Gate-to-Source Voltage (V)
TC = - 55 °C
0.0
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
0
0.0
VDS = 10 V
VDS = 20 V
6
VDS = 30 V
4
2
1.4
VGS = 4.5 V
1.2
1.0
0.8
0
0
6
12
18
Qg - Total Gate Charge (nC)
Gate Charge
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4
24
30
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
Si4618DY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.10
100
ID = 8 A
I S - Source Current (A)
R DS(on) - On-Resistance (Ω)
150 °C
10
1
25 °C
0.1
0.01
0.08
0.06
0.04
125 °C
0.02
25 °C
0.00
0.001
0.2
0.4
0.6
0.8
1.0
0
1.2
1
2
3
4
5
6
7
8
9
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.5
100
0.2
80
- 0.1
Power (W)
VGS(th) Variance (V)
0.00
ID = 5 mA
- 0.4
10
60
40
ID = 250 µA
- 0.7
- 1.0
- 50
20
0
- 25
0
25
50
75
100
125
150
0.001
TJ - Temperature (°C)
0.01
0.1
1
10
Time (s)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
Limited by RDS(on)*
I D - Drain Current (A)
10
1 ms
1
10 ms
100 ms
0.1
TA = 25 °C
Single Pulse
0.01
0.1
* VGS
1s
10 s
DC
1
100
10
VDS - Drain-to-Source Voltage (V)
minimum VGS at which R DS(on) is specified
Safe Operating Area, Junction-to-Ambient
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
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Si4618DY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
I D - Drain Current (A)
8
6
4
2
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
2.5
1.20
2.0
0.96
Power Dissipation (W)
Power Dissipation (W)
Current Derating*
1.5
1.0
0.5
0.72
0.48
0.24
0.00
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power Derating, Junction-to-Foot
Power Derating, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
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Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
Si4618DY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 110 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
0.01
10-4
4. Surface Mounted
10-3
10-2
10-1
1
10
100
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
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Si4618DY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50
5
VGS = 10 V thru 5 V
4
I D - Drain Current (A)
I D - Drain Current (A)
40
30
3V
20
10
3
2
TC = 125 °C
1
TC = 25 °C
TC = - 55 °C
0
0.0
0
0.6
1.2
1.8
2.4
3.0
0
1
VDS - Drain-to-Source Voltage (V)
2
3
4
5
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.012
2800
0.011
2240
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
Ciss
VGS = 4.5 V
0.010
0.009
VGS = 10 V
0.008
1680
1120
Coss
560
Crss
0.007
0
0
10
20
30
40
50
0
12
18
24
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
10
30
1.8
ID = 8 A
VGS = 10 V
ID = 8 A
8
RDS(on) - On-Resistance
(Normalized)
VGS - Gate-to-Source Voltage (V)
6
VDS = 10 V
VDS = 30 V
6
VDS = 20 V
4
1.5
VGS = 4.5 V
1.2
0.9
2
0
0
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8
9
18
27
36
45
0.6
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
150
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
Si4618DY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.05
100
ID = 8 A
150 °C
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
10
1
25 °C
0.1
0.01
0.04
0.03
0.02
125 °C
0.01
25 °C
0.00
0.001
0.00
0.2
0.4
0.6
0.8
1.0
0
1.2
2
3
4
5
6
7
8
9
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
10
200
10-1
10-2
160
30 V
10-3
Power (W)
I S - Source Current (A)
1
10 V
10-4
10-5
120
80
40
20 V
10-6
0
25
50
75
100
125
0
0.001
150
0.01
VSD - Source-to-Drain Voltage (V)
0.1
1
10
Time (s)
Single Pulse Power, Junction-to-Ambient
Reverse Current (Schottky)
100
Limited by RDS(on)*
I D - Drain Current (A)
10
1 ms
1
10 ms
100 ms
0.1
1s
10 s
TA = 25 °C
Single Pulse
0.01
0.1
1
* VGS
DC
10
100
VDS - Drain-to-Source Voltage (V)
minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
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Si4618DY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
17
I D - Drain Current (A)
14
10
7
3
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
5
1.5
4
1.2
Power Dissipation (W)
Power Dissipation (W)
Current Derating*
3
2
0.9
0.6
0.3
1
0.0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power Derating, Junction-to-Foot
Power Derating, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
www.vishay.com
10
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
Si4618DY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 125 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
100
10
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74450.
Document Number: 74450
S09-2109-Rev. B, 12-Oct-09
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11
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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1
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72606
Revision: 21-Jan-08
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