VISHAY SI4630DY

Si4630DY
Vishay Siliconix
N-Channel 25-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
25
RDS(on) (Ω)
ID (A)a
0.0027 at VGS = 10 V
36
0.0032 at VGS = 4.5 V
29
Qg (Typ)
49 nC
• Halogen-free According to IEC 61249-2-21
Available
• TrenchFET® Power MOSFET
• 100 % Rg Tested
APPLICATIONS
• Synchronous Buck - Low Side
- Notebook
- Server
- Workstation
• Synchronous Rectifier - POL
SO-8
D
S
1
8
D
S
2
7
D
S
3
6
D
G
4
5
D
G
Top View
S
Ordering Information: Si4630DY-T1-E3 (Lead (Pb)-free)
Si4630DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Symbol
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
ID
IDM
Pulsed Drain Current
TC = 25 °C
TA = 25 °C
IS
Single Pulse Avalanche Current
Avalanche Energy
L = 0.1 mH
IAS
EAS
Maximum Power Dissipation
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
PD
Continuous Source-Drain Diode Current
TJ, Tstg
Operating Junction and Storage Temperature Range
Limit
25
± 16
40
32
Unit
V
27b, c
21b, c
70
7.0
A
3.0b, c
30
45
7.8
5.0
mJ
W
3.5b, c
2.2b, c
- 55 to 150
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambientb, d
Maximum Junction-to-Foot (Drain)
t ≤ 10 s
Steady State
Symbol
RthJA
RthJF
Typical
29
13
Maximum
35
16
Unit
°C/W
Notes:
a. Based on TC = 25 °C.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under Steady State conditions is 80 °C/W.
Document Number: 73685
S09-0138-Rev. C, 02-Feb-09
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Si4630DY
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
25
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
ΔVDS/TJ
VGS(th) Temperature Coefficient
ΔVGS(th)/TJ
Gate-Source Threshold Voltage
ID = 250 µA
VGS(th)
VDS = VGS, ID = 250 µA
Gate-Source Leakage
IGSS
VDS = 0 V, VGS = ± 16 V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
Forward Transconductancea
RDS(on)
gfs
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
Rise Time
Turn-Off DelayTime
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off DelayTime
Fall Time
tr
mV/°C
-6
1.0
2.2
V
± 100
nA
VDS = 25 V, VGS = 0 V
1
VDS = 25 V, VGS = 0 V, TJ = 55 °C
10
VDS ≥ 5 V, VGS = 10 V
VGS = 10 V, ID = 20 A
30
0.0027
VGS = 4.5 V, ID = 15 A
0.0026
0.0032
VDS = 15 V, ID = 20 A
120
6670
VDS = 15 V, VGS = 0 V, f = 1 MHz
997
pF
531
VDS = 15 V, VGS = 10 V, ID = 20 A
VDS = 15 V, VGS = 4.5 V, ID = 20 A
107.5
161
49
73
15.7
nC
13.6
f = 1 MHz
VDD = 15 V, RL = 1.5Ω
ID ≅ 10 A, VGEN = 4.5 V, Rg = 1 Ω
1.5
2.25
37
56
122
185
71
tf
15
23
td(on)
17
26
93
140
tr
Ω
S
47
td(off)
µA
A
0.0022
td(on)
td(off)
V
28
VDD = 15 V, RL = 1.5 Ω
ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω
tf
60
90
9
15
Ω
ns
Drain-Source Body Diode Characteristics
Continous Source-Drain Diode Current
Pulse Diode Forward Currenta
Body Diode Voltage
IS
TC = 25 °C
7
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
70
IS = 3 A
IF = 13 A, dI/dt = 100 A/µs, TJ = 25 °C
A
0.72
1.1
V
47
70
ns
50
75
nC
23
24
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 73685
S09-0138-Rev. C, 02-Feb-09
Si4630DY
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
70
1.2
VGS = 10 thru 3 V
1.0
50
I D - Drain Current (A)
ID - Drain Current (A)
60
40
30
20
0.8
0.6
25 °C
0.4
0.2
10
TC = 125 °C
- 55 °C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.0
2.5
0.6
VDS - Drain-to-Source Voltage (V)
1.2
1.8
2.4
3.0
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.0034
8500
0.0030
C - Capacitance (pF)
R DS(on) - On-Resistance (mΩ)
Ciss
6800
VGS = 4.5 V
0.0026
VGS = 10 V
5100
3400
0.0022
1700
0.0018
Coss
Crss
0
0
10
20
30
40
50
60
0
5
ID - Drain Current (A)
10
20
25
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
10
1.6
ID = 20 A
ID = 20 A
8
VDS = 10 V
VDS = 15 V
VGS = 20 V
4
2
(Normalized)
6
1.4
R DS(on) - On-Resistance
VG S - Gate-to-Source Voltage (V)
15
VGS = 4.5 V
1.2
VGS = 10 V
1.0
0.8
0
0
22
44
66
88
110
0.6
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 73685
S09-0138-Rev. C, 02-Feb-09
150
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Si4630DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100.000
R DS(on) - Drain-to-Source On-Resistance (Ω )
0.010
I S - Source Current (A)
10.000
150 °C
1.000
0.100
25 °C
0.010
0.001
0.008
0.006
125 °C
0.004
0.002
25 °C
0.000
0.00
0.2
0.4
0.6
0.8
1.0
0
1.2
1
2
3
4
5
6
7
8
9
10
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.5
200
ID = 250 µA
0.2
160
Power (W)
VGS(th) (V)
ID = 5 mA
- 0.1
- 0.4
120
80
- 0.7
- 1.0
- 50
40
- 25
0
25
50
75
100
125
0
0.001
150
0.01
0.1
1
TJ - Temperature (°C)
Time (s)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
10
100
Limited by RDS(on)*
1 ms
I D - Drain Current (A)
10
10 ms
1
100 ms
1s
10 s
0.1
TA = 25 °C
Single Pulse
0.01
0.1
* VGS
1
DC
10
100
VDS - Drain-to-Source Voltage (V)
minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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Document Number: 73685
S09-0138-Rev. C, 02-Feb-09
Si4630DY
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
45
40
ID - Drain Current (A)
35
30
Package Limited
25
20
15
10
5
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
10
2.0
8
1.6
Power (W)
Power (W)
Current Derating*
6
1.2
4
0.8
2
0.4
0
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power, Junction-to-Foot
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 73685
S09-0138-Rev. C, 02-Feb-09
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Si4630DY
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.05
PDM
0.1
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 60 °C/W
3. TJM – TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73685.
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Document Number: 73685
S09-0138-Rev. C, 02-Feb-09
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72606
Revision: 21-Jan-08
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Document Number: 91000
Revision: 11-Mar-11
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