VISHAY SI4202DY-T1-GE3

Si4202DY
Vishay Siliconix
Dual N-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
30
RDS(on) ()
ID (A)
0.014 at VGS = 10 V
12.1
0.017 at VGS = 4.5 V
11
Qg (Typ.)
5.4 nC
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• 100 % UIS Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Synchronous Buck
- Notebooks
- Servers
- STB
SO-8
S1
1
8
D1
G1
2
7
D1
S2
3
6
D2
G2
4
5
D2
D1
D2
G1
G2
Top View
Ordering Information: Si4202DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
S1
S2
N-Channel MOSFET
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
30
Gate-Source Voltage
VGS
± 20
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
TA = 25 °C
Continuous Source Drain Diode Current
11
ID
9.7a, b
8.2a, b
IDM
Avalanche Current
Single-Pulse Avalanche Energy
TC = 25 °C
TA = 25 °C
L = 0 1 mH
Maximum Power Dissipation
TA = 25 °C
3.1
IS
2a, b
IAS
15
EAS
11.25
mJ
3.7
2.6
PD
W
2.4a, b
1.7a, b
TA = 70 °C
TJ, Tstg
Operating Junction and Storage Temperature Range
A
50
TC = 25 °C
TC = 70 °C
V
12.1
TA = 70 °C
Pulsed Drain Current
Unit
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Maximum Junction-to-Ambienta, c
t  10 s
RthJA
50
62.5
Maximum Junction-to-Foot (Drain)
Steady State
RthJF
33
41
Unit
°C/W
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. Maximum under steady state conditions is 110 °C/W.
Document Number: 67092
S10-2602-Rev. A, 15-Nov-10
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Si4202DY
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
30
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VDS/TJ
VGS(th) Temperature Coefficient
VGS(th)/TJ
Gate-Source Threshold Voltage
ID = 250 µA
VGS(th)
VDS = VGS, ID = 250 µA
Gate-Source Leakage
IGSS
VDS = 0 V, VGS = ± 20 V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
RDS(on)
Forward Transconductancea
gfs
V
33
mV/°C
- 5.3
1.0
2.5
V
± 100
nA
VDS = 30 V, VGS = 0 V
1
VDS = 30 V, VGS = 0 V, TJ = 55 °C
10
VDS 5 V, VGS = 10 V
20
µA
A
VGS = 10 V, ID = 8 A
0.0115
0.0140
VGS = 4.5 V, ID = 5 A
0.0138
0.0170
VDS = 15 V, ID = 8 A
33

S
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
710
VDS = 15 V, VGS = 0 V, f = 1 MHz
tr
td(off)
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
VDS = 15 V, VGS = 10 V, ID = 8 A
VDS = 15 V, VGS = 4.5 V, ID = 8 A
8
1.6
nC
1.6
f = 1 MHz
VDD = 15 V, RL = 3 
ID  5 A, VGEN = 4.5 V, Rg = 1 
0.5
2.5
5
11
22
18
35
28
8
16
td(on)
8
16
VDD = 15 V, RL = 3 
ID  5 A, VGEN = 10 V, Rg = 1 
tf
Fall Time
17
5.4
14
td(off)
Turn-Off Delay Time
11.2
tf
tr
Rise Time
pF
63
td(on)
Turn-On Delay Time
Rise Time
146
9
18
17
34
8
16

ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward
Currenta
Body Diode Voltage
IS
TC = 25 °C
3.1
ISM
VSD
50
IS = 3 A
0.75
1.2
A
V
Body Diode Reverse Recovery Time
trr
13
26
ns
Body Diode Reverse Recovery Charge
Qrr
5.5
11
nC
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
IF = 5 A, dI/dt = 100 A/µs, TJ = 25 °C
8
5
ns
Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 67092
S10-2602-Rev. A, 15-Nov-10
Si4202DY
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10
50
V GS = 10 V thru 4 V
8
ID - Drain Current (A)
ID - Drain Current (A)
40
30
V GS = 3 V
20
6
4
T C = 25 °C
2
10
T C = 125 °C
T C = - 55 °C
V GS = 2 V
0
0.0
0
0.5
1.0
1.5
2.0
0
2.5
1
3
4
5
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Transfer Characteristics
Output Characteristics
0.020
1000
0.018
800
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
2
0.016
V GS = 4.5 V
0.014
V GS = 10 V
Ciss
600
400
Coss
0.012
200
0.010
0
Crss
0
10
20
30
40
0
50
18
24
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
Capacitance
30
2.0
ID = 8 A
ID = 8 A
8
1.7
V DS = 15 V
6
V DS = 10 V
V DS = 20 V
4
2
V GS = 10 V
(Normalized)
RDS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
12
On-Resistance vs. Drain Current
10
0
0.0
6
1.4
V GS = 4.5 V
1.1
0.8
2.4
4.8
7.2
9.6
12.0
0.5
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 67092
S10-2602-Rev. A, 15-Nov-10
150
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Si4202DY
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
0.060
10
0.048
RDS(on) - On-Resistance (Ω)
IS - Source Current (A)
ID = 8 A
T J = 150 °C
1
0.1
T J = 25 °C
0.036
0.024
T J = 125 °C
0.012
0.01
T J = 25 °C
0.001
0.0
0.000
0.2
0.4
0.6
0.8
1.0
0
1.2
1
2
VSD - Source-to-Drain Voltage (V)
4
5
6
7
8
9
10
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.4
30
0.2
25
0.0
20
Power (W)
VGS(th) Variance (V)
3
- 0.2
ID = 5 mA
- 0.4
15
10
ID = 250 μA
- 0.6
- 0.8
- 50
5
- 25
0
25
50
75
100
125
0
0.01
150
1
TJ - Temperature (°C)
100
Time (s)
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
100
Limited by R DS(on)*
ID - Drain Current (A)
10
1 ms
1
10 ms
100 ms
0.1
1s
10 s
DC
TA = 25 °C
Single Pulse
0.01
0.01
0.1
BVDSS Limited
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
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Document Number: 67092
S10-2602-Rev. A, 15-Nov-10
Si4202DY
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
12
ID - Drain Current (A)
10
8
6
4
2
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
4.0
1.5
3.2
1.2
2.4
0.9
Power (W)
Power (W)
Current Derating*
1.6
0.8
0.6
0.3
0.0
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
TC - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power, Junction-to-Case
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 67092
S10-2602-Rev. A, 15-Nov-10
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Si4202DY
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
Notes:
PDM
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = R thJA = 110 °C/W
3. T JM - T A = PDMZthJA(t)
Single Pulse
0.01
10 -4
10 -3
4. Surface Mounted
10 -2
10 -1
1
100
10
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?67092.
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Document Number: 67092
S10-2602-Rev. A, 15-Nov-10
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72606
Revision: 21-Jan-08
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Vishay
Disclaimer
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including but not limited to the warranty expressed therein.
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Document Number: 91000
Revision: 11-Mar-11
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