High Frequency Noise Cancellation Technology.

How Does PotatoSemi Kill inside Noise Of IC ?
Voltage mode differential Logic. New Patent IP.
Improved CMOS logic by using high frequency noise cancellation technology
VDD VDD
Potato IC
Normal IC
vv
Input1
Input2
Input3
2 1
High Frequency
Noise Cancellation
bonding diagram
18
17
5
16
5
15
6
7
14
7
14
8
13
8
13
Die
6
OUT
A
B
A
B
16
Die
15
Normal IC
bonding diagram
11 12
High
Frequency
Differential
to Single
Noise
Cancellation
Translator
A
Input
Pad
A
OUT
B
Input
Pad
OUT
A
OUT
B
Q
A
OUT
Output
Pad
B
OUT
OUT
B
Q
Normal
High
Noise OUT
Logic Core
A
OUT
B
D
CK
D
SET
SET
Q
CK
Q
RESET
RESET
Q
Q
A
OUT
C
OUT
C
B
OUT
B
vv
vv
t
vv
t
gg
PotatoSemi
vv
gg
17
Normal Chip Die
S
S
D S S Q
D
CK
CK R R Q
R
R
D
D
CK
CK
A
gg
18
4
9 10
High
OUT
Frequency
A
Voltage
Mode
Noise
B Cancellation
Differential
Logic Core OUT
B
OUT
A
3
11 12
A
OUT
B
GND GND
Potato Chip Die
OUT
A
B
A
B
20 19
4
Single to
Differential
Noise
Cancellation
Translator
A
B
A
B
2 1
3
Single to
Differential
Noise
Cancellation
Translator
B
gg
Output1
Output2
Output3
20 19
9 10
A
Die
High frequency noise
cancellation technology
t
Contact Potato Semiconductor for IP or detail.
t
gg
Normal High Noise
Noise Cancellation Logic
Voltage Mode Differential Logic
Improved CMOS logic by using high frequency noise cancellation technology
Voltage Mode Differential CMOS Logic
NAND gate
OUT
A
A
C
OUT
A
B
OUT
A
B
OUT
B
B
A
OUT
A
B
C
B
OUT
Advantage:
1. Very high output frequency. (The max. frequency can reach process max. frequency.)
2. Switching noise can be eliminating by note to note noise cancellation.
(Noise from note A & noise from note A bar will cancel each other. Noise from note B & noise from note B bar
will cancel each other. Noise from note C & noise from note C bar will cancel each other. Noise from note out
& noise from note out bar will cancel each other.)
3. Rail to rail output signals.
4. Without switching noise, logic output signal can be much stronger then other logic output signal.
5. Low jitter.
6. Output signals can drive long distance.
7. No error bit.
8. No static current.
9. Design is very similar to normal CMOS logic. It can be used for high frequency & high performance VLSI design.
Disadvantage:
More complicate design then normal CMOS logic
Bigger die size then normal low speed CMOS logic.
Example:
Potato Semiconductor ICs are using this technology such as
Normal static CMOS Logic
NAND gate
A
B
OUT
Current mode differential Logic
Dynamic Logic
Dynamic NAND gate
A
CLK
B
Current Mode Differential NAND gate
OUT
A
OUT
B
OUT
VCC
R1
CLK
R2
OUT
OUT
A
B
A
B
OUT
A
B
OUT
VB1
VB2
VEE (-4.5 to -5.2V)
Advantage:
Advantage:
Advantage:
1. Simple.
2. Small Die size.
3. No static current
1. Higher output frequency then normal logic
2. Less input capacitance & less switching
noise from input A & B then normal static logic.
1. High output frequency.
2. Low noise.
3. Low jitter.
Disadvantage:
Disadvantage:
Disadvantage:
1. High switching noise.
2. Low operating frequency.
3. Higher error bit rate.
4. Higher jitter.
5. higher propagation delay.
6. weak output signal.
1. High Power consumption.
2. Can not run lower clock frequency
3. Output signal is switching all the time.
1. Current source design with high static current.
2. Complicate design.
3. Difficult to design a perfect current source.
4. Need many extra components such as 50 ohm
loading resistors.
Example:
Example:
Example:
Most low frequency logic ICs are using this
technology such as regular 74 series CMOS logic.
Most high clock frequency ASIC ICs are using
this technology such as graphic chips.
They usually work with a big fan.
Most high frequency outputs are using this technology such as ECL logic, PECL, LVDS, CML etc.
VDD
All electronics engineers know decoupling capacitor.
However, do you know how to make them working properly?
GND
There are four examples show below.
Only last circuit can clean noise.
VDD
Only opposite noise plus decoupling capacitor working together can
How does decoupling capacitor work? release electronics from capacitor & clean up IC & system noise.
Bring Power into ICs
GND
Example 1
Normal CMOS logic without decoupling capacitor
Power voltage between vv & gg will change because of the switching noise.
VDD
A
vv
Die
gg
Input
B
Output
A
B
NAND
vv
OUT
VV
NOR
OUT
gg
gg
t
GND
Example 2
Normal CMOS logic with decoupling capacitor
Decoupling capacitor will maintain power voltage between vv & gg, but it can not clean noise
.
VDD
A
Input
vv
gg
B
Output
A
B
NAND
vv
OUT
VV
NOR
OUT
GND
gg
t
gg
Example 3
Voltage mode differential logic without decoupling capacitor
Power voltage between vv & gg will change because of the positive noise & its opposite noise.
VDD
Input
vv
Die
gg
Output
GND
A
B
A
B
NAND
A
B
A
B
NOR
OUT
OUT
OUT
vv
VV
gg
gg
OUT
t
Example 4 (Potato technology )
Voltage mode differential logic with decoupling capacitor
Positive noise & its opposite noise will cancel each other.
VDD
Input
vv
gg
GND
Output
A
B
A
B
NAND
A
B
A
B
NOR
OUT
OUT
OUT
OUT
vv
VV
release electronics
release electronics
gg
gg
t
How does the New Technology work ?
By using our special IO interface, logic cells & design rule, we can convert most of existing
Logic chips into much higher frequency than it was before. After we convert the standard
chips, all chips become much more reliable, much less noise and much higher running
frequency.
Compare to 74 Series Logic
PotatoSemi
TI
A
Y
B
Fairchild
Renesa
NXP
PO74G32A
SN74ALVC32
74LVX32
HD74LV32A
74ALVC32
1.65V ~ 3.6V
1.65V ~ 3.6V
2V - 3.6V
2V ~ 5.5V
1.65V ~ 3.6V
Max.
Frequency
2 GHz
200 MHz
200 MHz
200 MHz
200 MHz
Propagation
delay (Max)
1.5 ns
2.8 ns
7.5 ns
6.5 ns
2.8 ns
Low input
capacitance
4.0 pf
4.0 pf
4.0 pf
4.0 pf
3.5 pf
Device
Vcc
OUT1
OUT2
OUT3
OUT4
Compare to Clock Buffers
OUT5
IN1
OUT6
OUT7
OUT8
OUT9
OUT10
PotatoSemi
Pericom
IDT
ICS
Cypress
NXP
Device
PO49FCT3807B
49FCT3807
74FCT3807E-D
MK3807-01
CY2CC810
PCK3807A
Vcc
1.65V ~ 3.6V
3.3V
3.3V
3.3V
2.5V or 3.3V
2.5V or 3.3V
Max. Frequency
800M Hz
156 MHz
166 MHz
100MHz
250MHz
150 MHz
pin to pin skew
80 ps
250 ps
100 ps
350 ps
380 ps
120 ps
Pulse skew
250 ps
250 ps
250 ps
350 ps
200 ps
300 ps
Propagation delay
(Max)
2.0 ns
2.5 ns
2.0 ns
3.8 ns
3.5 ns
2.5 ns
Low input
capacitance
3 pf
3.0 pf
3 pf
5 pf
3 pf
3 pf
How does the New Technology work ?
Compare to GHz Bus Switch
A0
SW
B0
A4
SW
B4
A5
SW
B5
A9
SW
B9
EN1
EN2
PotatoSemi
Pericom
TI
Fairchild
Device
PO3B1000A
PI3CH1000
SN74CB3Q3384A
FST3384
Vcc
1.65V ~ 3.6V
2.5V / 3.3V
2.3V ~ 3.6V
4.0V~5.5V
Wide Bandwidth
( -3db ) AC
1.2GHz
500 MHz
500 MHz
N/A
Near-Zero Delay
Yes
Yes
Yes
Yes
Special design for
differential signals
Yes
No
No
No
18
8
9
20
Ron (Max.) DC
Con T( yp.)
7.9 pf
6.4 pf
10 pf
5 pf
Ultra-Low Quiescent Power
(Typ.)
0.1µA
N/A
1000 µA
0.1µA
Quiescent Power (Max.)
3 µA
800 µA
2000 µA
3 µA
D0
Compare to GHz Translator
D0
OUT0
D1
OUT1
D1
PotatoSemi
Device
OnSemi
PO100HSTL23A MC100EPT23-D
Micrel
TI
ICS
SY89323L
SN65LVDS9637D
ICS83023I
Vcc
2.4V ~ 3.6V
3V-3.6V
3V-3.6V
3V-3.6V
3V-3.6V
Max. Frequency
1 GHz
275 MHz
275 MHz
200 MHz
350 MHz
pin to pin skew
150 ps
125 ps
300 ps
400 ps
60 ps
output skew
(different package)
300 ps
500 ps
500 ps
1000 ps
500 ps
propagation delay
(Max)
1.8 ns
2.4 ns
2.5 ns
3 ns
2.4 ns
Next Generation Logic Cells
The best way to improve an IC is from the core circuit structure!
High Cost
High Cost
High Cost
Low Cost &
Easy implement
Best
Performance
High Frequency
Noise
Cancellation
CMOS Logic
Current
Performance
DIP, SMC
, BGA, Flip Chip
Improve
Package
45nm, 55nm, 65nm,
90nm, 0.13um, 0.18um,
0.25um, 0.35um, 0.5um
Improve
Process
GHz CMOS Output
X86, Dual Core,
64 Architecture, etc.
Improve
Architecture
50 years old
High Noise
CMOS Logic
Improve
Circuit
Structure
CMOS technology has been widely used for
more then 50 years. It delivers the low cost
with high yield. However, because of the
unbalanced CMOS structure, it will generate
high noise into Power & ground. From the
past 50 years of IC history, our GHz CMOS
output driver is the only technology that you
can kill your chip internal ground and
power noise without scarifies your output
performance. Because of this noise cancellation
technology, our output frequency can be 7 to
10 times faster then anyone else in this world.
In addition, because of this low noise-tech
nology, any ICs with our output drivers can
deliver the accuracy without any error.
The example shows the output signal from
our standard logic PO74G32A. The VCC is
3V. The output frequency from the measurement is 2GHz with probe loading. The max
frequency will be more than 2GHz. Vp-p is
2.075V. Vhigh is 2.175V. Vlow is 100mV.