SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B 3 2 1 20 19 4B VCC SN55LVDS32FK (TOP VIEW) 1Y 4 18 4A G 5 17 4Y NC 6 16 NC 2Y 7 15 G 2A 8 14 3Y 9 10 11 12 13 3A The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100 mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. 3 3B description 15 NC D 16 2 1B D 1 NC D D 1B 1A 1Y G 2Y 2A 2B GND GND D D D SN55LVDS32 . . . J OR W SN65LVDS32D (Marked as LVDS32 or 65LVDS32) (TOP VIEW) 1A D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard Operates with a Single 3.3-V Supply Designed for Signaling Rate of Up To 400 Mbps Differential Input Thresholds ± 100 mV Max Typical Propagation Delay Time of 2.1 ns Power Dissipation 60 mW Typical per Receiver at 200 MHz Bus-Terminal ESD Protection Exceeds 8 kV Low-Voltage TTL (LVTTL) Logic Output Levels Pin-Compatible with the AM26LS32, MC3486, and µA9637 Open-Circuit Fail Safe 2B D SN65LVDS3486D (Marked as LVDS3486) (TOP VIEW) 1B 1A 1Y 1,2EN 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y 3,4EN 3Y 3A 3B SN65LVDS9637D (Marked as DK637 or LVDS37) SN65LVDS9637DGN (Marked as L37) (TOP VIEW) VCC 1Y 2Y GND The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are characterized for operation from – 40°C to 85°C. The SN55LVDS32 is characterized for operation from – 55°C to 125°C. 1 8 2 7 3 6 4 5 1A 1B 2A 2B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) – 40°C to 85°C SN65LVDS9637D SN65LVDS9637DGN — — — — — SN55LVDS32FK SN55LVDS32J SN55LVDS32W – 55°C to 125°C MSOP (DGN) CHIP CARRIER (FK) CERAMIC DIP (J) FLAT PACK (W) SN65LVDS32D — — — — SN65LVDS3486D — — — — ’LVDS32 logic diagram (positive logic) G G 1A 1B ’LVDS3486D logic diagram (positive logic) 4 1A 12 2 1B 1,2EN 3 1Y 1 2 3 1Y 1 2A 4 6 2Y 2Y 2B 3A 3B 4A 4B 10 3A 11 9 3Y 3B 10 11 9 3Y 12 3,4EN 14 15 13 4Y 4A 4B 2 5 5 14 15 POST OFFICE BOX 655303 13 4Y • DALLAS, TEXAS 75265 2B 2 1Y 7 6 2B 5 8 2A 2A 7 1A 1B 7 6 ’LVDS9637D logic diagram (positive logic) 3 2Y SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 Function Tables SN55LVDS32, SN65LVDS32 SN65LVDS3486 ENABLES DIFFERENTIAL INPUT OUTPUT DIFFERENTIAL INPUT ENABLE OUTPUT A, B G G Y A, B EN Y VID ≥ 100 mV H X X L H H VID ≥ 100 mV H X H H –100 mV < VID < 100 mV H X X L ? ? –100 mV < VID < 100 mV H X ? ? VID ≤ –100 mV H X X L L L VID ≤ –100 mV H X L L X L H Z X L Z Open H X X L H H Open H X H H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate logic symbol† G G SN55LVDS32, SN65LVDS32 4 SN65LVDS3486 ≥1 12 4 1, 2EN EN 2 1A 1A 1B 2A 2B 3A 3B 4A 4B 6 2A 3 1 5 6 7 10 11 12 3, 4EN 2Y 14 4A 14 13 15 3Y 13 15 4B 4Y 11 9 3B 9 2Y EN 10 3A 3Y 1Y 5 7 2B 1Y 3 1 1B 2 EN 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Function Table logic symbol† SN65LVDS9637 SN65LVDS9637 DIFFERENTIAL INPUT OUTPUT A, B Y 1A VID ≥ 100 mV –100 mV < VID < 100 mV H 1B ? 2A VID ≤ –100 mV Open L 2B H H = high level, L = low level, ? = indeterminate POST OFFICE BOX 655303 8 7 6 5 2 3 1Y 2Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. • DALLAS, TEXAS 75265 3 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 equivalent input and output schematic diagrams EQUIVALENT OF EACH A OR B INPUT EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS VCC VCC 300 kΩ TYPICAL OF ALL OUTPUTS VCC 300 kΩ 50 Ω 5Ω Input Y Output A Input 7V B Input 7V 7V 7V absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input voltage range, VI (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65_C to 150_C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D (8) 725 mW 5.8 mW/°C 464 mW 377 mW — D (16) 950 mW 7.6 mW/°C 608 mW 494 mW — DGN 2.14 W 17.1 mW/°C 1.37 W 1.11 W — FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW W 1000 mW 8.0 mW/°C 640 mW 520 mW 200 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 recommended operating conditions MIN Supply voltage, VCC 3 High-level input voltage, VIH G, G, 1,2EN, or 3,4EN Low-level input voltage, VIL G, G, 1,2EN, or 3,4EN NOM MAX 3.3 3.6 2 Magnitude of differential input voltage, |VID| |V ID 2 free air temperature, temperature TA Operating free-air | V V 0.1 Common-mode input voltage, VIC (see Figure 1) UNIT 2.4 * 0.8 V 0.6 V |V ID 2 | SN65 prefix – 40 VCC – 0.8 85 SN55 prefix – 55 125 V V °C COMMON-MODE INPUT VOLTAGE RANGE vs DIFFERENTIAL INPUT VOLTAGE VIC – Common Mode Input Voltage – V 2.5 2 Max at VCC >3.15 V Max at VCC = 3 V 1.5 1 ÁÁ ÁÁ ÁÁ 0.5 Min 0 0 0.1 0.2 0.3 0.4 0.5 VID – Differential Input Voltage – V 0.6 Figure 1. VIC Versus VID and VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER TEST CONDITIONS SN65LVDS32, SN65LVDS3486, SN65LVDS9637 MIN VITH+ VITH– Positive-going differential input voltage threshold VOH VOL High-level output voltage ICC Supply current See Figure 2 and Table 1 Negative-going differential input voltage threshold‡ IOH = –8 mA IOL = 8 mA Low-level output voltage II Input current (A or B inputs) II(OFF) IIH Power-off input current (A or B inputs) SN65LVDS32,, SN65LVDS3486 Enabled, SN65LVDS9637 No load MAX 100 –100 No load V 10 18 0.25 0.5 5.5 10 –2 –10 – 20 – 1.2 –3 VI = 3.6 V mV mV 0.4 Disabled VCC = 0, VIH = 2 V UNIT 2.4 VI = 0 VI = 2.4 V High-level input current (EN, G, or G inputs) TYP† 6 V mA µA 20 µA 10 µA IIL Low-level input current (EN, G, or G inputs) VIL = 0.8 V 10 µA IOZ High-impedance output current VO = 0 or VCC ± 10 µA † All typical values are at TA = 25°C and with VCC = 3.3 V. ‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for the negative-going differential input voltage threshold only. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ SN65LVDSxxxx switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SN65LVDS32, SN65LVDS3486, SN65LVDS9637 UNIT MIN TYP MAX tpLH tpHL Propagation delay time, low-to-high-level output 1.5 2.1 3 ns Propagation delay time, high-to-low-level output 1.5 2.1 3 ns tsk(p) tsk(o) Pulse skew (|tPHL – tPLH|) 0 0.4 ns 0.1 0.3 ns 1 ns tsk(pp) tr Channel-to-channel output skew† Part-to-part skew‡ CL = 10 pF, See Figure 3 Output signal rise time, 20% to 80% 0.6 tf tpHZ Output signal fall time, 80% to 20% 0.7 Propagation delay time, high-level-to-high-impedance output 6.5 12 ns tpLZ tpZH Propagation delay time, low-level-to-high-impedance output 5.5 12 ns 8 12 ns Propagation delay time, high-impedance-to-high-level output See Figure 4 ns ns tpZL Propagation delay time, high-impedance-to-low-level output 3 12 ns † tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. ‡ tsk(pp) is the magnitude of the different in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 SN55LVDS32 Selectrical characteristics over recommended operating conditions (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER TEST CONDITIONS VITH+ VITH– Positive-going differential input voltage threshold VOH VOL High-level output voltage Negative-going differential input voltage threshold‡ See Figure g 2,, Table 1,, and Note 2 IOH = –8 mA IOL = 8 mA Low-level output voltage Supply current II Input current (A or B inputs) II(OFF) IIH Power-off input current (A or B inputs) 100 –100 10 18 0.25 0.5 –2 –10 – 20 – 1.2 –3 Disabled VI = 0 VI = 2.4 V High-level input current (EN, G, or G inputs) VCC = 0, VIH = 2 V VI = 2.4 V mV V 0.4 No load UNIT mV 2.4 Enabled, ICC SN55LVDS32 TYP† MAX MIN 6 V mA µA 20 µA 10 µA IIL Low-level input current (EN, G, or G inputs) VIL = 0.8 V 10 µA IOZ High-impedance output current VO = 0 or VCC ± 12 µA † All typical values are at TA = 25°C and with VCC = 3.3 V. ‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for the negative-going differential input voltage threshold only. NOTE 2: |VITH| = 200 mV for operation at – 55°C. SN55LVDS32 switching characteristics over recommended operating conditions (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER tpLH tpHL tsk(o) tr TEST CONDITIONS Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output Channel-to-channel output skew† Output signal rise time, 20% to 80% CL = 10 pF, See Figure 3 CL = 10 pF, pF See Figure 3 SN55LVDS32 MAX UNIT MIN TYP 1.3 2.3 6 ns 1.4 2.2 6.1 ns 0.1 ns 0.6 ns 0.7 ns tf tpHZ Output signal fall time, 80% to 20% Propagation delay time, high-level-to-high-impedance output 6.5 12 ns tpLZ tpZH Propagation delay time, low-level-to-high-impedance output 5.5 12 ns 8 14 ns 3 12 ns Propagation delay time, high-impedance-to-high-level output See Figure 4 tpZL Propagation delay time, high-impedance-to-low-level output † tsk(o) is the maximum delay time difference between drivers on the same device. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION A Y VID B (VIA + VIB)/2 VIA VIC VO VIB Figure 2. Voltage Definitions ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES 8 RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE VIA 1.25 V VIB 1.15 V VID 100 mV VIC 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V –100 mV 2.35 V 0.1 V 0V 100 mV 0.05 V 0V 0.1 V –100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V –600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V –600 mV 2.1 V 0.6 V 0V 600 mV 0.3 V 0V 0.6 V –600 mV 0.3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VID VIA CL 10 pF VIB VO VIA 1.4 V VIB 1V 0.4 V 0 –0.4 V VID tPHL tPLH 80% VO 20% 80% 20% VOH 1.4 V VOL tf tr NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 3. Timing Test Circuit and Wave Forms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION B 1.2 V 500 Ω A G Inputs (see Note A) 10 pF (see Note B) ± VO VTEST G 1,2EN or 3,4EN 2.5 V VTEST A 1V 2V 1.4 V 0.8 V G, 1,2EN, or 3,4EN 2V 1.4 V 0.8 V tPLZ G tPLZ tPZL tPZL Y VTEST 2.5 V 1.4 V VOL +0.5 V VOL 0 1.4 V A G, 1,2EN, or 3,4EN 2V 1.4 V 0.8 V G 2V 1.4 V 0.8 V tPHZ tPHZ tPZH tPZH VOH VOH –0.5 V Y 1.4 V 0 NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 4. Enable/Disable Time Test Circuit and Wave Forms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS SN55LVDS32, SN65LVDS32 SUPPLY CURRENT vs FREQUENCY LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE Four Receivers, Loaded Per Figure 3, Switching Simultaneously VCC = 3.6 V VCC = 3.3 V 65 VCC = 3 V 55 45 35 25 15 50 150 100 200 2.7 2.5 VCC = 3 V VCC = 3.3 V 2.3 VCC = 3.6 V 2.1 1.9 1.7 1.5 –50 f – Frequency – MHz 0 50 TA – Free-Air Temperature – °C Figure 5 100 Figure 6 HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL(D)– High-To-Low Propagation Delay Time – ns I CC – Supply Current – mA(rms) 75 t PLH(D)– Low-To-High Propagation Delay Time – ns 85 2.7 2.5 2.3 VCC = 3 V 2.1 VCC = 3.3 V 1.9 VCC = 3.6 V 1.7 1.5 –50 0 50 TA – Free-Air Temperature – °C 100 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 APPLICATION INFORMATION using an LVDS receiver with RS-422 data Receipt of data from a TIA/EIA-422 line driver may be accomplished using a TIA/EIA-644 line receiver with the addition of an attenuator circuit. This technique gives the user a very high-speed and low-power 422 receiver. If the ground noise between the transmitter and receiver is not a concern (less than ±1 V), the answer can be as simple as shown below in Figure 8. The use of a resistor divider circuit in front of the LVDS receiver attenuates the 422 differential signal to LVDS levels. The resistors present a total differential load of 100 Ω to match the characteristic impedance of the transmission line and to reduce the signal 10:1. The maximum 422 differential output signal or 6 V is reduced to 600 mV. The high input impedance of the LVDS receiver prevents input bias offsets and maintains a better than 200-mV differential input voltage threshold at the inputs to the divider. This circuit is used in front of each LVDS channel that also receives 422 signals. R1 45.3 Ω ’LVDS32 R3 5.11 Ω A R4 5.11 Ω B Y R2 45.3 Ω NOTE A: The components used were standard values. R1, R2 = NRC12F45R3TR, NIC Components, 45.3 Ohm, 1/8W, 1%, 1206 Package R3, R4 = NRC12F5R11TR, NIC Components, 5.11 Ohm, 1/8W, 1%, 1206 Package The resistor values do not need to be 1% tolerance. However, it can be difficult locating a supplier of resistors having values less than 100 Ω in stock and readily available. The user may find other suppliers with comparable parts having tolerances of 5% or even 10%. These parts are adequate for use in this circuit. Figure 8. RS-422 Data Input to an LVDS Receiver Under Low Ground Noise Conditions If ground noise between the RS-422 driver and LVDS receiver is a concern, then the common-mode voltage must be attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS receiver ground. This modification to the circuit increases the common-mode voltage from ±1 V to greater than ±4.5 V. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 APPLICATIONS INFORMATION The devices are generally used as building blocks for high-speed point-to-point data transmission where ground differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers approach ECL speeds without the power and dual supply requirements. TRANSMISSION DISTANCE vs SIGNALING RATE Transmission Distance – m 100 30% Jitter (see Note A) 10 5% Jitter (see Note A) 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 10 100 1000 Signaling Rate – Mbps NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudo-random data pattern. Figure 9. Typical Transmission Distance Versus Signaling Rate 1 1B VCC 16 0.1 µF (see Note A) 100 Ω 2 3 VCC 4 5 6 1A 4B 2Y 4Y G 2A 100 Ω 7 4A 2B 3Y 3A 0.001 µF (see Note A) 15 1Y G 3.3 V 14 100 Ω (see Note B) 13 12 11 See Note C 10 100 Ω 8 GND 3B 9 NOTES: A. Place a 0.1 µF and a 0.001 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitors should be located as close as possible to the device terminals. B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%. C. Unused enable inputs should be tied to VCC or GND as appropriate. Figure 10. Typical Application Circuit Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 APPLICATION INFORMATION 1/4 ’LVDS31 Strb/Data_TX TpBias on Twisted-Pair A Strb/Data_Enable TP 55 Ω ’LVDS32 5 kΩ Data/Strobe 55 Ω 3.3 V TP 20 kΩ 500 Ω VG on Twisted-Pair B 1 Arb_RX 500 Ω 20 kΩ 3.3 V 20 kΩ 500 Ω 2 Arb_RX 500 Ω 20 kΩ 3.3 V 7 kΩ Twisted-Pair B Only 7 kΩ 10 kΩ Port_Status 3.3 kΩ NOTES: A. B. C. D. Resistors are leadless thick-film (0603) 5% tolerance. Decoupling capacitance is not shown but recommended. VCC is 3 V to 3.6 V. The differential output voltage of the ’LVDS31 can exceed that allowed by IEEE1394. Figure 11. 100-Mbps IEEE 1394 Transceiver 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 APPLICATION INFORMATION fail safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV if it is within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high level, regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt Y B VIT ≈ 2.3 V Figure 12. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pull-up currents from the receiver and the fail-safe feature. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 APPLICATION INFORMATION 0.01 µF 1 VCC 16 0.1 µF (see Note A) 1B 100 Ω 2 3 VCC 4 5 6 1A 4B 2Y 4Y G 2A 100 Ω 7 4A 2B 3Y 3A 5V 1N645 (2 places) 15 1Y G ≈3.6 V 14 100 Ω (see Note B) 13 12 11 See Note C 10 100 Ω 8 GND 3B 9 NOTES: A. Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitor should be located as close as possible to the device terminals. B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%. C. Unused enable inputs should be tied to VCC or GND as appropriate. Figure 13. Operation with 5-V Supply related information IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com for more information. For more application guidelines, please see the following documents: D D D D D D 16 Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014) Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038) Reducing EMI with LVDS (SLLA030) Slew Rate Control of LVDS Circuits (SLLA034) Using an LVDS Receiver with RS-422 Data (SLLA031) Evaluating the LVDS EVM (SLLA033) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 MECHANICAL INFORMATION D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 MECHANICAL INFORMATION DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 Thermal Pad (See Note D) 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073271/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-187 PowerPAD is a trademark of Texas Instruments Incorporated. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 MECHANICAL INFORMATION FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 MECHANICAL INFORMATION J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE 14 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.310 (7,87) 0.310 (7,87) 0.310 (7,87) 0.310 (7,87) A MIN 0.290 (7,37) 0.290 (7,37) 0.290 (7,37) 0.290 (7,37) B MAX 0.785 (19,94) 0.785 (19,94) 0.910 (23,10) 0.975 (24,77) B MIN 0.755 (19,18) 0.755 (19,18) C MAX 0.300 (7,62) 0.300 (7,62) 0.300 (7,62) 0.300 (7,62) C MIN 0.245 (6,22) 0.245 (6,22) 0.245 (6,22) 0.245 (6,22) DIM B 8 14 C 1 7 0.065 (1,65) 0.045 (1,14) 0.100 (2,54) 0.070 (1,78) 0.020 (0,51) MIN 0.930 (23,62) A 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.100 (2,54) 0°–15° 0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20) 4040083/D 08/98 NOTES: A. B. C. D. E. 20 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 MECHANICAL INFORMATION W (R-GDFP-F16) CERAMIC DUAL FLATPACK Base and Seating Plane 0.285 (7,24) 0.245 (6,22) 0.006 (0,15) 0.004 (0,10) 0.085 (2,16) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.305 (7,75) 0.275 (6,99) 0.355 (9,02) 0.235 (5,97) 1 0.355 (9,02) 0.235 (5,97) 16 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.440 (11,18) 0.371 (9,42) 0.025 (0,64) 0.015 (0,38) 8 9 1.025 (26,04) 0.745 (18,92) 4040180-3 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL-STD-1835 GDFP1-F16 and JEDEC MO-092AC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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