HD74LV166A Parallel-Load 8-bit Shift Register REJ03D0321–0300Z (Previous ADE-205-268A (Z)) Rev.3.00 Jun. 04, 2004 Description The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV166AFPEL HD74LV166ARPEL HD74LV166ATELL SOP–16 pin(JEITA) SOP–16 pin(JEDEC) TSSOP–16 pin FP–16DAV FP–16DNV TTP–16DAV FP RP T EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Rev.3.00 Jun. 04, 2004 page 1 of 9 HD74LV166A Function Table Inputs Internal outputs Output CLR SH/LD CLK INH CLK SER A ... H QA QB QH L H H H H H X X L H H X X L L L L H X L ↑ ↑ ↑ ↑ X X X H L X X X a ... h X X X L QA0 a H L QA0 L QB0 b QAn QAn QB0 L QH0 h QGn QGn QH0 Note: H: High level L: Low level ↑: Low to high transition X: Immaterial a ... h: Parallel data Outputs remain unchanged. QA0 ... QH0: Data shifted from the previous stage on a positive edge at the clock input. QAn ... QGn: Pin Arrangement 16 VCC SER 1 A 2 15 SH/LD B 3 14 H C 4 13 QH D 5 12 G CLK INH 6 11 F CLK 7 10 E 9 CLR GND 8 (Top view) Rev.3.00 Jun. 04, 2004 page 2 of 9 HD74LV166A Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range VCC Input voltage range*1 Output voltage range*1, 2 VI VO V V V Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)*3 IIK IOK IO –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±25 ±50 Storage temperature Tstg ICC or IGND PT mA mA mA mA mW 785 500 –65 to 150 Conditions Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range Output current VI VO IOH 2.0 0 0 — — — — — — — — 0 0 0 5.5 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 V V V µA mA –40 85 °C IOL Input transition rise or fall rate ∆t /∆v Operating free-air temperature Ta Note: Unused or floating inputs must be held high or low. Rev.3.00 Jun. 04, 2004 page 3 of 9 µA mA ns/V Conditions H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V HD74LV166A Logic Diagram A SER B C D E F CLR G H SH/LD CLK CLK INH R CP S CD Q R CP S Q CD QH Timing Diagram CLK CLK INH CLR SER SH/LD Parallel Inputs A H B L C H D L E H L F G H H H H Output QH Serial shift Clear Rev.3.00 Jun. 04, 2004 page 4 of 9 Inhibit Load H L H L H Serial shift L H L HD74LV166A DC Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V)* Min Typ Max Unit Input voltage VIH 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 — — — — VCC – 0.1 2.0 2.48 3.8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 — — — — 0.1 0.4 0.44 0.55 ±1 20 V Input current Quiescent supply current IIN ICC 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 Output leakage current IOFF 0 — — Input capacitance CIN 3.3 — 1.7 VIL Output voltage VOH VOL Test Conditions µA µA IOL = –50 µA IOL = –2 mA IOL = –6 mA IOL = –12 mA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, IO = 0 5 µA VI or VO = 0 V to 5.5 V — pF VI = VCC or GND V Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00 Jun. 04, 2004 page 5 of 9 HD74LV166A Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 50 40 80 65 — — 45 35 — — MHz CL = 15 pF CL = 50 pF Propagation delay time tPLH/tPHL — — — — 6.0 12.2 15.3 10.8 14.2 — 19.8 23.3 16.0 19.5 — 1.0 1.0 1.0 1.0 7.0 22.0 26.0 18.0 22.0 — ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 7.0 6.5 7.0 — — — — — — 7.0 8.5 8.5 — — — 8.5 –0.5 –0.5 –0.5 8.0 8.5 — — — — — — — — — — — — 9.5 0.0 0.0 0.0 9.0 9.0 — — — — — — tPHL Setup time tsu Hold time th Pulse width tw FROM (Input) TO (Output) CLK QH CLR CLR inactive before CLK ↑ CLK INH before CLK ↑ Data before CLK ↑ ns SH/LD high before CLK ↑ SER before CLK ↑ PAR data after SH/LD ↑ SER data after CLK ↑ SH/LD high after CLK ↑ CLR low CLK H or L ns ns VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 65 60 115 90 — — 55 50 — — MHz CL = 15 pF CL = 50 pF Propagation delay time tPLH/tPHL — — — — 4.0 8.6 10.9 7.9 10.4 — 15.4 18.9 12.5 16.3 — 1.0 1.0 1.0 1.0 4.0 18.0 21.5 15.0 18.5 — ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 5.0 5.0 5.0 — — — — — — 5.0 6.0 6.0 — — — 5.0 0.0 0.0 0.0 6.0 6.0 — — — — — — — — — — — — 6.0 0.0 0.0 0.0 7.0 7.0 — — — — — — tPHL Setup time tsu Hold time th Pulse width tw Rev.3.00 Jun. 04, 2004 page 6 of 9 ns ns ns FROM (Input) TO (Output) CLK QH CLR CLR inactive before CLK ↑ CLK INH before CLK ↑ Data before CLK ↑ SH/LD high before CLK ↑ SER before CLK ↑ PAR data after SH/LD ↑ SER data after CLK ↑ SH/LD high after CLK ↑ CLR low CLK H or L HD74LV166A Switching Characteristics (cont) VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Test Conditions Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax 110 95 165 125 — — 90 85 — — MHz CL = 15 pF CL = 50 pF Propagation delay time tPLH/tPHL — — — — 3.5 6.0 7.7 5.4 6.9 — 9.9 11.9 8.6 10.6 — 1.0 1.0 1.0 1.0 3.5 11.5 13.5 10.0 12.0 — ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 3.5 4.5 4.0 — — — — — — 3.5 4.5 4.0 — — — 4.0 1.0 1.0 1.0 5.0 4.0 — — — — — — — — — — — — 4.0 1.0 1.0 1.0 5.0 4.0 — — — — — — tPHL Setup time tsu Hold time th Pulse width tw FROM (Input) TO (Output) CLK QH CLR CLR inactive before CLK ↑ CLK INH before CLK ↑ Data before CLK ↑ ns SH/LD high before CLK ↑ SER before CLK ↑ PAR data after SH/LD ↑ SER data after CLK ↑ SH/LD high after CLK ↑ CLR low CLK H or L ns ns Operating Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 5.0 — — 36.1 37.5 — — pF f = 10 MHz Test Circuit Measurement point CL* Note: C L includes the probe and jig capacitance. Rev.3.00 Jun. 04, 2004 page 7 of 9 HD74LV166A Waveforms tW VCC CLR 50%VCC 50%VCC tn tn+1 tn 0V tn+1 VCC tsu CLK 50%VCC 50%VCC 50%VCC 0V tW tsu Data 50%VCC th tsu 50%VCC 50%VCC th VCC 50%VCC 50%VCC 0V tPHL tPHL tPHL VOH Output QH 50%VCC 50%VCC 50%VCC VOL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns 2. The output are measured one at a time with one transition per measurement. Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.70 ± 0.20 0.15 0.12 M *Ni/Pd/Au plating Rev.3.00 Jun. 04, 2004 page 8 of 9 Package Code JEDEC JEITA Mass (reference value) FP-16DAV — Conforms 0.24 g HD74LV166A As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 + 0.10 6.10 – 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.15 0.25 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DNV Conforms Conforms 0.15 g As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 *0.20 ± 0.05 1.0 0.13 M Rev.3.00 Jun. 04, 2004 page 9 of 9 *0.15 ± 0.05 1.10 Max *Ni/Pd/Au plating 0.10 0.07 +0.03 –0.04 6.40 ± 0.20 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. 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