HD74ALVCH16820 3.3-V 10-bit Flip Flops with Dual Outputs REJ03D0034-0400Z (Previous ADE-205-170B(Z)) Rev.4.00 Oct.02.2003 Description The flip flops of the HD74ALVCH16820 are edge triggeredd D-type flip flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable ((OE) input can be used to place the ten outputs in either a normal al logic state (high or low logic level) or a high tputs neither load nor drive the bus lines significantly. impedance state. In the high impedance state, the outputs The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE input does not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features • • • • • VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors Rev.4.00, Oct.02.2003, page 1 of 11 HD74ALVCH16820 Function Table Output Qn *1 Inputs OEn *2 CLK D L ↑ H H L ↑ L L L L X Q0 *1 H X X Z H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Notes: 1. Output level before the indicated steady state input conditions were established. 2. n = 1, 2 Rev.4.00, Oct.02.2003, page 2 of 11 HD74ALVCH16820 Pin Arrangement 1OE 1 56 CLK 1Q1 2 55 D1 1Q2 3 54 NC 53 GND GND 4 2Q1 5 52 D2 2Q2 6 VCC 7 51 NC 3Q1 8 49 D3 3Q2 9 48 NC 4Q1 10 47 D4 50 VCC GND 11 46 GND 4Q2 12 45 NC 5Q1 13 44 D5 5Q2 14 43 NC 6Q1 15 42 D6 6Q2 16 41 NC 7Q1 17 40 D7 39 GND GND 18 7Q2 19 38 NC 8Q1 20 37 D8 8Q2 21 36 NC VCC 22 35 VCC 9Q1 23 34 D9 9Q2 24 33 NC GND 25 32 GND 10Q1 26 31 D10 10Q2 27 30 NC 2OE 28 29 NC (Top view) Rev.4.00, Oct.02.2003, page 3 of 11 HD74ALVCH16820 Absolute Maximum Ratings Item Supply voltage Input voltage *1 Symbol Ratings Unit VCC –0.5 to 4.6 V Conditions VI –0.5 to 4.6 V Output voltage *1, 2 VO –0.5 to VCC +0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC VCC, GND current / pin ICC or IGND ±100 mA Maximum power dissipation *3 at Ta = 55°C (in still air) PT 1 W Storage temperature Tstg –65 to 150 °C TSSOP Notes: Stresses beyond those listed under “absolute e maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional unctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended operating conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current IOH — –12 mA — –12 VCC = 2.7 V — –24 VCC = 3.0 V — 12 — 12 VCC = 2.7 V — 24 VCC = 3.0 V Low level output current IOL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. Rev.4.00, Oct.02.2003, page 4 of 11 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCH16820 Logic Diagram 1OE 2OE CLK 1 28 2 56 1Q1 C1 D1 55 3 1D To nine other channels Rev.4.00, Oct.02.2003, page 5 of 11 1Q2 HD74ALVCH16820 Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) *1 Input voltage VIH VIL Output voltage VOH Min Max Unit 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 V Test Conditions IOH = –100 µA Min to Max VCC–0.2 — 2.3 2.0 — IOH = –6 mA, VIH = 1.7 V 2.3 1.7 — IOH = –12 mA, VIH = 1.7 V 2.7 2.2 — IOH = –12 mA, VIH = 2.0 V 3.0 2.4 — IOH = –12 mA, VIH = 2.0 V 3.0 2.0 — IOH = –24 mA, VIH = 2.0 V Min to Max — 0.2 IOL = 100 µA 2.3 — 0.4 IOL = 6 mA, VIL = 0.7 V 2.3 — 0.7 IOL = 12 mA, VIL = 0.7 V 2.7 — 0.4 IOL = 12 mA, VIL = 0.8 V 3.0 — 0.55 IOL = 24 mA, VIL = 0.8 V IIN 3.6 — ±5 IIN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V IOZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current ICC 3.6 — 40 µA VIN = VCC or GND 3.0 to 3.6 — 750 µA VIN = one input at (VCC–0.6) V, other inputs at VCC or GND VOL Input current Off state output current *2 ∆ICC µA VIN = VCC or GND Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter IOZ includes the input leakage current. Rev.4.00, Oct.02.2003, page 6 of 11 HD74ALVCH16820 Switching Characteristics (Ta = -40 to 85°C) Item Symbol VCC (V) Min Typ Max Unit Maximum clock frequency fmax 2.5±0.2 150 — — MHz 2.7 150 — — Propagation delay time Output enable time Output disable time Setup time Hold time Pulse width Input capacitance Output capacitance 3.3±0.3 150 — — tPLH 2.5±0.2 1.0 — 5.9 tPHL 2.7 — — 5.5 3.3±0.3 1.0 — 4.8 tZH 2.5±0.2 1.0 — 6.4 tZL 2.7 — — 6.1 3.3±0.3 1.0 — 5.0 tHZ 2.5±0.2 1.3 — 5.7 tLZ 2.7 — — 5.0 3.3±0.3 1.0 — 4.5 2.5±0.2 1.7 — — 2.7 1.8 — — 3.3±0.3 1.4 — — 2.5±0.2 1.1 — — 2.7 1.1 — — 3.3±0.3 1.0 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — 3.3 — 3.5 — 3.3 — 6.0 — 3.3 — 7.0 — tsu th tw CIN CO Rev.4.00, Oct.02.2003, page 7 of 11 FROM (Input) TO (Output) ns CLK Q ns OE Q ns OE Q ns ns ns pF Control inputs Data inputs pF Outputs HD74ALVCH16820 • Test Circuit See under table 500 Ω S1 OPEN GND *1 C L = 50 pF 500 Ω Load Circuit for Outputs Symbol Vcc=2.5±0.2 V t PLH / t PHL OPEN t su / t h / t w t ZH/ t HZ t ZL / t LZ Vcc = 2.7 V, 3.3±0.3 V OPEN GND GND 4.6 V 6.0 V Note: 1. C L includes probe and jig capacitance. Rev.4.00, Oct.02.2003, page 8 of 11 HD74ALVCH16820 • Waveforms – 1 tr tf VIH 90 % Vref 90 % Input Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL • Waveforms – 2 tr VIH 90 % Vref Timing Input 10 % tsu GND th VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND Rev.4.00, Oct.02.2003, page 9 of 11 HD74ALVCH16820 • Waveforms – 3 Output Control tf tr 90 % Vref VIH 90 % Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B VOL + 0.3 V t HZ VOH – 0.3 V Vref VOL VOH ≈VOL1 TEST VIH Vref VOH1 VOL1 = 2.7 V, Vcc=2.5±0.2 V Vcc 3.3±0.3 V 2.3 V 2.7 V 1.2 V 2.3 V 1.5 V 3.0 V GND GND Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.4.00, Oct.02.2003, page 10 of 11 HD74ALVCH16820 Package Dimensions As of January, 2003 14.0 14.2 Max 56 Unit: mm 6.10 29 *0.19 ± 0.05 0.50 28 0.08 M 1.0 8.10 ± 0.20 0.10 *Ni/Pd/Au plating Rev.4.00, Oct.02.2003, page 11 of 11 0˚ – 8˚ *0.15 ± 0.05 1.20 Max 0.65 Max 0.10 ± 0.05 1 0.50 ± 0.1 Package Code JEDEC JEITA Mass (reference value) TTP-56DAV — — 0.23 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is alwa always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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