HD74ALVCH16269 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs REJ03D0046-0200Z (Previous ADE-205-136(Z)) Rev.2.00 Oct.02.2003 Description The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high speed microprocessors. Data is stored in the internal B port registers on the low to high transition of the clock (CLK) input when the appropriate clock enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B to A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the period that the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active low output enables (OEA, OEB1, OEB2). Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features • • • • • VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors Rev.2.00, Oct.02.2003, page 1 of 12 HD74ALVCH16269 Function Table Inputs Outputs CLK OEA OEB A 1B, 2B ↑ H H Z Z ↑ H L Z Active ↑ L H Active Z ↑ L L Active Active Output enable Inputs CLKENA1 Outputs CLKENA2 CLK A 1B 2B *1 2B0 *1 H H X X 1B0 L X ↑ L L X L X ↑ H H X X L ↑ L X L X L ↑ H X H A-to-B storage (OEB = L) Inputs Output A CLK SEL 1B 2B X H X X A0 *1 X L X X A0 *1 ↑ H L X L ↑ H H X H ↑ L X L L ↑ L X H H B-to-A storage (OEA = L) H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established. Rev.2.00, Oct.02.2003, page 2 of 12 HD74ALVCH16269 Pin Arrangement 56 OEB2 OEA 1 OEB1 2 55 CLKENA2 2B3 3 54 2B4 GND 4 53 GND 2B2 5 52 2B5 2B1 6 VCC 7 51 2B6 A1 8 49 2B7 A2 9 48 2B8 A3 10 47 2B9 50 VCC GND 11 46 GND A4 12 45 2B10 A5 13 44 2B11 A6 14 43 2B12 A7 15 42 1B12 A8 16 41 1B11 A9 17 40 1B10 GND 18 39 GND A10 19 38 1B9 A11 20 37 1B8 A12 21 36 1B7 VCC 22 35 VCC 1B1 23 34 1B6 1B2 24 33 1B5 GND 25 32 GND 1B3 26 31 1B4 30 CLKENA1 NC 27 SEL 28 29 CLK (Top view) Rev.2.00, Oct.02.2003, page 3 of 12 HD74ALVCH16269 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC –0.5 to 4.6 V Input voltage *1, 2 VI –0.5 to 4.6 V –0.5 to VCC +0.5 Output voltage *1, 2 Conditions Except I/O ports I/O ports VO –0.5 to VCC +0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC TSSOP ±100 Maximum power dissipation *3 at Ta = 55°C (in still air) PT 1 W Storage temperature Tstg –65 to 150 °C Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current IOH — –12 mA — –12 VCC = 2.7 V — –24 VCC = 3.0 V — 12 — 12 VCC = 2.7 V — 24 VCC = 3.0 V Low level output current IOL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. Rev.2.00, Oct.02.2003, page 4 of 12 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCH16269 Logic Diagram 29 CLK OEB1 2 OEB2 56 CLKENA1 30 CLKENA2 55 SEL 28 OEA 1 C1 1D C1 1D C1 1D 1D C1 A1 8 C1 G1 1 1 1D CE C1 1D CE C1 1D 1 of 12 Channels Rev.2.00, Oct.02.2003, page 5 of 12 23 6 1B1 2B1 HD74ALVCH16269 Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) *1 Min Max Unit Input voltage VIH 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 VIL Output voltage VOH Input current IOH = –100 µA Min to Max VCC–0.2 — 2.3 2.0 — IOH = –6 mA, VIH = 1.7 V 2.3 1.7 — IOH = –12 mA, VIH = 1.7 V 2.7 2.2 — IOH = –12 mA, VIH = 2.0 V 3.0 2.4 — IOH = –12 mA, VIH = 2.0 V 3.0 2.0 — IOH = –24 mA, VIH = 2.0 V Min to Max — 0.2 IOL = 100 µA 2.3 — 0.4 IOL = 6 mA, VIL = 0.7 V 2.3 — 0.7 IOL = 12 mA, VIL = 0.7 V 2.7 — 0.4 IOL = 12 mA, VIL = 0.8 V 3.0 — 0.55 IOL = 24 mA, VIL = 0.8 V IIN 3.6 — ±5 IIN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V VOL V Test Conditions µA VIN = VCC or GND *2 IOZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current ICC 3.6 — 40 µA VIN = VCC or GND ∆ICC 3.0 to 3.6 — 750 µA VIN = one input at (VCC–0.6) , other inputs at VCC or GND Off state output current Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter IOZ includes the input leakage current. Rev.2.00, Oct.02.2003, page 6 of 12 HD74ALVCH16269 Switching Characteristics Item Symbol VCC (V) Min Typ Max Unit Maximum clock frequency fmax 2.5±0.2 135 — — MHz 2.7 135 — — 3.3±0.3 135 — — 2.5±0.2 1.0 — 8.8 2.7 — — 7.3 3.3±0.3 1.0 — 6.2 2.5±0.2 1.0 — 7.0 2.7 — — 5.8 3.3±0.3 1.0 — 5.0 2.5±0.2 1.0 — 8.4 2.7 — — 6.7 3.3±0.3 1.0 — 6.1 2.5±0.2 1.0 — 8.1 2.7 — — 6.2 3.3±0.3 1.0 — 5.9 2.5±0.2 1.4 — 8.3 2.7 — — 6.9 3.3±0.3 1.0 — 6.1 2.5±0.2 1.5 — 7.7 2.7 — — 6.8 3.3±0.3 1.0 — 5.6 Propagation delay time Output enable time Output disable time tPLH tPHL tZH tZL tHZ tLZ ns FROM (Input) TO (Output) CLK B A ns CLK B A ns CLK B A Input capacitance CIN 3.3 — 3.5 — pF Control inputs Output capacitance CIN / O 3.3 — 9.0 — pF A or B ports Rev.2.00, Oct.02.2003, page 7 of 12 HD74ALVCH16269 Switching Characteristics (cont.) Item Symbol VCC (V) Setup time tsu 2.5±0.2 2.0 2.7 2.0 3.3±0.3 1.7 — — 2.5±0.2 2.2 — — 2.7 2.1 — — 3.3±0.3 1.8 — — 2.5±0.2 1.6 — — 2.7 1.6 — — 3.3±0.3 1.3 — — 2.5±0.2 1.0 — — CLKENA1 or 2.7 1.2 — — CLKENA2 before LK↑ 3.3±0.3 0.9 — — 2.5±0.2 1.5 — — 2.7 1.6 — — 3.3±0.3 1.3 — — 2.5±0.2 0.7 — — 2.7 0.6 — — 3.3±0.3 0.6 — — 2.5±0.2 0.7 — — 2.7 0.6 — — 3.3±0.3 0.6 — — 2.5±0.2 1.1 — — 2.7 0.7 — — 3.3±0.3 0.7 — — Hold time Pulse width th tw Min Typ Max Unit FROM (Input) — — ns A data before CLK↑ — — B data before CLK↑ SEL before CLK↑ OE before CLK↑ ns A data after CLK↑ B data after CLK↑ SEL aftrer CLK↑ 2.5±0.2 1.0 — — CLKENA1 or 2.7 0.8 — — CLKENA2 after CLK↑ 3.3±0.3 1.1 — — 2.5±0.2 0.8 — — 2.7 0.8 — — 3.3±0.3 0.8 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — Rev.2.00, Oct.02.2003, page 8 of 12 OE after CLK↑ ns CLK “H” or “L” HD74ALVCH16269 • Test Circuit See under table 500 Ω S1 OPEN GND *1 C L = 50 pF 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN GND GND 4.6 V 6.0 V Note: 1. C L includes probe and jig capacitance. Rev.2.00, Oct.02.2003, page 9 of 12 HD74ALVCH16269 • Waveforms – 1 tr tf VIH 90 % Vref 90 % Input Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL • Waveforms – 2 tr VIH 90 % Vref Timing Input 10 % tsu GND th VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND Rev.2.00, Oct.02.2003, page 10 of 12 HD74ALVCH16269 • Waveforms – 3 Output Control tf tr 90 % Vref VIH 90 % Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B VOL + 0.3 V t HZ VOH – 0.3 V Vref VOL VOH ≈VOL1 TEST VIH Vref VOH1 VOL1 Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V 2.3 V 2.7 V 1.2 V 2.3 V 1.5 V 3.0 V GND GND Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00, Oct.02.2003, page 11 of 12 HD74ALVCH16269 Package Dimensions As of January, 2003 Unit: mm 25 12.70 48 19.68 20.00 Max 39 34 1 10 15 0.80 *0.32 ± 0.10 0.30 ± 0.05 0.13 24 0.80 M 14.30 ± 0.20 0.94 Max *Dimension including the plating thickness Base material dimension Rev.2.00, Oct.02.2003, page 12 of 12 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-48/40DA — — 0.60 g 0.78 0.10 0.05 ± 0.05 4.00 * 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0˚ – 5˚ Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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