Data Sheet

EM78P567
8-BIT OTP MICRO-CONTROLLER
Version 6.6
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan, R.O.C.
TEL: (03) 5639977
FAX: (03) 5630118
EM78P567/P566/P565
8-bit micro-controller
I.General Description
The EM78P567/P566/P565 is an 8-bit RISC type microprocessor with low power , high speed CMOS technology .
There are 16Kx13/8Kx13/4Kx13 bits Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It
provides Security bits and some One time programmable Option bits to protect the OTP memory code from any external
access as well as to meet user’s options.
The EM78P567/P566/P565 is integrated onto a single chip are on_chip watchdog (WDT) , RAM , A/D , D/A , tone
generator, programmable real time clock /counter , internal interrupt , power down mode and tri-state I/O .
II.Feature
CPU
•Operating voltage range : 2.5V∼5.5V
•16K×13 Electrical One Time Programmable Read Only Memory (EM78P567)
•8K×13 Electrical One Time Programmable Read Only Memory (EM78P566)
•4K×13 Electrical One Time Programmable Read Only Memory (EM78P565)
•0.5K×8 on chip RAM
•Up to 36 bi-directional tri-state I/O ports (EM78P567,EM78P566)
•Up to 24 bi-directional tri-state I/O ports (EM78P565)
•8 level stack for subroutine nesting
•8-bit real time clock/counter (TCC)
•A 8 bit counters (COUNTER1) with a 8 bit prescaler which can be a interrupt source.
•A 8 bit counters (COUNTER2) with a 8 bit prescaler which can be a interrupt source.
•Selective signal sources and with overflow interrupt
•Programmable free running on chip watchdog timer
•99.9％ single instruction cycle commands
•Four modes (internal clock 3.58MHz, external clock 32.768KHz)
Sleep mode : CPU and 3.58MHz clock turn off, 32.768KHz clock turn off
IDLE mode : CPU and 3.58MHz clock turn off, 32.768KHz clock turn on
Green mode : 3.58MHz clock turn off, CPU and 32.768KHz clock turn on
Normal mode : 3.58MHz clock turn on , CPU and 32.768KHz clock turn on
•Four open drain ports
•Input port interrupt function
• Four channels A/D circuit with 8 bits resolution.
• I/O internal pull high
•12 interrupt source , 8 external , 4 internal
•Dual clocks operation (Internal PLL 3.58MHz , External 32.768KHz)
•28 pin SOP(EM78P565AM, POVD disable) (EM78P565BM, POVD enable) or Chip (EM78P565H)
•32 pin SOP(EM78P565AWM, POVD disable)(EM78P565BWM, POVD enable) or
Chip (EM78P565H)
•42 pin SDIP (EM78P566AR, POVD disable) (EM78P566BR, POVD enable) or Chip(EM78P566H)
•42 pin SDIP (EM78P567AR, POVD disable) (EM78P567BR, POVD enable) or Chip(EM78P567H)
•44 pin QFP (EM78P566AQ, POVD disable) (EM78P566BQ, POVD enable) or Chip(EM78P566H)
•44 pin QFP (EM78P567AQ, POVD disable) (EM78P567BQ, POVD enable) or Chip(EM78P567H)
•48 pin QFP (EM78P567TAQ, POVD disable) (EM78P567TBQ, POVD enable) or Chip(EM78P567H)
•Build in 8-bit D/A converter (R-2R)
•Dual Tone generators
•3.58MHz clock output shared with IO PORT
1
EM78P567/P566/P565
8-bit micro-controller
III.Application
1.
2.
3.
4.
adjunct units
answering machines
feature phones
cordless phones
IV.Pin Configuration
42pin SDIP
EM78P567AR
EM78P567BR
EM78P566AR
EM78P566BR
P75/INT5
P76/INT6
P77/INT7
XIN
XOUT
PLLC
GND
TONE
P80
P81
P82
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P95/AD3
P94/AD2
P93/AD1
P92/DAOUT
P91
P90
P87
P86
P85
P84
P83
P67
P66
P65
P64
P63
P62
P61
P60/3.58M
PA1
PA0
RESET
VDD
AVDD
P97/VREF
P96/AD4
P95/AD3
P94/AD2
P93/AD1
P92/DAOUT
P91
P90
22
21
20
19
18
17
16
15
14
13
12
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P62
P63
P64
P65
P66
P67
P70/INT0
P71/INT1
P72/INT2
P73/INT3
P74/INT4
P70/INT0
P71/INT1
P72/INT2
P73/INT3
P74/INT4
P75/INT5
P76/INT6
P77/INT7
XIN
XOUT
PLLC
GND
TONE
P80
P81
P82
P83
P84
P85
P86
P87
44pinQFP
EM78P567AQ
EM78P567BQ
EM78P566AQ
EM78P566BQ
2
P61
P60/3.58M
PA3
PA2
PA1
PA0
RESET
VDD
AVDD
P97/VREF
P96/AD4
EM78P567/P566/P565
8-bit micro-controller
P70/INT0
1
32
P67
P71/INT1
2
31
P66
P72/INT2
3
30
P65
P73/INT3
4
29
P64
P74/INT4
5
28
P75/INT5
6
27
P76/INT6
7
26
P77/INT7
8
25
XIN
9
24
XOUT
10
23
PLLC
11
22
AVDD
GND
12
21
P97/VREF
TONE
13
20
P96/AD4
P90
14
19
P95/AD3
P91
15
18
16
17
P92/DAOUT
P63
P62
P61
P60/3.58M
RESET
P67
1
28
P66
P73/INT3
2
27
P65
P74/INT4
3
26
P64
P75/INT5
4
25
P63
P76/INT6
5
24
P62
P77/INT7
6
23
P61
XIN
7
22
P60/3.58M
XOUT
8
21
RESET
PLLC
9
20
AVDD,VDD
GND
10
19
P97/VREF
TONE
11
18
P96/AD4
P90
12
17
P95/AD3
P91
13
16
P94/AD2
14
15
P93/AD1
VDD
P94/AD2
P93/AD1
P92/DAOUT
32 pin SOP
28 pin SOP
EM78P565AWM
EM 78P565AM
EM78P565BWM
EM 78P565BM
P63
P64
P65
P66
P67
P70/INT0
P71/INT1
P72/INT2
P73/INT3
P74/INT4
P75/INT5
NC
37
38
39
40
41
42
43
44
45
46
47
48
P76/INT6
P77/INT7
XIN
XOUT
PLLC
GND
TONE
P80
P81
P82
P83
P84
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
P96/AD4
P95/AD3
P94/AD2
P93/AD1
P92/DAOUT
P91
P90
TONE
GND
P87
P86
P85
48 pin TQFP
EM78P567TAQ
EM78P567TBQ
3
NC
P62
P61
P60/3.58M
PA3
PA2
PA1
PA0
RESET
VDD
AVDD
P97/VREF
EM78P567/P566/P565
8-bit micro-controller
OTP PIN NAME
VDD
VPP
DINCK
ACLK
DATAIN
PGMB
OEB
GND
MASK ROM PIN NAME
VDD
/RESET
P65
P64
P63
P62
P61
GND
P.S.
Fig1. Pin Assignment
V.Functional Block Diagram
Xin Xout
ROM
WDT timer
Oscillator
timing control
prescalar
R1(TCC)
Control sleep
and wake-up
on I/O port
STACK
R2
GENERAL
RAM
Interruption
control
Instruction
register
ALU
R3
R5
Instruction
decoder
R4
ACC
DATA & CONTROL BUS
0.5k RAM
PORT6
PORT7
PORT8
PORT9
PORTA
IOC6 R6
IOC7 R7
IOC8 R8
IOC9 R9
IOCA RA
P60~P67
P70~P77
P80~P87
P90~P97
PA0~PA3
Fig2. Block diagram
4
EM78P567/P566/P565
8-bit micro-controller
VI.Pin Descriptions
PIN
VDD
AVDD
GND
Xin
Xout
PLLC
I/O
POWER
POWER
I
O
I
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
P7.0 ~P7.7
PORT7(0)
PORT7(1)
PORT7(2)
PORT7(3)
PORT7(4)
PORT7(5)
PORT7(6)
PORT7(7)
PORT7
P6.0 ~P6.7
PORT6
P8.0 ~P8.7
P9.0 ~P9.7
PORT8
PORT9
VREF
PORT9(7)
AD1
AD2
AD3
AD4
DAOUT
PA.0 ~PA.3
TONE
RESET
3.58M
OTP pin
PORT9(3)
PORT9(4)
PORT9(5)
PORT9(6)
PORT9(2)
PORTA
O
I
PORT6(0)
OEB(P61)
PGMB(P62)
DATAIN(P63)
ACLK(P64)
I
I
I/O
I
DINCK(P65)
VPP(RESET)
I
I
DESCRIPTION
Digital power
Analog power
Ground
Input pin for 32.768 kHz oscillator
Output pin for 32.768 kHz oscillator
Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u with
GND .
External interrupt
PORT 7 can be INPUT or OUTPUT port each bit.
Internal Pull high function.
PORT 6 can be INPUT or OUTPUT port each bit.
Internal Pull high function.
PORT 8 can be INPUT or OUTPUT port each bit.
PORT 9 can be INPUT or OUTPUT port each bit.
P90 to P93 have Open drain function.
Reference voltage input of AD converter-circuit . User use internal
reference voltage. This pin is normal IO PORT.
The first input of A/D converter.
The second input of A/D converter.
The third input of A/D converter.
The fourth input of A/D converter.
DA signal output
PORTA can be INPUT or OUTPUT port each bit.
Dual Tone generator output
Normally high
3.58MHz clock output shared with PORT6(0)
Output enable. Active low
Program write enable. Active low
Data pin
CLK for OTP memory address increment . Increasing a address needs
two clocks.
Data latch clock. Latch a bit at the falling edge
Programming voltage input. Vpp can be varied from 10.5V to 12.5V
5
EM78P567/P566/P565
8-bit micro-controller
VII.Functional Descriptions
VII.0 OTP ROM
1. OTP ROM
* The OTP ROM’s size is 16k x13 bits which can be serially writen and read.
2. Operation Mode
mode
DATAIN(p63)
ACLK(p64)
DINCK(p65)
1.Regular mode
0
0
0
2.OTP row mode
1
0
0
3.Option mode
0
1
0
4.Bit line stress
1
1
0
5.Word line stress
0
0
1
6.Test mode
0
1
1
1.
2.
Regular mode: This mode is provided to program and verify OTP memory only.
OTP row mode: This mode is designed to provide capability programming and verifying of ROM data for the plastic
OTP packages. One external row is added in addition to the regular ROM array. The user’s data can be sequentially written
into the ROM memory in OTP row by advancing the consecutive address to avoid the circuit change of program counter in
microcontroller.
3.
Option mode(Option register) :
The mode provides user a special mode for selecting option.
Bit12..Bit1
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Code
TONEEN
DAEN
ADEN
ROM2
ROM1
/PT
Bit0 :/PT :Protect bit 0/1=enable /disable
* Bits 2~1: ROM2 and ROM1 bits can select three type of chip
(ROM2,ROM1) = (1,1)= EM78567; (ROM2,ROM1) = (1,0)= EM78566; (ROM2,ROM1) = (0,0)= EM78565
* Bit3: ADEN: A bit to enable or disable AD circuit.
1/0 = AD valid / AD invalid
* Bit4: DAEN: A bit to enable or disable DA circuit.
1/0 = DA valid / DA invalid
* Bit5: TONEEN: A bit to enable or disable AD circuit.
1/0 = TONE valid / TONE invalid
Bit6..Bit12: code for user ID
4.
Bit line stress mode : This mode is provides to test the reliability of ROM cells. Bit line mode is to apply the
programmed drain voltage on all bit lines but all word lines are ground.
5.
Word line stress mode : This mode is provides to test the reliability of ROM cells. Word line mode is to apply the
programming gate voltage on all word lines but all bit lines are ground.
6.
Test mode : This mode is provided for verifying the speed of data from OTP memory.
3. Mode selection
Mode is selected by voltage switch on VPP pin. The timing is as follow.
12V
VPP
P63~P65
internal
latch
5V
Trs
Tcsu
code
Tchd
Mode
.
6
EM78P567/P566/P565
8-bit micro-controller
4.
Regular mode: Program and Verify
After selecting the regular mode, writer can program instruction into OTP by following timing chart . The OTP ‘s
address is increased by internal counter.
VPP
12V
DATAIN
BIT13…BIT1
BIT13…BIT1
DINCK
Tpwd 200us typical
PGMB
OEB
ACLK
ADDRESS
(INTERNAL)
0000
0001
Toed 300ns minimum
OUTPUT LATCH
DATAIN
bit13
Tdsu
bit12
…...
bit0
DATAIN
Tdsu
DINCK
DINCK
bit13 bit12
…... bit0
Tdhd 100ns MIN
5.
Test mode: Verify
After selecting the test mode, writer can verify instruction by following timing chart . The OTP ‘s address is increased
by internal counter. The waveform is same as regular mode.
7
EM78P567/P566/P565
8-bit micro-controller
VII.1 Operational Registers
1. R0 (Indirect Addressing Register)
* R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as register
actually accesses data pointed by the RAM Select Register (R4).
2. R1 (TCC)
* Increased by an external signal edge applied to TCC , or by the instruction cycle clock.
Written and read by the program as any other register.
3.
R2 (Program Counter)
* The structure is depicted in Fig. 3.
* Generates 16K × 13 on-chip ROM addresses to the relative programming instruction codes.
* "JMP" instruction allows the direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
* "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared
to "0''.
* "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
* "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The
most significant bit (A10~A13) will be loaded with the content of bit PS0~PS3 in the status register (R5) upon the
execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
CALL
A13 A12 A11 A10
A9 A8
A7~A0
RET
RETL
RETI
0000 PAGE0 0000~03FF
0001 PAGE1 0400~07FF
0010 PAGE2 0800~0BFF
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
1110 PAGE14 3800~3BFF
1111 PAGE15 3C00~3FFF
Fig.3
Program counter organization
8
EM78P567/P566/P565
8-bit micro-controller
ADDRESS
REGISTER
CONTROL REGISTER
(PAGE0)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R0
R1(TCC)
R2(PC)
R3(STATUS)
R4(RSR)
R5(ROM PAGE)
R6(PORT6)
R7(PORT7)
R8(PORT8)
R9(PORT9)
RA(PORTA,CLK,WDT)
RB(DA data)
RC(0.5K RAM ADDRESS)
RD(0.5K RAM DATA)
RE(AD CONTROL)
RF(INT FLAG)
10
:
1F
16X8
COMMON
REGISTER
20
:
3F
BANK0 ~BANK3
32X8 ~32X8
REGISTER
Fig.4
CONTROL REGISTER
(PAGE1)
page0
IOC5(P6 PULL HIGH)
IOC6
IOC7
IOC8
IOC9
IOCA(OPEN DRAIN)
IOCB(COUNTER1)
IOCC(COUNTER2)
IOCD(AD OUTPUT DATA)
IOCE(PORT7 PULL HIGH)
IOCF(INT CONTROL)
page1
IOCB(COUNTER1 SCALAR)
IOCC(COUNTER2 SCALAR)
IOCD(TONE Generator1)
IOCE(TONE Generator2)
RC(ADDRESS) RD(DATA)
0
BANK1 BANK2
:
256X8 256X8
255
Data memory configuration
4.
R3 (Status Register)
7
6
5
4
3
2
1
0
DASRC
PAGE
DAST
T
P
Z
DC
C
* Bit 0 (C) Carry flag
* Bit 1 (DC) Auxiliary carry flag
* Bit 2 (Z) Zero flag
* Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
* Bit 4 (T) Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
ENT
MARK
T wake up from
p mode
T time out (not sleep mode
SET wake up from sleep
wer up
* Bit 5 (DAST) DA START signal. When R3 bit5 is set by software in NORMAL mode . The DA converter start converting. If
user clean this bit , DA converter will stop. DAOUT pin send DA signal.
0/1= STOP/START
* Bit 6 PAGE : change IOCB ~ IOCC to another page , 0/1 => page0 / page1
* Bit 7 (DASRC) DA convert circuit ‘s reference voltage. 0/1 =>VDD/2.55V
9
EM78P567/P566/P565
8-bit micro-controller
DASRC
(bit7 of R3)
2R
DAOUT
buffer
R
8-bit
D/A
ref.
volt.
2R
DAST
R
2R
(bit5 of R3)
2R
5. R4 (RAM Select Register)
* Bits 0 ~ 5 are used to select up to 64 registers in the indirect addressing mode.
* Bits 6 ~ 7 determine which bank is activated among the 4 banks.
* See the configuration of the data memory in Fig. 4.
6.
R5 (Program Page Select Register)
7
6
5
ADCLK1
ADCLK0 P_TONE2
* Bit 0 (PS0) ~ 3 (PS3) Page select bits
Page select bits
PS3
PS2
PS1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
4
3
2
1
0
P_TONE1
PS3
PS2
PS1
PS0
PS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Program memory page (Address)
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Page 14
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EM78P567/P566/P565
8-bit micro-controller
1
1
1
1
Page 15
*User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user can use far jump (FJMP)
or far call (FCALL) instructions to program user's code. And the program page is maintained by EMC's complier. It will
change user's program by inserting instructions within program.
*Bit4: Power control bit of Tone generator 1 . User can use this bit to power on the tone generator.
*Bit5: Power control bit of Tone generator 2 . User can use this bit to power on the tone generator.
R5(5,4)
Tone generator2
Tone generator1
00
Power off
Power off
01
Power off
Power on
10
Power on
Power off
11
Power on
Power on
*Bit 6~7: AD circuit ‘s sampling clock source.
ADCLK1
ADCLK0
Sampling rate
Operation voltage
0
0
44K
>=3V
0
1
22K
>=2.5V
1
0
11K
>=2.5V
1
1
5.5K
>=2.5V
6. R6 ~ R9 (Port 6 ~ Port 9)
* Five 8-bit I/O registers.
7.
RA (clock and RA register)
7
6
5
4
3
IDLE
/358E
/WDTE
RAMS
PA3
* Bit0 ~ Bit3 : I/O register
* Bit4 : (RC RD controlled General RAM selection bit)
0/1 = bank0/bank1.
* Bit5: (/WDTE , Watch Dog Timer register)
This control bit used to enable Watchdog timer.
0/1=disable/enable
* Bit6(PLL enable signal)
0/1=DISABLE(GREEN MODE) / ENABLE (NORMAL MODE)
2
PA2
1
PA1
The relation between 32.768K and 3.58M can see Fig5.
PLL
3.58MHz
Sub-clock
32.768KHz
To PORT6(0)
1
RA bit6
switch
To system clock
0
Fig5. The relation between 32.768KHz and 3.58MHz .
* Bit7 IDLE: sleep mode selection bit
0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go.
11
0
PA0
EM78P567/P566/P565
8-bit micro-controller
Sub-clock and CPU will close in sleep mode.
Into
TCC time out
WDT time out
Port7 bit0
SLEEP mode
RA(7,6)=(0,0)
+ SLEP
X
RESET
Run from
address “0”
X
CUP will close in IDLE mode but sub-clock.
IDLE mode
RA(7,6)=(1,0)
+ SLEP
Wake-up
+ Interrupt
+ Next instruction
X
Wake-up
+ Interrupt
+ Next instruction
GREEN mode
RA(7,6)=(x,0)
no SLEP
Interrupt
NORMAL mode
RA(7,6)=(x,1)
no SLEP
Interrupt
RESET
Run from
address “0”
Interrupt
RESET
Run from
address “0”
Interrupt
*Port7 bit0 is a falling edge trigger port.
*"X" is mean no function
8.
RB(DA data register)
7
6
5
4
3
2
1
0
C7
C6
C5
C4
C3
C2
C1
C0
* Bit 7 – Bit0 are DA converter data control register. Bit7 is MSB and bit0 is LSB.
* Please set to NORMAL mode before DA converter start.
* User can select reference voltage by R3 bit7. And enable or disable power of DA converter by R3 bit5.
9.
10.
RC (RAM ADDRESS)
7
6
5
4
3
2
1
0
CIDA7 CIDA6 CIDA5 CIDA4 CIDA3 CIDA2 CIDA1 CIDA0
* Bit 0 ~ Bit 7 select General RAM address up to 256. User can select two banks by RA bit4.
RD(RAM DATA)
* Bit 0 ~ Bit 8 are 0.5K RAM indirect data transfer register.
User can see RA register how to select RAM banks.
11.
RE( AD control)
7
6
SAD3
SAD2
5
SAD1
4
SVREF
3
START
2
ADPWR
1
IN1
0
IN0
* Bit1~Bit0 (input of AD converter selection ) : These two bits can choose one of three AD input.
(IN1,IN0)
0 0
0 1
1 0
1 1
INPUT
AD1
AD2
AD3
AD4
* Bit2 (ADPWR: AD converter power control register): 1/0=enable/disable
12
EM78P567/P566/P565
8-bit micro-controller
* Bit3 (START: AD converter start to sample): Set to “1” , the AD will start to sample data. This bit will be cleared by
hardware automatically after a sampling.
* Bit4 This register can switch AD converter reference voltage coming from internal or external voltage.
If the register set to internal, then the voltage will be VDD and port9 bit7 is a normal I/O PORT. If it set to external
reference voltage, then the voltage will connected to PORT9 bit7.
0/1=internal/external reference voltage.
* Bit5 This register can switch PORT9 bit3 as IO port or AD converter input1. 0/1= IO PORT / AD input
* Bit6 This register can switch PORT9 bit4 as IO port or AD converter input2. 0/1= IO PORT / AD input
* Bit7 This register can switch PORT9 bit5 as IO port or AD converter input3. 0/1= IO PORT / AD input
And it can switch PORT9 bit6 as IO port or AD converter input4. 0/1= IO PORT / AD input
•
•
•
•
•
•
•
This is a CMOS multi-channel 8-bit successive approximation A/D converter.
Features
44kHz maximum conversion speed at 5V.
Adjusted full scale input
External reference voltage input or internal reference voltage
4 analog inputs multiplexed into one A/D converter
Power down mode for power saving
A/D conversion complete interrupt
Interrupt register, A/D control and status register, and A/D data register
12. RF (Interrupt Status Register)
7
6
5
0
0
ADI
4
EXTINT2
3
EXTINT1
2
CNT2
* "1" means interrupt request, "0" means non-interrupt
* Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows .
* Bit 1 (CNT1) counter1 interrupt flag.
* Bit 2 (CNT2) counter2 interrupt flag .
* Bit 3 (EXTINT1) external pin interrupt flag (INT0 ~INT3) .
* Bit 4 (EXTINT2) external pin interrupt flag (INT4 ~INT7) .
* Bit 5 (ADI) AD interrupt flag after a sampling .
* Bit 6~7: ‘0’ always
* High to low edge trigger , Refer to the Interrupt subsection.
* IOCF is the interrupt mask register. User can read and clear RF register.
*
13. R10~R3F (General Purpose Register)
R10~R3F (Banks 0~3) all are general purpose registers.
VII.2 Special Purpose Registers
1. A (Accumulator)
* Internal data transfer, or instruction operand holding
* It's not an addressable register.
2.
CONT (Control Register)
7
6
5
4
3
2
0
INT
TS
0
PAB PSR2
* Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
1
PSR1
13
0
PSR0
1
CNT1
0
TCIF
EM78P567/P566/P565
8-bit micro-controller
PSR2
PSR1
PSR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
* Bit 3 (PAB) Prescaler assignment bit.
0/1 : TCC/WDT
* Bit 4 unused
* Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: 16.38KHz
* Bit 6 : (INT)INT enable flag
TCC Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
0: interrupt masked by DISI or hardware interrupt
1: interrupt enabled by ENI/RETI instructions
* Bit 7 : unused
* CONT register is readable and writable.
3.
IOC5 (PORT6 pull high control register)
7
6
5
4
3
P6PH7
P6PH6
P6PH5
P6PH4
P6PH3
* IOC5 can control the pull high circuit of PORT6 individually.
* 0/1 = disable /enable pull high circuit
2
P6PH2
1
P6PH1
0
P6PH0
4. IOC6 ~ IOC9 (I/O Port Control Register)
* Five I/O direction control registers.
* "1" put the relative I/O pin into high impedance (input port), while "0" put the relative I/O pin as output.
5.
IOCA (OPEN DRAIN and IOCA)
7
OD3
*
*
*
*
*
6
OD2
5
OD1
4
OD0
3
IOCA3
2
IOCA2
1
IOCA1
0
IOCA0
Bit0 ~ bit3: PortA I/O direction control registers. "1" put the relative I/O pin into high impedance (input port), while "0" put
the relative I/O pin as output.
Bit4: OD0 : Open drain control register on PORT9 bit0. 0/1= disable/enable open-drain function.
Bit5: OD1 : Open drain control register on PORT9 bit1. 0/1= disable/enable open-drain function.
Bit6: OD2 : Open drain control register on PORT9 bit2. 0/1= disable/enable open-drain function.
Bit7: OD3 : Open drain control register on PORT9 bit3. 0/1= disable/enable open-drain function.
6. IOCB (COUNTER1)
PAGE0 :
7
6
CNT1B7 CNT1B6
5
CNT1B5
4
CNT1B4
3
CNT1B3
2
CBT1B2
1
CNT1B1
Control register for 8 bit up-counter (COUNTER1) preset and read . ( write = preset
After a interruption , it will count from “00”.
PAGE1:
14
0
CNT1B0
INSTRUCTION: IOW
0x0B ) .
EM78P567/P566/P565
8-bit micro-controller
7
6
5
4
3
2
1
0
0
P92S
S3.58M CNT1CLK PS2
PS1
Bit0~Bit2: COUNTER1 prescaler
PS2
PS1
PS0
COUNTER1
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit3: COUNTER1 clock source. 0/1 = 16.38KHz/system clock
Bit4: S3.58M . It can switch PORT6 bit0 as IO port or 3.58Mhz clock output .
0/1= IO PORT / 3.58MHz clock
Bit5: P92S . It can switch PORT9 bit2 as IO port or DA signal output .
0/1= IO PORT / DA signal output.
Bit6 ~Bit7: ‘0’always
0
PS0
7. IOCC (COUNTER2)
PAGE0 :
7
6
5
4
3
2
1
0
CNT2B7 CNT2B6 CNT2B5 CNT2B4 CNT2B3 CBT2B2 CNT2B1 CNT2B0
Control register for 8 bit up-counter (COUNTER2) preset and read . ( write = preset INSTRUCTION: IOW
After a interruption , it will count from “00”.
PAGE1:
7
6
5
4
3
2
1
0
0
0
0
0
CNT2CLK PPS2
PPS1
PPS0
Bit0~Bit2: COUNTER2 prescaler
PPS2
PPS1
PPS0
COUNTER1
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Bit3:COUNTER2 clock source. 0/1 = 16.38KHz/system clock
Bit4~Bit7: ‘0’always
8.
IOCD (AD converter data register)
PAGE0:
7
6
5
4
AD7
AD6
AD5
AD4
* Bit 0 ~ 7 : AD converter ‘s output data
3
AD3
2
AD2
1
AD1
0
AD0
PAGE1:
7
6
5
4
3
2
1
0
T17
T16
T15
T14
T13
T12
T11
T10
Tone generator 1 ‘s frequency divider. Please Run in Normal mode .
15
0x0B ) .
EM78P567/P566/P565
8-bit micro-controller
Clock source = 111843Hz
T17~T10 = ‘11111111’ => Tone generator1 will has 438Hz SIN wave output.
:
T17~T10 = ‘00000010’ => Tone generator1 will has 55921Hz SIN wave output.
T17~T10 = ‘00000001’ => Tone generator1 will has 111843Hz SIN wave output.
T17~T10 = ‘00000000’ => no used
9.
IOCE (port7 pull high control Register)
PAGE0:
7
6
5
4
3
2
1
0
P7PH7 P7PH6 P7PH5 P7PH4 P7PH3 P7PH2 P7PH1 P7PH0
* IOCE page0 can control the pull high circuit of PORT7 individually.
* 0/1 = disable /enable pull high circuit
PAGE1:
7
6
5
4
3
2
1
0
T27
T26
T25
T24
T23
T22
T21
T20
Tone generator 2 ‘s frequency divider. Please Run in Normal mode.
Clock source = 111843Hz
T27~T20 = ‘11111111’ => Tone generator1 will has 438Hz SIN wave output.
:
T27~T20 = ‘00000010’ => Tone generator1 will has 55921Hz SIN wave output.
T27~T20 = ‘00000001’ => Tone generator1 will has 111843Hz SIN wave output.
T27~T20 = ‘00000000’ => no used
TONE1(IOCD)
ROW FREQ.
(0xA0)
699.02Hz
1
2
3
(0x91)
771.33Hz
4
5
6
(0X83)
853.76Hz
7
8
9
(0X77)
939.86Hz
*
0
#
1202.6 (0X5D)
1331.5(0X54)
1471.7(0X4C)
TONE2(IOCE)
A
B
C
D
1644.8(0X44)
10. IOCF (Interrupt Mask Register)
7
0
6
0
5
ADI
4
EXTINT2
3
EXTINT1
2
CNT2
1
CNT1
* Bit 0 ~ 5 interrupt enable bit.
0: disable interrupt
1: enable interrupt
* IOCF Register is readable and writable.
It is very important to save ACC,R3 and R5 when processing a interruption.
Instruction
Note
0x08
MOV
A_BUFFER,A
;Save ACC
0x09
SWAP
A_BUFFER
0x0A
SWAPA 0x03
;Save R3 status
0x0B
MOV
R3_BUFFER,A
0x0C
MOV
A,0x05
;Save ROM page register
0x0D
MOV
R5_BUFFER,A
16
0
TCIF
EM78P567/P566/P565
8-bit micro-controller
0x0E
:
:
:
:
:
:
:
:
PAGE
:
:
MOV
MOV
SWAPA
MOV
SWAPA
RETI
@0
A,R5_BUFFER
0X05,A
R3_BUFFER
0X03,A
A_BUFFER
;set page0
:
:
;Return R5
;Return R3
;Return ACC
VII.3 TCC/WDT Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or
WDT only at the same time.
An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register.
See the prescaler ratio in CONT register.
Fig. 6 depicts the circuit diagram of TCC/WDT.
Both TCC and prescaler will be cleared by instructions which write to TCC each time.
•
•
•
•
• The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
• The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
16.38KHz
Fig. 6
Block diagram of TCC WDT
VII.4 I/O Ports
17
EM78P567/P566/P565
8-bit micro-controller
The I/O registers, Port 6 ~ Port A, are bi-directional tri-state I/O ports. Port 6,7 can be pulled-high internally by
software control. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC6 ~ IOCA ) under
program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown
in Fig.7. Port9 bit0 to bit3 have open drain function.
control
Fig. 7
The circuit of I/O port and I/O control register
18
EM78P567/P566/P565
8-bit micro-controller
.
VII 5
RESET and Wake-up
The RESET can be caused by
(1) Power on reset, or Voltage detector
(2) WDT timeout. (if enabled and in GREEN or NORMAL mode)
Note that only Power on reset, or only Voltage detector in Case(1) is enabled in the system by CODE Option bit. If Voltage
detector is disabled, Power on reset is selected in Case (1). Refer to Fig. 8.
Fig. 8
Block diagram of Reset of controller
Once the RESET occurs, the following functions are performed.
•
•
•
•
•
•
•
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
The Watchdog timer and prescaler are cleared.
The Watchdog timer is disabled.
The CONT register is set to all "1"
The other register (bit7..bit0)
R5 = “00000000”
IOC5 = “00000000”
R6 = PORT
IOC6 = “11111111"
R7 = PORT
IOC7 = "11111111"
R8 = PORT
IOC8 = "11111111"
R9 = PORT
IOC9 = "11111111"
RA = "0000xxxx”
IOCA = "00001111"
RB = "11111111"
Page0 IOCB = "xxxxxxxx" Page1 IOCB = "00000000"
RC = "00000000"
Page0 IOCC = "xxxxxxxx" Page1 IOCC = "00000000"
RD = "xxxxxxxx"
Page0 IOCD = "xxxxxxxx" Page1 IOCD = "11111111"
RE = "00000000"
Page0 IOCE = "00000000" Page1 IOCE = "11111111"
RF = "00000000"
IOCF = "00000000"
The controller can be awakened from SLEEP mode or IDLE mode (execution of "SLEP" instruction, named as
SLEEP MODE or IDLE mode) by (1)TCC time out (IDLE mode only) (2) WDT time-out (if enabled) The two cases will
cause the controller wake up and run from next instruction in IDLE mode and reset in SLEEP mode . After wake-up , user
19
EM78P567/P566/P565
8-bit micro-controller
should control WATCH DOG in case of reset in GREEN mode or NORMAL mode. The WATCH DOG should be open
RA register before into SLEEP mode or IDLE mode . The first one case will set a flag in RF bit0 . And it will go to address
0x08 when TCC generate a interrupt and it will jump to next instruction from “SLEP” after return interrupt.
Into
TCC time out
WDT time out
SLEEP mode
RA(7,6)=(0,0)
+ SLEP
x
RESET
Run from
address “0”
IDLE mode
RA(7,6)=(1,0)
+ SLEP
Wake-up
=> Interrupt
=> Next
instruction
Wake-up
+ Next instruction
GREEN mode
RA(7,6)=(x,0)
no SLEP
Interrupt
NORMAL mode
RA(7,6)=(x,1)
no SLEP
Interrupt
RESET
Run from
address “0”
RESET
Run from
address “0”
VII.6 Interrupt
The IC has internal interrupts which are falling edge triggered, as followed : TCC timer overflow interrupt (internal) ,
two 8-bit counters overflow interrupt and AD converter interrupt.
If these interrupt sources change signal from high to low , then RF register will generate '1' flag to corresponding
register if you enable IOCF register.
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask register.
Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when
enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine
the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be
cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
There are eight external interrupt pins including INT0 .. INT7 .
External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT7 bit0 to bit3 . If IOCF bit 3 (EXTINT1) is
enable then these signal will cause interrupt and set a flag to RF bit3 , or these signals will be treated as general input data .
External interrupt INT4 , INT5 , INT6 , INT7 signals are from PORT7 bit4 to bit7 . If IOCF bit 4 (EXTINT2) is
enable then these signal will cause interrupt and set a flag to RF bit4 , or these signals will be treated as general input data .
After reset, the next instruction will be fetched from address 000H and the instruction inturrept is 001H and the
hardware inturrept is 008H.
TCC will go to address 0x08 in GREEN mode or NORMAL mode after time out. It will go to address 0x08 for
interrupt sub-routine and run next instruction from “SLEP” instruction after return interrupt in IDLE mode . These two
cases will set a RF flag.
Please save R3,R5 and ACC value before processing interrupt sub-routine. And return buffer value before RETI
instruction.
It is very important to save ACC,R3 and R5 when processing a interruption.
0x08
0x09
0x0A
0x0B
0x0C
Instruction
MOV
A_BUFFER,A
SWAP
A_BUFFER
SWAPA 0x03
MOV
R3_BUFFER,A
MOV
A,0x05
20
Note
;Save ACC
;Save R3 status
;Save ROM page register
EM78P567/P566/P565
8-bit micro-controller
0x0D
0x0E
:
:
:
:
:
:
:
:
MOV
PAGE
:
:
MOV
MOV
SWAPA
MOV
SWAPA
RETI
R5_BUFFER,A
@0
;set page0
:
:
;Return R5
A,R5_BUFFER
0X05,A
R3_BUFFER
0X03,A
A_BUFFER
;Return R3
;Return ACC
VII.7 Instruction Set
Instruction set has the following features:
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.
The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational
registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register
bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the
operation. "k'' represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
HEX
MNEMONIC OPERATION
0
0
0
0
0
0
0
0
0
0
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 rrrr
0001 0000
0001 0001
0001 0010
0001 0011
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
0
0
0
0
0
0
0
0
0
0
0
0
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0010
0010
0001 0100
0001 rrrr
0010 0000
01rr
rrrr
1000 0000
11rr
rrrr
00rr
rrrr
01rr
rrrr
10rr
rrrr
11rr
rrrr
00rr
rrrr
01rr
rrrr
0014
001r
0020
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
CONTR
IOR R
TBL
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2 bits 9,10 do not clear
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ VR → A
A ∨ VR → R
21
STATUS
AFFECTE
D
None
C
None
T,P
T,P
None
None
None
None
None
None
None
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
EM78P567/P566/P565
8-bit micro-controller
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0110
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
06rr
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
RRCA R
0
0110
01rr
rrrr
06rr
RRC R
0
0110
10rr
rrrr
06rr
RLCA R
0
0110
11rr
rrrr
06rr
RLC R
0
0111
00rr
rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
1
0111
0111
0111
100b
101b
110b
111b
00kk
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
kkkk
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
kkkk
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
1
1
1
1
1
1
1
1
01kk
1000
1001
1010
1011
1100
1101
1110
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
0001
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E01
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
1
1
1110
1111
1000
kkkk
kkkk
kkkk
1E8k
1Fkk
PAGE k
ADD A,k
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1)
R(0) → C, C → A(7)
R(n) → R(n-1)
R(0) → C, C → R(7)
R(n) → A(n+1)
R(7) → C, C → A(0)
R(n) → R(n+1)
R(7) → C, C → R(0)
R(0-3) → A(4-7)
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP]
(Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP]
001H → PC
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
K→R5
k+A → A
None
Z,C,DC
22
C
C
C
None
None
None
None
None
None
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
None
EM78P567/P566/P565
8-bit micro-controller
VII.8 CODE Option Register
The chip has one CODE option register which is not part of the normal program memory. The option bits cannot be
accessed during normal program execution.
7
-
6
-
5
TONEEN
4
DAEN
3
ADEN
* Bit 0 :(/POVD) : Power on voltage detector.
0: enable
1: disable
/POVD
1.6V reset
power on reset
1
0
No
Yes
1.6V POVD reset
suggestion
EM78P567
Normal mode
EM78P567
GREEN mode
IDLE mode
SLEEP mode
EM78567
Normal mode
EM78567
GREEN mode
IDLE mode
SLEEP mode
yes
yes
2
ROM2
1
ROM1
0
/povd
sleep mode
current
1uA
15uA
POVD
Disable
Disable
Disable
Enable or disable
* Bits 2~1: ROM2 and ROM1 bits can select three type of chip
(ROM2,ROM1) = (1,1)= EM78567; (ROM2,ROM1) = (1,0)= EM78566; (ROM2,ROM1) = (0,0)= EM78565
* Bit3: ADEN: A bit to enable or disable AD circuit.
1/0 = AD valid / AD invalid
* Bit4: DAEN: A bit to enable or disable DA circuit.
1/0 = DA valid / DA invalid
* Bit5: TONEEN: A bit to enable or disable AD circuit.
1/0 = TONE valid / TONE invalid
* Bit6,7 : unused
In OTP version, we name disabled POVD as A-type OTP and enabled POVD as B-type
OTP.
VII.9 AD converter
•
•
•
•
•
This is a CMOS multi-channel 8-bit successive approximation A/D converter.
Features
44kHz maximum conversion speed at 5V.
Adjusted full scale input
External reference voltage input or internal reference voltage
4 analog inputs multiplexed into one A/D converter
Power down mode for power saving
23
EM78P567/P566/P565
8-bit micro-controller
• A/D conversion complete interrupt
• Interrupt register, A/D control and status register, and A/D data register
START (bit3 of RE)
ADCLK0~ADCLK1
(bit6,7 of R5)
SVREF
Start F.F.
Clock
generator
(bit4 of RE)
P97/VREF
P97
Ladder
and
decoder
Switch
VDD
ADPWR
(bit2 of RE)
Mux
SAR
latch
A/D
power
control
8-bit
shift
register
INTEN
ADI
(bit5 of IOCF)
IN0~IN1
(bit1,0 of RE)
AD1~AD4 4
SAD1~SAD3
(bit5~7 of RE)
output latch
Mux
4
P93~P96
8
ADI
AD7 ~ AD0
(bit5 of RF)
(IOCD PAGE0)
Switch
4
P93/AD1~P96/AD4
RE( AD control)
7
6
SAD3
SAD2
5
SAD1
4
SVREF
3
START
2
ADPWR
1
IN1
0
IN0
* Bit1~Bit0 (input of AD converter selection ) : These two bits can choose one of three AD input.
(IN1,IN0)
0 0
0 1
1 0
1 1
INPUT
AD1
AD2
AD3
AD4
24
EM78P567/P566/P565
8-bit micro-controller
* Bit2 (ADPWR: AD converter power control register): 1/0=enable/disable
* Bit3 (START: AD converter start to sample): Set to “1” , the AD will start to sample data. This bit will be cleared by
hardware automatically after a sampling.
* Bit4 This register can switch AD converter reference voltage coming from internal or external voltage.
If the register set to internal , then the voltage will be VDD and port9 bit7 is a normal I/O PORT. If it set to external
reference voltage , then the voltage will connected from PORT9 bit7. 0/1=internal/external reference voltage.
* Bit5 This register can switch PORT9 bit3 as IO port or AD converter input1. 0/1= IO PORT / AD input
* Bit6 This register can switch PORT9 bit4 as IO port or AD converter input2. 0/1= IO PORT / AD input
* Bit7 This register can switch PORT9 bit5 as IO port or AD converter input3. 0/1= IO PORT / AD input
And it can switch PORT9 bit6 as IO port or AD converter input4. 0/1= IO PORT / AD input
RF (Interrupt Status Register)
7
6
5
4
3
2
1
0
0
0
ADI
IOCD (AD converter data register)
7
AD7
6
AD6
5
AD5
4
AD4
3
AD3
2
AD2
1
AD1
0
AD0
IOCF (Interrupt Mask Register)
7
0
6
0
5
ADI
4
-
3
-
2
-
1
-
0
-
There are four registers for A/D converter. Use one bit of interrupt control register (IOCF bit5) for A/D conversion
complete interrupt. The status and control register of A/D (RE and RF) responses the A/D conversion status or takes control
on A/D. The A/D data register (IOCD) stores A/D conversion result.
ADI bit in IOCF register is end of A/D conversion complete interrupt enable/disable. It enables/disables ADI flag
in RF register when A/D conversion is complete. ADI flag indicates the end of an A/D conversion. The A/D converter sets
the interrupt flag, ADI in RF register when a conversion is complete. The interrupt can be disabled by setting ADI bit in
IOCF register to ‘0’.
The A/D converter has four analog input channels AD1~AD3 multiplexed into one sample and hold to A/D
module. Reference voltage can be driven from VREF pin or internal power. The A/D converter itself is of an 8-bit
successive approximation type and produces an 8-bit result in the IOCD data register. A conversion is initiated by setting a
control bit START in RE register. Prior to conversion, the appropriate channel must be selected by setting IN0~IN1 bits in
RE register and allowed for enough time to sample data. Every conversion data of A/D need 10-clock cycle time. The
minimum conversion time required is 20 us (50K sample rate). START bit in RE register must be set to begin a conversion.
It will be automatically reset in hardware when conversion is complete. At the end of conversion, the START bit is cleared
and the A/D interrupt is activated if ADIE in IOCF = 1. ADI will be set when conversion is complete. It can be reset in
software.
If ADI = 0 in IOCF, when A/D start conversion by setting START= 1 then A/D will continue conversion without
stop and hardware won’t reset START bit. In this condition, ADI is deactived. After ADI in IOCF set, ADI in RF will
activate again.
To minimum operating current , all biasing circuits in the A/D module that consume DC current are power down
when ADPWR bit in RE register is a ’0’. When ADPWR bit is a ‘1’, A/D converter module is operating.
User has to set PORT93 to PORT97 as AD converter input pin or bi-direction IO PORT.
25
EM78P567/P566/P565
8-bit micro-controller
1
2
3
4
5
6
7
8
9
10
START
SAMPLE
ADI(IOCF) =1
Clear by software
ADI(RF)
DATA
26
EM78P567/P566/P565
8-bit micro-controller
VIII.Absolute Operation Maximum Ratings
RATING
DC SUPPLY VOLTAGE
INPUT VOLTAGE
OPERATING TEMPERATURE RANGE
SYMBOL
Vdd
Vin
Ta
VALUE
-0.3 To 6
-0.5 TO Vdd +0.5
0 TO 70
UNIT
V
V
℃
IX DC Electrical Characteristic
(Ta=0°C ~ 70°C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Condition
IIL1
Input Leakage Current for
VIN = VDD, VSS
input pins
IIL2
Input Leakage Current for
VIN = VDD, VSS
bi-directional pins
VIH
Input High Voltage
VIL
Input Low Voltage
VIHT
Input High Threshold
/RESET, TCC
Voltage
VILT
Input Low Threshold
/RESET, TCC
Voltage
VIHX
Clock Input High Voltage
OSCI
VILX
Clock Input Low Voltage
OSCI
VOH1
Output High Voltage
IOH = -1.6mA
(port6,7,8,A)
(port9)
IOH = -6.0mA
VOL1
Output Low Voltage
IOL = 1.6mA
(port6,7,8,A)
(port9)
IOL = 6.0mA
IPH
Pull-high current
Pull-high active input pin at
VSS
ISB1
Power down current
All input and I/O pin at
(SLEEP mode)
VDD, output pin floating,
WDT disabled
ISB2
Low clock current
CLK=32.768KHz, AD , DA,
(IDLE mode)
Tone generator block
disable , All input and I/O
pin at VDD, output pin
floating, WDT disabled
ISB3
Low clock current
CLK=32.768KHz, AD , DA,
(GREEN mode)
Tone generator block
disable , All input and I/O
pin at VDD, output pin
floating, WDT disabled
ICC
Operating supply current
/RESET = High,
(NORMAL mode)
CLK=3.58MHz, All input
and I/O pin at VDD, output
27
Min
Typ
Max
±1
Unit
µA
±1
µA
0.8
V
V
V
0.8
V
1.5
V
V
V
2.5
2.0
3.5
2.4
2.4
0.4
V
V
-10
0.4
-15
V
µA
2
4
µA
20
35
µA
30
50
µA
1.6
2.0
mA
EM78P567/P566/P565
8-bit micro-controller
pin floating, AD, DA , Tone
generator block disable
Vref1
Vref2
Vref3
Vmax
Vmax
Enl
Einl
Tcv
Tda
DA DC reference voltage
Tone generator reference
voltage
AD external reference
voltage
Tone1 signal strength
Tone2 signal strength
Differential nonlinear error
Integral nonlinear error
Conversion time
DA output valid time
Root mean square voltage
Root mean square voltage
Set sampling rate =44KHz
28
2.25
0.5
VDD
0.7
V
VDD
1.8
VDD
V
180
200
±1
±2
20
3
ｍV
ｍV
LSB
LSB
uS
uS
130 155
150 175
EM78P567/P566/P565
8-bit micro-controller
IX
AC Electrical Characteristic
(Ta=0°C ~ 70°C, VDD=5V, VSS=0V)
Symbol
Dclk
Tins
Parameter
Input CLK duty cycle
Instruction cycle time
Device delay hold time
Tdrh
TCC input period
Ttcc
Watchdog timer period
Twdt
Note 1: N= selected prescaler ratio.
(OTP AC Characteristic)
Description
Vpp to VDD level setup time
Mode code setup time
Mode code hold time
Data setup time
Data hold time
Program write pulse width
Output enable setup time
Data clock pulse width
Conditions
Min
45
Typ
50
60
550
18
32.768K
3.58M
Note 1
Ta = 25°C
Max
55
(Tins+20)/N
18
Symbol
Trs
Tcsu
Tchd
Tdsu
Tdhd
Tpwd
Toed
Tph
XI. Timing Diagrams
29
Min
2
3
2
100
100
Typ
200
300
100
Max
Unit
uS
uS
uS
nS
nS
uS
nS
nS
Unit
%
us
ns
ms
ns
ms
EM78P567/P566/P565
8-bit micro-controller
ins
`
Fig.10 AC timing
30
EM78P567/P566/P565
8-bit micro-controller
XII. Application Circuit
ANTENNE
EXPANDER
DATA FILTER
SHAPER
R-DAT
AUDIO
VDD
VDD
FCD
FCD
RSSI
POWER ON
RESET
/RESET
/RESET
EM78567
TEST
EM78567
TEST
GND
GND
OPTION
RF
RF
MODULE
MODULE
TB31223
TB31223
SECURITY
CODE
PLL
CONTROL
XIN
XIN
DC POWER
SUPPLY
30P
30P
32768
XOUT
XOUT
PLLC
PLLC
CONTROLS
PAGE
PAGE
DATA FILTER
COMPRESSOR
R-DAT
R-DAT
0.01u
PAGE
TELE LINE
DTMF
DTMF
RELAY CONTROL
RELAY CONTROL
RING
RING
TELEPHONE
TELEPHONE
LINE
LINE
INTERFACE
INTERFACE
MODE IN
Fig.11.application circuit1 (Base unit)
31
EM78P567/P566/P565
8-bit micro-controller
ANTENNE
EXPANDER
RX-AF
EARPIECE
DATA FILTER
SHAPER
R-DAT
AUDIO
VDD
VDD
LOBAT
LOBAT
BATTERY
DETECTOR
RSSI
DC POWER
SUPPLY
POWER ON
RESET
/RESET
/RESET
RF
RF
MODULE
MODULE
TB31223
TB31223
EM78567
EM78567
IO
IO
LCD MODULE
TEST
TEST
GND
GND
PLL
CONTROL
XIN
XIN
30P
30P
32768
XOUT
XOUT
CONTROLS
KEYPAD
PLLC
PLLC
0.01u
DATA FILTER
T-DAT
T-DAT
PORT
PORT
COMPRESSOR
MIC
Fig.12.application circuit2 (Handset unit)
32
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