EM78811
EM78811
8-BIT
8-BIT MICRO-CONTROLLER
TELECOM
PRODUCT
MICRO-CONTROLLER
FORFOR
TELECOM
PRODUCT
GENERAL DESCRIPTION
The EM78811 is an 8-bit CID (Call Identification) RISC type microprocessor with low power , high speed
CMOS technology. Integrated onto a single chip are on_chip watchdog (WDT) , RAM , ROM , programmable
real time clock /counter , internal interrupt , power down mode , LCD driver , FSK decoder , DTMF generator
and tri-state I/O . The EM78811 provides a single chip solution to design a CID of calling message_display .
FEATURES
CPU
• Operating voltage range : 2.5V~5.5V
• 16K X13 on chip ROM
• 2.8K X 8 on chip RAM
• Up to 32 bi-directional tri-state I/O ports
• 8 level stack for subroutine nesting
• 8-bit real time clock/counter (TCC)
• Two sets of 8 bit counters can be interrupt sources
• Selective signal sources and trigger edges , and with overflow interrupt
• Programmable free running on chip watchdog timer
• 99.9% single instruction cycle commands
• Three modes (internal clock 3.679MHz)
1. sleep mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn off
2. Idle mode : CPU and 3.679 MHz clock turn off, 32.768KHz clock turn on
3. Green mode : 3.679MHz clock turn off, CPU and 32.768KHz clock turn on
4. Normal mode : 3.679MHz clock turn on , CPU and 32.768KHz clock turn on
• Ring on voltage detector and low battery detector
• Input port wake up function
• 8 interrupt source , 4 external , 4 internal
• 100 QFP or chip
• Port key scan function
• Port interrupt, Pull high and Open drain functions
• Clock frequency 32.768KHz
• Main clock can switch to 1.84MHz by code option
CID
• Operation Volltage 3.5 ~5.5V for FSK
• Operation Volltage 2.5 ~5.5V for DTMF
• Bell 202 , V.23 FSK demodulator
• DTMF generator
• Ring detector on chip
LCD
• LCD operation voltage chosen by software
• Common driver pins : 16
• Segment driver pins : 60
• 1/4 bias
• 1/8,1/16 duty
* This specification are subject to be changed without notice.
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
APPLICATION
1. adjunct units
2. answering machines
3. feature phones
PIN ASSIGNMENTS
SEG42
SEF43
TEST
SEG44/P8.0
SEG45/P8.1
SEG46/P8.2
SEG47/P8.3
SEG48/P8.4
SEG49/P8.5
SEG50/P8.6
SEG51/P8.7
SEG52/P9.0
SEG53/P9.1
SEG54/P9.2
SEG55/P9.3
SEG56/P9.4
SEG57/P9.5
SEG58/P9.6
SEG59/P9.7
VDD1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AVSS
DTMF
PLLC
RINGTIME
RDET1
RING
TIP
NC
XIN
XOUT
AVDD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
VDD2
SEG17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
EM78811
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
RESET
P7.7
P7.6
P7.5
P7.4
P7.3/INT3
P7.2/INT2
P7.1/INT1
P7.0/INT0
COM15/P6.7
COM14/P6.6
COM13/P6.5
COM12/P6.4
COM11/P6.3
COM10/P6.2
COM9/P6.1
COM8/P6.0
COM7
COM6
COM5
COM4
COM3
VSS2
COM2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
COM1
COM0
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
FUNCTIONAL BLOCK DIAGRAM
ROM
CPU
RAM
CLK
TIMING
CONTROL
I/O PORT
I/O PORT
TIMER
INPUT PORT
FSK
INPUT
INPUT PORT
FSK
DEMODULATOR
DTMF
* This specification are subject to be changed without notice.
LCD
LATCH
& DRIVER
LCD
OUTPUT
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
Xin Xout
TCC
WDTTimer
R2
Oscillator/Timing
Control
WDT Timeout
Stack
ROM
Prescaler
R1(TCC)
RAM
Control
sleep and
wake-up
on I/O ports
R4
ALU
Instruction
register
Interrupt
Controller
Instruction
Decoder
R3
ACC
DATA & CONTROLL BUS
IOC7 I/O
PORT
R7
CALLER ID
RAM
P70˜P77
LCD RAM
COM0˜COM7
SEG0˜SEG35
LCD Driver
RA
Ring det
Carrier det
Data
/FSKPWR
FSK
Decoder
TIP
RING
RING DET1
RING TIME
low battery
detect
P80˜P87
SEG44˜SEG51
P90˜P97
SEG52˜SEG59
IOC8 I/O
PORT
R8 8
IOC9 I/O
PORT
R9 9
* This specification are subject to be changed without notice.
Row
RB Column
IOC6 I/O
PORT
R6 6
DTMF output
DTMF
P60˜P67
COM8˜COM15
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
PIN DESCRIPTIONS
Symbol
VDD1,VDD2
AVDD
VSS1,VSS2
AVSS
XTin
XTout
COM0..COM7
COM8..COM15
SEG0..SEG43
SEG44..SEG51
SEG52..SEG59
PLLC
TIP
RING
RDET1..RDET 2
/RING TIME
INT0
INT1
INT2
INT3
Type
POWER
POWER
I
O
O
O (PORT6)
0 (PORT8)
O (PORT9)
I
I
I
I
P7.0~P7.7
I
PORT7(0)
PORT7(1)
PORT7(2)
PORT7(3)
PORT7(4:7)
PORT7
P6.0~P6.7
PORT6
P8.0~P8.7
PORT8
P9.0~P9.7
PORT9
TEST
DTMF
RESET
I
O
I
Function
digital power
analog power
digital ground
analog ground
Input pin for 32.768 kHz oscillator
Output pin for 32.768 kHz oscillator
Common driver pins of LCD drivers
Segment driver pins of LCD drivers
PORT9 AS FUNCTION KEY CAN WAKE UP WATCHDOG.
Phase loop lock capacitor, connect a capacitor 0.01µ to 0.047µ with AVSS.
Should be connected with TIP side of twisted pair lines
Should be connected with TIP side of twisted pair lines
Detect the energy on the twisted pair lines.These two pins coupled to the twisted pair
lines through an attenuating network.
Determine if the incoming ring is valid. An RC network may be connected to the pin.
PORT7(0)~PORT7(3) signal can be interrupt signals.
IO port
PORT 7 can INPUT or OUTPUT port each bit.
Internal Pull high function.
Key scan function. Bit6,7 has open drain function
PORT6 can be INPUT or OUTPUT port each bit.
And shared with common signal.
PORT 8 can be INPUT or OUTPUT port each bit.
And shared with Segment signal.
PORT 9 can be INPUT or OUTPUT port each bit.
And can be set to wake up watch dog timer.
And shared with Segment signal.
Test pin into test mode , normal low
DTMF tone output
FUNCTION DESCRIPTION
Operational Registers
R0 (Indirect Addressing Register)
* R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using
R0 as register actually accesses data pointed by the RAM Select Register (R4).
R1 (TCC)
* Increased by an external signal edge applied to TCC , or by the instruction cycle clock Written and read by
the program as any other register.
* This specification are subject to be changed without notice.
4
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
R2 (Program Counter)
* The structure is depicted in Fig. 4.
* Generates 16Kx13 ( 14 on-chip ROM addresses to the relative programming instruction codes.
* "JMP" instruction allows the direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
* "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits
are cleared to "0''.
* "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits
are cleared to "0''.
* "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't
change. The most significant bit (A10~A13) will be loaded with the content of bit PS0~PS3 in the status
register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
CALL
PC
A13 A12 A11 A10
A9 A8
A7~A0
RET
RETL
RETI
1000
2000
Page 8
0000
0000
Page 0
1001
23FF
2400
Page 9
0001
03FF
0400
Page 1
1010
27FF
2800
2CFF
2D00
Page 10
0010
Page 11
0011
07FF
0800
0CFF
0D00
1011
Page 2
Page 3
1100
2FFF
3000
Page 12
0100
0FFF
1000
Page 4
1101
33FF
3400
Page 13
0101
13FF
1400
Page 5
Page 14
0110
Page 15
0111
1110
1111
37FF
3800
3CFF
3D00
3FFF
17FF
1800
1CFF
1D00
1FFF
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Stack 6
Stack 7
Stack 8
Page 6
Page 7
Fig.4 Program counter organization
* This specification are subject to be changed without notice.
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
00
01
02
03
04
R0
R1(TCC)
R2(PC)
R3(STATUS)
R4(RSR)
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R5(Program Page)
10
:
1F
16x8
Common
Register
IOC6
IOC7
IOC8
IOC9
IOCA(RAM,IO,PAGE ctl )
IOCB(lcd address
)
IOCC(lcd data
)
IOCD(PULL HIGH control)
IOCE(IO,Vlcd control )
IOCF(interrupt control)
R6(PORT6)
R7(PORT7)
R8(PORT8)
R9(PORT9)
RA(FSK STATUS)
RB(DTMF)
RC(CID ADRESS)
RD(CID DATA)
RE(LCD,WDT,WUE)
RF(INTERRUPT)
20
:
3F
00 BANK0
32X8
REGISTER
01 BANK1
32X8
REGISTER
10 BANK2
32X8
REGISTER
IOCB(COUNTER1)
IOCC(COUNTER2)
IOCE(OTHER )
11 BANK3
32X8
REGISTER
IOCB IOCC
CALLER RAM
00h
:
ffH
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
BAND1 BAND2 BAND3 BAND4 BAND5 BAND6 BAND7 BAND8 BAND9 BAND10
256X8 256X8 256X8 256X8 256X8 256X8 256X8 256X8 256X8 256X8
00h LCD RAM
: 120x8
:
:
78h
Fig.5 Data memory configuration
R3 ( Status Register )
7
-
6
page
5
-
4
T
3
P
2
Z
1
DC
0
C
• Bit 0 (C) : Carry flag
• Bit 1 (DC) : Auxiliary carry flag
• Bit 2 (Z) : Zero flag
• Bit 3 (P) : Power down bit. Set to 1 during power on or by a “WDTC” command and reset to 0 by a
SLEP” command.
• Bit 4 (T) : Time-out bit. Set to 1 by the “SLEP” and “WDTC” command, or during power up and reset
to 0 by WDT time out.
EVENT
WDT wake up from sleep mode
WDT time out (not sleep mode)
/RESET wake up from sleep
power up
T
0
0
1
1
P
0
1
0
1
REMARK
• Bit 5 : unused
• Bit 6 PAGE : change IOCB~IOCE to another page, 0/1→page0/page1
• Bit 7 : unused
R4 ( RAM Select Register )
• Bit 0 ~ 5 are used to select up to 64 register in the indirect addressing mode.
• Bit 6 ~ 7 determine which bank is actived among the 4 banks.
• See the configuration of the data memory in Fig.5.
* This specification are subject to be changed without notice.
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
R5 (Program Page Select Register)
7
-
6
-
5
-
4
-
• Bir0 (PS0) ~ 3 (PS3) Page select bits
Page selects bits
PS3
PS2
PS1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
:
:
:
1
1
1
3
PS3
PS0
0
1
0
1
0
1
0
1
1
1
;
1
2
PS2
1
PS1
0
PS0
Program memory page (Address)
Page 0 ( 0000 - 03FF )
Page 1 ( 0400 - 07FF )
Page 2 ( 0800 - 0BFF )
Page 3 ( 0C00 - 0FFF )
Page 4 (1000 - 13FF )
Page 5 ( 1400 - 17FF )
Page 6 ( 1800 - 1BFF )
Page 7 ( 1C00 - 1FFF )
Page 8 ( 2000 - 23FF)
Page 9 (2400 - 27FF)
:
Page 15 (3C00 - 3FFF)
• User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user can use
far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is maintained
by EMC's complier. It will change user's program by inserting instructions within program.
• Bit4~7 : unused
R6 ~ R9 (Port 6 ~ Port 9)
• Five 8-bit I/O registers.
RA (FSK Status Register)(bit0,1,2,4 read only))
7
IDLE
6
/358E
5
/LPD
4
/LOW-BAT
3
/FSKPWR
2
DATA
1
/CD
0
/RD
• Bit0 (Read Only) (Ring detect signal)
0/1 : Ring Valid/Ring Invalid
• Bit1(Read Only)(Carrier detect signal)
0/1 : Carrier Valid/Carrier Invalid
• Bit2(Read Only)(FSK demodulator output signal)
Fsk data transmitted in a baud rate 1200 Hz. Data from FSK demodulator when /CD is Low.
• Bit3(read/write)(FSK block power up signal)
1/0 : FSK demodulator block power up/FSK demodulator power down
The relation between Bit0 to Bit3 is shown in Fig.6.
* This specification are subject to be changed without notice.
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
SLEEP MODE
Begin
set /FSKPWR='0'
/RINGTIME='0'
or EXTERNAL KEYS
PRESSED
sleep mode
No
/RD and /CD ='1'
/RD and /CD ='1' and
nothing to do for 30
sec , /FSKPWR='0'
FSK decoder
begin its work
WAKE UP MODE
8-bit wake up andÁ
set /FSKPWR='1'
accept data from
FSK decoder
wake up
mode
/FSKPWR='1'
/RINGTIME ='0'
or external keys
pressed
Yes
DATA transfer
DATA transfer
to Micro
Yes
/RD and /CD ='1'
data end and 30
sec nothing to do.
No
Flow Diagram between 8-bit
and FSK decoder
STATE Diagram between 8-bit
and FSK decoder
Fig6. The relation between Bit0 to Bit3.
• Bit4(Read Only)(Low battery signal)
0/1 = Battery voltage is low/Normal . If the battery voltage is under 3.6V then sends a ‘0’ signal to RA register
bit4 or sends a '1' signal to this bit.
• Bit5(read/Write)(Low battery detect enable)
0/1 = low battery detect DISABLE/ENABLE. The relation between /LPD,/POVD and /LOW_BAT can see
Fig7.
Vdd
/POVD
/LPD
s2
1 on
0 off
to Low bat
+
-
1 on
To reset
1 on
Vref
s2
1 on
0 off
/LPD
Fig7. The relation between /LPD,/POVD
• Bit6(read/write)(PLL enable signal)
0/1=DISABLE/ENABLE, The relation between 32.768K and 3.679M can see Fig8.
32.768K
PLL
3.679M
1
switch
To system clock
/358E
0
Fig8. The relation between 32.768K and 3.58K .
* This specification are subject to be changed without notice.
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
• Bit7 IDLE : Sleep mode selection bit
0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go.
These two modes can be waken up by TCC clock or Watch Dog or PORT9 and run from "SLEP" next
instruction.
TCC time out
SLEEP moe
RA(7,6)=(0,0)
+SLEP
X
WDT time out
RESET
Port9 wake-up
RESET
IDLE mode
RA(7,6)=(1,0)
+SLEP
Wake-up
+Interrupt
+Next instruction
Wake-up
+Next instruction
Wake-up
+Next instruction
GREEN mode
RA(7,6)=(x,0)
no SLEP
Interrupt
NORMAL mode
RA(7,6)=(x,1)
no SLEP
Interrupt
RESET
RESET
RESET
RESET
RB(DTMF tone row and column register) (read/write)
7
6
5
4
3
2
1
0
c7
c6
c5
c4
r3
r2
r1
r0
• Bit 0 - Bit 3 are row-frequency tone.
• Bit 4 - Bit 7 are column-frequency tone.
• Initial RB is equal to high. Bit7~0 are all "1", turn off DTMF power.
bit3~0
1110
1101
1011
0111
Column freq
bit 7~4
Row freq
699.2 Hz
771.6 Hz
854 Hz
940.1 Hz
1
4
7
*
1203 Hz
1110
2
5
8
0
1331.8 Hz
1101
3
6
9
#
1472 Hz
1011
A
B
C
D
1645.2 Hz
0111
RC(CALLER ID address)(read/write)
7
6
5
CIDA7 CIDA6 CIDA5
4
3
2
CIDA4 CIDA3 CIDA2
1
CIDA1
0
CIDA0
• Bit 0 ~ Bit 7 select CALLER ID RAM address up to 256.
RD(CALLER ID RAM data)(read/write)
• Bit 0 ~ Bit 8 are CALLER ID RAM data transfer register.
User can see IOCA register how to select CID RAM banks.
RE(LCD Driver,WDT Control)(read/write)
7
-
6
/WDTE
5
/WUP9H
4
3
/WUP9L /WURING
2
LCD_C2
1
0
LCD_1 LCD_M
• Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency.
• Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking.
change the display duty must set the “LCD_C2,LCD_C1” to “00”.
* This specification are subject to be changed without notice.
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
LCD_C2, LCD_C1
0
0
0
1
1
1
LCD Display Control
change duty
Disable (turn off LCD)
Blanking
LCD display enable
LCD_M
0
1
:
:
duty
1/16
1/8
:
:
bias
1/4
1/4
• Bit3 (/WURING, RING Wake Up Enable): used to enable the wake-up function of /RINGTIME input pin.
(1/0=enable/disable)
• Bit4 (/WUP9L, PORT9 low nibble Wake Up Enable): used to enable the wake-up function of low nibble in
PORT9.(1/0=enable/disable)
• Bit5 (/WUP9H, PORT9 high nibble Wake Up Enable): used to enable the wake-up function of high nibble
in PORT9.(1/0=enable/disable)
• Bit6 (/WDTE,Watch Dog Timer Enable)
Control bit used to enable Watchdog timer.
(1/0=enable/disable)
The relation between Bit3 to Bit6 can see the diagram 9.
• Bit7 unused
/WURING
/RINGTIME
/WUP9L
PORT9(3:0)
/WDTEN 1/0=enable/disable
/WUP9H
PORT9(7:4)
/WDTE
fig.9 Wake up function and control signal
RF (Interrupt Status Register)
7
6
5
4
3
2
INT3
FSKDATA
C8_2
C8_1
INT2
INT1
1
INT0
0
TCIF
* “1” means interrupt request, “0” means non-interrupt
* Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows.
* Bit 1 (INT0) external INT0 pin interrupt flag .
* Bit 2 (INT1) external INT1 pin interrupt flag .
* Bit 3 (INT2) external INT2 pin interrupt flag .
* Bit 4 (C8_1) internal 8 bit counter interrupt flag .
* Bit 5 (C8_2) internal 8 bit counter interrupt flag .
* Bit 6 (FSKDATA) FSK data interrupt flag.
* Bit 7 (INT3) external INT3 pin interrupt flag.
* High to low edge trigger , Refer to the Interrupt subsection.
* IOCF is the interrupt mask register. User can read and clear.
R10~R3F (General Purpose Register)
• R10~R3F (Banks 0~3) all are general purpose registers.
* This specification are subject to be changed without notice.
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
Special Purpose Registers
A (Accumulator)
• Internal data transfer, or instruction operand holding
• It’s not an addressable register.
CONT (Control Register)
7
-
6
-
5
TS
4
3
PAB
2
PSR2
1
PSR1
0
PSR0
Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
Bit 3 ( PAB ) Prescaler assignment bit
0/1 : TCC/WDT
Bit 4 : unsed
Bit 5 ( TS ) : TCC signal source
0 : internal instruction cycle clock
1 : 16.38KHz
Bit 6: unused
Bit 7: unused
• CONT register is readable and writable
IOC6 ~ IOC9 (I/O Port Control Register)
• Five I/O direction control registers.
• "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output.
• User can see IOCB register how to switch to normal I/O port.
* This specification are subject to be changed without notice.
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
IOCA (CALLER ID RAM,IO ,PAGE Control Register)(read/write,initial "00000000")
7
P8SH
6
P8SL
5
-
4
CALL_4
3
CALL_3
2
CALL_2
1
CALL_1
0
0
• Bit4~Bit1:"0000" to "1001" are ten blocks of CALLER ID RAM area. User can use 2.5K RAM with RC
ram address.
• Bit 5 unused
• Bit6: port8 low nibble switch, 0/1= normal I/O port/SEGMENToutput .
• Bit7: port8 high nibble switch , 0/1= normal I/O port/SEGMENT output.
IOCB (LCD ADDRESS)
PAGE0 : Bit6 ~ Bit0 = LCDA6 ~ LCDA0
The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below:
COM15~COM8
40H (Bit15~Bit8)
41H
:
:
7BH
7CH
7DH
7EH
7FH
COM7~COM0
00H (Bit7~Bit0)
01H
:
:
3BH
3CH
3DH
3EH
3FH
SEG0
SEG1
:
:
SEG59
Empty
Empty
Empty
Empty
PAGE1 : 8 bit up-counter (COUNTER1) preset and read out register . ( write = preset ) . After a interruption
, it will count from "00".
IOCC (LCD DATA)
PAGE0 : Bit7 ~ Bit0 = LCD RAM data register
PAGE1 : 8 bit up-counter (COUNTER2) preset and read out register . ( write = preset) After a interruption
, it will count from "00".
IOCD (Pull-high Control Register)
PAGE0:
7
PH7
6
PH6
5
PH5
4
PH4
3
PH3
2
PH2
1
PH1
0
PH0
• Bit 0 ~ 7 (/PH#) Control bit used to enable the pull-high of PORT7(#) pin.
1: Enable internal pull-high
0: Disable internal pull-high
* This specification are subject to be changed without notice.
10.12.1998
12
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
IOCE (Bias,PLL Control Register)
PAGE0 :
7
P9SH
6
P9SL
5
P6S
4
Bias3
3
Bias2
2
Bias1
1
PHR
0
SC
• Bit 0 : SC(SCAN KEY signal) 0/1=disable/enable. once you enablethis bit, all of the LCD signal will have
a low pulse during a common period. This pulse has 30µs width. Please use the procedure to implement the
key scan function.
a.
b.
c.
d.
e.
f.
g.
h.
set port7 as input port.
set IOCD page0 port7 pull high.
enable scan key signal. And enable interruption.
Once push a key. Set RA(6)=1 and switch to normal mode.
Blank LCD. Disable scan key signal.
Set P6S=0. Port6 sent probe signal to port7 nd read port7. Get the key.
Note!! A probe signal should be delay a instruction at least to another probe signal.
Set P6S=1. Port6 as LCD signal. Enable LCD.
KEY5
KEY1
P63
KEY2
P62
KEY3
P61
KEY4
P60
P73
P72
P71
P70
Fig10. Key scan circuit
VDD
V1
V2
V3
V4
VLCD
GND
com2
VDD
V1
V2
V3
V4
VLCD
GND
seg
30µs
Fig11. Key scan signal
* This specification are subject to be changed without notice.
10.12.1998
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
• Bit 1 :PORT7 PULL HIGH register option. Please use defaut value.
• Bit 2~4 (Bias1~Bias3) Control bits used to choose LCD operation voltage.
LCD operate voltage
000
001
010
011
100
101
110
111
Vop (VDD 5V)
0.60VDD
0.66VDD
0.74VDD
0.82VDD
0.87VDD
0.93VDD
0.96VDD
1.00VDD
VDD=5V
3.0V
3.3V
3.7V
4.0V
4.4V
4.7V
4.8V
5.0V
• Bit5:port6 switch , 0/1= normal I/O port/COMMON output
• Bit6:port9 low nibble switch , 0/1= normal I/O port/SEGMENT output . Bit7:port9 high nibble switch
PAGE1 :
7
OD7
6
OD6
5
C2S
4
C1S
3
PSC1
2
PSC0
1
CDRD
0
-
• Bit0: unused
• Bit1: cooked data or raw data select bit , 0/1 ==> cooked data/raw data
• Bit3~Bit2: counter1 prescaler , reset=(0,0)
(PSC1,PSC0) = (0,0)=>1:1 , (0,1)=>1:2 , (1,0)=>1:4 , (1,1)=>1:8
• Bit4:counter1 source , (0/1)=(32768Hz/3.679MHz if enable) scale=1:1
• Bit5:counter2 source , (0/1)=(32768Hz/3.679MHz if enable) scale=1:1
• Bit6: PORT7(6) open drain control, 0/1=disable/enable
• Bit7: PORT7(7) open drain control, 0/1=disable/enable
IOCF (Interrupt Mask Register)
7
6
5
INT3
FSKDATA
C8-2
• Bit 0 ~ 7 interrupt enable bit.
0: disable interrupt
1: enable interrupt
• IOCF Register is readable and writable.
4
C8-1
3
INT2
2
INT1
1
INT0
0
TCIF
TCC/WDT Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only
or WDT only at the same time.
• An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register.
• See the prescaler ratio in CONT register.
• Fig. 12 depicts the circuit diagram of TCC/WDT.
• Both TCC and prescaler will be cleared by instructions which write to TCC each time.
• The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
• The prescaler will not be cleared by the SLEP instruction, when assigned to TCC mode.
* This specification are subject to be changed without notice.
10.12.1998
14
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
CLK(=Fosc/2)
Data Bus
0
1
TCC
(16.38KHz CLK)
M
U
X
1
TS
TE
0
WDT
0
SYNC
2 cycle
PAB
M
U
X
1
M
U
X
TCC(R1)
TCC overflow interrupt
8-bit Counter
PSR0~PSR2
8-to-1 MUX
PAB
WDTE
PAB
MUX
WDT timeout
Fig. 12 Block diagram of TCC WDT
I/O Ports
The I/O registers, Port 6 ~ Port 9, are bi-directional tri-state I/O ports. Port 7 can be pulled-high internally by
software control. The I/O ports can be defined as “input” or “output” pins by the I/O control registers (IOC6 ~
IOC9 ) under program control. The I/O registers and I/O control registers are both readable and writable. The
I/O interface circuit is shown in Fig.13. Port 7 bit6 and bit7 can be open drain.
PCRD
Q PR D
CLK
Q CL
PCWR
Q PR D
PORT
CLK
Q CL
IOD
PDWR
PDRD
0
1
M
U
X
Fig. 13 The circuit of I/O port and I/O control register
* This specification are subject to be changed without notice.
10.12.1998
15
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
RESET and Wake-up
The RESET can be caused by
(1) Power on reset, or Voltage detector
(2) WDT timeout. (if enabled and in GREEN or NORMAL mode)
Note that only Power on reset, or only Voltage detector in Case(1) is enabled in the system by CODE Option bit.
If Voltage detector is disabled, Power on reset is selected in Case (1). Refer to Fig. 14
VDD
D Q
CLK
CLR
Oscillator
.
Power-on
Reset
1
0
CLK
M
U
X
Voltage
Detector
/Enable
Code
Option
WDTE
18 ms
WDT
RESET
Fig. 14 Block diagram of Reset of controller
Once the RESET occurs, the following functions are performed.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all “0”.
• When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
• The Watchdog timer and prescaler are cleared.
• The Watchdog timer is disabled.
• The CONT register is set to all “1”
• The other register (bit7. . bit0)
R5 =
R6 =
R7 =
R8 =
R9 =
RA =
RB =
RC =
RD =
RE =
RF =
"00000000"
PORT
PORT
PORT
PORT
"000x0xxx
"11111111"
"00000000"
"xxxxxxxx"
"00000000"
"00000000"
IOC6
IOC7
IOC8
IOC9
IOCA
IOCB
IOCC
IOCD
IOCE
IOCF
* This specification are subject to be changed without notice.
=
=
=
=
=
=
=
=
=
=
"11111111"
"11111111"
"11111111"
"11111111"
"00000000"
"00000000"
"0xxxxxxx"
"00000000"
"00000000"
"00000000"
Page1 IOCB = "00000000"
Page1 IOCC = "00000000"
Page1 IOCE = "00000000"
10.12.1998
16
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
RA(7)=0 SLEEP mode
RA(7,6)
TCC
Sleep
0 0+SLEEP
x
WDT
RESET
Port 9
wakeup
RESET
IDLE
1 0+SLEEP
Wakeup
+int
+Next ins
wakeup
Next ins
wakeup
Next ins
Green
x 0 No Slep
int
Normal
x 1 No slep
int
RESET
RESET
RESET
RESET
X: No function
The controller can be awakened from SLEEP mode or IDLE mode (execution of “SLEP” instruction, named as
SLEEP MODE or IDLE mode controllered by RA bit 7) by (1) TCC time out (2)WDT time-out (if enabled) or,
(3) external input at PORT9 (4) RINGTIME pin. The four cases will cause the controller wake up and run from
next instruction in IDLE mode, reset in SLEEP mode. After wakeup, user should control WATCH DOG in case
of reset in GREEN mode or NORMAL mode. The last three should be open RE register before into SLEEP mode
or IDLE mode. The first one case should set a flag in IOCF bit0. After time-out, it will go to address 0x08, then
return to next instruction.
Interrupt
The CALLER ID IC has internal interrupts which are falling edge triggered, as followed : TCC timer overflow
interrupt (internal) , two 8-bit counters overflow interrupt .
If these interrupt sources change signal from high to low , then RF register will generate ‘1’ flag to corresponding
register if you enable IOCF register.
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask
register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the
interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in
the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RF register.
The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling
interrupts to avoid recursive interrupts.
There are four external interrupt pins including INT0 , INT1 , INT2 , INT3 . The INT0 to INT3 sent to the different
interrupt flag . And three internal counter interrupt available.
External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT7 bit0 to bit3 . If IOCF is enable then these
signal will cause interrupt , or these signals will be treated as general input data .
After resetting, the next instruction will be fetched from address 000H, and the software interrupt is 001H and
the hardware interrupt is 008H.
TCC will go to address 0x08 in GREEN mode or NORMAL mode after time out. And it will run next instruction
from "SLEP" instruction. These two cases will set a RF flag.
* This specification are subject to be changed without notice.
10.12.1998
17
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
Instruction Set
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O
register.
The symbol “R” represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. “b’’ represents a bit field designator which selects the number of the bit,
located in the register “R’’, affected by the operation. “k’’ represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
HEX
MNEMONIC
OPERATION
0
0
0
0
0
0
0
0
0
0
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0011
0100
rrrr
0000
0001
0010
0011
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
0
0
0
0000 0001 0100
0000 0001 rrrr
0000 0010 0000
0014
001r
0020
CONTR
IOR R
TBL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2 bits 9,10
do not clear
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A∨R→ A
A∨R→ R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R(0) → C, C → A(7)
0000
0001
0000
0000
0000
0000
0001
0001
0001
0001
01rr
1000
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
rrrr
0000
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
* This specification are subject to be changed without notice.
STATUS
AFFECTED
None
C
None
T,P
T,P
None
None
None
None
None
None
None
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
C
10.12.1998
18
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
INSTRUCTION BINARY
HEX
MNEMONIC
0
0
0
0101 11rr rrrr
0110 00rr rrrr
0110 01rr rrrr
05rr
06rr
06rr
DJZ R
RRCA R
RRC R
0
0110 10rr rrrr
06rr
RLCA R
0
0110 11rr rrrr
06rr
RLC R
0
0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
1
0111
0111
0111
100b
101b
110b
111b
00kk
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
0000
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
kkkk
1
1
1
1
1
1
1
1
01kk
1000
1001
1010
1011
1100
1101
1110
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
0001
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E01
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
1
1
1110 1000 kkkk
1111 kkkk kkkk
1E8k
1Fkk
PAGE k
ADD A,k
OPERATION
R-1 → R, skip if zero
R(n) → A(n-1)
R(n) → R(n-1)
R(0) → C, C → R(7)
R(n) → A(n+1)
R(7) → C, C → A(0)
R(n) → R(n+1)
R(7) → C, C → R(0)
R(0-3) → A(4-7)
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP]
(Page, k) → PC
(Page, k) → PC
k→A
A⁄k→A
A&k→A
A⊕k→A
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP]
001H → PC
K→R5
k+A → A
STATUS
AFFECTED
None
C
C
C
None
None
None
None
None
None
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
None
Z,C,DC
CODE Option Register
The CALLER ID IC has one CODE option register which is not part of the normal program memory. The option
bits cannot be accessed during normal program execution.
7
-
6
-
5
-
4
-
3
-
2
-
1
/POVD
0
MCLK
Bit 0 : main clock selection, 0/1=3.68MHz/1.84MHz
Bit 1 ( /POVD ) : Power on voltage detector.
0 : enable
1 : disable
* This specification are subject to be changed without notice.
10.12.1998
19
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
/POVD
2.2V reset
1
0
no
yes
power on
reset
yes
yes
3.6V detect no
reset
yes
yes
3.6V detect control
by RA(5)
yes
yes
sleep mode
current
1µA
20µA
Bit 2~7 : unused, must be "0"s.
* This specification are subject to be changed without notice.
10.12.1998
20
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
FSK FUNCTION
Tip
Ring
Ring det1
/Ring Time
Band Pass
Filter
FSK
demodul
Data Valid
Energy Det
Circuit
DATA OUT
/CD
Power /FSKPWR
Up
Ring
Det
Circuit
/RD
OSC in
OSC out
CLOCK
Fig15. FSK Block Diagram
Function Descriptions
The CALLER ID IC is a CMOS device designed to support the Caller Number Deliver feature which is offered
by the Regional Bell Operating Companies.The FSK block comprises two paths: the signal path and the ring
indicator path. The signal path consist of an input differential buffer,a band pass filter, an FSK demodulator and
a data valid with carrier detect circuit. The ring detector path includes a clock generator, a ring detect circuit and
a power-up logic circuit.
In a typical application, the ring detector maintains the line continously while all other functios of the chip are
inhibited. If a ring signal is sent, the /RINGTIME pin will has a low signal. User can use this signal to wake up
whole chip or read /RD signal from RA register.
A /FSKPWR input is provided to active the block regardless of the presence of a power ring signal. If /FSKPWR
is sent low, the FSK block will power down whenever it detects a valid ring signal, it will power on when
/FSKPWR is high.
The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this
signal to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends
it to a post filter. The output data is then made available at DATA OUT pin. This data, as sent by the central office,
includes the header information (alternate “1” and “0”) and 150 ms of marking which precedes the date , time
and calling number. If no data is present, the DATA OUT pin is held in a high state. This is accomplished by an
carrier detect circuit which determines if the in-band energy is high enough. If the incoming signal is valid and
thus the demodulated data is transferred to DATA OUT pin . If it is not, then the FSK demodulator is blocked.
* This specification are subject to be changed without notice.
10.12.1998
21
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
Ring detect circuit
When Vdd is applied to the circuit, the RC netwiok will charge cap C1 to Vdd holding/RING TIME off. The
resistor network R2 to R3 attenuates the incoming power ring applied to the top of R2. The values given have
been chosen to provide a sufficient voltage at DET1 pin, to turn on the Schmitt trigger input. When Vt+ of the
Schmitt is exceeded, cap C1 will discharge.
The value of R1 and C1 must be chosen to hold the /RING TIME pin voltage below the Vt+ of the Schmitt
between the individual cycle of the power ring With /RINGTIME enabled, this signal will be a /RD signal in
RA throught a buffer.
/Ring Time
/Ring Time
Vdd
R1 C1
/RD
det1
R2
R3
Fig16. Ring detect circuit
DTMF ( Dual Tone Multi Frequency ) Tone Generator
Built-in DTMF generator can generate dialing tone signals for telephone of dialing tone type. There are two kinds
of DTMF tone . One is the group of row frequency, the other is the group of column frequency, each group has
4 kinds of frequency , user can get 16 kinds of DTMF frequency totally. DTMF generator contains a row
frequency sine wave generator for generating the DTMF signal which selected by low order 4 bits of RB and a
column frequency sine wave generator for generating the DTMF signal which selected by high order 4 bits
of RB. This block can generate single tone by filling one bit zero to this register.
If all the values are high , the power of DTMF will turn off until one or two low values.
Either high or low 4 bits must be set by an effective value, otherwise, if any ineffective value or both 4 bits are
load effective value, tone output will be disable. Recommend value refer to table as follow please :
* This specification are subject to be changed without notice.
10.12.1998
22
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
SYSTEM CLOCK
Low frequency generator
ROW
Register
DTMF low-freq
selection
Sine wave
generator
Sine wave
generator
DTMF high-freq
selection
COLUMN
Register
DTMF tone
Adder output
High frequency generator
Fig17. DTMF Block Diagram
RB ( DTMF Register )
• Bit 0 - Bit 3 are row-frequency tone.
• Bit 4 - Bit 7 are column-frequency tone.
• Initial RB is equal to HIGH.
• Except below values of RB ,the other values of RB are not effect. If RB is set by ineffective value, the DTMF
output will be disable and there is no tone output.
• Bit 7 ~ 0 are all “1” , turn off DTMF power .
bit 3~0
1110
1101
1011
0111
Column freq
bit 7~4
Row freq
699.2Hz
771.6Hz
854Hz
940.1Hz
Xin=3.58MHz
1
4
7
*
1203Hz
1110
2
5
8
0
1331.8Hz
1101
3
6
9
#
1472Hz
1011
A
B
C
D
1645.2Hz
0111
LCD Driver
The CALLER ID IC can drive LCD directly and has 60 segments and 16 commons that can drive 60*16 dots
totally. LCD block is made up of LCD driver , display RAM, segment output pins , common output pins and LCD
operating power supply pins.
Duty , bias , the number of segment , the number of common and frame frequency are determined by LCD mode
register . LCD control register.
The basic structure contains a timing control which uses the basic frequency 32.768KHz to generate the proper
timing for different duty and display access. RE register is a command register for LCD driver, the LCD display(
disable, enable, blanking) is controlled by LCD_C and the driving duty and bias is decided by LCD_M and the
display data is stored in data RAM which address and data access controlled by registers RC and RD.
* This specification are subject to be changed without notice.
10.12.1998
23
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
32.768KHz
RC(address)
LCD timing control
RE(LCD_C,LCD_M)
RD(data)
RAM
LCD duty control
Display data control
Bias control
LCD commom control
Vdd-Vlcd
LCD SEGMENT control
COM
SEG
Fig18. LCD DRIVER CONTROL
LCD Driver Control
RE(LCD Driver Control)(initial state “00000000”)
7
6
5
4
-
3
-
2
LCD_C2
1
LCD_C1
0
LCD_M
• Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency.
• Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking.
change the display duty must set the LCD_C to “00”.
LCD_C
bit2,1
0 0
0 1
1 1
LCD Display Control
change duty
Disable(turn off LCD)
Blanking
LCD display enable
LCD_M
bit 0
0
1
:
:
LCD driving method/frame freq.
duty bias
1/16 1/4
1/8 1/4
:
:
LCD display area
The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below:
COM15 ~ COM8
40H (Bit15 ~ Bit8)
41H
:
:
7BH
7CH
7DH
7EH
7FH
COM7 ~ COM0
00H (Bit7 ~ Bit0)
01H
:
:
3BH
3CH
3DH
3EH
3FH
* This specification are subject to be changed without notice.
SEG0
SEG1
:
:
SEG59
empty
empty
empty
empty
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
• IOCB(LCD Display RAM address)
7
6
5
4
3
2
1
0
LCD6
LCD5
LCD4
LCD3
LCD2
LCDA1
LCD0
Bit 0 ~ Bit 6 select LCD Display RAM address up to 120.
LCD RAM can be write whether in enable or disable condition and read only in disable condition.
• IOCC(LCD Display data) : Bit 0 ~ Bit 8 are LCD data.
LCD COM and SEG signal
• COM signal : The number of COM pins varies according to the duty cycle used, as following: in 1/8 duty
mode COM8 ~ COM15 must be open. in 1/16 duty mode COM0 ~ COM15 pins must be used.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 ..
COM15
1/8
o
o
o
o
o
o
o
o
x
..
x
1/16 o
o
o
o
o
o
o
o
o
..
o
x:open,o:select
• SEG signal: The 60 segment signal pins are connected to the corresponding display RAM address 00h to 3Bh.
The high byte and the low byte bit7 down to bit0 are correlated to COM15 to COM0 respectively .
When a bit of display RAM is 1, a select signal is sent to the corresponding segment pin, and when the bit
is 0 , a non-select signal is sent to the corresponding segment pin.
• COM, SEG and Select/Non-select signal is shown as following:
* This specification are subject to be changed without notice.
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
frame
com0 ... com7
VDD
V1
V2
V3
VLCD
com0
VDD
V1
V2
V3
VLCD
com1
VDD
V1
V2
V3
VLCD
com2
VDD
V1
V2
V3
VLCD
seg
dark
VDD
V1
V2
V3
VLCD
seg
light
Fig.19 Lcd wave 1/4 bias , 1/8 duty
* This specification are subject to be changed without notice.
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EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
frame
com0 ... com15
VDD
V1
V2
V3
VLCD
com0
VDD
V1
V2
V3
VLCD
com1
VDD
V1
V2
V3
VLCD
com2
VDD
V1
V2
V3
VLCD
seg
dark
VDD
V1
V2
V3
VLCD
seg
light
Fig.20 Lcd wave 1/4 bias , 1/16 duty
* This specification are subject to be changed without notice.
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
LCD Bias control
IOCE (Bias Control Register)
7
6
5
4
Bias3
3
Bias2
2
Bias1
1
0
• Bit 2~4 (Bias1~Bias3) Control bits used to choose LCD operation voltage .
Bias3 Bias2 Bias1
000
001
010
011
100
101
110
111
LCD operate voltage
0.60 VDD
0.66 VDD
0.74 VDD
0.82 VDD
0.87 VDD
0.93 VDD
0.96 VDD
1.00 VDD
Vop (VDD 5V)
3.0V
3.3V
3.7V
4.0V
4.4V
4.7V
4.8V
5.00V
• Bit 5~7 unused
Vdd
R=1K
Vop=Vdd-Vlcd
R
R
Vop
R
R
V1
000
V3
Vlcd
Bias3˜1
MUX
8.2R
V2
:
001
0.4R
010
0.4R
011
0.3R
100
0.3R
101
0.2R
110
0.1R
111
0.1R
Vop=Vdd-Vlcd
R=1K
Vss
Fig.19 LCD bias circuit
* This specification are subject to be changed without notice.
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
ABSOLUTE MAXIMUM RATINGS
Items
Sym.
Temperature under bias
Input voltage
Operating temperature range
VDD
VIN
TA
Condition
Rating
Unit
-0.3 to 6
- 0.5 to VDD+ 0.5
0 to 70
V
V
°C
DC ELECTRICAL CHARACTERISTICS (TA= 0°C~70°C, VDD = 5V±5%; VSS = 0V)
(VDD=2.5V to 5.5V for CPU ; VDD=3.5V to 5.5V for FSK ; VDD=2.5V to 5.5V for DTMF)
Parameter
Input Leakage Current
for input pins
Input Leakage Current
for bi-directional pins
Input High Voltage
Input Low voltage
Input High Threshold
Voltage
Input Low Threshold
Voltage
Clock Input High Voltage
Clock Input Low Voltage
Output High Voltage
(port5,6,7,8)
(port9)
Output Low Voltage
(port5,6,7,8)
(port9)
Com Voltage drop
Segment Voltage drop
LCD Drive Reference
Voltage
Pull-high Current
Power Down Current
Low Clock Current
Operating Supply
Sym.
Condition
Min.
Typ.
Max.
Unit
IIL1
VIN = VDD, VSS
±1
µA
IIL2
VIN = VDD, VSS
±1
µA
0.8
V
V
V
0.8
V
1.5
V
V
V
VIH
VIL
VIHT RESET, TCC, RDET1
VILT
2.5
2.0
RESET, TCC, RDET1
VIHX OSCI
VILX OSCI
VOH1 IOH = -1.6 mA
3.5
2.4
VOL1
IOH = -6.0 mA
IOL = 1.6 mA
VCOM
VSEG
VLCD
IOL = 6.0 mA
I O = ±50 µA
I O = ±50 µA
Contrast adjustment
IPH
ISB1
ISB2
ICC
Pull-high active input pin at VSS
All input and I/O pin at VDD, output pin
floating, WDT disabled
CLK=32.768 KHz, FSK, DTMF block
disable,All input and I/O pin at VDD,
output pin floating, WDT disabled,
LCD enable
RESET=HIGH, CLK=3.679MHz, output pin
floating, FSK, DTMF block disable
* This specification are subject to be changed without notice.
2.4
-
-
-50
-100
4
0.4
V
V
0.4
2.9
3.8
V
V
V
-240
µA
µA
100
µA
3
mA
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
AC ELECTRICAL CHARACTERISTIC ( TA = 0 ~ 70°C, VDD = 5V`VSS = 0V )
Parameter
Sym.
Input CLK duty cycle
Instruction cycle time
Dclk
Tins
Device delay hold time
Tdrh
TCC input period
Ttcc
Watchdog timer period
Twdt
Note 1: N = selected prescaler ratio.
Condition
Min.
Typ.
Max.
Unit
45
50
60
550
18
55
%
µs
µs
ms
ns
ms
32.768K
3.679M
Note 1
TA = 25°C
(Tin+20)/N
18
( FSK Band Pass Filter AC Characteristic)(VDD = 5V`TA=25° C )
Characteristic
Input Sensitivity TIP and RING pin1 and pin2 VDD=+5V
Band Pass Filter
Min.
Typ.
Max.
Unit
-35
-48
—
dBm
dBm
Typ.
Max.
Unit
400
10
14
20
20
10
—
FSK DECODER BLOCK FUNCTION TIMING
( VDD = 5.0V ± 5%, VSS = 0V TA = operating temperature range, unless otherwise note )
Parameter
OSC start up
(32.768KHz)
(3.679MHz PLL)
Carrier detect low
Data out to Carrier det low
Power up to FSK(setup time) PS(1)
/RD low to Ringtime low
End of FSK to Carrier Detect high
Sym.
Min.
Tosc
—
Tcdl
Tdoc
Tsup
Trd
Tcdh
—
—
—
10
10
15
8
—
ms
ms
ns
ms
ms
ms
PS (1) : Please watch out the setup time.
* This specification are subject to be changed without notice.
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
TIMING DIAGRAMS
AC Test Input/Output Waveform
2.4
2.0
2.0
0.8
0.8
0.45
AC Testing : Input are driven at 2.4V for logic "1", and 0.45V for logic "0". Timing
measurements are made at 2.0V for logic "1", and 0.8V for logic "0".
RESET Timing
NOP
Instruction 1
Executed
Tdrh
TCC Input Timing
Tins
CLK
TCC
Ttcc
Fig.20 AC timing
* This specification are subject to be changed without notice.
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
FIRST RING
2 SECONDS
0.5 SEC
0.5 SEC
SECOND RING
2 SECONDS
TIP/RING
/RING TIME
/RD
Tpd
Trd
Tcdh
Tcdl
/CD
Tdoc
DATA
DATA
Tosc
OSC
POWER
3.68 MHz
Tsup
Fig.23 FSK Power Down Mode Timing Diagram
* This specification are subject to be changed without notice.
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8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
APPLICATION CIRCUIT
POWER
0.1uF
100
1000p
250V
Vdd
TIP
30k
AVDD
1000p
250V
FUSE
RING
DET1
TIP
30k
0.1u
250V
ZNR
250V
100K
K1
K2
4004
4004
K3
Vdd
4004
RING
0.1uF
VDD1
VDD2
K4
4004
270k
470k
0.1u
250V
DIAL
/PULSE
/RINGTIME
MUTE
AVSS
0.22u
30k
TEST
To Phone
VSS2
PLLC
TONE
/HKS
10n
AVSS
Xin
C1
Xout
32.768K
C2
LCD DISPLAY
Fig.24 Application Circuit
* This specification are subject to be changed without notice.
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