EMC EM78P806A

EM78P806A
8-BIT OTP MICRO-CONTROLLER
Version 1.5
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1st RD., Science-Based Industrial Park
Hsin Chu City, Taiwan, R.O.C.
TEL: (03) 5639977
FAX: (03) 5630118
Version History
Specification Revision History
Version
EM78P568
1.0
1.5
Content
Initial version
1.add osc and reset timing spec
2.add osc and reset timing figure Fig.23
3.add LCD flame rate spec
4.add typical spec. for current consumption
User Application Note
Release Date
2001/03/01
2004/07/13
EM78P806A
8-bit OTP Micro-controller
I.General Description
The EM78P806A is an 8-bit CID (Call Identification) RISC type microprocessor with low power , high speed CMOS
technology . Integrated onto a single chip are on_chip watchdog (WDT) , RAM , ROM , programmable real time clock
/counter , internal interrupt , power down mode , LCD driver , FSK decoder , DTMF receiver , Tone generator and tri-state
I/O . The EM78P806A provides a single chip solution to design a CID of calling message display .
II.Feature
CPU
•Operating voltage range : 2.5V∼5.5V
•8K×13 on chip ROM
•1.1K×8 on chip RAM
•Up to 36 bi-directional tri-state I/O ports
•8 level stack for subroutine nesting
•8-bit real time clock/counter (TCC) with 8-bit prescaler
•Two sets of 8 bit counters can be interrupt sources
•Selective signal sources and overflow interrupt
•Programmable free running on chip watchdog timer
•99.9％ single instruction cycle commands
•four modes (Main clock 3.579 , 1.79, 0.895 or 0.447MHz generated by internal PLL)
1. Sleep mode : CPU and Main clock turn off, 32.768KHz clock turn off
2. Idle mode : CPU and Main clock turn off, 32.768KHz clock turn on
3. Green mode : Main clock turn off, CPU and 32.768KHz clock turn on
4. Normal mode : Main clock turn on , CPU and 32.768KHz clock turn on
•Ring on voltage detector and low battery detector (2.5V or 3.5V)
•Input port wake up function
•9 interrupt source , 4 external , 5 internal
•100 pin QFP(EM78P806AAQ, POVD disable)(EM78P806ABQ, POVD enable) or 80 pin chip form
(EM78P806AH)
•IO Port key scan function
•IO Port interrupt , pull high ,wake-up and open drain functions
•External Sub-Clock frequency is 32.768KHz
•Dual TONE Generators
CID
•Operation Volltage 2.5 ∼5.5V for FSK
•Operation Volltage 2.5 ∼5.5V for DTMF receiver
•Bell 202 , V.23 FSK demodulator
•DTMF receiver
•Ring detector on chip
•Line energy detect
LCD
•LCD operation voltage chosen by software
•Common driver pins : 16 (8 of 16 Common shared by I/O)
•Segment driver pins : 40 (20 of 40 Segment shared by I/O)
•1/4 bias
•1/8,1/16 duty
III.Application
1. adjunct units
2. answering machines
3. feature phones
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
1
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
IV.Pin Configuration
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
SEG31/P8.7
SEG30/P8.6
SEG29/P8.5
SEG28/P8.4
SEG27/P8.3
SEG26/P8.2
SEG25/P8.1
SEG24/P8.0
SEG23/P5.7
SEG22/P5.6
SEG21/P5.5
SEG20/P5.4
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
NC
NC
NC
NC
EM78P806AQ
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
100 PIN QFP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
TEST
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
NC
NC
NC
NC
NC
AVSS
TONE
PLLC
RINGTIME
RDET1
RING
TIP
XIN
XOUT
EST
ST/GT
AVDD
COM15/P6.7
COM14/P6.6
COM13/P6.5
COM12/P6.4
COM11/P6.3
COM10/P6.2
COM9/P6.1
COM8/P6.0
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
SEG32/P9.0
SEG33/P9.1
SEG34/P9.2
SEG35/P9.3
SEG36/P9.4
SEG37/P9.5
SEG38/P9.6
SEG39/P9.7
VDD
RESET
P70/INT0
P71/INT1
P72/INT2
P73/INT3
P74
P75
P76
P77
NC
Fig.1 Pin Assignment
OTP PIN NAME
VDD
VPP
DINCK
ACLK
PGMB
OEB
DATAIN
GND
MASK ROM PIN NAME
VDD,AVDD
/RESET
P77
P76
P75
P74
P73
GND,AVSS,TEST
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
2
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
V.Functional Block Diagram
Xin Xout PLLC
ROM
WDT timer
Oscillator
timing control
prescalar
R1(TCC)
Control sleep
and wake-up
on I/O port
STACK
R2
GENERAL
RAM
Interruption
control
Instruction
register
ALU
R3
R5
Instruction
decoder
R4
ACC
DATA & CONTROL BUS
RAM
TONE
PORT6
PORT5
IOC6 R6
IOC5 R5
PORT7
PORT8
PORT9
IOC7 R7
IOC8 R8
IOC9 R9
P70~P77
P80~P87
P90~P97
LCD
DRIVER
FSK DECODER
DTMF RECEIVER
P60~P67
p54~P57
Fig.2 Block diagram
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
3
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VI.Pin Descriptions
PIN
VDD
AVDD
VSS
AVSS
Xtin
Xtout
COM0..COM7
COM8..COM15
SEG0...SEG19
SEG20..SEG23
SEG24..SEG31
SEG32..SEG39
PLLC
TIP
RING
RDET1
/RING TIME
EST
ST/GT
INT0..INT3
P5.4 ~P.57
P7.0 ~P7.7
P6.0 ~P6.7
P8.0 ~P8.7
P9.0 ~P9.7
TEST
TONE
RESET
I/O
POWER
POWER
I
O
O
O (PORT6)
O
O (PORT5)
O (PORT8)
O (PORT9)
I
I
I
I
DESCRIPTION
digital power
analog power
digital ground
analog ground
Input pin for 32.768 kHz oscillator
Output pin for 32.768 kHz oscillator
Common driver pins of LCD drivers
Segment driver pins of LCD drivers
Phase loop lock capacitor, 0.01u to 0.047u with AVSS
Should be connected with TIP side of twisted pair lines
Should be connected with RING side of twisted pair lines
Detect the energy on the twisted pair lines . These two pins coupled to
the twisted pair lines through an attenuating network.
I
Determine if the incoming ring is valid. An RC network may be
connected to the pin.
O
Early steering output. Presents a logic high immediately when the
digital algorithm detects a recognizable tone-pair (signal condition).
Any momentary loss of signal condition will cause EST to return to a
logic low.
I/O
Steering input/guard time output (bi-directional). A voltage greater than
Vtst detected at ST causes the device to register the detected tone-pair
and update the output latch.
A voltage less than Vtst frees the device to accept a new tone-pair. The
GT output acts to reset the external steering time-constant; its state is a
function of EST and the voltage on ST .
PORT7(0..3) PORT7(0)~PORT7(3) signal can be interrupt signals.
PORT5
PORT5 can be INPUT or OUTPUT port each bit.
And shared with Segment signal.
PORT7
PORT7 can be INPUT or OUTPUT port each bit.
Internal Pull high function.
Key scan function.
Bit6,7 open drain function
PORT6
PORT6 can be INPUT or OUTPUT port each bit.
And shared with Common signal.
PORT8
PORT 8 can be INPUT or OUTPUT port each bit.
And shared with Segment signal.
PORT9
PORT 9 can be INPUT or OUTPUT port each bit.
And shared with Segment signal.
Bit6,7 has wake-up function.
I
Test pin into test mode , normal low
O
Tone generator’s output
I
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
4
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VII.Functional Descriptions
VII.1 Operational Registers
1. R0 (Indirect Addressing Register)
* R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as
register actually accesses data pointed by the RAM Select Register (R4).
2. R1 (TCC)
* Increased by an external signal edge applied to TCC , or by the instruction cycle clock.
Written and read by the program as any other register.
3. R2 (Program Counter)
* The structure is depicted in Fig. 4.
* Generates 8K × 13 on-chip ROM addresses to the relative programming instruction codes.
* "JMP" instruction allows the direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
* "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are
cleared to "0''.
* "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
* "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The
most significant bit (A10~A12) will be loaded with the content of bit PS0~PS2 in the status register (R5) upon the
execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
CALL
PC
A12 A11 A10
A9 A8
A7~A0
000 PAGE0 0000~03FF
001 PAGE1 0400~07FF
RET
RETL
RETI
010 PAGE3 0800~0BFF
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
110 PAGE6 1800~1BFF
111 PAGE7 1C00~1FFF
Fig.4 Program counter organization
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
5
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
ADDRESS
REGISTER
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R0
R1(TCC)
R2(PC)
R3(STATUS)
R4(RSR)
R5
R6(PORT6)
R7(PORT7)
R8(PORT8)
R9(PORT9)
RA
RB
RC
RD
RE
RF(Interrupt Flag)
10
:
1F
16X8
COMMON
REGISTER
20
:
3F
BANK0 ~ ~ ~BANK3
32X8 ~ ~ ~32X8
REGISTER
CONTROL REGISTER
(PAGE0)
CONTROL REGISTER
(PAGE1)
page0
IOC5
IOC6(PORT6 control)
IOC7(PORT7 control)
IOC8(PORT8 control)
IOC9(PORT9 control)
IOCA
IOCB
IOCC
IOCD
IOCE
IOCF(Interrupt Mask)
page1
IOCB(COUNTER1)
IOCC(COUNTER2)
IOCD
IOCE
RC(ADDRESS) RD(DATA)
IOCB(ADDRESS) IOCC(DATA)
0
BANK1 BANK2
:
256X8 256X8
255
General RAM
LCD RAM
Fig.5 Data memory configuration
4. R3 (Status Register)
7
6
5
4
3
2
1
0
PAGE
P_TONE2 P_TONE1
T
P
Z
DC
C
* Bit 0 (C) Carry flag
* Bit 1 (DC) Auxiliary carry flag
* Bit 2 (Z) Zero flag
* Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP"
command.
* Bit 4 (T) Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT
timeout.
EVENT
T
P
WDT wake up from
0
0
REMARK
sleep mode
WDT time out (not sleep mode
0
1
/RESET wake up from sleep
1
0
power up
1
1
Low pulse on /RESET
x
x
x .. don't care
*Bit5: Power control bit of Tone generator 1 . User can use this bit to power on the tone generator.
*Bit6: Power control bit of Tone generator 2 . User can use this bit to power on the tone generator.
Tone frequency controlled by IOCD and IOCE.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
6
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
R3(6,5)
Tone generator2
Tone generator1
00
Power off
Power off
01
Power off
Power on
10
Power on
Power off
11
Power on
Power on
* Bit 7 PAGE : change IOCB ~ IOCE to another page , 0/1 => page0 / page1
5. R4 (RAM Select Register)
* Bits 0 ~ 5 are used to select up to 64 registers in the indirect addressing mode.
* Bits 6 ~ 7 determine which bank is activated among the 4 banks.
* See the configuration of the data memory in Fig. 5.
6. R5 (Program Page Select Register)
7
6
5
4
3
2
1
0
R57
R56
R55
R54
PWDN
PS2
PS1
PS0
* Bit 0 (PS0) ~ Bit2 (PS2) Page select bits should be set before JMP or CALL instruction.
Page select bits
PS2
PS1
PS0
Program memory page (Address)
0
0
0
Page 0
0
0
1
Page 1
0
1
0
Page 2
0
1
1
Page 3
1
0
0
Page 4
1
0
1
Page 5
1
1
0
Page 6
1
1
1
Page 7
User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user
can use far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program
page is maintained by EMC's complier. It will change user's program by inserting instructions within program.
*Bit3 : PWDN : DTMF receiver circuit power control signal. Be sure open main clock before using DTMF receiver
circuit . A logic low applied to PWDN will shut down power of the device to minimize the power consumption in
a standby mode. It stops functions of the filters.
0/1= power down/ power up
*Bit4 ~7: 4-bit I/O registers.
6. R6 ~ R9 (Port 6 ~ Port 9)
* Four 8-bit I/O registers.
7. RA (FSK Status Register)(bit 0,1,2,4 read only)
7
6
5
4
3
2
1
0
IDLE
/358E CLK2
CLK1
/FSKPWR
DATA
/CD
/RD
* Bit0 (Read Only) (Ring detect signal) 0/1 : Ring Valid/Ring Invalid
* Bit1(Read Only)(Carrier detect signal)
0/1 : Carrier Valid/Carrier Invalid
* Bit2(Read Only)(FSK demodulator output signal)
Fsk data transmitted in a baud rate 1200 Hz. Data from FSK demodulator when /CD is low.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
7
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
* Bit3(read/write)(FSK block power up signal) FSK controlled by software totally.
1/0 : FSK demodulator block power up/FSK demodulator power down
* The relation between Bit0 to Bit3 is shown in Fig.6.
SLEEP MODE
Begin
set /FSKPWR='0'
/RINGTIME ='0'
or external keys
pressed
sleep mode
No
/RD and /CD ='1'
/RD and /CD ='1' and
nothing to do for 30
sec , /FSKPWR='0'
/FSKPWR='1'
FSK decoder
begin its work
/RINGTIME ='0'
or external keys
pressed
Yes
WAKE UP MODE
8-bit wake up and　set /FSKPWR='1'
accept data from
FSK decoder
wake up
mode
DATA transfer
to Micro
Yes
/RD and /CD ='1'
data end and 30
sec nothing to do.
No
Flow Diagram between 8-bit
and FSK decoder
STATE Diagram between 8-bit
and FSK decoder
Fig.6 The relation between Bit0 to Bit3.
* Bit4~ Bit5: MAIN clock selection bits.
User can choose the main clock by CLK1 and CLK2. All the clock is list below.
CLK2, CLK1
MAIN clock
/358E
CPU’s clock
0,0
3.579/8MHz
1
3.579/8MHz
0,1
3.579/4MHz
1
3.579/4MHz
1,0
3.579/2MHz
1
3.579/2MHz
1,1
3.579MHz
1
3.579MHz
0,0
X
0
32768HZ
0,1
X
0
32768HZ
1,0
X
0
32768HZ
1,1
X
0
32768HZ
* Bit6(read/write)(PLL enable signal)
0/1=DISABLE/ENABLE
The relation between 32.768kHz and PLL can see Fig.7.
PLL
MAIN CLOCK
32768Hz
0.459MHz
0.919MHz
1.839MHz
3.579MHz
/358E CLK1 CLK2
SUB-CLOCK
Fig.7 The relation between 32.768kHz and PLL .
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
8
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
* Bit7 IDLE: sleep mode selection bit
0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go.
These two modes can be waken up by TCC clock or Watch Dog or PORT9 and run from “SLEP” next instruction.
Wakeup signal
IDLE mode
GREEN mode
NORMAL mode
RA(7,6)=(1,0)
RA(7,6)=(x,0)
RA(7,6)=(x,1)
+ SLEP
no SLEP
no SLEP
TCC time out
Wake-up
Interrupt
Interrupt
+ Interrupt
+ Next instruction
WDT time out
RESET
Wake-up
RESET
RESET
+ Next instruction
Port96,97
RESET
Wake-up
X
X
/RINGTIME pin
+ Next instruction
PORT70~73
RESET
Wake-up
Interrupt
Interrupt
+ Interrupt
+ Next instruction
*P70 ~ P73 's wakeup function is controlled by IOCF(1,2,3) and ENI instruction.
*P70 's wakeup signal is a rising or falling signal defined by CONT REGISTER bit7.
*/RINGTIME pin , Port96,Port97 ,Port71,Port72 and Port73 's wakeup signal is a falling edge signal.
8.
SLEEP mode
RA(7,6)=(0,0)
+ SLEP
X
RB
7
P8SH
6
P8SL
5
TDP2
4
TDP1
3
LOW_BAT
2
CALL_2/RANGE
1
/LPD
0
CALL_1
Bit0(CALL_1) : CALLER ID RAM selection bit
*Bit1(/LPD): Low battery detect disable/enable, 0/1= disable/enable
*Bit2(CALL_2/RANGE) : CALLER ID RAM selection / low power detect voltage range
ps. When code option bit2(CIDEN) is “1”, extra CID RAM can be selected and RB bit2 is CALL_2.
User cannot use SDT function. At this mode, (Bit2,Bit0)=(CALL_2,CALL_1) can be set "00" to "11"
for four blocks of CALLER ID RAM area. User can use 1.0K RAM with RC ram address. Also low
voltage detect voltage is fixed at 2.5V
When code option bit2(CID) is “0”, low power detect voltage range can be selected and RB bit2 is
RANGE. At this mode, setting RANGE = 0/1 = 2.5V/3.5V
*Bit3(LOW_BAT):Low battery signal, 0/1 = battery voltage is low/normal.
VDD
/LPD
RANGE
LOW_BAT
VDD>3.7V
1
1
1
VDD<3.5V
1
1
0
VDD>2.7V
1
0
1
VDD<2.5V
1
0
0
Any
0
X
X
* Bit 5 ~ 4:Tone detection present time setup.
TDP2,TDP1
Tdp
0,0
20 ms
0,1
15 ms
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
9
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
1,0
10 ms
1,1
5 ms
*Bit6: port8 low nibble switch, 0/1= normal I/O port/SEGMENT output .
*Bit7: port8 high nibble switch , 0/1= normal I/O port/SEGMENT output
9.
RC
7
6
5
4
3
2
CIDA7 CIDA6 CIDA5 CIDA4 CIDA3 CIDA2
* Bit 0 ~ Bit 7 select CALLER ID RAM address up to 256.
10.
1
CIDA1
0
CIDA0
RD
* Bit 0 ~ Bit 8 are CALLER ID RAM data transfer register.
User can see RB(0) register how to select CID RAM banks.
11.
RE
7
6
5
4
3
2
1
0
STD
/WDTE /WUP97 /WUP96 /WURING LCD_C2 LCD_C1 LCD_M
* Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency.
* Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking. change the display duty must set the
"LCD_C2,LCD_C1" to "00".
LCD_C2,LCD_C1 LCD Display Control
LCD_M duty
bias
0 0
Change duty
0
1/16
1/4
Disable(turn off LCD)
1
1/8
1/4
0 1
Blanking
:
:
1 1
LCD display enable
:
:
* Bit3 (/WURING, RING Wake Up Enable): used to enable the wake-up function of /RINGTIME input pin.
(1/0=enable/disable)
* Bit4 (/WUP96, PORT9 bit6 Wake Up Enable): used to enable the wake-up function of PORT9 bit6 .
(1/0=enable/disable)
* Bit5 (/WUP97, PORT9 bit7 Wake Up Enable): used to enable the wake-up function of PORT9 bit7 .
(1/0=enable/disable)
* Bit6 (/WDTE,Watch Dog Timer Enable)
Control bit used to enable Watchdog timer.
(1/0=enable/disable)
* Bit7:STD: Delayed steering output. Presents a logic high when a received tone-pair has been registered and
the output latch updated; returns to logic low when the voltage on St/GT falls below V tst.
(0/1= No DATA/DATA Valid )
/WURING
/RINGTIME
/WUP96
PORT96
/WDTEN 0/1=enable/disable
/WUP97
PORT97
/WDTE
Fig.8 Wake up function and control signal
12. RF (Interrupt Status Register)
7
6
/STD
FSKDATA
5
C8_2
4
C8_1
3
INT2/INT3
2
1
INT1 INT0
0
TCIF
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
10
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
* "1" means interrupt request, "0" means non-interrupt
* Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows .
* Bit 1 (INT0) external INT0 pin interrupt flag .
* Bit 2 (INT1) external INT1 pin interrupt flag .
* Bit 3 (INT2/INT3) external INT2 and INT3 pin interrupt flag .
* Bit 4 (C8_1) internal 8 bit counter interrupt flag .
* Bit 5 (C8_2) internal 8 bit counter interrupt flag .
* Bit 6 ( FSKDATA ) FSK data interrupt flag
* Bit 7 (/STD) The inverse signal of DTMF receiver data ready STD interrupt flag.
* High to low edge trigger , Refer to the Interrupt subsection. (INT0 can be triggered by low to high signal , refer to
CONT bit 7)
* IOCF is the interrupt mask register. User can read and clear.
13. R10~R3F (General Purpose Register)
* R10~R3F (Banks 0~3) all are general purpose registers.
VII.2 Special Purpose Registers
1. A (Accumulator)
* Internal data transfer, or instruction operand holding
* It's not an addressable register.
2. CONT (Control Register)
7
6
5
4
3
2
1
0
INT_EDGE INT
TS
PAB PSR2 PSR1 PSR0
* Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
* Bit 3 (PAB) Prescaler assignment bit.
0/1 : TCC/WDT
* Bit 4 unused
* Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: 16.38KHz
* Bit 6 : (INT)INT enable flag
0: interrupt masked by DISI or hardware interrupt
1: interrupt enabled by ENI/RETI instructions
* Bit 7 : INT_EDGE
0:P70 's interruption source is a rising edge signal.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
11
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
1:P70 's interruption source is a falling edge signal.
* CONT register is readable and writable.
3. IOC5
7
6
5
4
3
2
1
0
IOC54
IOC54
IOC54
IOC54
Q4
Q3
Q2
Q1
*Bit0 ~ Bit3 : Q4~Q1: DTMF receiver data . To provide the code corresponding to the last valid tone-pair
received (see code table). STD signal in RE Delayed steering output. Presents a logic high when a
received tone-pair has been registered and the Q4~Q1 output latch updated and generate a interruption
(IOCF has enabled); returns to logic low when the voltage on ST/GT falls below Vtst.
F low
F high
Key
PWDN
Q4~Q1
697
1209
1
1
0001
697
1336
2
1
0010
697
1477
3
1
0011
770
1209
4
1
0100
770
1336
5
1
0101
770
1477
6
1
0110
852
1209
7
1
0111
852
1336
8
1
1000
852
1477
9
1
1001
941
1209
0
1
1010
941
1336
*
1
1011
941
1477
#
1
1100
697
1633
A
1
1101
770
1633
B
1
1110
852
1633
C
1
1111
941
1633
D
1
0000
Any
Any
Any
0
XXXX (x:unknown)
*Bit4~Bit7: I/O direction control registers of PORT5.
* "1" put the relative I/O pin into high impedance (input port), while "0" put the relative I/O pin as output.
4. IOC6 ~ IOC9 (I/O Port Control Register)
* Four I/O direction control registers.
* "1" put the relative I/O pin into high impedance (input port), while "0" put the relative I/O pin as output.
5.
IOCA
7
6
5
4
3
2
1
0
P9SH P9SL
P6S
P5S
Bias3 Bias2
Bias1
SC
* Bit 0 :SC (SCAN KEY signal ) 0/1 = disable/enable. Once you enable this bit , all of the LCD signal will have a
low pulse during a common period. This pulse has 30us width. Please use the procedure to implement the key
scan function.
a.
set port7 as input port
b.
set IOCD page0 port7 pull high
c.
enable scan key signal
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
d.
Once push a key . Set RA(6)=1 and switch to normal mode.
e.
Blank LCD. Disable scan key signal.
f.Set P6S =0. Port6 sent probe signal to port7 and read port7. Get the key.
g.
Note!! A probe signal should be delay a instruction at least to another probe signal.
h.
Set P6S =1. Port6 as LCD signal. Enable LCD.
i.
KEY5
KEY1
vdd
v1
v2
v3
vlcd
Gnd
com2
P63
KEY2
P62
KEY3
vdd
v1
v2
v3
vlcd
Gnd
seg
P61
KEY4
P60
P73
P72
P71
P70
30us
Fig.9 Key scan circuit
*
Bit 3~1 (Bias3~Bias1) Control bits used to choose LCD operation voltage .
LCD operate voltage Vop (VDD 5V)
VDD=5V
3.0V
000
0.60VDD
3.3V
001
0.66VDD
0.74VDD
3.7V
010
0.82VDD
4.0V
011
100
0.87VDD
4.4V
101
0.93VDD
4.7V
4.8V
110
0.96VDD
5.0V
111
1.00VDD
* Bit4: port5 nibble switch, 0/1= normal I/O port/SEGMENT output .
* Bit5:port6 switch , 0/1= normal I/O port/COMMON output
* Bit6:port9 low nibble switch , 0/1= normal I/O port/SEGMENT output . Bit7:port9 high nibble switch
6. IOCB (LCD ADDRESS)
PAGE0 : Bit6 ~ Bit0 = LCDA6 ~ LCDA0
The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below:
COM15 ~ COM8
COM7 ~ COM0
40H (Bit15 ~ Bit8)
00H (Bit7 ~ Bit0)
SEG0
41H
01H
SEG1
:
:
:
67H
27H
SEG39
:
:
Empty
7FH
3FH
Empty
PAGE1 : 8 bit up-counter (COUNTER1) preset and read out register . ( write = preset ) . After a interruption , it
will count from “00”.
7. IOCC (LCD DATA)
PAGE0 : Bit7 ~ Bit0 = LCD RAM data register
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
13
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
PAGE1 : 8 bit up-counter (COUNTER2) preset and read out register . ( write = preset) After a interruption , it will
count from “00”.
8. IOCD
PAGE0 :
7
6
5
4
3
2
1
0
T17
T16
T15
T14
T13
T12
T11
T10
Tone generator 1 ‘s frequency divider. Please Run in Normal mode .
Clock source = 111843Hz
T17~T10 = ‘11111111’ => Tone generator1 will has 438Hz SIN wave output.
:
T17~T10 = ‘00000010’ => Tone generator1 will has 55921Hz SIN wave output.
T17~T10 = ‘00000001’ => Tone generator1 will has 111843Hz
T17~T10 = ‘00000000’ => no used
PAGE1:
7
6
5
4
3
2
1
0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
* Bit 0 ~ 7 (/PH#) Control bit used to enable the pull-high of PORT7(#) pin.
1: Enable internal pull-high
0: Disable internal pull-high
9. IOCE
PAGE0 :
7
6
5
4
3
2
1
0
T27
T26
T25
T24
T23
T22
T21
T20
Tone generator 2 ‘s frequency divider. Please Run in Normal mode.
Clock source = 111843Hz
T27~T20 = ‘11111111’ => Tone generator1 will has 438Hz SIN wave output.
:
T27~T20 = ‘00000010’ => Tone generator1 will has 55921Hz SIN wave output.
T27~T20 = ‘00000001’ => Tone generator1 will has 111843Hz SIN wave output.
T27~T20 = ‘00000000’ => no used
TONE1(IOCD)
ROW FREQ.
(0xA0)
699.02Hz
1
2
3
(0x91)
771.33Hz
4
5
6
(0X83)
853.76Hz
7
8
9
(0X77)
939.86Hz
*
0
#
1202.6 (0X5D)
1331.5(0X54)
1471.7(0X4C)
TONE2(IOCE)
A
B
C
D
1644.8(0X44)
PAGE1 :
7
6
5
4
3
2
1
0
OP77 OP76
C2S
C1S
PSC2 PSC1
PSC0
CDRD
* Bit0: cooked data or raw data select bit , 0/1 ==> cooked data/raw data
* Bit3~Bit1: counter1 prescaler , reset=(0,0.0)
(PSC2,PSC1,PSC0)
0,0,0
0,0,1
0,1,0
0,1,1
1,0,0
Scaler
1:1
1:2
1:4
1:8
1:16
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
14
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
1,0,1
1:32
1,1,0
1:64
1,1,1
1:128
* Bit4:counter1 source , (0/1)=(32768Hz/MAIN clock if enable)
* Bit5:counter2 source , (0/1)=(32768Hz/MAIN clock if enable)
* Bit6:P76 opendrain control (0/1)=(disable/enable)
* Bit7:P77 opendrain control (0/1)=(disable/enable)
10. IOCF (Interrupt Mask Register)
7
6
/STD
FSKDATA
5
C8_2
4
C8_1
3
INT2/INT3
scale=1:1
2
INT1
1
INT0
0
TCIF
* Bit 0 ~ 7 interrupt enable bit.
0: disable interrupt
1: enable interrupt
* IOCF Register is readable and writable.
VII.3
TCC/WDT Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT
only at the same time.
• An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register.
• See the prescaler ratio in CONT register.
• Fig. 10 depicts the circuit diagram of TCC/WDT.
• Both TCC and prescaler will be cleared by instructions which write to TCC each time.
• The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
• The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
16.38KHz
Fig.10 Block diagram of TCC WDT
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
15
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VII.4 I/O Ports
The I/O registers, Port5 ~ Port 9, are bi-directional tri-state I/O ports. Port 7 can be pulled-high internally by software control.
The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC6 ~ IOC9 ) under program control.
The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.11.
Fig.11 The circuit of I/O port and I/O control register
VII.5 RESET and Wake-up
The RESET can be caused by
(1) Power on reset, or Voltage detector
(2) WDT timeout. (if enabled and in GREEN or NORMAL mode)
Note that only Power on reset, or only Voltage detector in Case(1) is enabled in the system by CODE Option bit. If Voltage
detector is disabled, Power on reset is selected in Case (1). Refer to Fig. 12.
Fig.12 Block diagram of Reset of controller
Once the RESET occurs, the following functions are performed.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all "0".
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
16
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
•
•
•
•
•
When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
The Watchdog timer and prescaler are cleared.
The Watchdog timer is disabled.
The CONT register is set to all "1"
The other register (bit7..bit0)
R5 = “xxxx0000”
IOC5 = “1111xxxx”
R6 = PORT
IOC6 = "11111111"
R7 = PORT
IOC7 = "11111111"
R8 = PORT
IOC8 = "11111111"
R9 = PORT
IOC9 = "11111111"
RA = "00000xxx
IOCA = "00000000"
RB = "00000000"
Page0 IOCB = "00000000" Page1 IOCB = "00000000"
RC = "00000000"
Page0 IOCC = "0xxxxxxx" Page1 IOCC = "00000000"
RD = "xxxxxxxx"
Page0 IOCD = "00000000" Page1 IOCD = "00000000"
RE = "x0000000"
Page0 IOCE = "00000000" Page1 IOCE = "00000000"
RF = "00000000"
IOCF = "00000000"
The controller can be awakened from SLEEP mode or IDLE mode (execution of "SLEP" instruction, named as
SLEEP MODE or IDLE mode) by (1)TCC time out (IDLE mode only) (2) WDT time-out (if enabled) or, (3) external
input at PORT9 (4)RINGTIME pin. The four cases will cause the controller wake up and run from next instruction in
IDLE mode , reset in SLEEP mode . After wake-up , user should control WATCH DOG in case of reset in GREEN
mode or NORMAL mode. The last three should be open RE register before into SLEEP mode or IDLE mode . The
first one case will set a flag in RF bit0 . And it will go to address 0x08 when TCC generate a interrupt .
VII.6 Interrupt
The CALLER ID IC has internal interrupts which are falling edge triggered, as followed : TCC timer overflow
interrupt (internal) , two 8-bit counters overflow interrupt .
If these interrupt sources change signal from high to low , then RF register will generate '1' flag to corresponding
register if you enable IOCF register.
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask register.
Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled)
generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine the source
of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared in
software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
There are four external interrupt pins including INT0 , INT1 , INT2 , INT3 . And four internal counter interrupt
available.
External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT7 bit0 to bit3 . If IOCF is enable then these
signal will cause interrupt , or these signals will be treated as general input data .
After reset, the next instruction will be fetched from address 000H and the instruction inturrept is 001H and the
hardware inturrept is 008H.
TCC will go to address 0x08 in GREEN mode or NORMAL mode after time out. And it will run next instruction
from “SLEP” instruction and then go to address 0x08 in IDLE mode . These two cases will set a RF flag.
VII.7 Instruction Set
Instruction set has the following features:
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
17
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
The symbol "R" represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the
selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'',
affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
HEX
0
0
0
0
0
0
0
0
0
0
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0011
0100
rrrr
0000
0001
0010
0011
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 0010 0000
0014
001r
0020
CONTR
IOR R
TBL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
06rr
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
RRCA R
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0110
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
MNEMONIC
01rr rrrr
1000 0000
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
01rr rrrr
10rr rrrr
11rr rrrr
00rr rrrr
0 0110 01rr
rrrr
06rr
RRC R
0 0110 10rr
rrrr
06rr
RLCA R
OPERATION
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2 bits 9,10 do not
clear
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ VR → A
A ∨ VR → R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1)
R(0) → C, C → A(7)
R(n) → R(n-1)
R(0) → C, C → R(7)
R(n) → A(n+1)
R(7) → C, C → A(0)
STATUS
AFFECTE
D
None
C
None
T,P
T,P
None
None
None
None
None
None
None
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
18
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
0 0110 11rr
rrrr
06rr
RLC R
0 0111 00rr
rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
1
0111
0111
0111
100b
101b
110b
111b
00kk
01rr rrrr
10rr rrrr
11rr rrrr
bbrr rrrr
bbrr rrrr
bbrr rrrr
bbrr rrrr
kkkk kkkk
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
1
1
1
1
1
1
1
1
01kk
1000
1001
1010
1011
1100
1101
1110
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
0001
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E01
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
1 1110 1000 0kkk
1 1111 kkkk kkkk
1E8k
1Fkk
PAGE k
ADD A,k
R(n) → R(n+1)
R(7) → C, C → R(0)
R(0-3) → A(4-7)
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP]
(Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP]
001H → PC
K->R5
k+A → A
C
None
None
None
None
None
None
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
None
None
Z,C,DC
VII.8 Option
VII.8.1 CODE Option Register
The CALLER ID IC has one CODE option register which is not part of the normal program memory. The option
bits cannot be accessed during normal program execution.
7
-
6
-
5
-
4
-
3
CIDEN
2
DTREN
1
FSKEN
0
/PROT
* Bit 0(/PROT) : protection bit
0/1 Î enable/disable protection
* Bit 1(FSKEN) : FSK circuit enable bit
0/1 Î disable/enable FSK circuit
* Bit 2(DTREN) : DTMF receiver circuit enable bit
0/1 Î disable/enable DTMF receiver circuit
* Bit 3(CIDEN) : extra CALLER ID enable bit
0 : disable Î User can only select 0.5k CALLER ID RAM by setting RB bit0(CALL_0) but low voltage
detection range can be selected 2.5V/3.5V by RB bit2(RANGE).
1 : enable ÎUser can select up to 1k CALLER ID RAM by setting RB bit2(CALL_2) and bit0(CAL_1) but
low voltage detection range is fixed at 2.5V.
* Bit 4 ~ Bit 7 : unused, must be "0"s.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
19
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VII.8.2 PAD Option
/POVD(power on voltage detect) reset can be enabled/disabled by PAD Option. This POVD pad is not shown on
the pin assignment. Internally or externally connecting this pad to GND/VDD to enable/disable /POVD reset.
/POVD
2.2V /POVD
reset
1.8V power on
reset
1
0
No
yes
yes
yes
Low power
detect without
reset
Yes
Yes
Low power detect sleep mode
current
Yes
yes
1uA
15uA
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
20
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VII.9 FSK FUNCTION
VII.8.1 Functional Block Diagram
Tip
Ring
Ring det1
/Ring Time
Band Pass
Filter
Ring
Det
Circuit
FSK
demodul
Data Valid
Energy Det
Circuit
Power
Up
/FSKPWR
DATA OUT
/CD
/RD
OSC in
OSC out
CLOCK
Fig.13 FSK Block Diagram
VII.8.2 Function Descriptions
The CALLER ID IC is a CMOS device designed to support the Caller Number Deliver feature which is offered by
the Regional Bell Operating Companies.The FSK block comprises two paths: the signal path and the ring indicator path. The
signal path consist of an input differential buffer,a band pass filter, an FSK demodulator and a data valid with carrier detect
circuit. The ring detector path includes a clock generator, a ring detect circuit .
In a typical application, the ring detector maintains the line continuously while all other functions of the chip are
inhibited. If a ring signal is sent, the /RINGTIME pin will has a low signal. User can use this signal to wake up whole chip or
read /RD signal from RA register.
A /FSKPWR input is provided to activate the block regardless of the presence of a power ring signal. If /FSKPWR
is sent low, the FSK block will power down whenever it detects a valid ring signal, it will power on when /FSKPWR is high.
The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this
signal to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends it to a post
filter. The output data is then made available at DATA OUT pin. This data, as sent by the central office, includes the header
information (alternate "1" and "0") and 150 ms of marking which precedes the date , time and calling number. If no data is
present, the DATA OUT pin is held in a high state. This is accomplished by an carrier detect circuit which determines if the
in-band energy is high enough. If the incoming signal is valid and thus the demodulated data is transferred to DATA OUT
pin . If it is not, then the FSK demodulator is blocked.
VII.8.3 Ring detect circuit
When Vdd is applied to the circuit, the RC network will charge cap C1 to Vdd holding /RING TIME off . The
resistor network R2 to R3 attenuates the incoming power ring applied to the top of R2. The values given have been chosen to
provide a sufficient voltage at DET1 pin, to turn on the Schmitt trigger input. When Vt+ of the Schmitt is exceeded, cap C1
will discharge.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
21
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
The value of R1 and C1 must be chosen to hold the /RING TIME pin voltage below the Vt+ of the Schmitt between
the individual cycle of the power ring. With /RINGTIME enabled, this signal will be a /RD signal in RA throught a buffer.
/Ring Time
R1
/Ring Time
C1
R2
/RD
Vdd
Det1
R3
Fig.14 ring detect circuit
VII.9 DTMF Receiver
High
group
filter
+
-
Zero
crossing
Detectors
Dial
tone
filter
Digital
Detection
Algorithm
Low
group
filter
Code
converter
and latch
Q4~Q1
Zero
crossing
Detectors
STD
Steering
logic
PWDN
CLK
POWER
CONTROL
VDD
ST/GT
EST
Fig.15 DTMF receiver function Block diagram
The DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a band
split filter section, which separates the high and low tones of receiver pair, followed by a digital counting section which
verifies the frequency and duration of the received tones before passing the corresponding code to the output bus.
FILTER SECTION
Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two
filters a sixth order for the high group and an eighth order for the low group. The bandwidths of which correspond to the
bands enclosing the low-group and high-group tones . The filter section also in corporate notches at 350Hz and 440 Hz for
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
22
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
exceptional dial-tone rejection. Each filter output is followed by a second-order switched-capacitor section which smooth the
signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent
detection of unwanted low-level signals and noise; the outputs of the comparators provide full-rail logic swings at the
frequencies of the incoming tones.
F low
F high
Key
PWDN
Q4~Q1
697
1209
1
1
0001
697
1336
2
1
0010
697
1477
3
1
0011
770
1209
4
1
0100
770
1336
5
1
0101
770
1477
6
1
0110
852
1209
7
1
0111
852
1336
8
1
1000
852
1477
9
1
1001
941
1209
0
1
1010
941
1336
*
1
1011
941
1477
#
1
1100
697
1633
A
1
1101
770
1633
B
1
1110
852
1633
C
1
1111
941
1633
D
1
0000
Any
Any
Any
0
XXXX (x:unknown)
Decoder Section
The decoder used digital counting techniques to determine the frequencies of the limited tones and to verify that they
correspond to standard DTMF frequencies. A complex averaging algorithm(protects) against tone simulation by extraneous
signals, such as voice, while providing tolerance to small frequency deviations and variations. This averaging algorithm has
been developed to ensure an optimum combination of immunity to talk-off? and tolerance to the presence
of interfering signals (third tones? and noise. When the detector recognizes the simultaneous presence of two valid tones
(referred to as signal condition? in some industry specifications), it raises the early steering flag (EST). Any subsequent loss
of signal condition will cause EST to fall.
Before registration of a decoded tone-pair, the receiver checks for a valid signal duration (referred to as character
recognition-condition?. This check is per-formed by an external RC time-constant driven by EST. A logic high on EST
causes VC to rise as the capacitor discharges. Provided signal-condition is maintained (EST remains high) for the validation
period , VC reaches the threshold (V tst ) of the steering logic to register the tone-pair, latching its corresponding 4-bit code
into the output latch.
At this point, the GT output is activated and drives VC to VDD . GT continues to drive high as long as EST remains
high. Finally after a short delay to allow the output latch to settle, the delayed-steering? output flag, STD, goes high,
signaling that a received tone-pair has been registered. The contents of the output latch are made available on the 4-bit output
register .
The steering circuit works in reverse to validate the inter digit pauses between signals. Thus, as well as rejecting signals
too short to be considered valid, the receiver will tolerate signal interruptions (drop-out? too short to be considered a valid
pause. The facility, together with the capability of selecting the steering time-constants externally, allows the designer to
tailor performance to meet a wide variety of system requirements.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
23
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
Guard Time Adjustment
VDD
VDD
C
ST/GT
EST
R
Fig.16 Guard Time
In many situations not requiring independent selection of receive and pause, the simple steering circuit of is applicable.
Component values are chosen according to the following formulae:
t REC = t DP + t GTP t ID = t DA + t GTA
The value of t DP is a parameter of the device and t REC is the minimum signal duration to be recognized by the
receiver. A value for C of 0.1 uF is recommended for most applications, leaving R to be selected by the designer. For
example, a suitable value of R for a t REC of 30mS would be 300k.
Different steering arrangements may be used to select independently the guard-times for tone-present (t GTP ) and toneabsent (t GTA ). This may be necessary to meet system specifications which place both accept and reject limits on both tone
duration and inter digital pause.
Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity.
Increasing t REC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain
signal condition for long enough to be registered. On the other hand, a relatively short t REC with a long t DO would be
appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be required.
VII.10 LCD Driver
The CALLER ID IC can drive LCD directly and has 60 segments and 16 commons that can drive 60*16 dots
totally. LCD block is made up of LCD driver , display RAM, segment output pins , common output pins and LCD operating
power supply pins.
Duty , bias , the number of segment , the number of common and frame frequency are determined by LCD mode
register . LCD control register.
The basic structure contains a timing control which uses the basic frequency 32.768KHz to generate the proper
timing for different duty and display access. RE register is a command register for LCD driver, the LCD display( disable,
enable, blanking) is controlled by LCD_C and the driving duty and bias is decided by LCD_M and the display data is stored
in data RAM which address and data access controlled by registers RC and RD.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
24
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
32.768KHz
RC(address)
RD(data)
LCD timing control
RE(LCD_C,LCD_M)
RAM
LCD duty control
Display data control
Bias control
Vdd-Vlcd
LCD commom control
COM
LCD SEGMENT control
SEG
Fig.17 LCD DRIVER CONTROL
VII.10.1 LCD Driver Control
1. RE(LCD Driver Control)(initial state "00000000")
7
6
5
4
3
2
1
0
LCD_C2 LCD_C1 LCD_M
*Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency.
*Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking. change the display duty must set the
LCD_C to "00".
LCD_C2,LCD_C1 LCD Display Control
LCD_M duty
bias
0 0
change duty
0
1/16
1/4
Disable(turn off LCD)
1
1/8
1/4
0 1
Blanking
:
:
1 1
LCD display enable
:
:
VII.10.2
LCD display area
The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below:
COM15 ~ COM8
40H (Bit15 ~ Bit8)
41H
:
:
67H
:
7DH
7EH
7FH
COM7 ~ COM0
00H (Bit7 ~ Bit0)
01H
:
:
27H
:
3DH
3EH
3FH
SEG0
SEG1
:
:
SEG39
empty
empty
empty
empty
*IOCB(LCD Display RAM address)
7
6
5
4
3
2
1
0
LCDA6 LCDA5 LCDA4 LCDA3 LCDA2 LCDA1 LCDA0
Bit 0 ~ Bit 6 select LCD Display RAM address up to 127.
LCD RAM can be write whether in enable or disable mode and read only in disable mode.
*IOCC(LCD Display data) : Bit 0 ~ Bit 8 are LCD data.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
25
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VII.10.3
LCD COM and SEG signal
* COM signal : The number of COM pins varies according to the duty cycle used, as following: in 1/8 duty mode COM8 ~
COM15 must be open. in 1/16 duty mode COM0 ~ COM15 pins must be used.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 .. COM15
1/8
o
o
o
o
o
o
o
o
x
..
x
1/16
o
o
o
o
o
o
o
o
o
..
o
x:open,o:select
* SEG signal: The 60 segment signal pins are connected to the corresponding display RAM address 00h to 3Bh. The high
byte and the low byte bit7 down to bit0 are correlated to COM15 to COM0 respectively .
When a bit of display RAM is 1, a select signal is sent to the corresponding segment pin, and when the bit is 0 , a non-select
signal is sent to the corresponding segment pin.
frame
vdd
v1
v2
v3
vlcd
com0
vdd
v1
v2
v3
vlcd
com1
vdd
v1
v2
v3
vlcd
com2
vdd
v1
v2
v3
vlcd
seg
dark
vdd
v1
v2
v3
vlcd
seg
light
*COM, SEG and Select/Non-select signal is shown as following:
Fig.18 Lcd wave 1/4 bias , 1/8 duty
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
26
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
frame
vdd
v1
v2
v3
vlcd
com0
vdd
v1
v2
v3
vlcd
com1
vdd
v1
v2
v3
vlcd
com2
vdd
v1
v2
v3
vlcd
seg
dark
vdd
v1
v2
v3
vlcd
seg
light
Fig.19 Lcd wave 1/4 bias , 1/16 duty
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
27
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VIII.Absolute Operation Maximum Ratings
RATING
DC SUPPLY VOLTAGE
INPUT VOLTAGE
OPERATING TEMPERATURE RANGE
SYMBOL
Vdd
Vin
Ta
VALUE
-0.3 To 6
-0.5 TO Vdd +0.5
0 TO 70
UNIT
V
V
℃
IX DC Electrical Characteristic
(Ta=0°C ~ 70°C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Condition
IIL1
Input Leakage Current for
VIN = VDD, VSS
input pins
IIL2
Input Leakage Current for
VIN = VDD, VSS
bi-directional pins
VIH
Input High Voltage
VIL
Input Low Voltage
VIHT
Input High Threshold
/RESET, TCC, RDET1
Voltage
VILT
Input Low Threshold
/RESET, TCC,RDET1
Voltage
VIHX
Clock Input High Voltage
OSCI
VILX
Clock Input Low Voltage
OSCI
VHscan Key scan Input High Voltage Port6 for key scan
VLscan
Key scan Input Low Voltage Port6 for key scan
VOH1
Output High Voltage
IOH = -1.6mA
(port5,6,7,8)
(port9)
IOH = -6.0mA
VOL1
Output Low Voltage
IOL = 1.6mA
(port5,6,7,8)
(port9)
IOL = 6.0mA
Vcom
Com voltage drop
Io=+/- 50 uA
Vseg
Segment voltage drop
Io=+/- 50 uA
Vlcd
LCD drive reference voltage Contrast adjustment
IPH
Pull-high current
Pull-high active input pin at
VSS
ISB1
Power down current
All input and I/O pin at
VDD, output pin floating,
WDT disabled
ISB2
Low clock current
CLK=32.768KHz, FSK,
(GREEN mode)
DTMF receiver ,TONE
block disable , All input and
I/O pin at VDD, output pin
floating, WDT disabled,
LCD enable
ISB3
Low clock current
CLK=32.768KHz, FSK,
(IDLE mode)
DTMF receiver ,TONE
block disable , All input and
I/O pin at VDD, output pin
floating, WDT disabled,
LCD enable
ISB4
Low clock current
CLK=32.768KHz, FSK,
(IDLE mode)
DTMF receiver ,TONE
block disable , All input and
Min
Typ
Max
±1
Unit
µA
±1
µA
0.8
V
V
V
0.8
V
2.5
2.0
3.5
1.5
3.5
1.5
2.4
2.4
-
V
V
V
V
V
0.4
V
V
-
0.4
2.9
3.8
V
V
V
-10
-15
µA
0.5
4
µA
55
90
µA
45
70
µA
15
40
µA
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
28
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
ICC1
Operating supply current
(CPU enable)
ICC2
Operating supply current
(CPU and DTMF receiver
enable)
ICC3
Operating supply current
(CPU and FSK enable)
Vref2
Tone generator reference
voltage
Tone1 signal strength
Tone2 signal strength
Vmax
Vmax
I/O pin at VDD, output pin
floating, WDT disabled,
LCD disable
/RESET=High,
CLK=3.679MHz, output pin
floating, FSK, DTMF
receiver , DA block disable
/RESET=High, DTMF
receiver enable ,
CLK=3.679MHz, output pin
floating, FSK, TONE block
disable
/RESET=High, FSK block
enable , CLK=3.679MHz,
output pin floating, DTMF
receiver and TONE block
disable
Root mean square voltage
Root mean square voltage
(Ta=0°C ~ 70°C, VDD=3V±5%, VSS=0V)
Symbol
Parameter
Condition
ISB1
Power down current
All input and I/O pin at
VDD, output pin floating,
WDT disabled
ISB2
Low clock current
CLK=32.768KHz, FSK,
(GREEN mode)
DTMF receiver ,DA block
disable , All input and I/O
pin at VDD, output pin
floating, WDT disabled,
LCD enable
ISB3
Low clock current
CLK=32.768KHz, FSK,
(IDLE mode)
DTMF receiver ,DA block
disable , All input and I/O
pin at VDD, output pin
floating, WDT disabled,
LCD enable
ISB3
Low clock current
CLK=32.768KHz, FSK,
(IDLE mode)
DTMF receiver ,DA block
disable , All input and I/O
pin at VDD, output pin
floating, WDT disabled,
LCD disable
ICC1
Operating supply current
/RESET=High,
(CPU enable)
CLK=3.579MHz, output pin
floating, FSK, DTMF
receiver , TONE block
disable
ICC2
Operating supply current
/RESET=High, DTMF
(CPU and DTMF receiver
receiver enable ,
enable)
CLK=3.679MHz, output pin
floating, FSK, TONE block
disable
1.5
2.2
mA
3.5
4.2
mA
3.5
4.2
mA
0.5
0.7
VDD
130 155
150 175
180
200
ｍV
ｍV
Min
Typ
0.1
Max
2
Unit
µA
35
45
µA
25
35
µA
10
25
µA
1.1
1.6
mA
1.6
2.6
mA
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
29
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
ICC3
Operating supply current
(CPU and FSK enable)
1.6
/RESET=High, FSK block
enable , CLK=3.579MHz,
output pin floating, DTMF
receiver and TONE block
disable
2.6
mA
Vref2
Tone generator reference
0.5
0.7
VDD
voltage
V1rms
Tone1 signal strength
Root mean square voltage
130 155
180
ｍV
V2rms
Tone2 signal strength
Root mean square voltage
1.259V1rms
ｍV
Ps. V1rms and V2rms has 2 dB difference. It means 20log(V2rms/V1rms) = 20log1.259 = 2 (dB)
IX
AC Electrical Characteristic
(Ta=0°C ~ 70°C, VDD=5V, VSS=0V)
Parameter
Conditions
Symbol
Input CLK duty cycle
Dclk
Instruction cycle time
32.768K
Tins
3.579M
Device delay hold time
Tdrh
TCC input period
Note 1
Ttcc
Min
45
Typ
50
60
550
18
Max
55
Unit
%
us
ns
ms
ns
(Tins+20
)/N
Watchdog timer period
18
Twdt
Ta = 25°C
Note 1: N= selected prescaler ratio.
(FSK and DTMF receiver Band Pass Filter AC Characteristic)(Vdd=5V ±10% ,Ta=+25℃)
CHARACTERISTIC
MIN
TYP
MAX
input sensitivity TIP and RING for FSK
-48
input sensitivity TIP and RING for DTMF receiver
-36
-34
4
(FSK AC Characteristic)
Description
Symbol
Min
Typ
Max
OSC start up(32.768KHz)
Tosc
-400
(3.579MHz PLL)
10
Carrier detect low
Tcdl
-10
14
Data out to Carrier det low
Tdoc
-10
20
Power up low to FSK(setup time)
Tsup
-15
20
/RD low to Ringtime low
Trd
10
End of FSK to Carrier Detect high
Tcdh
8
--Ringtime low pulse delay
Tpd
1
Please watch out the FSK setup time
(OTP AC Characteristic)
Description
Symbol
Min
Typ
Max
Vpp to VDD level setup time
Trs
2
Mode code setup time
Tcsu
3
Mode code hold time
Tchd
2
Data setup time
Tdsu
100
Data hold time
Tdhd
100
Program write pulse width
Tpwd
200
Output enable setup time
Toed
300
Data clock pulse width
Tph
100
(DTMF receiver AC Characteristic)
Description
Symbol
Min Typ
Max Unit
Tone Present Detection Time
Tdp
Note1
the guard-times for tone-present
Tgtp
30
ms
ms
UNIT
dBm
dBm
Unit
ms
ms
ns
ms
ms
ms
ms
Unit
uS
uS
uS
nS
nS
uS
nS
nS
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
30
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
(C=0.1uF, R=300K)
the guard-times for tone-absent
(C=0.1uF, R=300K)
Propagation Delay (St to Q)
Tone Absent Detection Time
Note1: Controlled by software
Note2: Controlled by RC circuit.
Tgta
30
mS
Tpq
Tda
8
Note2
μs
ms
OSC and reset timing characteristics (see Fig.23 for details)
Description
Oscillator timing characteristic
OSC start up
32.768kHz
3.579MHz PLL
Reset timing characteristic
The minimum width of reset low pulse
The delay between reset and program start
Embedded LCD driver
Symbol
Parameter
Frame
LCD frame frequency
Symbol
Min
Toscs
400
Trst
Tdrs
Condition
1/8, 1/16 duty
Typ
Max
Unit
5
1500
10
ms
us
3
18
uS
mS
Min Typ Max Unit
64
Hz
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
31
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
XI. Timing Diagrams
ins
`
Fig.20 AC timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
32
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
0.5 SEC
FIRST RING 0.5 SEC
2 SECONDS
SECOND RING
2 SECONDS
TIP/RING
/RING TIME
/RD
Tpd
Trd
Tcdh
Tcdl
/CD
Tdoc
DATA
DATA
Tosc
OSC
POWER
3.58 MHz
Tsup
Fig.21 FSK Timing Diagram
TONE
TONE
Tdp
Tgta
EST
Tgtp
Vtst
ST/GT
Tpq
Q4..Q1
STD
LINE_ENG
Fig.22 DTMF receiver timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
33
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VDD
OSC
Power
on reset
Toscs
Trst
/RESET
Tdrs
Tdrs
Program
Active
Fig.23 OSC and reset timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
34
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
XII. Application Circuit
1
2
4
3
D
D
VDD
1000P
TIP
RING
1000P
TIP
0.1u 250V
FUSE
VSS
AVDD
VDD
30K
DET1
VDD
C
0.1u
100
30K
RINGTIME
270K
0.22u
EST
ST/GT
0.1u
300K
C
VSS
RING
470K
DET1
0.01u
AVSS
AVSS
PLLC
VSS
XIN
TEST
33K
TO PHONE
XOUT
32768
27
VSS
0.1u 250V
VDD
27
RESET
470K
COMMON
SEGMENT
B
100K
B
0.1u
100K
NPN
LCD DISPLAY
Title
A
Size
A
Number
Revision
A
Date:
File:
1
2
3
3-Nov-1998
C:\ADVSCH\78806_1.SCH
Sheet of
Drawn By:
4
Fig.24 application circuit
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
35
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
附錄: EM78R806 SPEC.
IV.Pin Configuration
P76
P77
NC
NC
4MPD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
NC
GND
IOD0
IOD1
IOD2
IOD3
IOD4
IOD5
IOD6
IOD7
INSEND
IRSEL
PH1OUT
X2OUT
/HOLD
NC
ENTCC
NC
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
NC
NC
GND
TONE
PLLC
RINGTIME
DET1
RING
TIP
NC
XIN
XOUT
VDD
EST
ST/GT
P67
P66
P65
P64
P63
P62
P61
P60
VDD
NC
GND
C7
C6
C5
C4
C3
C2
C1
VDD
C0
S0
S1
EPS
CA-1
CA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
P75
P74
P73
P72
/RESET
P71
P70
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
GND
NC
VDD
S25
S24
S23
S22
S21
GND
S20
S19
S18
S17
S16
S15
S14
S13
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
GND
RC4M
VDD
CD12
CD11
CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
NC
CA12
CA11
CA10
CA9
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
Fig.1 Pin Assignment
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
36
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
VI.Pin Descriptions
PIN
VDD
I/O
POWER
DESCRIPTION
Power
GND
POWER
Ground
Xtin
Xtout
COM0..COM7
COM8..COM15
SEG0...SEG23
SEG24..SEG31
SEG32..SEG39
PLLC
I
O
O
O (PORT6)
O
O (PORT8)
O (PORT9)
I
Input pin for 32.768 kHz oscillator
Output pin for 32.768 kHz oscillator
Common driver pins of LCD drivers
TIP
RING
RDET1
I
I
I
/RING TIME
I
EST
O
ST/GT
I/O
INT0
INT1
INT2
INT3
PORT7(0)
PORT7(1)
PORT7(2)
PORT7(3)
PORT7(4:7) IO port
PORT7
PORT 7 can be INPUT or OUTPUT port each bit.
Internal Pull high function.
Key scan function.
Bit6,7 open drain function
PORT6
PORT 6 can be INPUT or OUTPUT port each bit.
And shared with Common signal.
PORT8
PORT 8 can be INPUT or OUTPUT port each bit.
And shared with Segment signal.
PORT9
PORT 9 can be INPUT or OUTPUT port each bit.
And shared with Segment signal.
Bit6,7 has wake-up function.
I
Test pin into test mode , normal low
O
DA converter’s output
I
P7.0 ~P7.7
P6.0 ~P6.7
P8.0 ~P8.7
P9.0 ~P9.7
TEST
DAOUT
RESET
X2OUT
O
Segment driver pins of LCD drivers
Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u with
AVSS
Should be connected with TIP side of twisted pair lines
Should be connected with TIP side of twisted pair lines
Detect the energy on the twisted pair lines . These two pins coupled to
the twisted pair lines through an attenuating network.
Determine if the incoming ring is valid.An RC network may be
connected to the pin.
Early steering output. Presents a logic high immediately when the
digital algorithm detects a recognizable tone-pair (signal condition).
Any momentary loss of signalcondition will cause ESt to return to a
logic low.
Steering input/guard time output (bi-directional). A voltage greater than
Vtst detected at ST causes the device to register the detected tone-pair
and update the output latch.
A voltage less than Vtst frees the device to accept a new tone-pair. The
GT output acts to reset the external steering time-constant; its state is a
function of EST and the voltage on ST (see truth table).
PORT7(0)~PORT7(3) signal can be interrupt signals.
System clock output.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
37
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
IX
CA-1
O
ERS
I
ENTCC
I
CA0~CA13
O
CD0~CD12
IRSEL
INSEND
I
O
O
/HOLD
I
CA-1 is used as address line to select low-order data (8 bits, through
CD0~CD7) or high-order data (5 bits, through CD0~CD4)
ERS=1 => CA-1 NO USE
ERS=0 => CA-1=0 HIGH ORDER DATA
CA-1=1 LOW ORDER DATA
Input pin used to select the external ROM data bus through bus
CD0~D12 or CD0~CD7 only.
HIGH/LOW = CD0~CD12 /
CD0~CD7.
TCC control pin with internal pull-high (560KΩ). TCC works
normally when ENTCC is high, and TCC counting is stopped when
ENTCC is low.
Program code address bus. CA0~CA13 are address output pins for
external programming ROM access.
Data access in terms of CA0 ~ CA12 addressing.
IRSEL is an output pin used to select an external EVEN/ODD ROM.
Used to indicate the instruction completion and ready for next
instruction.
Microcontroller hold request.
IOD0~IOD7
PH1OUT
O
O
I/O data bus.
Phase 1 output
AC Electrical Characteristic
Tdiea
Delay from Phase 3 end to
INSEND active
Tdiei
Delay from Phase 4 end to
INSEND inactive
Tiew
INSEND pulse width
Tdca
Delay from Phase 4 end to
CA Bus valid
Tacc
ROM data access time
Tcds
ROM data setup time
Tcdh
ROM data hold time
Tdca-1
Delay time of CA-1
Note 1: N= selected prescaler ratio.
Cl=100pF
30
ns
Cl=100pF
30
ns
30
ns
ns
30
ns
ns
ns
ns
30
C1=100pF
100
20
20
C1=100pF
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
38
07/13/2004 V1.5
EM78P806A
8-bit OTP Micro-controller
3
4
1
2
3
4
1
2
3
CLK
Tdiea
Tdiei
Tiew
/INSEND
Tdca
CA13:0
CD12:0
Tacc
Tcdh
Tcds
EPS=1 CA-1=DISABLE
3
4
1
2
3
4
1
2
3
CLK
Tdiea
Tdiei
Tiew
/INSEND
Tdca
CA-1
Tdca-1
CA13:0
CD7:0
Tacc
HIGH ORDER
DATA
Tcds
LOW ORDER
DATA
Tcdh
EPS=0 CA-1=0 HIGH ORDER DATA CA-1=1 LOW ORDER DATA
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
39
07/13/2004 V1.5